STMicroelectronics STM706, STM706P, STM708 Technical data
FEAT URES SUM MARY
■ PRECISION V
– STM706/708
T: 3.00V ≤ V
S: 2.88V ≤ V
R; STM706P: 2.59V ≤ V
■ RST AND RST OUTPUTS
■ 200ms (TYP) t
■ WATCHDOG TIMER - 1.6sec (TYP)
■ MANUAL RESET INPUT (MR)
■ POWER-FAIL COMPARATOR (PFI/PFO)
■ LOW SUPPLY CURRENT - 40µA (TYP)
■ GUARANTEED RST (RST) ASSERTION
DOWN TO V
■ OPERATING TEMPERAT UR E:
–40°C to 85°C (Industrial Grade)
MONITO R
CC
RST
RST
rec
= 1.0V
CC
≤ 3.15V
≤ 3.00V
RST
≤ 2.70V
STM706, STM706P, STM708
3V Supervisor
Figure 1. Packages
8
1
SO8 (M)
TSSOP8 3x3 (DS)
Table 1. Device Options
Watchdog
Input
STM706 ✔✔✔ ✔✔
STM706P
STM708 ✔✔✔✔
Note: 1. Push-Pull Output
(2)
2. The STM706P is identical to the STM706R, except its res et output is act i ve-high.
✔✔ ✔✔✔
Watchdog
Output
Active-Low
(1)
RST
Active-High
(1)
RST
Manual
Reset Input
Power-fail
Comparator
1/25July 2004
STM706/706P/708
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 1. Device Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram (STM706/706P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. Logic Diagram (STM708). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 4. STM706/706P SO8 Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 5. STM706/706P TSSOP8 Connec tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 6. STM708 SO8 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 7. STM708 TSSOP8 Connection s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 8. Block Diagram (STM706/706P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 9. Block Diagram (STM708) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 10.Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Reset Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Push-button Reset Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Watchdog Input (STM706/706P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Watchdog Output (STM706/706P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power-fail Input/Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ensuring a Valid Reset Output Down to V
= 0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
CC
Figure 11.Reset Output Valid to Ground Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Interfacing to Microprocessors with Bi-directional Reset Pins . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 12.Interfacing to Microprocessors with Bi-directional Reset I/O. . . . . . . . . . . . . . . . . . . . . . . 9
TYPICAL OPERATING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 13.Supply Current vs. Temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 14.V
Threshold vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
PFI
Figure 15.Reset Comparator Propagation Delay vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 16.Power-up t
vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
rec
Figure 17.Normalized Reset Threshold vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 18.Watchdog Time-out Period vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 19.PFI to PFO
Figure 20.RST
Output Voltage vs. Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Propagation Delay vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 21.RST Output Voltage vs. Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 22.RST
Response Time (Assertion). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 23.RST Response Time (Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 24.Power-fail Comparator Response Time (Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 25.Power-fail Comparator Response Time (De-Assertion) . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 26.V
to Reset Propagation Delay vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
CC
2/25
STM706/706P/708
Figure 27.Maximum Transient Duration vs. Reset Threshold Overdrive. . . . . . . . . . . . . . . . . . . . . 16
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 28.AC Testing Input/Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 29.Power-fail Comparator Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 30.MR
Figure 31.Watchdog Timing (STM706/706P ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 6. DC and A C Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 32.SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical. . . . . . . 20
Table 7. S O8 – 8-lead Plast ic Small Outline, 150 mils body widt h, Package Mechanical Data . . 20
Figure 33.TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Outline . . . . . . . . . . . 21
Table 8. TS SOP 8 – 8-lead, Thin Shrink Smal l Outline, 3x3mm body size , Mechanical Data . . . . 21
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 9. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 10.Marking Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 11.Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3/25
STM706/706P/708
SUMMARY DESCRIPT ION
The STM70X SUPERVISORs are self-contained
devices which provide microprocessor supervisory functions. A precision voltage reference and
comparator monitors the V
tolerance condition. When an invalid V
tion occurs, the reset output (RST
(or high in the ca se of RST). These devices also
offer a watchdog timer (except for STM708) as
well as a power-fail comparator to provide the sys-
input for an out-of-
CC
CC
condi-
) is forced low
tem with an early warning of impending power failure.
The STM706P is identical to the STM706R, except
its reset output is active-high.
These devices are available in a standard 8-pin
SOIC package or a space-saving 8-pin TSSOP
package.
Figure 2. Logic Diagram (STM706/706P)
V
CC
WDI
MR
STM706
PFI
Note: 1. For STM 7 06P only.
V
SS
WDO
RST (RST)
PFO
AI08841
Figure 3. Logic Diagram (STM708)
(1)
Table 2. Signal Names
MR Push-button Reset Input
WDI Watchdog Input
WDO
RST
(1)
RST
V
CC
PFI Power-fail Input
PFO
V
SS
NC No Conn ect
Note: 1. For STM 7 06P/708 onl y.
Watchdog Output
Active-Low Reset Output
Active-High Reset Output
Supply Voltage
Power-fail Output
Ground
4/25
MR
PFI
V
CC
STM708
V
SS
RST
RST
PFO
AI08842
STM706/706P/708
Figure 4. STM706/706P SO8 Connecti ons
SO8
MR
V
V
PFI
Note: 1. For STM706P reset output is active-high.
CC
SS
1
2
3
4
8
7
6
5
WDO
RST(RST)
WDI
PFO
AI08837
(1)
Figure 5. STM706/706P TSSOP8 C onnecti on s
RST(RST)
(1)
WDO
MR
V
CC
Note: 1. For STM706P reset output is active-high.
TSSOP8
1
2
3
4
WDI
8
PFO
7
PFI
6
V
5
SS
AI08838
Table 3. Pin Description
Pin
Name FunctionSTM706P STM706 STM708
SO8 TSSOP8 SO8 TSSOP8 SO8 TSSOP8
131313MR
6868––WDI
8282––WDO
Figure 6. STM708 SO8 Connections
SO8
MR
V
V
PFI
CC
SS
1
2
3
4
RST
8
RST
7
NC
6
PFO
5
AI08839
Figure 7. STM708 TSSOP8 Connections
TSSOP8
RST
RST
MR
V
CC
Push-button Reset Input.
A logic low on /MR asserts the reset output. Reset
remains asserted as long as MR
MR returns high. This active-low input has an internal
pull-up. It can be driven from a TTL or CMOS logic line,
or shorted to ground with a switch. Leave open if
unused.
Watchdog Input.
If WDI remains high or low for 1.6sec, the internal
watchdog timer runs out and reset (or WDO
triggered. The internal watchdog timer clears while
reset is asserted or when WDI sees a rising or falling
edge.
The watchdog function cannot be disabled by allowing
the WDI pin to float.
Watchdog Output.
goes low when a transition does not occur on
WDO
WDI within 1.6sec, and remains low until a transition
occurs on WDI (indicating the watchdog interrupt has
been serviced). WDO
below the reset threshold; however, unlike the reset
output, WDO
reset threshold.
Note: For those devices with a WDO
watchdog timeout will not trigger reset unless WDO
connected to MR
goes high as soon as VCC exceeds the
1
2
3
4
also goes low when VCC falls
.
NC
8
PFO
7
PFI
6
V
5
is low and for t
SS
AI08840
) is
output, a
rec
after
is
5/25
STM706/706P/708
Pin
Name FunctionSTM706P STM706 STM708
SO8 TSSOP8 SO8 TSSOP8 SO8 TSSOP8
Active-Low Reset Output.
Pulses low for t
––7171RST
71––82RST
242424
464646PFI
575757PFO
353535
––––68NCNo Connect.
whenever VCC is below the reset threshold or when MR
is a logic low. It remains low for t
rises above the reset threshold, the watchdog triggers a
reset, or MR
Active-High Reset Output.
Inverse of RST
V
Supply Voltage.
CC
PFI Power-fail Input.
When PFI is less than V
PFO remains high. Connect to ground if unused.
PFO Power-fail Output.
When PFI is less than V
PFO remains high. Leave open if unused.
V
Ground.
SS
when triggered, and stays low
rec
after either VCC
rec
goes from low to high.
.
, PFO goes low; otherwise,
PFI
, PFO goes low; otherwise,
PFI
Figure 8. Block Diagram (STM706/706P)
WDI
V
CC
V
MR
PFI
Note: 1. For STM 7 06P only.
CC
WDI
Transitional
Detector
V
RST
V
WATCHDOG
PFI
TIMER
COMPARE
COMPARE
t
rec
Generator
WDO
RST(RST)
PFO
AI08829
(1)
6/25
Figure 9. Block Diagram (STM708)
V
CC
V
CC
MR
STM706/706P/708
V
RST
COMPARE
t
rec
Generator
RST
RST
PFI
Figure 10. Hardware Hookup
Unregulated
Voltage
R1
R2
V
PFI
COMPARE
Regulator
V
V
CC
IN
0.1µF
From Microprocessor
Push-button
V
CC
WDI
PFI
MR
STM70X
(1)
WDO
PFO
RST
RST
PFO
AI08830
(1)
To Microprocessor IRQ
To Microprocessor NMI
(2)
To Microprocessor Reset
Note: 1. For STM706/706P.
2. For ST M 706P/708.
AI08843
7/25
STM706/706P/708
OPERATION
Reset Output
The STM70X SUPERVI SOR asserts a reset signal to the MCU whenever V
set threshold (V
(if WDO
is connected to M R), or when the Push-
button Reset Input (MR
), a watchdog time-out o ccurs
RST
) is taken low. RST is guar-
anteed to be a log ic lo w (log ic hig h for S T M70 6P/
708) for V
CC
< V
down to VCC =1V for TA = 0°C
RST
to 85°C.
During power-up, once V
threshold an internal timer keeps RST
reset time-out period, t
rec
returns high.
drops below the reset threshold, RST goes
If V
CC
low. Each time RST
is asserted, it stays low for at
least the reset time-out period (t
goes below the reset threshold the internal timer
clears. The reset timer starts when V
above the reset threshold.
Push-button Reset Input
A logic low on MR
asserted while MR
asserts reset. Reset remains
is low, and for t
30., page 18) after it returns high. The MR
has an internal 40kΩ pull-up resistor, allowing it to
be left open if not used. This input can be driven
with TTL/CMOS-logic levels or with open-drain/
collector outputs. Connect a normally open momentary switch from MR
ual reset function; external debounce circuitry is
not required. If MR
is driven from long cables or
the device is used in a noisy environment, connect
a 0.1µF capacitor from M R
ditional noise immunity. MR
when not used.
V
CC
Watchdog Input (STM706/706P)
The watchdog timer can be used to detect an outof-control MCU. If the MCU does not toggle the
Watchdog Input (WDI) within t
Watchdog Output pin (WDO
ternal 1.6sec timer is cleared by either:
1. a reset pulse, or
2. by toggling WDI (high-to-low or low-to-high),
which can detect pulses as short as 50ns.
See F igure 31., page 18 for STM706/706 P.
The timer remains cleared and does not count for
as long as reset is asserted. As soon as reset is released, the timer starts counting.
goes below the re-
CC
exceeds the reset
CC
low for the
. After this interval RST
). Any time V
rec
rec
CC
(see Figure
CC
returns
input
to GND to create a man-
to GND to provide ad-
may float, or be tied to
(1.6sec), the
WD
) is asserted. The in-
Watchdog Output (STM706/706P)
When V
drops below the reset threshold, WDO
CC
will go low even if the wa tchdog timer has not yet
timed out. However, unlike the reset output, WDO
goes high as soon as VCC exceeds the reset
thres h old. W DO
pulse by connecting it to the MR
may be used to generate a reset
input.
Power-fail Input/Output
The Power-fail Input (PFI) is compared to an internal reference voltage (independent from the V
RST
comparator). If PFI is less than the power-fail
threshold (V
), the Power-Fail Output (PFO) will
PFI
go low. This function is intended for use as an undervoltage detector to signal a failing power supply. Typically PFI is connected through an external
voltage divider (see Figure 10. , page 7) to either
the unregulated DC input (if it is a vailable) or the
regulated output of the V
regulator. The voltage
CC
divider can be set up such that the voltage at PFI
falls below V
regulated V
several milliseconds before the
PFI
input to the STM70X or the micro-
CC
processor drops below the minimum operating
voltage.
If the comparator is unused, PFI should be connected to V
and PFO left unconnected. PFO
SS
may be connected to MR on t he STM70X s o that
a low voltage on PFI will gene ra te a reset output.
Ensuring a Valid Reset Output Down to
=0V
V
CC
When V
falls below 1V, the state of the RST out-
CC
put can no longer be guaranteed, and becomes
essentially an open circuit. If a high value pulldown resistor is added to the RST
pin, the output
will be held low during this condition. A resistor value of approximately 100kΩ will be large enough to
not load the output under operating conditions, but
still sufficient to pull RST
to ground during this low
voltage condition (see Figure 11).
Figure 11. Reset Output Valid to Ground Circuit
STM70X
RST
R1
8/25
AI08844
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