FEAT URES SUMMARY
■ 5V OPERATING VOLTAGE
■ PRECISION V
– STM705/707/813L
4.50V ≤ V
– STM706/708
4.25 ≤ V
■ RST AND RST OUTPUTS
■ 200ms (TYP) t
■ WATCHDOG TIMER - 1.6sec (TYP)
■ MANUAL RESET INPUT (MR)
■ POWER-FAIL COMPARATOR (PFI/P FO )
■ LOW SUPPLY CURRENT - 40µA (TYP)
■ GUARANTEED RST (RST) ASSERTION
DOWN TO V
■ OPERATING TEMPERAT UR E:
–40°C to 85°C (Industrial Grade)
CC
RST
RST
rec
CC
≤ 4.50V
= 1.0V
MONITO R
≤ 4.75V
STM705, STM706,
STM707, STM708, STM813L
5V Supervisor
Figure 1. Packages
8
1
SO8 (M)
TSSOP8 3x3 (DS)
Table 1. Device Options
Watchdog
Input
STM705 ✔✔✔ ✔✔
STM706 ✔✔✔ ✔✔
STM707 ✔✔✔✔
STM708 ✔✔✔✔
STM813L ✔✔ ✔✔✔
Note: 1. Push-pull Output
Watchdog
Output
Active-Low
(1)
RST
Active-High
(1)
RST
Manual
Reset Input
Power-fail
Comparator
1/27March 2005
STM705/706/707/708/813L
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 1. Device Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram (STM705/706/813L ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. Logic Diagram (STM707/708) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 4. STM705/706/813L SO8 Connec tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 5. STM705/706/813L TSSO P8 Connec tions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 6. STM707/708 SO8 Conne ctions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 7. STM707/708 TSSOP8 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 8. Block Diagram (STM705/706/813L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 9. Block Diagram (STM707/708). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 10.Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Reset Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Push-button Reset Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Watchdog Input (STM705/706/813L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Watchdog Output (STM705/706/813L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-fail Input/Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ensuring a Valid Reset Output Down to V
= 0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CC
Figure 11.Reset Output Valid to Ground Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Interfacing to Microprocessors with Bi-directional Reset Pins . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 12.Interfacing to Microprocessors with Bi-directional Reset I/O. . . . . . . . . . . . . . . . . . . . . . 10
TYPICAL OPERATING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 13.Supply Current vs. Temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 14.V
Threshold vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
PFI
Figure 15.Reset Comparator Propagation Delay vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 16.Power-up t
vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
rec
Figure 17.Normalized Reset Threshold vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 18.Watchdog Time-out Period vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 19.PFI to PFO
Figure 20.Output Voltage vs. Load Current (V
Figure 21.Output Voltage vs. Load Current (V
Figure 22.RST
Output Voltage vs. Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Propagation Delay vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
= 5V; V
CC
= 0V; V
CC
= 2.8V; TA = 25°C). . . . . . . . . . . . . . 14
BAT
= 2.8V; TA = 25°C). . . . . . . . . . . . . . 15
BAT
Figure 23.RST Output Voltage vs. Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 24.RST
Response Time (Assertion). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 25.RST Response Time (Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2/27
STM705/706/707/708/813L
Figure 26.Power-fail Comparator Response Time (Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 27.Power-fail Comparator Response Time (De-Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 28.Maximum Transient Duration vs. Reset Threshold Overdrive. . . . . . . . . . . . . . . . . . . . . 18
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 4. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 5. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 29.AC Testing Input/Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 30.Power-fail Comparator Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 31.MR
Figure 32.Watchdog Timing (STM705/706/8 13L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 6. DC and A C Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 33.SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical. . . . . . . 23
Table 7. S O8 – 8-lead Plast ic Small Outline, 150 mils body widt h, Package Mechanical Data . . 23
Figure 34.TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Outline . . . . . . . . . . . 24
Table 8. TS SOP 8 – 8-lead, Thin Shrink Smal l Outline, 3x3mm body size , Mechanical Data . . . .24
Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 9. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 10.Marking Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 11.Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3/27
STM705/706/707/708/813L
SUMMARY DESCRIPTION
The STM705/706/707/708/813L Supervisors are
self-contained devices which provide microprocessor supervisory functions. A precision voltage
reference and comparator m oni tors th e V
for an out-of-tolerance condition. When an invalid
condition occurs, the reset output (RST) is
V
CC
forced low (or high in the case of RST).
CC
input
These devices also offer a watchdog timer (except
for STM707/708) as well as a power-fail comparator to provide the system with an early warning of
impending power failure.
These devices are available in a standard 8-pin
SOIC package or a space-saving 8-pin TSSOP
package.
Figure 2. Logic Diagram (STM705/706/813L)
V
CC
WDO
WDI
MR
STM705/706;
STM813L
PFI
V
Note: 1. For STM70 5/706 only.
2. For STM813L only.
SS
RST
RST
PFO
AI08825
(1)
(2)
Figure 3. Logic Diagram (STM707/708)
V
CC
RST
MR
STM707/708
RST
PFI
PFO
V
SS
AI08826
Table 2. Signal Names
MR Push-button Reset Input
WDI Watchdog Input
4/27
WDO
RST
(1)
RST
V
CC
PFI Power-fail Input
PFO
V
SS
NC No Conn ect
Note: 1. For STM81 3L only.
Watchdog Output
Active-Low Reset Output
Active-High Reset Output
Supply Voltage
Power-fail Output
Ground
STM705/706/707/708/813L
Figure 4. STM705/706/813L SO8 Connections
SO8
MR
V
V
PFI
Note: 1. For STM813L, reset outp ut is active-hi gh.
CC
SS
1
2
3
4
8
7
6
5
WDO
RST(RST)
WDI
PFO
AI08827a
(1)
Figure 5. STM705/706/813L TSSOP8 Connections
TSSOP8
(1)
CC
1
2
3
4
(RST)RST
WDO
MR
V
Note: 1. For STM813L, reset outp ut is active-hi gh.
WDI
8
PFO
7
PFI
6
V
5
SS
AI09114
Figure 6. STM707/708 SO8 Connections
SO8
MR
V
V
PFI
CC
SS
1
2
3
4
8
7
6
5
RST
RST
NC
PFO
AI08828a
Figure 7. STM707/708 TSSOP8 Connection s
TSSOP8
RST
RST
MR
V
CC
1
2
3
4
NC
8
PFO
7
PFI
6
V
5
SS
AI09115
5/27
STM705/706/707/708/813L
Pin Descrip tio ns
.A logic low on MR asserts the reset out put.
MR
Reset remains asserted as long as MR
after MR returns high. This active-low input
for t
rec
has an internal pull-up. It can be driven from a TTL
or CMOS logic line, or shorted to ground with a
switch. Leave open if unused.
WDI. If WDI remains high or low for 1.6sec, the internal watchdog timer runs out and reset (or WDO
is triggered. The internal watchdog timer clears
while reset is asserted or when WDI s ees a rising
or falling edge.
The watchdog function can be di sabled by allowing the WDI pin to float.
.It goes low when a transition does not oc-
WDO
cur on WDI within 1.6sec, and rem ain s low until a
transition occurs on WDI (indicating the watchdog
interrupt has been serviced). WDO
when V
falls below the reset threshold; howev-
CC
er, unlike the reset output, WDO
soon as V
exceeds the reset threshold.
CC
Note: For those devices with a WDO
watchdog timeout will not trigger reset unless
is connected to MR.
WDO
is low and
also goes low
goes high as
output, a
.Pulses low when triggered, and stays low
RST
whenever V
when MR
either V
CC
is below the reset threshold or
CC
is a logic low. It remains low for t
rises above the res et thresho ld, or M R
goes from low to high.
RST. Goes high with triggered, and stays high
is above the reset threshold or
CC
is a logic high. It stays high for t
falls below the reset threshold, or MR
)
whenever V
when MR
either V
CC
goes from high to low.
PFI. When PF I is less than V
otherwise, PFO
remains high. Con nect t o ground
, PFO goes low;
PFI
if unused.
.When PFI is less than V
PFO
otherwise, PFO
remains high. Leave open if un-
, PFO goes low;
PFI
used.
rec
rec
after
after
Table 3. Pin Description
Pin Name Function
STM813L
111MR
6 – 6 WDI Watchdog Input
8–8WDO
–77RST
7 8 – RST Active-High Reset Output
222
4 4 4 PFI PFI Power-fail Input
555PFO
333
– 6 – NC No Connect
STM707
STM708
STM705
STM706
Push-button Reset Input
Watchdog Output
Active-Low Reset Output
V
Supply Voltage
CC
PFO Power-fail Output
V
Ground
SS
6/27
Figure 8. Block Diagram (STM705/706/813L)
STM705/706/707/708/813L
WDI
WDI
Transitional
Detector
V
CC
V
CC
V
RST
MR
PFI
V
PFI
Note: 1. For STM81 3L only.
Figure 9. Block Diagram (STM707/708)
V
CC
MR
V
CC
V
RST
WATCHDOG
TIMER
COMPARE
COMPARE
COMPARE
t
rec
Generator
t
rec
Generator
WDO
RST(RST)
PFO
AI08829
RST
RST
(1)
PFI
V
PFI
COMPARE
PFO
AI08830
7/27
STM705/706/707/708/813L
Figure 10. Hardware Hookup
Unregulated
Voltage
Note: 1. For STM70 5/ 7 06/813L.
R1
R2
Regulator
V
V
CC
IN
0.1µF
From Microprocessor
Push-button
V
CC
STM705/706/
707/708;
STM813L
(1)
WDI
PFI
MR
WDO
PFO
RST
(1)
To Microprocessor IRQ
To Microprocessor NMI
To Microprocessor Reset
AI08831
8/27
OPERATION
Reset Output
The STM705/706/707/708/813L Supervisor asserts a reset signal to the MCU whenever V
goes below the reset threshold (V
dog time-out occurs (if WDO
is tied to MR), or
when the Push-button Reset Input (MR
low. RST
is guaranteed to be a logic low (logic
high for STM707/708/813L) for V
=1V for TA = 0°C to 85°C.
to V
CC
During power-up, once V
exceeds the reset
CC
threshold an internal timer keeps RST
reset time-out period, t
. After this interval RST
rec
CC
RST
< V
), a watch-
) is ta ken
RST
low for the
returns high.
drops below the reset threshold, RST goes
If V
CC
low. Each time RST
least the reset time-out period (t
is asserted, it stays low for at
). Any time V
rec
goes below the reset threshold the internal timer
clears. The reset timer starts when V
CC
above the reset threshold.
Push-button Reset Input
A logic low on MR
asserted while MR
asserts reset. Reset remains
is low, and for t
(see Figure
rec
31., page 21) after it returns high. The MR
has an internal 40kΩ pull-up resistor, allowing it to
be left open if not used. This input can be driven
with TTL/CMOS-logic levels or with open-drain/
collector outputs. Connect a normally open momentary switch from MR
to GND to create a manual reset function; external debounce circuitry is
not required. If MR
is driven from long cables or
the device is used in a noisy environment, connect
a 0.1µF capacitor from M R
ditional noise immunity. MR
when not used.
V
CC
to GND to provide ad-
may float, or be tied to
CC
down
CC
returns
input
STM705/706/707/708/813L
Watchdog Input (STM705/706/813L)
The watchdog timer can be used to detect an outof-control MCU. If the MCU does not toggle the
Watchdog Input (WDI) within t
set is asserted. The internal 1.6sec timer is
cleared by either:
1. a reset pulse, or
2. by toggling WDI (high-to-low or low-to-high),
which can detect pulses as short as 50ns. If
WDI is tied high or low, a reset pulse is
triggered every 1.8sec (t
connected to MR
.
See F igure 32., page 21 for STM705/706/813L.
The timer remains cleared and does not count for
as long as reset is asserted. As soon as reset is released, the timer starts counting.
Note: The watchdog function may be disabled by
floating WDI or tri-stating the driver connected to
WDI. When tri-stated or disconnected, the maximum allowable leakage current is 10uA and the
maximum allowable load capacitance is 200pF.
Watchdog Output (STM705/706/813L)
When V
drops below the reset threshold, WDO
CC
will go low even if the wa tchdog timer has not yet
timed out. However, unlike the reset output, WDO
goes high as soon as VCC exceeds the reset
thres h old. W D O
may be used to generate a reset
pulse by connecting it to the MR
Power-fail Input/Output
The Power-fail Input (PFI) is compared to an internal reference voltage (independent from the V
comparator). If PFI is less than the power-fail
threshold (V
), the Power-Fail Output (PFO) will
PFI
go low. This function is intended for use as an undervoltage detector to signal a failing power supply. Typically PFI is connected through an external
voltage divider (see Figure 10. , page 8) to either
the unregulated DC input (if it is a vailable) or the
regulated output of the V
CC
divider can be set up such that the voltage at PFI
falls below V
regulated V
several milliseconds before the
PFI
input to the STM705/ 706/707/708/
CC
813L or the microprocessor drops below the minimum operating voltage.
If the comparator is unused, PFI should be connected to V
and PFO left unconnected. PFO
SS
may be connected to MR on the STM703/704/818
so that a low voltage on P FI will generat e a reset
output.
(1.6sec), the re-
WD
+ t
WD
), if WDO is
rec
input.
RST
regulator. The voltage
9/27
STM705/706/707/708/813L
Ensuring a Valid Reset Output Down to
=0V
V
CC
When V
falls below 1V, the state of the RST out-
CC
put can no longer be guaranteed, and becomes
essentially an open circuit. If a high value pulldown resistor is added to the RST
pin, the output
will be held low during this condition. A resistor value of approximately 100kΩ will be large enough to
not load the output under operating conditions, but
still sufficient to pull RST
to ground during this low
voltage condition (see Figure 11).
Figure 11. Reset Output Valid to Ground Circuit
STMXXX
RST
R1
AI08835
Interfacing to Microprocessors with Bidirectional Reset Pins
Microprocessors with bi-directional reset pins can
contend with the STM705-708 reset output. For
example, if the reset output is driven high a nd t he
micro wants to pull it low, signal contention will result. To prevent this from occurring, connect a
4.7kΩ resistor between the reset output and the
micro’s reset I/O as in Figure 12.
Figure 12. Interfacing to Microprocessors with Bi-directional Reset I/O
Buffered Reset to other
System Components
V
CC
STMXXX
GND
4.7k
RST
V
CC
Microprocessor
RST
GND
AI08836
10/27
TYPICAL OPERATING CHARACTERISTICS
Note: Typical values are at TA = 25°C .
Figure 13. Supply Current vs. Temperature (no load )
30
25
20
15
10
Supply Current (µA)
5
STM705/706/707/708/813L
VCC = 2.7V
VCC = 3.0V
VCC = 3.6V
VCC = 4.5V
VCC = 5.5V
0
–40 –20 0 20 40 60 80 100 120
Figure 14. V
1.270
1.265
1.260
1.255
1.250
1.245
Threshold (V)
PFI
1.240
V
1.235
1.230
Threshold vs. Temperature
PFI
VCC = 3.0V
VCC = 4.5V
VCC = 4.75V
VCC = 5.5V
Temperature (°C)
AI09141b
1.225
–40 –20 0 20 40 60 80 100 120
Temperature (°C)
AI09142b
11/27
STM705/706/707/708/813L
Figure 15. Reset Comparator Propagation Delay vs. Temperature
30
28
26
24
22
20
18
16
Propagation Delay (µs)
14
12
10
–40 –20 0 20 40 60 80 100 120
Temperature (°C)
AI09143b
Figure 16. Power-up t
240
235
230
225
(ms)
rec
t
220
215
210
–40 –20 0 20 40 60 80 100 120
vs. Temperature
rec
Temperature (°C)
VCC = 3.0V
VCC = 4.5V
VCC = 5.5V
AI09144b
12/27
Figure 17. Normalized Reset Threshold vs. Temperature
1.004
1.002
1.000
0.998
Normalized Reset Threshold
0.996
–40 –20 0 20 40 60 80 100 120
Temperature (°C)
Figure 18. Watchdog Time-out Period vs. Temperature
STM705/706/707/708/813L
AI09145b
1.90
1.85
1.80
1.75
1.70
Watchdog Time-out Period (sec)
1.65
1.60
–40 –20 0 20 40 60 80 100 120
Temperature (°C)
VCC = 3.0V
VCC = 4.5V
VCC = 5.5V
AI09146b
13/27
STM705/706/707/708/813L
Figure 19. PFI to PFO Propagation Delay vs. Temperature
4.0
3.0
2.0
1.0
PFI to PFO Propagation Delay (µs)
0.0
–40 –20 0 20 40 60 80 100 120
Temperature (°C)
VCC = 3.0V
VCC = 3.6V
VCC = 4.5V
VCC = 5.5V
AI09148b
Figure 20. Output Voltage vs. Load Current (V
5.00
4.98
(V)
OUT
V
4.96
4.94
0 1020304050
= 5V; V
CC
I
OUT
(mA)
= 2.8V; TA = 25°C)
BAT
AI10496
14/27
STM705/706/707/708/813L
Figure 21. Output Voltage vs. Load Current (VCC = 0V; V
2.80
2.78
2.76
2.74
(V)
OUT
2.72
V
2.70
2.68
2.66
0.0 0.2 0.4 0.6 0.8 1.0
I
(mA)
OUT
Figure 22. R
5
4
ST Output Voltage vs. Supply Voltage
= 2.8V; TA = 25°C)
BAT
V
RST
V
CC
AI10497
5
4
(V)
RST
V
3
3
(V)
CC
2
1
0
500ms/div
AI09149b
V
2
1
0
15/27
STM705/706/707/708/813L
Figure 23. RS T Ou t put V ol ta ge vs . Su ppl y V ol ta ge
5
4
V
V
RST
CC
5
4
3
(V)
RST
2
V
1
0
Figure 24. R
5V
V
CC
5V
ST Response Time (Assertion)
500ms/div
1V/div
4V
4V
3
2
1
0
AI09150b
(V)
CC
V
Note: V
16/27
RST
= 4.603V at 25°C.
RST
5µs/div
1V/div
0V
AI09151b
Figure 25. RST Response Time (Assertion)
V
CC
1V/div
RST
1V/div
STM705/706/707/708/813L
5V
4V
4V
0V
5µs/div
Note: V
= 4.603V at 25°C.
RST
Figure 26. Power-fail Com p a rat or Response Tim e (Assertion)
5V
PFO
1.3V
PFI
AI09152b
1V/div
0V
500mV/div
500ns/div
0V
AI09153b
17/27
STM705/706/707/708/813L
Figure 27. Power-fail Comparator Response Time (De-A ssertion )
5V
PFO
0V
PFI
0V
500ns/div
Figure 28. Maximum Transient Duration vs. Reset Thresh old Over drive
6000
5000
1V/div
1.3V
500mV/div
AI09154b
18/27
4000
Reset occurs
above the curve.
3000
2000
Transient Duration (µs)
1000
0
0.001 0.01 0.1 1 10
Reset Comparator Overdrive, V
– VCC (V)
RST
AI09156b
STM705/706/707/708/813L
MAXIMUM RA T ING
Stressing the device above the rating listed in the
Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress
ratings only and operation of the device at t hese or
any other conditions ab ove those i ndicated in t he
Operating sections of this specificat ion is not im-
Table 4. Absolute Maximum Ratings
Symbol Parameter Value Unit
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevan t quality documents.
T
STG
(1)
T
SLD
V
IO
V
CC
I
O
P
D
Note: 1. Reflow at peak temperature of 255°C t o 260°C for < 30 seconds (to tal thermal budget not to ex ceed 180°C for between 90 to 150
seconds).
Storage Temperature (VCC Off)
Lead Solder Temperature for 10 seconds 260 °C
Input or Output Voltage
Supply Voltage –0.3 to 7.0 V
Output Current 20 mA
Power Dissipation 320 mW
–55 to 150 °C
–0.3 to V
CC
+0.3
V
19/27
STM705/706/707/708/813L
DC AND AC PARAMETERS
This section summarizes t he operating m easurement conditions, and the DC and AC characteristics of the device. The parameters in the D C and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Table 5. Operating and AC Measurement Conditions
Parameter
Supply Voltage
V
CC
Ambient Operating Temperature (T
)
A
Input Rise and Fall Times ≤ 5ns
Input Pulse Voltages
Input and Output Timing Ref. Voltages
Figure 29. AC Testing Input/Output Waveforms
Conditions summarized in Table 5, Operating and
AC Measurement Conditions. Designers should
check that the operating cond itions in their circuit
match the operating conditions when relying on
the quoted parameters.
STM705/706/707/708;
STM813L
1.0 to 5.5 V
–40 to 85 °C
0.2 to 0.8V
0.3 to 0.7V
CC
CC
Unit
V
V
0.8V
0.2V
CC
CC
0.7V
0.3V
AI02568
CC
CC
Figure 30. Power-fail Comp a rat or Waveform
V
CC
V
RST
PFO
RST
trec
AI08834b
20/27
Figure 31. MR Timing Waveform
MR
tMLRL
(1)
RST
STM705/706/707/708/813L
tMLMH
Note : 1. RS T for STM805.
Figure 32. Watchdog Timing (STM705/706/813L )
V
CC
RST
WDI
WDO
trec
Table 6. DC and AC Characteristics
CC
CC
I
LI
Alter-
native
Description
Operating Voltage
VCC Supply Current
Input Leakage Current (MR)
Input Leakage Current (PFI)
Input Leakage Current (WDI)
IH
IH
IL
IL
Input High Voltage (MR)
Input High Voltage (WDI)
Input Low Voltage (MR)
Input Low Voltage (WDI)
Sym
V
I
V
V
V
V
trec
AI07837a
tWD
AI08833
Test Condition
(1)
Min Typ Max Unit
1.2
(2)
5.5 V
25 60 µA
4.5V < V
0V = V
WDI = VCC, time average
CC
IN
= V
< 5.5V
CC
75 125 300 µA
–25 2 +25 nA
120 160 µA
WDI = GND, time average –20 –15 µA
4.5V < V
V
(max) < VCC < 5.5V 0.7V
RST
4.5V < V
V
(max) < VCC < 5.5V 0.3V
RST
< 5.5V
CC
< 5.5V
CC
2.0 V
CC
0.8 V
CC
V
V
21/27
STM705/706/707/708/813L
Sym
V
OL
V
OL
V
OH
V
OH
Alter-
native
Description
Output Low Voltage (PFO, RST,
RST, WDO
)
Output Low Voltage (RST)
Output High Voltage (RST, RST,
)
WDO
Output High Voltage (PFO
)
Output High Voltage (RST)
Test Condition
= V
V
CC
I
= 3.2mA
SINK
I
= 50µA, VCC = 1.0V,
SINK
T
= 0°C to 85°C
A
= 100µA, VCC = 1.2V
I
SINK
I
SOURCE
VCC = V
I
SOURCE
= V
V
CC
I
SOURCE
VCC = 1.1V,
TA = 0°C to 85°C
I
SOURCE
VCC = 1.2V
(max),
RST
= 1mA,
(max)
RST
= 75µA,
(max)
RST
= 4µA,
= 4µA,
(1)
Min Typ Max Unit
0.3 V
0.3 V
0.3 V
2.4 V
0.8V
CC
0.8 V
0.9 V
V
Power-fail Comparator
V
t
PFD
PFI
PFI Input Threshold
PFI to PFO Propagation Delay 2 µs
PFI Falling (V
CC
= 5V)
1.20 1.25 1.30 V
Reset Thresholds
V
RST
Reset Threshold
(3)
STM705/707/813L 4.50 4.65 4.75 V
STM706/708 4.25 4.40 4.50 V
Reset Threshold Hysteresis 25 mV
t
rec
RST Pulse Width 140 200 280 ms
Push-button Reset Input
t
MLMH
t
MLRLtMRD
t
MR
MR Pulse Width 150 ns
MR to RST Output Delay 250 ns
Watchdog Timer (STM705/706/813L)
t
WD
Watchdog Timeout Period
WDI Pulse Width
Note: 1. Valid for Am bie nt Oper ati ng Te mpe ratur e: TA = –40 to 85°C ; VCC = 4.75V to 5.5 V for STM705 /7 07/81 3L; VCC = 4.5V to 5.5V for
STM706/7 08 (except wher e noted).
(min) = 1.0V for TA = 0°C to +85°C.
2. V
CC
CC
falling.
3. For V
4.5V < V
4.5V < V
< 5.5V
CC
< 5.5V
CC
1.12 1.60 2.24 s
50 ns
22/27
STM705/706/707/708/813L
PACKAG E MECHANICAL
Figure 33. SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mech anical
h x 45˚
A2
A
C
B
e
ddd
D
8
E
H
1
Note: Drawing is not to scale.
LA1 α
SO-A
Table 7. SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanica l Data
Symb
Typ Min Max Typ Min Max
A – 1.35 1.75 – 0.053 0.069
mm inches
A1 – 0.10 0.25 – 0.004 0.010
B – 0.33 0.51 – 0.013 0.020
C – 0.19 0.25 – 0.007 0.010
D – 4.80 5.00 – 0.189 0.197
ddd– –0.10– –0.004
E – 3.80 4.00 – 0.150 0.157
e1.27– –0.050– –
H – 5.80 6.20 – 0.228 0.244
h – 0.25 0.50 – 0.010 0.020
L – 0.40 0.90 – 0.016 0.035
α –0°8°–0°8°
N8 8
23/27
STM705/706/707/708/813L
Figure 34. TSSOP8 – 8-lead, Thin Shrink Sma ll Outline, 3x3mm body size, Outline
D
8
1
CP
Note: Drawing is not to scale.
5
EE1
4
A1
A2A
eb
L
L1
TSSOP8BM
Table 8. TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Mechanical Data
Symb
Typ Min Max Typ Min Max
A – –1.10– –0.043
mm inches
c
α
A1 – 0.05 0.15 – 0.002 0.006
A2 0.85 0.75 0.95 0.034 0.030 0.037
b – 0.25 0.40 – 0.010 0.016
c – 0.13 0.23 – 0.005 0.009
CP – – 0.10 – – 0.004
D 3.00 2.90 3.10 0.118 0.114 0.122
e0.65– –0.026– –
E 4.90 4.65 5.15 0.193 0.183 0.203
E1 3.00 2.90 3.10 0.118 0.114 0.122
L 0.55 0.40 0.70 0.022 0.016 0.030
L1 0.95 – – 0.037 – –
α –0°6°–0°6°
N8 8
24/27
STM705/706/707/708/813L
PART NUMBERING
Table 9. Ordering Information Scheme
Example: STM705 M 6 E
Device Type and Reset Threshold Voltage
STM705/707/813L = V
STM706/708 = V
Package
M = SO8
DS = TSSOP8
Temperature Range
6 = –40 to 85°C
RST
= 4.50V to 4.75V
RST
= 4.25V to 4.50V
Shipping Method
E = Tubes
F = Tape & Reel
For other options, or for more information on any aspect of this device, please contact the ST Sales Office
nearest you.
Table 10. Marking Description
Part Number Reset Threshold Package Topside Marking
STM705 4.63V
STM706 4.38V
STM707 4.63V
STM708 4.38V
STM813L 4.63V
SO8
705
TSSOP8
SO8
706
TSSOP8
SO8
707
TSSOP8
SO8
708
TSSOP8
SO8
813L
TSSOP8
25/27
STM705/706/707/708/813L
REVISION HISTORY
Table 11. Document Revision History
Date Version Revision Details
September 2003 1.0 First Issue
31-Oct-03 1.1 Update DC Characteristics (Table 6)
12-Dec-03 2.0
16-Jan-04 2.1
09-Apr-04 3.0 Reformatted; update characteristics (Figure 15, 19, 22, 23, 24, 25, 28; Table 6)
25-May-04 4.0 Update characteristics (Table 3, 6)
02-Jul-04 5.0 Document promoted; corrected waveform (Figure 30)
21-Sep-04 6.0 Clarify root part numbers, pin descriptions (Figure 2, 3, 10; Table 5, 6, 9)
08-Mar-05 7.0
Reformatted; update characteristics (Figure 1, 2, 3, 4, 6, 8, 9, 10, 31, 32, 30; Table
6, 8, 10)
Add Typical Characteristics (Figure 13, 14, 15, 16, 17, 18, 19, 22, 23, 24, 25, 26,
27, 28)
Update Typical Characteristics (Figure 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
24, 25, 26, 27, 28)
26/27
STM705/706/707/708/813L
Information furnished is believed to be accurate and reliable. However, STMicroelectronics a ssumes no responsibility fo r the c onsequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authori zed for use as criti cal component s in life support devices or sys tems without express written approval of STMicroele ct ronics.
The ST logo is a registered trademark of STMi croelectronics.
All other nam es are the property of their r espective owners
© 2005 STMi croelectroni cs - All rights reserved
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27/27
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