STMicroelectronics STM690A, STM692A, STM703, STM704, STM802 Technical data

STM690A, STM692A, STM703 STM704, STM802, STM805, STM817/8/9

5V Supervisor with Battery Switchover

FEATURES SUMMARY

■5V OPERATING VOLTAGE

■NVRAM SUPERVISOR FOR EXTERNAL LPSRAM

■CHIP-ENABLE GATING (STM818 only) FOR EXTERNAL LPSRAM (7ns max PROP DELAY)

■RST AND RST OUTPUTS

■200ms (TYP) trec

■WATCHDOG TIMER - 1.6sec (TYP)

■AUTOMATIC BATTERY SWITCHOVER

■LOW BATTERY SUPPLY CURRENT - 0.4µA (TYP)

■POWER-FAIL COMPARATOR (PFI/PFO)

■LOW SUPPLY CURRENT - 40µA (TYP)

■GUARANTEED RST (RST) ASSERTION DOWN TO VCC = 1.0V

■OPERATING TEMPERATURE: –40°C to 85°C (Industrial Grade)

Table 1. Device Options

Figure 1. Packages

8

1

SO8 (M)

TSSOP8 3x3 (DS)*

		Watchdog	Active-			Active-	Manual	Battery	Power-fail	Chip-	Battery
				Low		High	Reset	Switch-		Enable	Freshness
		Input							Comparator
			RST(1)			RST(1)	Input	over		Gating	Seal
STM690A
STM692A
STM703
STM704
STM802L/M
STM805L
STM817L/M
STM818L/M
STM819L/M

Note: 1. All RST and RST outputs are push-pull.

* Contact local ST sales office for availability.

March 2005

1/37

STM690A/692A/703/704/802/805/817/818/819

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 1. Device Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 2. Logic Diagram (STM690A/692A/802/805/817) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. Logic Diagram (STM703/704/819). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 4. Logic Diagram (STM818). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 5. STM690A/692A/802/805/817 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 6. STM703/704/819 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 7. STM818 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 3. Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 8. Block Diagram (STM690A/692A/802/805/817) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 9. Block Diagram (STM703/704/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 10.Block Diagram (STM818) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 11.Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Reset Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Push-button Reset Input (STM703/704/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Watchdog Input (NOT available on STM703/704/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Back-up Battery Switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 4. I/O Status in Battery Back-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Chip-Enable Gating (STM818 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Chip Enable Input (STM818 only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Chip Enable Output (STM818 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 12.Chip-Enable Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 13.Chip Enable Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Power-fail Input/Output (NOT available on STM818) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 14.Power-fail Comparator Waveform (STM817/818/819) . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 15.Power-fail Comparator Waveform (STM690A/692A/703/704/802/805) . . . . . . . . . . . . . 13

Using a SuperCap™ as a Backup Power Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Negative-Going VCC Transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Battery Freshness Seal (STM817/818/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 16.Using a SuperCap™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 17.Freshness Seal Enable Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

TYPICAL OPERATING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 18.VCC-to-VOUT On-Resistance vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
Figure 19.VBAT-to-VOUT On-Resistance vs. Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15

2/37

STM690A/692A/703/704/802/805/817/818/819

Figure 20.Supply Current vs. Temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 21.Battery Current vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 22.VPFI Threshold vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 23.Reset Comparator Propagation Delay vs. Temperature (Other than STM817/818/819) 17 Figure 24.Reset Comparator Propagation Delay vs. Temperature (VBAT=3.0V; STM817/818/819)18 Figure 25.Power-up trec vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 26.Normalized Reset Threshold vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 27.Watchdog Time-out Period vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 28.E to ECON On-Resistance vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 29.PFI to PFO Propagation Delay vs. Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 30.Output Voltage vs. Load Current (VCC = 5V; VBAT = 2.8V; TA = 25°C). . . . . . . . . . . . . . 21 Figure 31.Output Voltage vs. Load Current (VCC = 0V; VBAT = 2.8V; TA = 25°C). . . . . . . . . . . . . . 21

Figure 32.RST Output Voltage vs. Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 33.RST Output Voltage vs. Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 34.RST Response Time (Assertion). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 35.RST Response Time (Assertion). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 36.Power-fail Comparator Response Time (Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 37.Power-fail Comparator Response Time (De-Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 38.Maximum Transient Duration vs. Reset Threshold Overdrive. . . . . . . . . . . . . . . . . . . . . 25 Figure 39.E to ECON Propagation Delay vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 5. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 6. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 40.E to ECON Propagation Delay Test Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 41.AC Testing Input/Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 42.MR Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 43.Watchdog Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 7. DC and AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 44.SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mech. Drawing. . . . 32 Table 8. SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical Data . . 32 Figure 45.TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Outline . . . . . . . . . . . 33 Table 9. TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Mechanical Data . . . . 33

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 10. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 11. Marking Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 12. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3/37

STM690A/692A/703/704/802/805/817/818/819

SUMMARY DESCRIPTION

The STM690A/692A/703/704/802/805/817/818/ 819 Supervisors are self-contained devices which provide microprocessor supervisory functions with the ability to non-volatize and write-protect external LPSRAM. A precision voltage reference and comparator monitors the VCC input for an out-of- tolerance condition. When an invalid VCC condition occurs, the reset output (RST) is forced low (or high in the case of RST). These devices also

offer a watchdog timer (except for STM703/704/ 819) as well as a power-fail comparator (except for STM818) to provide the system with an early warning of impending power failure.

These devices are available in a standard 8-pin SOIC package or a space-saving 8-pin TSSOP package.

Figure 2. Logic Diagram (STM690A/692A/802/ 805/817)

		VCC VBAT
	WDI			VOUT
		STM690A/
		692A/802/			RST(RST)(1)
	PFI	805/817
				PFO

VSS

AI07894

Note: 1. For STM805, reset output is active-high.

Figure 3. Logic Diagram (STM703/704/819)

VCC VBAT

VOUT

MR

STM703/

704/819

PFI

RST

PFO

VSS

AI07895

4/37

Figure 4. Logic Diagram (STM818)

VCC VBAT

WDI

VOUT

STM818

RST

E

ECON

VSS

AI07896

Table 2. Signal Names

Push-button Reset Input

MR

WDI

Watchdog Input

Active-Low Reset Output

RST

RST

Active-High Reset Output

(1)

Chip Enable Input

E

CON(1)

Conditioned Chip Enable Output

E

VOUT

Supply Voltage Output

VCC

Supply Voltage

VBAT

Back-up Supply Voltage

PFI

Power-fail Input

Power-fail Output

PFO

VSS

Ground

Note: 1. STM818

STM690A/692A/703/704/802/805/817/818/819

Figure 5. STM690A/692A/802/805/817

Connections

SO8/TSSOP8

VOUT	1	8		VBAT
VCC	2	7		RST(RST)(1)
VSS	3	6		WDI
PFI	4	5		PFO
			AI07889

Note: 1. For STM805, reset output is active-high.

Figure 6. STM703/704/819 Connections

SO8/TSSOP8

VOUT	1	8		VBAT
VCC	2	7		RST
VSS
	3	6		MR
PFI	4	5		PFO
			AI07890

Figure 7. STM818 Connections

SO8/TSSOP8

VOUT			1	8		VBAT
VCC			2	7
						RST
VSS			3	6		WDI
	E		4	5		E	CON
					AI07892

5/37

STM690A/692A/703/704/802/805/817/818/819

Pin Descriptions

MR. A logic low on /MR asserts the reset output. Reset remains asserted as long as MR is low and for trec after MR returns high. This active-low input has an internal pull-up. It can be driven from a TTL or CMOS logic line, or shorted to ground with a switch. Leave open if unused.

WDI. If WDI remains high or low for 1.6sec, the internal watchdog timer runs out and reset is triggered. The internal watchdog timer clears while reset is asserted or when WDI sees a rising or falling edge.

The watchdog function can be disabled by allowing the WDI pin to float.

RST. Pulses low for trec when triggered, and stays low whenever VCC is below the reset threshold or

when MR is a logic low. It remains low for trec after either VCC rises above the reset threshold, the

watchdog triggers a reset, or MR goes from low to high.

RST. Pulses high for trec when triggered, and stays high whenever VCC is above the reset threshold or when MR is a logic high. It remains

high for trec after either VCC falls below the reset threshold, the watchdog triggers a reset, or MR

goes from high to low.

Table 3. Pin Description

VOUT. When VCC is above the switchover voltage

(VSO), VOUT is connected to VCC through a P- channel MOSFET switch. When VCC falls below

VSO, VBAT connects to VOUT. Connect to VCC if no battery is used.

VBAT. When VCC falls below VSO, VOUT switches

from VCC to VBAT. When VCC rises above VSO + hysteresis, VOUT reconnects to VCC. VBAT may exceed VCC. Connect to VCC if no battery is used.

E. The input to the chip-enable gating circuit. Connect to ground if unused.

ECON. ECON goes low only when E is low and reset is not asserted. If ECON is low when reset is as- serted, ECON will remain low for 15µs or until E

goes high, whichever occurs first. In the disabled mode, ECON is pulled up to VOUT.

PFI. When PFI is less than VPFI or when VCC falls below 2.4V (or VSO), PFO goes low; otherwise,

PFO remains high. Connect to ground if unused.

PFO. When PFI is less than VPFI, or VCC falls be- low 2.4V (or VSO), PFO goes low; otherwise, PFO

remains high. Leave open if unused.

Pin

Name

Function

STM690A

STM703

STM818

STM692A

STM704

STM805

STM802

STM819

STM817

–

–

6

–

MR

Push-button Reset Input

6

6

–

6

WDI

Watchdog Input

7

7

7

–

RST

Active-Low Reset Output

–

–

–

7

RST

Active-High Reset Output

1

1

1

1

VOUT

Supply Output for External LPSRAM

2

2

2

2

VCC

Supply Voltage

8

8

8

8

VBAT

Backup-Battery Input

4

–

–

–

E

Chip Enable Input

5

–

–

–

E

CON

Conditioned Chip Enable Output

–

4

4

4

PFI

PFI Power-fail Input

–

5

5

5

PFO

PFO

Power-fail Output

3

3

3

3

VSS

Ground

6/37

STM690A/692A/703/704/802/805/817/818/819

Figure 8. Block Diagram (STM690A/692A/802/805/817)

VCC			VOUT
VBAT
VSO	COMPARE
VRST	COMPARE
WDI	WATCHDOG	trec	RST(RST)	(1)
	TIMER	Generator
PFI	COMPARE
VPFI			PFO
			AI07897

Note: 1. For STM805, reset output is active-high.

Figure 9. Block Diagram (STM703/704/819)

VCC		VOUT
VBAT
VSO	COMPARE
VRST	COMPARE
MR	trec	RST
	Generator
PFI	COMPARE
VPFI		PFO
		AI07898

7/37

STM690A/692A/703/704/802/805/817/818/819

Figure 10. Block Diagram (STM818)

VCC			VOUT
VBAT
VSO	COMPARE
VRST	COMPARE
WDI	WATCHDOG	trec	RST
	TIMER	Generator
	ECON OUTPUT
	CONTROL
E			ECON
			AI07899a

Figure 11. Hardware Hookup

Unregulated	Regulator
	VIN	VCC	VCC		VOUT	VCC
Voltage
						VCC
			STM690A/692A/			LPSRAM
			703/704/802/805/
		0.1 F
			817/818/819			E
						E
						0.1 F
			WDI(1)
	From Microprocessor
			E(2)	E	(2)
	R1				CON
			PFI(3)	PFO(3)		To Microprocessor NMI
	R2
		Push-Button	MR(4)		RST	To Microprocessor Reset
			VBAT
						AI07893

Note: 1. For STM690A/692A/802/805/817/818.

2.For STM818 only.

3.Not available on STM818.

4.For STM703/704/819.

8/37

STM690A/692A/703/704/802/805/817/818/819

OPERATION

Reset Output

The STM690A/692A/703/704/802/805/817/818/ 819 Supervisor asserts a reset signal to the MCU whenever VCC goes below the reset threshold

(VRST), a watchdog time-out occurs, or when the Push-button Reset Input (MR) is taken low. RST is

guaranteed to be a logic low (logic high for

STM805) for 0V < VCC < VRST if VBAT is greater than 1V. Without a back-up battery, RST is guar-

anteed valid down to VCC =1V.

During power-up, once VCC exceeds the reset threshold an internal timer keeps RST low for the reset time-out period, trec. After this interval RST returns high.

If VCC drops below the reset threshold, RST goes low. Each time RST is asserted, it stays low for at

least the reset time-out period (trec). Any time VCC goes below the reset threshold the internal timer

clears. The reset timer starts when VCC returns above the reset threshold.

Push-button Reset Input (STM703/704/819)

A logic low on MR asserts reset. Reset remains

asserted while MR is low, and for trec (see Figure 42., page 28) after it returns high. The MR input

has an internal 40kΩ pull-up resistor, allowing it to be left open if not used. This input can be driven with TTL/CMOS-logic levels or with open-drain/ collector outputs. Connect a normally open momentary switch from MR to GND to create a manual reset function; external debounce circuitry is

not required. If MR is driven from long cables or the device is used in a noisy environment, connect a 0.1µF capacitor from MR to GND to provide additional noise immunity. MR may float, or be tied to VCC when not used.

Watchdog Input (NOT available on STM703/ 704/819)

The watchdog timer can be used to detect an out- of-control MCU. If the MCU does not toggle the Watchdog Input (WDI) within tWD (1.6sec typ), the reset is asserted. The internal watchdog timer is cleared by either:

1.a reset pulse, or

2.by toggling WDI (high-to-low or low-to-high), which can detect pulses as short as 50ns. If WDI is tied high or low, a reset pulse is triggered every 1.8sec (tWD + trec).

The timer remains cleared and does not count for as long as reset is asserted. As soon as reset is released, the timer starts counting (see Figure 43., page 28).

Note: The watchdog function may be disabled by floating WDI or tri-stating the driver connected to WDI. When tri-stated or disconnected, the maximum allowable leakage current is 10uA and the maximum allowable load capacitance is 200pF.

Note: Input frequency greater than 20ns (50MHz) will be filtered.

9/37

STM690A/692A/703/704/802/805/817/818/819

Back-up Battery Switchover

In the event of a power failure, it may be necessary to preserve the contents of external SRAM through VOUT. With a backup battery installed with voltage VBAT, the devices automatically switch the SRAM to the back-up supply when VCC falls.

Note: If back-up battery is not used, connect both VBAT and VOUT to VCC.

This family of Supervisors does not always con-

nect VBAT to VOUT when VBAT is greater than VCC. VBAT connects to VOUT (through a 100Ω switch) when VCC is below VRST and VBAT. This is done to allow the back-up battery (e.g., a 3.6V lithium cell)

to have a higher voltage than VCC.

Assuming VBAT > 2.0V, switchover at VSO ensures that battery back-up mode is entered before VOUT gets too close to the 2.0V minimum required to reliably retain data in most external SRAMs. When VCC recovers, hysteresis is used to avoid oscillation around the VSO point. VOUT is connected to VCC through a 3Ω PMOS power switch.

Note: The back-up battery may be removed while VCC is valid, assuming VBAT is adequately decoupled (0.1µF typ), without danger of triggering a reset.

Table 4. I/O Status in Battery Back-up

Pin

Status

VOUT

Connected to VBAT through internal switch

VCC

Disconnected from VOUT

PFI

Disabled

Logic low

PFO

High impedance

E

CON

Logic high

E

WDI

Watchdog timer is disabled

Logic low

WDO

Disabled

MR

Logic low

RST

RST

Logic high

VBAT

Connected to VOUT

10/37

Chip-Enable Gating (STM818 only)

Internal gating of the chip enable (E) signal prevents erroneous data from corrupting the external CMOS RAM in the event of an undervoltage condition. The STM818 uses a series transmission gate from E to ECON (see Figure 12., page 11). During normal operation (reset not asserted), the E transmission gate is enabled and passes all E transitions. When reset is asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS RAM. The short E propagation delay from E to ECON enables the STM818 to be used with most µPs. If E is low when reset asserts, ECON remains low for typically 15µs to per- mit the current WRITE cycle to complete. Connect E to VSS if unused.

Chip Enable Input (STM818 only)

The chip-enable transmission gate is disabled and E is high impedance (disabled mode) while reset is asserted. During a power-down sequence when VCC passes the reset threshold, the chip-enable transmission gate disables and E immediately becomes high impedance if the voltage at E is high. If E is low when reset asserts, the chip-enable transmission gate will disable 15µs after reset asserts (see Figure 13., page 11). This permits the current WRITE cycle to complete during powerdown.

Any time a reset is generated, the chip-enable transmission gate remains disabled and E remains high impedance (regardless of E activity) for the reset time-out period. When the chip enable transmission gate is enabled, the impedance of E ap- pears as a 40Ω resistor in series with the load at ECON. The propagation delay through the chip-en- able transmission gate depends on VCC, the source impedance of the drive connected to E,

and the loading on ECON. The chip enable propagation delay is production tested from the 50%

point on E to the 50% point on ECON using a 50Ω driver and a 50pF load capacitance (see Figure

40., page 28). For minimum propagation delay, minimize the capacitive load at ECON and use a low-output impedance driver.

Chip Enable Output (STM818 only)

When the chip-enable transmission gate is enabled, the impedance of ECON is equivalent to a 40Ω resistor in series with the source driving E. In the disabled mode, the transmission gate is off

and an active pull-up connects ECON to VOUT (see Figure 12., page 11). This pull-up turns off when

the transmission gate is enabled.

STM690A/692A/703/704/802/805/817/818/819

Figure 12. Chip-Enable Gating

	VCC	trec	RST
	COMPARE
		Generator
	VRST
			VOUT
	ECON OUTPUT
	CONTROL
	E		ECON
	AI08802

Figure 13. Chip Enable Waveform

VCC	VRST
ECON	VBAT
RST	trec	15µs	trec
E
			AI08803b

11/37

STM690A/692A/703/704/802/805/817/818/819

Power-fail Input/Output (NOT available on STM818)

The Power-fail Input (PFI) is compared to an internal reference voltage (independent from the VRST comparator). If PFI is less than the power-fail threshold (VPFI), the Power-Fail Output (PFO) will go low. This function is intended for use as an undervoltage detector to signal a failing power supply. Typically PFI is connected through an external voltage divider (see Figure 11., page 8) to either the unregulated DC input (if it is available) or the regulated output of the VCC regulator. The voltage divider can be set up such that the voltage at PFI falls below VPFI several milliseconds before the regulated VCC input to the STM690A/692A/703/ 704/802/805/817/818/819 Supervisor or the microprocessor drops below the minimum operating voltage.

During battery back-up, the power-fail comparator turns off and PFO goes (or remains) low (see Figure 14 and Figure 15., page 13). This occurs after VCC drops below 2.4V (or VSO). When power returns, PFO is forced high (STM817/819 only), irre-

spective of VPFI for the WRITE protect time (trec). At the end of this time, the power-fail comparator

is enabled and PFO follows PFI. If the comparator is unused, PFI should be connected to VSS and PFO left unconnected. PFO may be connected to MR on the STM703/704/818 so that a low voltage on PFI will generate a reset output.

Applications Information

These Supervisor circuits are not short-circuit protected. Shorting VOUT to ground - excluding pow- er-up transients such as charging a decoupling capacitor - destroys the device. Decouple both

VCC and VBAT pins to ground by placing 0.1µF capacitors as close to the device as possible.

Figure 14. Power-fail Comparator Waveform (STM817/818/819)

VCC
VRST
VSO (or 2.4V)
	trec
PFO
(STM817/819)
PFO follows PFI	PFO follows PFI
	RST to ECON Delay (STM818)
RST
ECON (STM818)
	AI08804a

12/37