STMicroelectronics STM32WLE5C8, STM32WLE5CB, STM32WLE5CC, STM32WLE5J8, STM32WLE5JB Datasheet

STM32WLE5xx STM32WLE4xx

Errata sheet

STM32WLE5xx, STM32WLE4xx device errata

Applicability

This document applies to the part numbers of STM32WLE5xx, STM32WLE4xx devices and the device variants as stated in this page.

It gives a summary and a description of the device errata, with respect to the device datasheet and reference manual RM0461.

Deviation of the real device behavior from the intended device behavior is considered to be a device limitation. Deviation of the description in the reference manual or the datasheet from the intended device behavior is considered to be a documentation erratum. The term “errata” applies both to limitations and documentation errata.

		Table 1. Device summary
	Reference	Part numbers
	STM32WLE5xx	STM32WLE5C8, STM32WLE5CB, STM32WLE5CC, STM32WLE5J8, STM32WLE5JB, STM32WLE5JC,
		STM32WLE5U8, STM32WLE5UB, STM32WLE5UC
	STM32WLE4xx	STM32WLE4C8, STM32WLE4CB, STM32WLE4CC, STM32WLE4J8, STM32WLE4JB, STM32WLE4JC,
		STM32WLE4U8, STM32WLE4UB, STM32WLE4UC

Table 2. Device variants

Reference		Silicon revision codes
	Device marking(1)		REV_ID(2)
STM32WLE5xx, STM32WLE4xx	Z		0x1001
	Y		0x1002

1.Refer to the device datasheet for how to identify this code on different types of package.

2.REV_ID[15:0] bitfield of DBGMCU_IDCODER register.

ES0506 - Rev 2 - April 2021	www.st.com
For further information contact your local STMicroelectronics sales office.

STM32WLE5xx STM32WLE4xx

Summary of device errata

1Summary of device errata

The following table gives a quick reference to the STM32WLE5xx, STM32WLE4xx device limitations and their status:

A = workaround available

N = no workaround available

P = partial workaround available

Applicability of a workaround may depend on specific conditions of target application. Adoption of a workaround may cause restrictions to target application. Workaround for a limitation is deemed partial if it only reduces the rate of occurrence and/or consequences of the limitation, or if it is fully effective for only a subset of instances on the device or in only a subset of operating modes, of the function concerned.

Table 3. Summary of device limitations

				Status
	Function	Section	Limitation	Rev.	Rev.
				Z	Y
		2.1.1	Interrupted loads to SP can cause erroneous behavior	A	A
	Core
		2.1.2	Store immediate overlapping exception return operation might vector to	A	A
			incorrect interrupt
		2.2.1	Wrong DMAMUX synchronization and trigger input connections to EXTI	A	-
		2.2.2	Overwriting with all zeros a Flash memory location previously	N	N
			programmed with all ones fails
		2.2.3	Option byte loading failure at high MSI system clock frequency	A	-
		2.2.4	A system reset occurs when nRST_SHDW is set and nRST_STDBY is	A	-
			cleared and Shutdown mode is entered
		2.2.5	FLASH_ECCR corrupted upon reset or power-down occurring during	A	A
			Flash memory program or erase operation
	System	2.2.6	Voltage drop on the 1.2 V regulated supply when switching MSI to 48 MHz	A	A
		2.2.7	Sensitivity affected by HSE activation in high bandwidth channel	A	-
		2.2.8	Sensitivity degradation in LNA boosted mode	A	A
		2.2.9	SysTick trigger in debug emulation generates HardFault	A	A
		2.2.10	Debug HALT command in debug emulation generates HardFault	A	-
		2.2.11	Potential deadlock condition on wakeup from a lower-power mode	A	-
		2.2.12	JTAG cannot be used without the JTAG NRST pin	N	-
		2.2.13	Flash PCROP is not operating properly	N	-
		2.2.14	TX spurs around carrier at a multiple of HSE clock frequency	A	A
		2.3.1	One-pulse mode trigger not detected in master-slave reset + trigger	P	P
			configuration
	TIM
		2.3.2	Consecutive compare event missed in specific conditions	N	N
		2.3.3	Output compare clear not working with external counter reset	P	P
		2.4.1	Device may remain stuck in LPTIM interrupt when entering Stop mode	A	A
	LPTIM	2.4.2	ARRM and CMPM flags are not set when APB clock is slower than kernel	P	P
			clock
		2.4.3	Device may remain stuck in LPTIM interrupt when clearing event flag	P	P
	RTC and TAMP	2.5.1	Alarm flag may be repeatedly set when the core is stopped in debug	N	N

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STM32WLE5xx STM32WLE4xx

Summary of device errata

			Status
Function	Section	Limitation	Rev.	Rev.
			Z	Y
	2.5.2	A tamper event fails to trigger timestamp or timestamp overflow events	N	N
		during a few cycles after clearing TSF
RTC and TAMP	2.5.3	REFCKON write protection associated to INIT KEY instead of CAL KEY	A	A
	2.5.4	Tamper flag not set on LSE failure detection	N	N
	2.5.5	Binary mode: SSR is not reloaded with 0xFFFF FFFF when SSCLR = 1	A	A
	2.6.1	Wrong data sampling when data setup time (tSU;DAT) is shorter than one	P	P
		I2C kernel clock period
I2C	2.6.2	Spurious bus error detection in master mode	A	A
	2.6.3	OVR flag not set in underrun condition	N	N
	2.6.4	Transmission stalled after first byte transfer	A	A
	2.7.1	Anticipated end-of-transmission signaling in SPI slave mode	A	A
USART	2.7.2	Data corruption due to noisy receive line	N	N
	2.7.3	DMA stream locked when transferring data to/from USART	A	A

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STM32WLE5xx STM32WLE4xx

Description of device errata

2Description of device errata

	The following sections describe limitations of the applicable devices with Arm® core and provide workarounds if
	available. They are grouped by device functions.
Note:	Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

2.1Core

Reference manual and errata notice for the Arm® Cortex®-M4 FPU core revision r0p1 is available from http:// infocenter.arm.com.

2.1.1Interrupted loads to SP can cause erroneous behavior

This limitation is registered under Arm ID number 752770 and classified into “Category B”. Its impact to the device is minor.

Description

If an interrupt occurs during the data-phase of a single word load to the stack-pointer (SP/R13), erroneous behavior can occur. In all cases, returning from the interrupt will result in the load instruction being executed an additional time. For all instructions performing an update to the base register, the base register will be erroneously updated on each execution, resulting in the stack-pointer being loaded from an incorrect memory location.

The affected instructions that can result in the load transaction being repeated are:

•LDR SP, [Rn],#imm

•LDR SP, [Rn,#imm]!

•LDR SP, [Rn,#imm]

•LDR SP, [Rn]

•LDR SP, [Rn,Rm]

The affected instructions that can result in the stack-pointer being loaded from an incorrect memory address are:

•LDR SP,[Rn],#imm

•LDR SP,[Rn,#imm]!

As compilers do not generate these particular instructions, the limitation is only likely to occur with hand-written assembly code.

Workaround

Both issues may be worked around by replacing the direct load to the stack-pointer, with an intermediate load to a general-purpose register followed by a move to the stack-pointer.

2.1.2Store immediate overlapping exception return operation might vector to incorrect interrupt

This limitation is registered under Arm ID number 838869 and classified into “Category B (rare)”. Its impact to the device is minor.

Description

The core includes a write buffer that permits execution to continue while a store is waiting on the bus. Under specific timing conditions, during an exception return while this buffer is still in use by a store instruction, a late change in selection of the next interrupt to be taken might result in there being a mismatch between the interrupt acknowledged by the interrupt controller and the vector fetched by the processor.

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STM32WLE5xx STM32WLE4xx

System

The failure occurs when the following condition is met:

1.The handler for interrupt A is being executed.

2.Interrupt B, of the same or lower priority than interrupt A, is pending.

3.A store with immediate offset instruction is executed to a bufferable location.

–STR/STRH/STRB <Rt>, [<Rn>,#imm]

–STR/STRH/STRB <Rt>, [<Rn>,#imm]!

–STR/STRH/STRB <Rt>, [<Rn>],#imm

4.Any number of additional data-processing instructions can be executed.

5.A BX instruction is executed that causes an exception return.

6.The store data has wait states applied to it such that the data is accepted at least two cycles after the BX is executed.

–Minimally, this is two cycles if the store and the BX instruction have no additional instructions between them.

–The number of wait states required to observe this erratum needs to be increased by the number of cycles between the store and the interrupt service routine exit instruction.

7.Before the bus accepts the buffered store data, another interrupt C is asserted which has the same or lower priority as A, but a greater priority than B.

Example:

The processor should execute interrupt handler C, and on completion of handler C should execute the handler for B. If the conditions above are met, then this erratum results in the processor erroneously clearing the pending state of interrupt C, and then executing the handler for B twice. The first time the handler for B is executed it

will be at interrupt C's priority level. If interrupt C is pended by a level-based interrupt which is cleared by C's handler then interrupt C will be pended again once the handler for B has completed and the handler for C will be executed.

As the STM32 interrupt C is level based, it eventually becomes pending again and is subsequently handled.

Workaround

For software not using the memory protection unit, this erratum can be worked around by setting DISDEFWBUF in the Auxiliary Control Register.

In all other cases, the erratum can be avoided by ensuring a DSB occurs between the store and the BX instruction. For exception handlers written in C, this can be achieved by inserting the appropriate set of intrinsics or inline assembly just before the end of the interrupt function, for example:

ARMCC:

...

__schedule_barrier(); __asm{DSB}; __schedule_barrier();

}

GCC:

...

__asm volatile ("dsb 0xf":::"memory");

}

2.2System

2.2.1Wrong DMAMUX synchronization and trigger input connections to EXTI

Description

By error, synchronization and trigger inputs of the DMAMUX peripheral are connected to interrupt output lines of the EXTI block, instead of being connected to its SYSCFG multiplexer output lines.

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STM32WLE5xx STM32WLE4xx

System

The EXTI interrupt lines exhibit a rising-edge transition upon each active transition (rising, falling or both) of corresponding GPIOs, as defined in the EXTI_RTSRx and EXTI_FTSRx registers.

As a consequence, the falling active edge option of the DMAMUX synchronization and trigger inputs is unusable because falling edges on these inputs do not occur upon GPIO events but upon clearing the EXTI interrupt pending flags (by setting the corresponding PIF bits of the EXTI_PRx register).

Workaround

For the DMAMUX synchronization and trigger events to occur upon determined rising or/and falling edge of the corresponding GPIOs:

•Set the desired active edge polarities of the corresponding GPIOs through the EXTI_RTSRx and EXTI_FTSRx registers.

•Set the active edge polarity to rising for all corresponding DMAMUX input lines, through the SPOL bits of the DMAMUX_CxCR register (for synchronization inputs) and the GPOL bits of the DMAMUX_RGxCR register (for trigger inputs).

•Ensure that EXTI interrupt pending flags corresponding to the GPIOs used for DMAMUX inputs are cleared in the EXTI interrupt service routine.

Note:

This can be ensured if using the HAL_GPIO_IrqHandler function provided by STMicroelectronics.

2.2.2Overwriting with all zeros a Flash memory location previously programmed with all ones fails

Description

Any attempt to re-program with all zeros (0x0000 0000 0000 0000) a Flash memory location previously programmed with 0xFFFF FFFF FFFF FFFF fails and the PROGERR flag of the FLASH_SR register is set.

Workaround

None.

2.2.3Option byte loading failure at high MSI system clock frequency

Description

The option bytes are not loaded correctly upon setting the OBL_LAUNCH bit of the FLASH_CR register when the frequency of MSI oscillator used as system clock source is higher than 16 MHz.

Workaround

Before loading the option bytes by setting the OBL_LAUNCH bit of the FLASH_CR register, either change the system clock source to other than MSI oscillator, or set the MSI clock frequency to less than 16 MHz.

2.2.4A system reset occurs when nRST_SHDW is set and nRST_STDBY is cleared and Shutdown mode is entered

Description

When the following configuration is selected:

•nRST_SHDW is set

•nRST_STDBY is cleared,

a system reset is generated when Shutdown mode is entered.

Workaround

The only valid configuration to avoid a reset after entering into Shutdown mode is the following:

•nRST_SHDW is set

•nRST_STDBY is set.

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