ST MICROELECTRONICS STM32WL55CCU6 Datasheet

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Page 1

STM32WL55xx STM32WL54xx

UFQFPN48 (7 x 7 mm)

UFBGA73 (5 x 5 mm)

WLCSP59

Multiprotocol LPWAN dual core 32-bit Arm® Cortex®-M4/M0+

LoRa

Features

Radio

• Frequency range: 150 MHz to 960 MHz

• Modulation: LoRa

BPSK

• RX sensitivity: (at 1.2 Kbit/s), (at 10.4 kHz, spreading factor 12)

• Transmitter high output power, programmable up to +22 dBm

• Transmitter low output power, programmable up to +15 dBm

• Compliant with the following radio frequency regulations such as ETSI EN 300 220, EN 300 113, EN 301 166, FCC CFR 47 Part 15, 24, 90, 101 and the Japanese ARIB STD-T30, T-67, T-108

• Compatible with standardized or proprietary protocols such as LoRaWAN W-MBus and more (fully open wireless system-on-chip)

Ultra-low-power platform

• 1.8 V to 3.6 V power supply

•

–40 °C to +105 °C temperature range

• Shutdown mode: 31 nA (V

• Standby (+ RTC) mode:

360 nA (V

• Stop2 (+ RTC) mode: 1.07 µA (V

• Active-mode MCU: < 72 µA/MHz (CoreMark

• Active-mode RX: 4.82 mA

• Active-mode TX: 15 mA at 10 dBm and 87 mA

at 20 dBm (LoRa

Core

• 32-bit Arm® Cortex®-M4 CPU

, (G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM

, (G)FSK, (G)MSK and

–123 dBm for 2-FSK –148 dBm for LoRa

= 3 V)

125 kHz)

, Sigfox™,

= 3 V)

Datasheet - production data

– Adaptive real-time accelerator (ART

Accelerator) allowing 0-wait-state execution from Flash memory, frequency up to 48 MHz, MPU and DSP instructions

– 1.25 DMIPS/MHz (Dhrystone 2.1)

• 32-bit Arm

Cortex®-M0+ CPU

– Frequency up to 48 MHz, MPU – 0.95 DMIPS/MHz (Dhrystone 2.1)

Security and identification

• Hardware encryption AES 256-bit

• True random number generator (RNG)

• Sector protection against read/write operations

(PCROP, RDP, WRP)

• CRC calculation unit

• Unique device identifier (64-bit UID compliant

with IEEE 802-2001 standard)

• 96-bit unique die identifier

• Hardware public key accelerator (PKA)

• Key management services

• Secure sub-GHz MAC layer

• Secure firmware update (SFU)

• Secure firmware install (SFI)

)

Supply and reset management

• High-efficiency embedded SMPS step-down converter

• SMPS to LDO smart switch

• Ultra-safe, low-power BOR (brownout reset)

with 5 selectable thresholds

• Ultra-low-power POR/PDR

November 2020 DS13293 Rev 1 1/145

This is information on a product in full production.

www.st.com

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STM32WL55/54xx

• Programmable voltage detector (PVD)

• V

mode with RTC and 20x32-byte backup

BAT

registers

Clock sources

• 32 MHz crystal oscillator

• TCXO support: programmable supply voltage

• 32 kHz oscillator for RTC with calibration

• High-speed internal 16 MHz factory trimmed

RC (± 1 %)

• Internal low-power 32 kHz RC

• Internal multi-speed low-power 100 kHz to

48 MHz RC

• PLL for CPU, ADC and audio clocks

Memories

• 256-Kbyte Flash memory

• 64-Kbyte RAM

• 20x32-bit backup register

• Bootloader supporting USART and SPI

interfaces

• OTA (over-the-air) firmware update capable

• Sector protection against read/write operations

System peripherals

• Mailbox and semaphores for communication between Cortex firmware

-M4 and Cortex®-M0+

Controllers

• 2x DMA controller (7 channels each) supporting ADC, DAC, SPI, I2C, LPUART, USART, AES and timers

• 2x USART (ISO 7816, IrDA, SPI)

• 1x LPUART (low-power)

• 2x SPI 16 Mbit/s (1 over 2 supporting I2S)

• 3x I2C (SMBus/PMBus™)

• 2x 16-bit 1-channel timer

• 1x 16-bit 4-channel timer (supporting

motor control)

• 1x 32-bit 4-channel timer

• 3x 16-bit ultra-low-power timer

• 1x RTC with 32-bit sub-second wakeup

counter

• 1x independent SysTick

• 1x independent watchdog

• 1x window watchdog

Rich analog peripherals (down to 1.62 V)

• 12-bit ADC 2.5 Msps, up to 16 bits with hardware oversampling, conversion range up to 3.6 V

• 12-bit DAC, low-power sample-and-hold

• 2x ultra-low-power comparators

Table 1. Device summary

Reference Part number

STM32WL55xx STM32WL55CC, STM32WL55JC, STM32WL55UC

STM32WL54xx STM32WL54CC, STM32WL54JC, STM32WL54UC

Up to 43 I/Os, most 5 V-tolerant

Development support

• Serial-wire debug (SWD), JTAG

• Dual CPU cross trigger capabilities

All packages ECOPACK2 compliant

2/145 DS13293 Rev 1

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STM32WL55/54xx Contents

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.2 Arm Cortex-M cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.3 Adaptive real-time memory accelerator (ART Accelerator) . . . . . . . . . . . 15

3.4 Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.5 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.5.1 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.5.2 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.6 Security memory management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.7 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.8 Global security controller (GTZC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.9 Sub-GHz radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.9.2 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.9.3 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.9.4 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.9.5 RF-PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.9.6 Intermediate frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.10 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.10.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.10.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.10.3 Linear voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.10.4 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.11 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.11.1 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.12 Peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.13 Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.14 Hardware semaphore (HSEM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.15 Inter-processor communication controller (IPCC) . . . . . . . . . . . . . . . . . . 38

DS13293 Rev 1 3/145

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Contents STM32WL55/54xx

3.16 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.17 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.18 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.18.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 39

3.18.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 39

3.19 Cyclic redundancy check (CRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.20 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.20.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.20.2 Internal voltage reference (V

3.20.3 V

battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

BAT

) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

REFINT

3.21 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.22 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.23 Comparator (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.24 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.25 Advanced encryption standard hardware accelerator (AES) . . . . . . . . . . 42

3.26 Public key accelerator (PKA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.27 Timer and watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.27.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.27.2 General-purpose timers (TIM2, TIM16, TIM17) . . . . . . . . . . . . . . . . . . . 43

3.27.3 Low-power timers (LPTIM1, LPTIM2 and LPTIM3) . . . . . . . . . . . . . . . . 44

3.27.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.27.5 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.27.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.28 Real-time clock (RTC), tamper and backup registers . . . . . . . . . . . . . . . 45

3.29 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.30 Universal synchronous/asynchronous receiver transmitter

(USART/UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.31 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 47

3.32 Serial peripheral interface (SPI)/integrated-interchip sound

interface (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.33 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4 Pinouts, pin description and alternate functions . . . . . . . . . . . . . . . . . 49

5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

4/145 DS13293 Rev 1

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STM32WL55/54xx Contents

5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.3.1 Main performances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.3.2 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.3.3 Sub-GHz radio characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.3.4 Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . 74

5.3.5 Embedded reset and power-control block characteristics . . . . . . . . . . . 75

5.3.6 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

5.3.7 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

5.3.8 Wakeup time from low-power modes and voltage scaling

transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

5.3.9 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

5.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 100

5.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

5.3.12 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

5.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

5.3.14 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

5.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

5.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

5.3.17 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

5.3.18 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

5.3.19 Analog-to-digital converter characteristics . . . . . . . . . . . . . . . . . . . . . . 116

5.3.20 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

5.3.21 V

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

BAT

5.3.22 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 122

5.3.23 Digital-to-analog converter characteristics . . . . . . . . . . . . . . . . . . . . . . 124

5.3.24 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

5.3.25 Timers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

5.3.26 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 130

DS13293 Rev 1 5/145

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Contents STM32WL55/54xx

6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

6.1 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

6.2 WLCSP59 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

6.3 UFBGA73 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

6.4 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

6/145 DS13293 Rev 1

Page 7

STM32WL55/54xx List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2. Main features and peripheral count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 3. Access status versus RDP level and execution mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 4. Sub-GHz radio transmit high output power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 5. FSK mode intermediate frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 6. LoRa mode intermediate frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 7. Functionalities depending on system operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 8. Low-power mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 9. MCU and sub-GHz radio operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 10. Peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 11. DMA1 and DMA2 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 12. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 13. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 14. Timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 15. I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 16. USART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 17. SPI and SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 18. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 19. STM32WL55/54xx pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 20. Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 21. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 22. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 23. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 24. Main performances at VDD = 3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 25. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 26. Operating range of RF pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 27. Sub-GHz radio power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 28. Sub-GHz radio power consumption in transmit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 29. Sub-GHz radio general specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 30. Sub-GHz radio receive mode specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 31. Sub-GHz radio transmit mode specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 32. Sub-GHz radio power management specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 33. Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 34. Embedded reset and power-control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 35. Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 36. Current consumption in Run and LPRun modes on CPU1, CoreMark code with data

running from Flash memory, ART enable (cache ON, prefetch OFF) . . . . . . . . . . . . . . . . 78

Table 37. Current consumption in Run and LPRun modes on CPU1 and CPU2, CoreMark code

with data running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 38. Current consumption in Run and LPRun modes on CPU1, CoreMark code

with data running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 39. Typical current consumption in Run and LPRun modes on CPU1, with different codes

running from Flash memory, ART enable (cache ON, prefetch OFF) . . . . . . . . . . . . . . . . 81

Table 40. Typical current consumption in Run and LPRun modes on CPU1,

with different codes running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 41. Current consumption in Sleep and LPSleep modes on CPU1, Flash memory ON . . . . . . 85

Table 42. Current consumption in Sleep and LPSleep modes on CPU1 and CPU2,

Flash memory ON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

DS13293 Rev 1 7/145

Page 8

List of tables STM32WL55/54xx

Table 43. Current consumption in LPSleep mode on CPU1, Flash memory in power-down . . . . . . . 86

Table 44. Current consumption in LPSleep mode on CPU1 and CPU2,

Flash memory in power-down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 45. Current consumption in Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 46. Current consumption during wakeup from Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 47. Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 48. Current consumption during wakeup from Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 49. Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 50. Current consumption during wakeup from Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 51. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 52. Current consumption during wakeup from Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 53. Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 54. Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 55. Current under Reset condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 56. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 57. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 58. Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 59. HSE32 crystal requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 60. HSE32 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 61. HSE32 TCXO regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 62. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 63. Low-speed external user clock characteristics – Bypass mode . . . . . . . . . . . . . . . . . . . . 100

Table 64. HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 65. MSI oscillator characteristics

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102

Table 66. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 67. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Table 68. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Table 69. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 70. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 71. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 72. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 73. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 74. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Table 75. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table 76. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 77. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 78. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Table 79. Analog switches booster characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Table 80. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Table 81. Maximum ADC R

values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

AIN

Table 82. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Table 83. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Table 84. V Table 85. V

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

BAT

charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

BAT

Table 86. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 87. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Table 88. DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Table 89. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Table 90. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 91. IWDG min/max timeout period at 32 kHz (LSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Table 92. Minimum I2CCLK frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Table 93. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

8/145 DS13293 Rev 1

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STM32WL55/54xx List of tables

Table 94. USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Table 95. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Table 96. Dynamic JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Table 97. Dynamic SWD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Table 98. UFQFPN48 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Table 99. UFBGA73 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Table 100. UFBGA recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . 141

Table 101. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Table 102. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

DS13293 Rev 1 9/145

Page 10

List of figures STM32WL55/54xx

List of figures

Figure 1. STM32WL55/54xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 2. sub-GHz radio system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 3. High output power PA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 4. Low output power PA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 5. Power-up/power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 6. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 7. Supply configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 8. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 9. UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 10. UFBGA73 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 11. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 12. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 13. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 14. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 15. VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 16. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 17. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 18. HSI16 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Figure 19. Typical current consumption vs. MSI frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Figure 20. I/O input characteristics - V

Figure 21. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 22. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 23. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 24. VREFOUT_TEMP when VRS = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Figure 25. VREFOUT_TEMP when VRS = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 26. 12-bit buffered/non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Figure 27. SPI timing diagram - Slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Figure 28. SPI timing diagram - Slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Figure 29. SPI timing diagram - Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Figure 30. UFQFPN48 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Figure 31. UFQFPN48 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Figure 32. UFQFPN48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Figure 33. UFBGA73 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Figure 34. UFBGA73 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Figure 35. UFBGA73 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

and V

on all I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

10/145 DS13293 Rev 1

Page 11

STM32WL55/54xx Introduction

1 Introduction

This document provides information on the STM32WL55/54xx microcontrollers.

®(a)

For information on the Arm

Cortex

-M4 Technical Reference Manual and to the Cortex®-M0+ Technical Reference

Cortex®-M4 and Cortex®-M0+ cores, refer respectively to the

Manual available from the www.arm.com website.

For information on LoRa

modulation, refer to the Semtech website

(https://www.semtech.com/technology/lora).

2 Description

The STM32WL55/54xx long-range wireless and ultra-low-power devices embed a powerful

and ultra-low-power LPWAN-compliant radio solution, enabling the following modulations:

LoRa

, (G)FSK, (G)MSK, and BPSK.

The LoRa

These devices are designed to be extremely low-power and are based on the

high-performance Arm

48 MHz. This core implements a full set of DSP instructions. It is complemented by an Arm

Cortex

modulation is available in STM32WLx5xx only.

Cortex®-M4 32-bit RISC core operating at a frequency of up to

-M0+ microcontroller. Both cores implement an independent memory protection unit

(MPU) that enhances the application security.

The devices embed high-speed memories (256-Kbyte Flash memory, 64-Kbyte SRAM), and

an extensive range of enhanced I/Os and peripherals.

The devices also embed several protection mechanisms for embedded Flash memory and

SRAM: readout protection, write protection and proprietary code readout protection.

In addition, the STM32WL55/54xx devices support the following secure services running on

Arm

Cortex-M0+: unique boot entry capable, secure sub-GHz MAC layer, secure firmware

update, secure firmware install and storage and management of secure keys.

These devices offer a 12-bit ADC, a 12-bit DAC low-power sample-and-hold, two

ultra-low-power comparators associated with a high-accuracy reference voltage generator.

The devices embed a low-power RTC with a 32-bit sub-second wakeup counter, one 16-bit

single-channel timer, two 16-bit four-channel timers (supporting motor control), one 32-bit

four-channel timer and three 16-bit ultra-low-power timers.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

DS13293 Rev 1 11/145

Page 12

Description STM32WL55/54xx

These devices also embed two DMA controllers (7 channels each) allowing any transfer

combination between memory (Flash memory, SRAM1 and SRAM2) and peripheral, using

the DMAMUX1 for flexible DMA channel mapping.

The devices also feature the standard and advanced communication interfaces listed below:

• inter-processor communication controller (mailbox) and semaphores for communication between the two Arm

Cortex®-M cores

• two USART (supporting LIN, smartcard, IrDA, modem control and ISO7816)

• one low-power UART (LPUART)

• three I2C (SMBus/PMBus)

• two SPIs (up to 16 MHz, one supporting I

The operating temperature/voltage ranges are

–40 °C to +105 °C (+85 °C with radio)

(a)

from a 1.8 V to 3.6 V power supply. A comprehensive set of power-saving modes allows the design of low-power applications.

The devices integrate a high-efficiency SMPS step-down converter and independent power supplies for ADC, DAC and comparator analog inputs.

A V

dedicated supply allows the LSE 32.768 kHz oscillator, the RTC and the backup

BAT

registers to be backed up. The devices can maintain these functions even if the main V not present, through a CR2032-like battery, a supercap or a small rechargeable battery.

Feature

CPU Arm

Maximum CPU frequency (MHz) 48

Flash memory density (Kbytes) 256

SRAM density (Kbytes)

Radio

Radio PA

SRAM1 32

SRAM2 32

LoRa

(G)FSK

BPSK

Low output power (up to 15 dBm)

High output power (up to 22 dBm)

Table 2. Main features and peripheral count

STM32WL55Cx

STM32WL54Cx

Available on STM32WL55xx devices.

Not available on STM32WL54xx devices

STM32WL55Jx

STM32WL54Jx

Cortex-M4 and Cortex-M0

Yes(G)MSK

Yes

STM32WL55Ux

STM32WL54Ux

General purpose 4

Timer

a. Devices with suffix 6 operate up to 85 °C. Devices with suffix 7 can operate up to 105 °C except radio.

12/145 DS13293 Rev 1

Low-power 3

SysTick 1

Page 13

STM32WL55/54xx Description

Table 2. Main features and peripheral count (continued)

Feature

STM32WL55Cx

STM32WL54Cx

STM32WL55Jx

STM32WL54Jx

SPI/I2S 2 (1 supporting I2S)

Communication interface

USART 2

LPUART 1

Independent 1

Watchdog

Window 1

RTC (with wakeup counter) 1

DMA (7 channels) 2

Mailbox and semaphores 1

AES 256 bits 1

RNG 1

PKA 1

P C R O P, R DP, WR P 1

CRC 1

64-bit UID compliant with IEEE 802-2001 standard

Security

96-bit die ID 1

STM32WL55Ux

STM32WL54Ux

Storage and management of secure

keys

Secure sub-GHz MAC layer

Secure firmware update 1

Secure firmware install 1

Tamper pins 3 3 2

Wakeup pins 3 3 2

GPIOs 29 43 22

ADC (number of channels, ext + int) 1 (9 + 4) 1 (12 + 4) 1 (8 + 4)

DAC (number of channels) 1 (1)

Internal VREFBUF No Yes No

Analog comparator 2

Operating voltage 1.8 to 3.6 V

Ambient operating temperature –40 °C to +85 °C

Junction temperature –40 °C to +105 °C

Package

UFQFPN48

(7x7 mm)

UFBGA73

(5x5 mm)

WLCSP59

DS13293 Rev 1 13/145

Page 14

Description STM32WL55/54xx

MSv66957V1

DMA1 (7 channels)

NVIC

TIM17

EXTI

TIM16

GPIO

ports A,B,C,H

PWR

SRAM1

RTC

TAMP

IWDG

LSE

32 kHz

HSE32 32 MHz

MSI 5 %

0.1-48MHz

HSI 1 % 16 MHz

PLL

Power supply

POR/PDR/BOR/PVD/PVM

ADC (12 bits ULP,

2 Msps, 12 channels)

Temperature sensor

APB1 and APB 2

Backup domain

JTAG/SWD

Flash interface arbiter

ART Accelerator

256-Kbyte

Flash memory

Sub-GHz

radio

RNG

LSI

32 kHz

LPTIM2

LPTIM1

CRC

RCC

SYSCFG/

COMP/VREF

HSEM

WWDG

SPI2S2

I2C3

LPUART1

SPI1

USART1

TIM2

MPU

SRAM2

backup memory

Cortex-M4

(DSP)

≤ 48 MHz

DMAMUX

DMA2 (7 channels)

LDO/SMPS

LPTIM3

TIM1

I2C1

I2C2

USART2

DAC

(12 bits)

AES

PKA

AHB1 and AHB2

TZSC

IPCC

NVIC

MPU

Cortex-M0+

≤ 48 MHz

SUBGHZ

SPI

CTI

TZIC

AHB3

Figure 1. STM32WL55/54xx block diagram

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STM32WL55/54xx Functional overview

3 Functional overview

3.1 Architecture

The devices embed a sub-GHz RF subsystem that interfaces with a generic microcontroller subsystem using an Arm Cortex-M4 (called CPU1) and an Arm Cortex-M0+ (called CPU2).

An RF low-layer stack is needed and is to be run on CPU1 or CPU2, whereas the host application code is preferably run on CPU1.

The RF subsystem communication is done through an internal SPI interface.

All secure code must be run by CPU2.

3.2 Arm Cortex-M cores

With its embedded Arm cores, the STM32WL55/54xx devices are compatible with all Arm tools and software.

Figure 1 shows the general block diagram of the STM32WL55/54xx devices.

Arm Cortex-M4

The Arm Cortex-M4 is a processor for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.

The Arm Cortex-M4 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an Arm core in the memory size usually associated with 8- and 16-bit devices.

This processor supports a set of DSP instructions that allow efficient signal processing and complex algorithm execution.

Arm Cortex-M0+

The Arm Cortex-M0+ is an entry-level processor for embedded systems. It has been developed to provide lowest power consumption in the Cortex-M family, while delivering good computation performance and response to interrupts.

The Arm Cortex-M0+ 32-bit RISC processor features good code-efficiency with ultra-low power consumption in the memory size usually associated with 8-bit and 16-bit devices.

3.3 Adaptive real-time memory accelerator (ART Accelerator)

The ART Accelerator is a memory accelerator that is optimized for STM32 industry-standard Arm Cortex-M4 processor. The ART Accelerator balances the inherent performance advantage of the Arm Cortex-M4 over Flash memory technologies, that normally require the processor to wait for the Flash memory at higher frequencies.

To release the processor near 60 DMIPS performance at 48 MHz, the ART Accelerator implements an instruction prefetch queue and branch cache, that increases the program execution speed from the 64-bit Flash memory. Based on CoreMark benchmark, the

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Functional overview STM32WL55/54xx

performance achieved thanks to the ART Accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 48 MHz.

3.4 Memory protection unit (MPU)

The memory protection unit (MPU) is used to manage the CPU1 and CPU2 accesses to memory, to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to eight protected areas that can in turn be divided up into eight subareas. The protection area sizes are between 32 bytes and the whole 4 Gbytes of addressable memory.

The MPU is especially helpful for applications where some critical or certified code must be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

3.5 Memories

3.5.1 Embedded Flash memory

The Flash memory interface manages the accesses from CPU1 AHB ICode/DCode and CPU2 AHB Sbus to the Flash memory. It implements the access, the erase and program Flash memory operations, and the read and write protection.

The main features of the Flash memory are listed below:

• Memory organization: 1 bank

– main memory: up to 256 Kbytes

– page size: 2 Kbytes

• 72-bit wide data read (64 bits plus 8 ECC bits)

• 72-bit wide data write (64 bits plus 8 ECC bits)

• Page erase and mass erase

Flexible protections can be configured thanks to option bytes:

• Readout protection (RDP) to protect the whole memory. Three levels are available:

– Level 0: no readout protection

– Level 1: memory readout protection. The Flash memory cannot be read from or

written to if either debug features are connected, boot in SRAM or bootloader is selected.

– Level 2: chip readout protection. Debug features (JTAG and serial wire), boot in

SRAM and bootloader selection are disabled (JTAG fuse). This selection can only be reverted by the secure CPU2.

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STM32WL55/54xx Functional overview

Table 3. Access status versus RDP level and execution mode

Area

Main memory

System memory

Option bytes

Backup registers

SRAM2

1. The option byte can be modified by the sub-GHz radio.

2. Erased when RDP changes from Level 1 to Level 0.

RDP level

Read Write Erase Read Write Erase

1 Yes Yes Yes No No No

2 Yes Yes Yes NA NA NA

1Yes No No Yes No No

2 Yes No No NA NA NA

1 Yes Yes Yes Yes Yes Yes

2Yes No

1Yes Yes NA

2YesYesNANANANA

1 Yes Yes Yes

2 Yes Yes Yes NA NA NA

User execution

(1)

• Write protection (WRP): the protected area is protected against erasing and

programming. Two areas can be selected, with 4-Kbyte granularity.

• Proprietary code readout protection (PCROP): two parts of the Flash memory can be

protected against read and write from third parties. The protected area is execute-only: it can only be reached by the STM32 CPU1/2, as an instruction code, while all other accesses (DMA, debug and CPU1/2 data read, write and erase) are strictly prohibited. Two areas can be selected, with 2-Kbyte granularity. An additional option bit (PCROP_RDP) is used to select if the PCROP area is erased or not when the RDP protection is changed from Level 1 to Level 0.

(1)

(2)

Debug, boot from SRAM or boot from

system memory (loader)

NA NA NA

No No NA

No No No

(2)

A section of the Flash memory can be secured for CPU2, and, in that case, cannot be accessed by CPU1.

The whole non-volatile memory embeds the error correction code (ECC) feature supporting:

• single error detection and correction

• double error detection

• address of the ECC fail can be read in the FLASH_ECCR register

The embedded Flash memory is shared between CPU1 and CPU2 on a time sharing basis. A dedicated hardware mechanism allows both CPUs to suspend write/erase operations.

3.5.2 Embedded SRAM

The devices feature up to 64 Kbytes of embedded SRAM, split in two blocks:

• SRAM1: up to 32 Kbytes mapped at address 0x2000 0000

• SRAM2: up to 32 Kbytes located at address 0x2000 8000 (contiguous to SRAM1), also

mirrored at 0x1000 0000, with hardware parity check (this SRAM can be retained in Standby mode)

The SRAMs can be accessed in read/write with 0 wait states for all CPU1/2 clock speeds.

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Functional overview STM32WL55/54xx

3.6 Security memory management

The devices contain many security blocks both for the sub-GHz MAC layer and the Host application, such as:

• securable RNG

• customer keys storage

• secure Flash memory partition for CPU2 only access

• secure SRAM partition, that can be accessed only by CPU2

• securable sub-GHz radio sub-system

• securable DMA channels

• securable AES: 128-and 256-bit AES, supporting ECB, CBC, CTR, GCM, GMAC and

CCM chaining modes

• securable PKA:

– modular arithmetic including exponentiation with maximum modulo size of

3136 bits

– elliptic curves over prime field scalar multiplication, ECDSA signature, ECDSA

verification with maximum modulo size of 521 bits

• cyclic redundancy check calculation unit (CRC)

3.7 Boot modes

At startup, BOOT0 pin and BOOT1 option bit are used to select one of the following boot options:

• Boot from user Flash memory

• Boot from boot system memory (where embedded bootloader is located)

• Boot from embedded SRAM

• Boot from system memory (where the embedded SFI is located)

The bootloader makes possible to download code from USART or SPI.

3.8 Global security controller (GTZC)

The GTZC includes the following sub-blocks:

• TZSC: security controller

This sub-block defines the secure/privileged state of slave peripherals. It also controls the unprivileged area size for the watermark memory peripheral controller (MPCWM).

• TZIC: security illegal access controller

This sub-block gathers all illegal access events in the system and generates a secure interrupt towards the secure CPU2 NVIC.

These sub-blocks are used to configure the system security and privilege such as:

• on-chip Flash memory and RAM with programmable privileged protection on both

secure and non-secure memory areas

• AHB and APB peripherals with programmable security and/or privileged access

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STM32WL55/54xx Functional overview

MSv62614V1

Sub-GHz radio

Sub-GHz

RF frontend

Radio control

SUBGHZSPI

hse32

Interrups

RFO_LP

RFO_HP

RFI_P

RFI_N

FSK

modem

LoRa

modem

(note)

Data

and

control

HSE32

OSC_IN

OSC_OUT

BUSY

HSERDY

HSEON

HSEBYPPWR

Note: LoRa modem is only available on STM32WL55xx devices.

VR_PA

VDDPA

PB0_VDDTCXO

3.9 Sub-GHz radio

3.9.1 Introduction

The sub-GHz radio is an ultra-low-power sub-GHz radio operating in the 150 - 960 MHz ISM band. LoRa, (G)FSK/(G)MSK modulation in transmit and receive, and (D)BPSK in transmit only, allow an optimal trade-off between range, data rate and power consumption. This subGHz radio is compliant with the LoRaWAN ETSI EN 300 220, EN 300 113, EN 301 166, FCC CFR 47 part 15, 24, 90, 101 and the ARIB STD-T30, T-67, T-108.

The sub-GHz radio consists of:

• an analog front-end transceiver, capable of outputting up to + 15 dBm maximum power

on its RFO_LP pin and up to + 22 dBm maximum power on RFO_HP pin

• a digital modem bank providing the following modulation schemes:

– LoRa Rx/Tx with bandwidth (BW) from 7.8 - 500 kHz, spreading factor (SF)

5 - 12, bit rate (BR) from 0.013 to 17.4 Kbit/s (real bitrate)

– FSK and GFSK Rx/Tx with BR from 0.6 to 300 Kbit/s

– (G)MSK Tx with BR from 0 to 10 Kbit/s

– BPSK and DBPSK TX only with bitrate for 100 and 600 bit/s

• a digital control including all data processing and sub-GHz radio configuration control

• a high-speed clock generation

specification v1.0 and radio regulations such as

3.9.2 General description

The sub-GHz radio provides an internal processing unit to handle communication with the system CPU. Communication is handled by commands sent over the SPI interface, and a set of interrupts is used to signal events. BUSY information signals operation activity and is used to indicate when the sub-GHz radio commands cannot be received.

The block diagram of the sub-GHz radio system is shown in the figure below.

Figure 2. sub-GHz radio system block diagram

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Functional overview STM32WL55/54xx

MSv62616V2

VLXSMPS

VFBSMPS (1.55V)

VDDPA

VR_PA (up to 3.1V)

RFO_HP

LDO/SMPS

REG

HP PA

VLXSMPS

VFBSMPS (1.55V)

VDDPA

VR_PA (up to 3.1V)

RFO_HP

LDO/SMPS

REG

HP PA

VDDSMPS (1.8 to 3.6V) VDDSMPS (1.8 to 3.6V)

LDO mode

SMPS mode

Note: Use of the SMPS is optional. When SMPS is not used, the BOM can be reduced by removing the coil between VLXSMPS and VFBSMPS pins.

3.9.3 Transmitter

The transmit chain comprises the modulated output from the modem, that directly modulates the RF-PLL. An optional pre-filtering of the bit stream can be enabled to reduce the power in the adjacent channel also dependent on the selected modulation scheme. The modulated signal from the RF-PLL directly drives the high output power PA (HP PA) or low output power PA (LP PA).

Transmitter high output power

Transmit high output power up to + 22 dBm, is supported through the RFO_HP RF pin.

For this, the REG PA must be supplied directly from V

on VDDSMPS pin, as shown in the

figure below.

The output power range is programmable in 32 steps of ~ 1 dB. The power amplifier ramping timing is also programmable.This allows adaptation to meet radio regulation requirements.

Figure 3. High output power PA

The table below gives the maximum transmit output power versus the V

DDPA

Table 4. Sub-GHz radio transmit high output power

supply (V) Transmit output power (dBm)

3.3 + 22

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2.7 + 20

2.4 + 19

1.8 + 16

supply level.

DDPA

Page 21

STM32WL55/54xx Functional overview

MSv62617V2

Note: Use of the SMPS is optional. When SMPS is not used, the BOM can be reduced by removing the coil between VLXSMPS and VFBSMPS pins.

VLXSMPS

VFBSMPS (1.55V)

VDDPA

VR_PA (up to 1.35V)

RFO_LP

LDO/SMPS

REG

LP PA

LDO mode SMPS mode

VDDSMPS (1.8 to 3.6V)

VLXSMPS

VFBSMPS (1.55V)

VDDPA

VR_PA (up to 1.35V)

RFO_LP

LDO/SMPS

REG

LP PA

VDDSMPS (1.8 to 3.6V)

Transmitter low output power

The transmit low output power up to + 15 dBm on full VDD range (1.8 to 3.6 V), is supported through the RFO_LP RF pin. For this, the REG PA must be supplied from the regulated V

FBSMPS

The output power range is programmable in 32 steps of ~1 dB. The power amplifier ramping timing is also programmable.This allows adaptation to meet radio regulation requirements.

supply at 1.55 V, as shown in the figure below.

Figure 4. Low output power PA

3.9.4 Receiver

3.9.5 RF-PLL

The receive chain comprises a differential low-noise amplifier (LNA), a down-converter to low-IF by mixer operation in quadrature configuration. The I and Q signals are low pass filtered and a  ADC converts them into the digital domain. In the digital modem, the signals are decimated, further down converted and channel filtered. The demodulation is done according to the selected modulation scheme.

The down mixing to low-IF is done by mixing the receive signal with the local RF-PLL located in the negative frequency, where -f frequency, f is located at f

is the received signal and fif is the intermediate frequency). The wanted signal

= flo + fif.

= -frf + -fif. (where flo is the local RF-PLL

The receiver features automatic I and Q calibration, that improves image rejection. The calibration is done automatically at startup before using the receiver, and can be requested by command.

The receiver supports LoRa, (G)MSK and (G)FSK modulations.

The RF-PLL is used as the frequency synthesizer for the generation of the local oscillator frequency (f

) for both transmit and receive chains. The RF-PLL uses auto calibration and

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Functional overview STM32WL55/54xx

uses the 32 MHz HSE32 reference. The sub-GHz radio covers all continuous frequencies in the range between 150 to 960 MHz.

3.9.6 Intermediate frequencies

The sub-GHz radio receiver operates mostly in low-IF configuration, except for specific highbandwidth settings.

Table 5. FSK mode intermediate frequencies

Setting name Bandwidth (kHz) f

RX_BW_467 467.0

RX_BW_234 234.3

RX_BW_117 117.3

RX_BW_58 58.6

RX_BW_29 29.3

RX_BW_14 14.6

RX_BW_7 7.3

RX_BW_373 373.6

RX_BW_187 187.2

RX_BW_93 93.8

RX_BW_46 46.9

RX_BW_23 23.4

RX_BW_11 11.7

RX_BW_5 5.8

RX_BW_312 312.0

RX_BW_156 156.2

RX_BW_78 78.2

(kHz)

250

200

RX_BW_39 39.0

RX_BW_19 19.5

RX_BW_9 9.7

RX_BW_4 4.8

Table 6. LoRa mode intermediate frequencies

Setting name Bandwidth (kHz) f

LORA_BW_500 500 0

LORA_BW_250 250

LORA_BW_62 62.5

LORA_BW_41 41.67 167

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(kHz)

250LORA_BW_125 125

Page 23

STM32WL55/54xx Functional overview

Table 6. LoRa mode intermediate frequencies (continued)

Setting name Bandwidth (kHz) f

LORA_BW_31 31.25 250

LORA_BW_20 20.83 167

LORA_BW_15 15.63 250

LORA_BW_10 10.42 167

LORA_BW_7 7.81 250

3.10 Power supply management

The devices embed two different regulators: one LDO and one DC/DC (SMPS). The SMPS can be optionally switched-on by software to improve the power efficiency. As LDO and SMPS operate in parallel, the SMPS switch-on is transparent to the user and only the power efficiency is affected.

3.10.1 Power supply schemes

The devices require a V independent supplies (V peripherals:

• V

= 1.8 V to 3.6 V

is the external power supply for the I/Os, the system analog blocks such as reset,

power management, internal clocks and low-power regulator. It is provided externally through VDD pins.

• V

DDSMPS

= 1.8 V to 3.6 V

is the external power supply for the SMPS step-down converter. It is provided externally through VDDSMPS supply pin and must be connected to the same supply as V

• V

FBSMPS

= 1.45 V to 1.62 V (1.55 V typical)

is the external power supply for the main system regulator. It is provided externally through VFBSMPS pin and is supplied through the SMPS step-down converter.

• V

= 0 V to 3.6 V (DAC minimum voltage is 1.71 V without buffer and 1.8 V with

DDA

buffer. COMP and ADC minimum voltage is 1.62 V. VREFBUF minimum voltage is

2.4 V)

is the external analog power supply for A/D converters, D/A converters, voltage

DDA

reference buffer, and comparators. The V voltage (see power-up and power-down limitations below) and must preferably be connected to V

• V

DDRF

= 1.8 V to 3.6 V

is an external power supply for the radio. It is provided externally through the

VDDRF pin and must be connected to the same supply as V

• V

DDRF1V5

= 1.45 V to 1.62 V

is an external power supply for the radio. It is provided externally through the

operating voltage supply between 1.8 V and 3.6 V. Several

DDSMPS

, V

FBSMPS

when these peripherals are not used.

, V

DDA

, V

) can be provided for specific

DDRF

voltage level is independent from the V

(kHz)

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Functional overview STM32WL55/54xx

MSv68044V1

0.3

BOR0

3.6

Operating modePower-on Power-down time

DDA

Invalid supply area V

DDA

< V

+ 300 mV

DDA

independent from V

VDDRF1V5 pin and must be connected externally to VFBSMPS.

• V

• VREF-, VREF

= 1.55 V to 3.6 V

BAT

is the power supply for RTC, TAMP, external clock 32 kHz oscillator and backup

BAT

registers (through power switch) when V

is the input reference voltage for ADC and DAC. It is also the output of the

REF+

is not present.

internal voltage reference buffer when enabled.

– When V

can be grounded when ADC/DAC is not active. The internal voltage reference

REF+

DDA

< 2 V, V  2 V, V

must be equal to V

REF+

must be between 2 V and V

REF+

DDA

buffer supports the following output voltages, configured with VRS bit in the VREFBUF_CSR register:

–V

around 2.048 V: this requires V

REF+

around 2.5 V: this requires V

REF+

DDA

 2.4 V.

DDA

 2.8 V.

During power up and power down, the following power sequence is required:

1. When V

During power down, V

< 1 V other power supplies (V

can temporarily become lower then other supplies only if the

) must remain below V

DDA

+ 300 mV.

energy provided to the device remains below 1 mJ. This allows external decoupling capacitors to be discharged with different time constants during this transient phase.

2. When V

An embedded linear voltage regulator is used to supply the internal digital power V V

is the power supply for digital peripherals, SRAM1 and SRAM2. The Flash memory

CORE

is supplied by V part V

DDI

> 1 V, all other power supplies (V

CORE

and VDD. V

is split in two parts: V

CORE

) become independent.

DDA

part and an interruptible

DDO

CORE

Figure 5.

Note: VDD, V

sequence.

DDRF

and V

DDSMPS

must be wired together, so they can follow the same voltage

Power-up/power-down sequence

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STM32WL55/54xx Functional overview

MSv50973V1

LDO/SMPS

LXSMPS

FBSMPS

BKP

DDO

DDI

BAT

MAIN

POR

mode

FW mode

RFLDO

DDSMPS

DDRF1V5

LPR

MSv50974V1

LDO/SMPS

LDO/SMPS supply LDO supply

LDO

MR LPR

DDRF1V5

FBSMPS

LXSMPS

DDSMPS

LDO/SMPS

LDO

MR LPR

DDRF1V5

FBSMPS

LXSMPS

DDSMPS

Figure 6. Power supply overview

The different supply configurations are shown in the figure below.

Figure 7. Supply configurations

DS13293 Rev 1 25/145

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Functional overview STM32WL55/54xx

The LDO or SMPS step-down converter operating mode can be configured by one of the following:

• by the MCU using the SMPSEN setting in PWR control register 5 (PWR_CR5), that depends upon the MCU system operating mode (Run, Stop, Standby or Shutdown).

• by the sub-GHz radio using SetRegulatorMode() command and the sub-GHz radio operating mode (Sleep, Calibrate, Standby, Standby with HSE32 or Active).

After any POR and NRST reset, the LDO mode is selected. The SMPS selection has priority over LDO selection.

While the sub-GHz radio is in Standby with HSE32 or in Active mode, the supply mode is not altered until the sub-GHz radio enters Standby or Sleep mode. The sub-GHz radio activity may add a delay for entering the MCU software requested supply mode.

The LDO or SMPS supply mode can be checked with the SMPSRDY flag in power status register 2 (PWR_SR2).

Note: When the radio is active, the supply mode is not changed until after the radio activity is

finished.

During Stop 1, Stop 2 and Standby modes, when the sub-GHz radio is not active, the LDO or SMPS step-down converter is switched off. When exiting low-power modes (except Shutdown), the SMPS step-down converter is set by hardware to the mode selected by the SMPSEN bit in PWR control register 5 (PWR_CR5). SMPSEN is retained in Stop and Standby modes.

Independently from the MCU software selected supply operating mode, the sub-GHz radio allows the supply mode selection while the sub-GHz radio is active (thanks to the sub-GHz radio SetRegulatorMode()command).

The maximum load current delivered by the SMPS can be selected by the sub- GHz radio SUBGHZ_SMPSC2R register.

The inrush current of the LDO and SMPS step-down converter can be controlled via the sub- GHz radio SUBGHZ_PCR register. This information is retained in all but the sub-GHz radio Deep-sleep mode.

The SMPS needs a clock to be functional. If for any reason this clock stops, the device may be destroyed. To avoid this situation, a clock detection is used to, in case of a clock failure, switch off the SMPS and enable the LDO. The SMPS clock detection is enabled by the subGHz radio SUBGHZ_SMPSC0R.CLKDE. By default, the SMPS clock detection is disabled and must be enabled before enabling the SMPS.

Danger: Before enabling the SMPS, the SMPS clock detection must be

enabled in the sub-GHz radio SUBGHZ_SMPSC0R.CLKDE.

3.10.2 Power supply supervisor

The devices integrate a power-on reset/power-down reset, coupled with a Brownout reset (BOR) circuitry.

BOR0 level cannot be disabled. Other BOR levels can be enabled by user option. When enabled, BOR is active in all power modes except in Shutdown

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STM32WL55/54xx Functional overview

Five BOR thresholds can be selected through option bytes.

During power-on, BOR keeps the device under reset until the supply voltage V the specified V

• When V

threshold:

BORx

drops below the selected threshold, a device reset is generated.

is above the V

can start.

The devices feature an embedded PVD (programmable voltage detector) that monitors the V

power supply and compares it with the V

when V

drops below the V

PVD

threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state.

The PVD is enabled by software and can be configured to monitor the V needed for the sub-GHz radio operation. For this, the PVD must select its lowest threshold, and the PVD and the wakeup must be enabled by the EWPVD bit in PWR_CR3 register. Only a voltage drop below the PVD level generates a wakeup event.

In addition, the devices embed a PVM (peripheral voltage monitor) that compares the independent supply voltage V functional supply range.

Finally, a radio end-of-life monitor provides information on the V low to operate the sub-GHz radio. When reaching the EOL level, the software must stop all radio activity in a safe way.

3.10.3 Linear voltage regulator

reaches

upper limit, the device reset is released and the system

BORx

threshold. An interrupt can be generated

threshold and/or when VDD is higher than the V

with a fixed threshold to ensure that the peripheral is in its

DDA

PVD

supply when V

PVD

supply level

is too

Two embedded linear voltage regulators supply all the digital circuitries, except for the Standby circuitry and the Backup domain. The main regulator (MR) output voltage (V can be programmed by software to two different power ranges (range 1 and range 2), to optimize the consumption depending on the system maximum operating frequency.

The voltage regulators are always enabled after a reset. Depending on the application modes, the V

supply is provided either by the main regulator or by the low-power

CORE

regulator (LPR).

When MR is used, a dynamic voltage scaling is proposed to optimize power as follows:

• range 1: high-performance range

The system clock frequency can be up to 48 MHz. The Flash memory access time for read access is minimum. Write and erase operations are possible.

• range 2: low-power range

The system clock frequency can be up to 16 MHz.The Flash memory access time for a read access is increased as compared to range 1. Write and erase operations are possible.

Note: MR is supplied by VDD during power-on or at wakeup from Stop1, Stop2, Standby or

Shutdown mode. MR is powered by LDO/SMPS after these transition phases.

3.10.4 VBAT operation

The VBAT pin is used to power the device V from an external battery, an external super-capacitor, or from V

domain (RTC, LSE and backup registers)

BAT

when no external battery

CORE

)

DS13293 Rev 1 27/145

Page 28

Functional overview STM32WL55/54xx

nor an external super-capacitor are present. Three anti-tamper detection pins are available in VBAT mode.

VBAT operation is automatically activated when V

An internal V

battery charging circuit is embedded and can be activated when VDD is

BAT

present.

Note: When the microcontroller is supplied only from V

alarm/events do not exit it from VBAT operation.

3.11 Low-power modes

The devices support several low-power modes to achieve the best compromise between low-power consumption, short startup time, available peripherals and available wakeup sources.

By default, the microcontroller is in Run mode, range 1, after a system or a power-on reset. It is up to the user to select one of the low-power modes described below:

• Sleep mode: CPU clock off, all peripherals including CPU core peripherals (among them NVIC, SysTick) can run and wake up the CPU when an interrupt or an event occurs.

• Low-power run mode (LPRun): when the system clock frequency is reduced below 2 MHz. The code is executed from the SRAM or from the Flash memory. The regulator is in low-power mode to minimize the operating current.

• Low-power sleep mode (LPSleep): entered from the LPRun mode.

• Stop 0 and Stop 1 modes: the content of SRAM1, SRAM2 and of all registers is

retained. All clocks in the V disabled. LSI and LSE can be kept running.

RTC can remain active (Stop mode with RTC, Stop mode without RTC). The sub-GHz radio may remain active independently from the CPUs.

Some peripherals with the wakeup capability can enable HSI16 RC during the Stop mode to detect their wakeup condition.

Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller wakeup time but a higher consumption compared with Stop 2.

In Stop 0 mode, the main regulator remains on, resulting in the fastest wakeup time but with much higher consumption. The active peripherals and wakeup sources are the same as in Stop 1 mode that uses the low-power regulator.

The system clock, when exiting Stop 0 or Stop 1 mode, can be either MSI up to 48 MHz or HSI16, depending on the software configuration.

• Stop 2 mode: part of the V and some peripherals preserve their contents (see Table 7).

All clocks in the V

domain are stopped. PLL, MSI, HSI16 and HSE32 are disabled.

CORE

LSI and LSE can be kept running.

RTC can remain active (Stop 2 mode with RTC, Stop 2 mode without RTC). The subGHz radio may also remain active independent from the CPUs.

Some peripherals with the wakeup capability can enable HSI16 RC during the Stop 2 mode to detect their wakeup condition (see Tab le 7).

The system clock when exiting from Stop 2 mode, can be either MSI up to 48 MHz or

domain are stopped. PLL, MSI, HSI16 and HSE32 are

CORE

domain is powered off. Only SRAM1, SRAM2, CPUs

CORE

is not present.

, external interrupts and RTC

BAT

28/145 DS13293 Rev 1

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STM32WL55/54xx Functional overview

HSI16, depending on the software configuration.

• Standby mode: V

domain is powered off. However, it is possible to preserve the

CORE

SRAM2 content as detailed below:

– Standby mode with SRAM2 retention when the RRS bit is set in the PWR control

– Standby mode when the RRS bit is cleared in the PWR control register 3

(PWR_CR3). In this case the main regulator and the low-power regulator are powered off.

All clocks in the V

domain are stopped. PLL, MSI, HSI16 and HSE32 are disabled.

CORE

LSI and LSE can be kept running.

Th RTC can remain active (Standby mode with RTC, Standby mode without RTC). The sub-GHz radio and the PVD may also remain active when enabled independent from the CPUs. In Standby mode, the PVD selects its lowest level.

The system clock, when exiting Standby modes, is MSI at 4 MHz.

• Shutdown mode: V

domain is powered off. All clocks in the V

CORE

domain are

CORE

stopped. PLL, MSI, HSI16, LSI and HSE32 are disabled. LSE can be kept running. The system clock when exiting the Shutdown mode, is MSI at 4 MHz. In this mode, the supply voltage monitoring is disabled and the product behavior is not guaranteed in case of a power voltage drop.

The table below summarizes the peripheral features over all available modes. Wakeup capability is detailed in gray cells.

Table 7. Functionalities depending on system operating mode

Stop 0 Stop 1 Stop 2 Standby Shutdown

Peripheral

Run

Sleep

LPRun

LPSleep

Wakeup capability

CPU1 Y R Y R R -R-R---- --

CPU2 Y R Y R R

Sub-GHz radio system O O O O O

(2)

Flash memory (256 Kbytes)

(2)O(3)

(3)

-R-R---- --

OOOOOOO- --

R -R-R-R-R -R

Flash memory interface Y Y Y Y R -R-R---- --

SRAM1 Y O

SRAM2 Y O

(2)

Backup registers Y Y Y Y R

Brownout reset (BOR) Y Y Y Y Y

Programmable voltage detector (PVD)

OOOOO

(2)

R -R-R---- --

R -R-R-O

-R-R-R-R -R

YYYYYYY- --

OOOOOO

(1)

Wakeup capability

(4)

-- --

(5)O(5)

- --

VBAT

Wakeup capability

DS13293 Rev 1 29/145

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Functional overview STM32WL55/54xx

Table 7. Functionalities depending on system operating mode

Peripheral

Peripheral voltage monitor (PVM3)

DMAx (x = 1, 2) O O O O R

DMAMUX1 O O O O R

High-speed internal (HSI16) O O O O O

High-speed external (HSE32) O O O

Low-speed internal (LSI) O O O O O

Low-speed external (LSE) O O O O O

Multi-speed internal (MSI) O O O O O

Clock security system (CSS) O O O O R

Clock security system on LSE O O O O O

Run

Sleep

LPRun

LPSleep

OOOOO

(7)O(7)O(7)

(1)

(continued)

Stop 0 Stop 1 Stop 2 Standby Shutdown

Wakeup capability

OOOOO- -- --

-R------ --

(6)

-O

(7)

-O

(6)

-O

(7)

-O

---- --

(7)

-O

-- --

-O-O-O-- --

-O-O-O-O -O

-O-O---- --

-R------ --

OOOOOOO- --

VBAT

RTC/auto wakeup O O O O O

Number of tamper pins 3 3 3 3 3

USARTx (x= 1, 2) O O O O O

Low-power UART (LPUART1) O O O O O

I2Cx (x = 1, 2) O O O O O

I2C3 O O O O O

SPI1 O O O O R

SUBGHZSPI O O O O R

SPI2S2 O O O O R

ADC O O O O R

DAC O O O O R

VREFBUF O O O O O

COMPx (x = 1, 2) O O O O O

Temperature sensor O O O O R

TIMx (x = 1, 2, 16, 17) O O O O R

LPTIM1 O O O O O

LPTIMx (x = 2, 3) O O O O O

Independent watchdog (IWDG)

OOOOOOOOOOOO- --

OOOOOOOO OO

O3O3O3O3 O3

(8)O(8)O(8)O(8)

(8)O(8)O(8)O(8)O(8)O(8)

(9)O(9)O(9)O(9)

(9)O(9)O(9)O(9)O(9)O(9)

- ---- --

- -- --

- ---- --

- -- --

-R------ --

-O-R---- --

OOOOO- -- --

-R------ --

OOOOO- -- --

OOO- ---- --

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STM32WL55/54xx Functional overview

Table 7. Functionalities depending on system operating mode

(1)

(continued)

Stop 0 Stop 1 Stop 2 Standby Shutdown

Peripheral

Run

Sleep

LPRun

LPSleep

Wakeup capability

VBAT

Wakeup capability

Window watchdog (WWDG) O O O O R -R-R---- --

SysTick timer O O O O R

True random number generator (RNG)

(10)

RRR-R------ --

-R-R---- --

AES hardware accelerator O O O O R -R------ --

PKA hardware accelerator O O O O R

CRC calculation unit O O O O R

IPCC O R O R R

HSEM O R O R R

GTZC TZSC O R O R R

GTZC TZIC O R O R R

-R------ --

-R-R---- --

-R------ --

-R-R---- --

EXTI O O O O R

GPIOs O O O O O OOOOO

1. Legend: Y = Yes (enabled). O = Optional (disabled by default and can be enabled by software). R = data retained.

- = Not available. Gray cells indicate wakeup capability.

2. The SRAM clock can be gated on or off.

3. Flash memory can be placed in power-down mode.

4. The SRAM2 content can optionally be retained when the PWR_CR3.RRS bit is set.

5. Only when the sub-GHz radio is active.

6. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by the peripheral, and only feeds the peripheral that requested it. HSI16 is automatically put off when the peripheral does not need it anymore.

7. HSE32 can be used by sub-GHz radio system.

8. USART reception is functional in Stop 0 and Stop 1 modes. LPUART1 reception is functional is Stop 0, Stop 1, and Stop 2 modes. LPUART1 generates a wakeup interrupt on Start address match or received frame event.

9. I2Cx (x= 1, 2) address detection is functional in Stop 0 and Stop 1 modes. I2C3 address detection is functional in Stop 0, Stop 1 and Stop 2 modes. I2C3 generates a wakeup interrupt in case of address match.

10. Voltage scaling range 1 only.

11. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.

12. The I/Os with wakeup from Standby/Shutdown capability are PA0, PC13 and PB3.

13. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode, but the configuration is lost when exiting the Shutdown mode.

ORORO- -- --

(11)

(12)

(13)

pins

(12)

DS13293 Rev 1 31/145

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Functional overview STM32WL55/54xx

Mode name Entry

Sleep (Sleep-now or Sleep-on-exit)

WFI or return from ISR

WFE Wakeup event

Table 8. Low-power mode summary

Wakeup

(1)

source

Any interrupt

LPRun Set LPR bit Clear LPR bit

Set LPR bit +

LPSleep

WFI or return from ISR

Set LPR bit + WFE

Any interrupt

Wakeup event OFF ON

LPMS = 0b000 +

Stop 0

SLEEPDEEP bit + WFI or return from ISR or WFE

Any EXTI line (configured in the EXTI registers).

Specific peripherals events

Stop 1

Stop 2 (with I2C3,

LPUART1, LPTIM1, SRAM1,

LPMS = 0b001 + SLEEPDEEP bit + WFI or return from ISR or WFE

LPMS = 0b010+ SLEEPDEEP bit + WFI or return from ISR or WFE

SRAM2)

Wakeup

system clock

Same as before entering Sleep mode

Same as LPRun clock

Same as before entering LPSleep mode

HSI16 when STOPWUCK = 1 in RCC_CFGR.

MSI with the frequency before entering the Stop mode when STOPWUCK = 0.

Vol tage

Effect on clocks

regulators

MR LPR

CPU clock OFF No effect on other clocks

ON ON

or analog clock sources

None OFF ON

CPU clock OFF

OFF ON

No effect on other clocks or analog clock sources

All clocks OFF except HSI16, LSI and

LSE

OFF

LPMS = 0b011+

Standby (with SRAM2)

Standby

Set RRS bit + SLEEPDEEP bit + WFI or return from ISR or WFE

LPMS = 0b011 + Clear RRS bit + SLEEPDEEP bit + WFI or return

Wakeup PVD, RFIRQ, wakeup RFBUSY, WKUP pin edge, RTC and TAMP event, LSECSS, external reset in NRST pin, IWDG reset

MSI 4 MHz

from ISR or WFE

LPMS = 0b1xx +

Shutdown

SLEEPDEEP bit + WFI or return from ISR or WFE

1. Refer to Table 7: Functionalities depending on system operating mode.

WKUP pin edge, RTC and TAMP event, external reset in NRST pin

MSI 4 MHz

32/145 DS13293 Rev 1

All clocks OFF

except LSI and LSE

All clocks OFF except LSE

OFF ON

OFF OFF

Page 33

STM32WL55/54xx Functional overview

Relation between MCU and sub-GHz radio operating modes

The CPUs and sub-GHz radio have their own operating modes (see the table below).

Table 9. MCU and sub-GHz radio operating modes

CPU operating mode

Run, Sleep

Sub-GHz radio operating mode Description

Sleep, Calibration, Standby, Active (FS, TX,

RX)

(1)

Deep-Sleep

LDO or SMPS regulator active, MCU running in main regulator (MR) mode

LDO and SMPS regulator off, MCU running in low power regulator (LPR) mode

LPRun, LPSleep

Stop 0

Sleep, Calibration, Standby, Active (FS, TX, RX)

Sleep, Calibration, Standby, Active (FS, TX,

RX)

(1)

Deep-Sleep

LDO or SMPS regulator active, MCU running in low power regulator (LPR) mode

LDO or SMPS regulator active, MCU running in main regulator (MR) mode

LDO and SMPS regulator off, MCU using low power regulator (LPR) mode

Stop 1 and Stop 2

Sleep, Calibration, Standby, Active (FS, TX, RX)

Deep-Sleep

LDO or SMPS regulator active, MCU using low power regulator (LPR) mode

LDO and SMPS regulator off, MCU regulator off or on in low power (LPR) mode

(2)

Standby

Sleep, Calibration, Standby, Active (FS, TX, RX)

Shutdown Deep-Sleep

1. In the MCU Run, Sleep and Stop 0 modes, the sub-GHz radio is prevented from entering Deep-sleep mode.

2. When retaining SRAM2 in Standby mode, the MCU uses the low-power regulator (LPR) mode.

3. When the CPU is in Shutdown mode, the sub-GHz radio cannot be activated and is forced in Deep-sleep mode.

(3)

LDO or SMPS regulator active, MCU regulator off or on in low power (LPR) mode

(2)

LDO and SMPS regulator off, MCU regulator off

3.11.1 Reset mode

In order to improve the consumption under reset, the I/Os state under and after reset is "analog state" (the I/O Schmitt trigger is disabled). In addition, the internal reset pull-up is deactivated when the reset source is internal.

This excludes the five serial-wire JTAG debug ports that are in pull-up/pull-down after reset.

3.12 Peripheral interconnect matrix

Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources and, consequently, reducing power-supply consumption. In addition, these hardware connections allow fast and predictable latency.

Depending on peripherals, these interconnections can operate in Run, Sleep, LPRun, LPSleep, Stop 0, Stop 1 and Stop 2 modes.

DS13293 Rev 1 33/145

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Functional overview STM32WL55/54xx

Table 10. Peripherals interconnect matrix

(1) (2)

Destination

Source

ADC

TIM1

TIM2

TIM16

TIM17

LPTIM1

LPTIM2

LPTIM3

DAC

COMP1

COMP2

DMAMUX1

TIM1 -X- - - - - XXXX - - -

TIM2 X

TIM16

TIM17 X

LPTIM1

LPTIM2

LPTIM3

ADC X

Temperature

sensor

(3)

VBAT

VREFINT

HSE32

- - - - - - XXXX - - -

- - - - - - - - - - - -X-

- - - - - - - - - - -X-

- - - - - -X-X- -X- -

- - - - - - - - - - -X-X

- - - - - - - - - - - -

- - - - - - -X- - - - - -

- - -X- - - - - - - - - -

IRTIM

SUBGHZSPI

LSE

MSI

LSI

MCO

GPIO EXTI

RTC

TAMP

COMP1 XXXXXX

COMP2 XXXXXX

SYST ERR X

1. For more details, refer to section “Interconnection details” of the reference manual.

2. The “-” symbol in grayed cells means no interconnect.

3. VDD on STM32WL55/4UxYx devices.

-XX- - - - - - - - - - -

- - -X- - - - - - - - - -

- -X- - - - - - - - - - -

- - -X- - - - - - - - - -

- - - - - - -XX- -X- -

- -X-XX- - - - - - - -

- - - -XX- - - - - - - -

- - - - - - - -

-XX- - - - - - - - - -

34/145 DS13293 Rev 1

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STM32WL55/54xx Functional overview

3.13 Reset and clock controller (RCC)

The following different clock sources can be used to drive the system clock (SYSCLK):

• HSI16 (high-speed internal) 16 MHz RC oscillator clock

• MSI (multi-speed internal) RC oscillator clock from 100 kHz to 48 MHz

• HSE32 (high-speed external) 32 MHz oscillator clock, with trimming capacitors.

• PLL clock

The MSI is used as system clock source after startup from reset, configured at 4 MHz.

The devices have the following additional clock sources:

• LSI: 32 kHz low-speed internal RC that may drive the independent watchdog and optionally the RTC used for auto-wakeup from Stop and Standby modes.

• LSE: 32.768 kHz low-speed external crystal that optionally drives the RTC used for auto-wakeup from Stop, Standby and Shutdown modes, or the real-time clock (RTCCLK).

Each clock source can be switched on or off independently when it is not used, to optimize power consumption.

Several prescalers can be used to configure the AHB frequencies (HCLK3/PCLK3, HCLK1, HCLK2), the high-speed APB2 (PCLK2) and the low-speed APB1 (PCLK1) domains. The maximum frequency of the AHB (HCLK3, HCLK1, and HCLK2), the PCLK1 and the PCLK2 domains is 48 MHz.

Most peripheral clocks are derived from their bus clock (HCLK, PCLK) except the following:

• The clock used for true RNG, is derived (selected by software) from one of the following sources:

– PLL VCO (PLLQCLK) (only available in Run mode)

– MSI (only available in Run mode)

– LSI clock

– LSE clock

• The ADC clock is derived (selected by software) from one of the following sources:

– system clock (SYSCLK) (only available in Run mode)

– HSI16 clock (only available in Run mode)

– PLL VCO (PLLPCLK) (only available in Run mode)

• The DAC uses the LSI clock in sample and hold mode

• The (LP)U(S)ARTs clocks are derived (selected by software) from one of the following

sources:

– system clock (SYSCLK) (only available in Run mode)

– HSI16 clock (available in Run and Stop modes)

– LSE clock (available in Run and Stop modes)

– APB clock (PCLK depending on which APB the U(S)ART is mapped) (available in

CRun and CSleep when also enabled in (LP)U(S)ARTxSMEN)

The wakeup from Stop mode is supported only when the clock is HSI16 or LSE.

DS13293 Rev 1 35/145

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Functional overview STM32WL55/54xx

• The I2Cs clocks are derived (selected by software) from one of the following sources:

– system clock (SYSCLK) (only available in Run mode)

– HSI16 clock (available in Run and Stop modes)

– APB clock (PCLK depending on which APB the I2C is mapped) (available in CRun

and CSleep when also enabled in I2CxSMEN.)

The wakeup from Stop mode is supported only when the clock is HSI16.

• The SPI2S2 I2S clock is derived (selected by software) from one of the following sources:

– HSI16 clock (only available in Run mode)

– PLL VCO (PLLQCLK) (only available in Run mode)

– external input I2S_CK (available in Run and Stop modes)

• The low-power timers (LPTIMx) clock is derived (selected by software) from one of the following sources:

– LSI clock (available in Run and Stop modes)

– LSE clock (available in Run and Stop modes)

– HSI16 clock (only available in Run mode)

– APB clock (PCLK depending on which APB the LPTIMx is mapped) (available in

Run and CStop when enabled in LPTIMxSMEN.)

– external clock mapped on LPTIMx_IN1 (available in Run and Stop modes)

The functionality in Stop mode (including wakeup) is supported only when the clock is LSI or LSE, or in external clock mode.

• The RTC clock is derived (selected by software) from one of the following sources:

– LSE clock

– LSI clock

– HSE32 clock divided by 32

The functionality in Stop mode (including wakeup) is supported only when the clock is LSI or LSE.

• The IWDG clock is always the LSI clock.

The RCC feeds the CPU1 system timer (SysTick) external clock with the AHB clock (HCLK1) divided by eight. The SysTick can work either with this clock or directly with the CPU1 clock (HCLK1), configurable in the SysTick control and status register.

FCLK1 acts as CPU1 free-running clock. For more details, refer to the programming manual STM32 Cortex-M4 MCUs and MPUs programming manual (PM0214).

The RCC feeds the CPU2 system timer (SysTick) external clock with the AHB clock (HCLK2) divided by eight. The SysTick can work either with this clock or directly with the CPU2 clock (HCLK2), configurable in the SysTick control and status register.

FCLK2 acts as CPU2 free-running clock.

36/145 DS13293 Rev 1

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STM32WL55/54xx Functional overview

MSv62604V2

LSI RCC 32 kHz

LSE OSC

32.768 kHz

LSCO

to IWDG

HSE32 OSC

32 MHz

HSE CSS

OSC_IN

OSC_OUT

HSI16 RC

16 MHz

MSI RC

100 kHz - 48 MHz

MCO

/1 - 16

/32

LSE CSS

PLL

SYSCLK

MSI

HSI16

HSE32

PLLRCLK

LSE

LSI

SYS clock

source control

SYSCLK

MSI

HSI16

CPU1

HPRE

/1,2,...,512

HCLK1

HCLK2

HCLK3

APB1

PPRE1

/1,2,4,8,16

to CPU1, AHB1, AHB2

to CPU1 FCLK

to CPU1 system timer

APB2

PPRE2

/1,2,4,8,16

PCLK1

PCLK2

to CPU2

to CPU2 FCLK

to CPU2 system timer

to AHB3, Flash, SRAM1, SRAM2

to APB1 TIMx

to APB2 TIMx

to USART1 to LPTIM1

to LPUART1

to ADC

to RTC

x1 or

to I2C1

PCLKn

SYSCLK

HSI16

PCLKn

LSI

LSE

PLLPCLK

SYSCLK

PCLKn

LSE

to APB2

to APB1

to RF

SYSCLK

MSI

to RNG

PLLQCLK

PLLRCLK

OSC32_IN

OSC32_OUT

LSI

LSE

LSI

LSE

HSEPRE

/1,2

to I2C2 to I2C3

to LPTIM3

to LPTIM2

PCLK3 to APB3

to USART2

HSI16

to SPI2S2

I2S_CKIN

HSI16

PLLPCLK

PLLQCLK

LSIPRE

/1,128

CPU2

C2HPRE

1,2,...,512

AHB3

SHDHPRE

/1,2,...,512

LSI DAC

Figure 8. Clock tree

DS13293 Rev 1 37/145

1. For full details about the internal and external clock source characteristics, refer to the electrical characteristics section in the device datasheet.

2. The ADC clock can additionally be derived from the AHB clock of the ADC bus interface, divided by a programmable factor (1, 2 or 4). When the programmable factor is 1, the AHB prescaler must be equal to 1.

3.14 Hardware semaphore (HSEM)

The HSEM provides a 16- (32-bit) register based semaphores. The semaphores can be used to ensure synchronization between different processes running between different cores. The HSEM provides a non blocking mechanism to lock semaphores in an atomic way. The following functions are provided:

• Locking a semaphore can be done in two ways:

– 2-step lock: by writing COREID and PROCID to the semaphore, followed by a

read check

– 1-step lock: by reading the COREID from the semaphore

• Interrupt generation when a semaphore is unlocked: Each semaphore may generate an interrupt on one of the interrupt lines.

Page 38

Functional overview STM32WL55/54xx

• Semaphore clear protection: A semaphore is only unlocked when COREID and PROCID match.

• Global semaphore clear per COREID

3.15 Inter-processor communication controller (IPCC)

The IPCC is used for communicating data between two processors.

The IPCC block provides a non blocking signaling mechanism to post and retrieve communication data in an atomic way. It provides the signaling for twelve channels:

• six channels in the direction from processor 1 to processor 2

• six channels in the opposite direction

It is then possible to have two different communication types in each direction.

The IPCC communication data must be located in a common memory, that is not part of the IPCC block.

3.16 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be achieved thanks to their mapping on the AHB2 bus.

The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.

3.17 Direct memory access controller (DMA)

The DMA (direct memory access) is used to provide high-speed data transfer between peripherals and memory, as well as memory to memory. Data can be quickly moved by DMA without any CPU actions. This keeps CPU resources free for other operations.

The DMA controller has 14 channels in total. A full cross matrix allows the peripherals, with DMA support, to be mapped on any of the available DMA channels. Each DMA channel has an arbiter for handling the priority between DMA requests.

The DMA main features are listed below:

• 14 independently configurable channels (requests)

• a full cross matrix between peripherals and all 14 channels and an hardware trigger

possibility through the DMAMUX1

• software programmable priorities between requests from channels of one DMA (four levels: very-high, high, medium, low), plus hardware priorities management in case of equality (example: request 1 has priority over request 2)

• independent source and destination transfer size (byte, half-word, word), emulating packing and unpacking. Source/destination addresses must be aligned on the data size.

• support for circular buffer management

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STM32WL55/54xx Functional overview

• three event flags (DMA half-transfer, DMA transfer complete and DMA transfer error), logically ORed together in a single interrupt request for each channel

• memory-to-memory transfer

• peripheral-to-memory, memory-to-peripheral, and peripheral-to-peripheral transfers

• access to Flash memory, SRAM, APB and AHB peripherals, as source and destination

• programmable number of data to be transferred (up to 65536)

• secure and privileged support per channel level configuration

Feature DMA1 DMA2

Number of channels 7 7

Table 11. DMA1 and DMA2 implementation

DMAMUX1 is used to route the peripherals with DMA source support, to any DMA channel.

3.18 Interrupts and events

3.18.1 Nested vectored interrupt controller (NVIC)

The devices embed an NIVC able to manage 16 priority levels, and to handle up to 62 maskable interrupt channels plus the 16 interrupt lines of the Cortex-M4.

The device also embeds an NVIC able to manage four priority levels, and handles up to 32 maskable interrupt channels plus the 16 interrupt lines of the Cortex-M0+.

The NVIC benefits are the following:

• low-latency interrupt processing

• interrupt entry vector table address passed directly to the core

• early processing of interrupts

• processing of late-arriving higher-priority interrupts

• support for tail chaining

• processor state automatically saved

• interrupt entry restored on interrupt exit, with no instruction overhead

The NVIC hardware block provides flexible interrupt management features with minimal interrupt latency.

3.18.2 Extended interrupt/event controller (EXTI)

The EXTI manages wakeup through configurable and direct event inputs. It provides wakeup requests to the power control, and generates interrupt requests to the CPU1/2 NVIC and events to the CPU1/2 event input.

Configurable events/interrupts come from peripherals that are able to generate a pulse and allow the selection between the event/interrupt trigger edge and a software trigger.

Direct events/interrupts come from peripherals having their own clearing mechanism.

DS13293 Rev 1 39/145

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Functional overview STM32WL55/54xx

3.19 Cyclic redundancy check (CRC)

The CRC calculation unit is used to get a CRC code from 8-, 16- or 32-bit data word and a generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the functional safety standards, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps to compute a signature of he software during runtime, to be compared with a reference signature generated at link time and stored at a given memory location.

3.20 Analog-to-digital converter (ADC)

A native 12-bit ADC is embedded into the devices. It can be extended to 16-bit resolution through hardware oversampling. The ADC has up to 12 external channels and four internal channels (temperature sensor, voltage reference, V ADC performs conversions in single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs.

The ADC frequency is independent from the CPU1/2 frequency, allowing maximum sampling rate of ~2 Msps even with a low CPU speed. An auto-shutdown function guarantees that the ADC is powered off except during the active conversion phase.

(a)

monitoring, DAC output). The

BAT

The ADC can be served by the DMA controller. It can operate in the whole V range.

The ADC features a hardware oversampler up to 256 samples, improving the resolution to 16 bits. Refer to the application note Improving STM32F1 Series, STM32F3 Series and STM32Lx Series ADC resolution by oversampling (AN2668).

An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all scanned channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

The events generated by the general-purpose timers (TIMx) can be internally connected to the ADC start triggers, to allow the application to synchronize A/D conversions with timers.

3.20.1 Temperature sensor

The temperature sensor (TS) generates a VTS voltage that varies linearly with temperature.

The temperature sensor is internally connected to the ADC VIN[12] input channel, to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor may vary from part to part due to process variation, the uncalibrated internal temperature sensor is suitable only for relative temperature measurements.

To improve the accuracy of the temperature sensor, each part is individually factorycalibrated by ST. The resulting calibration data is stored in the device engineering bytes, accessible in read-only mode.

supply

a. VDD on STM32WL55/54UxYx devices.

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STM32WL55/54xx Functional overview

Calibration value

name

TS_CAL1

TS_CAL2

Table 12. Temperature sensor calibration values

TS ADC raw data acquired at 30 °C (± 5 °C), V

= V

DDA

TS ADC raw data acquired at 130 °C (± 5 °C), V

= V

DDA

= 3.3 V (± 10 mV)

REF+

= 3.3 V (± 10 mV)

REF+

3.20.2 Internal voltage reference (V

V is internally connected to the ADC VIN[13] input channel.

V and stored in the device engineering bytes. It is accessible in read-only mode.

provides a stable (bandgap) voltage output for the ADC and comparators. V

REFINT

is individually and precisely measured, for each part, by ST, during production test

REFINT

Table 13. Internal voltage reference calibration values

Calibration value name Description Memory address

VREFINT_CAL

Raw data acquired at 30 °C (± 5 °C),

= V

DDA

REF+

Description Memory address

0x1FFF 75A8 - 0x1FFF 75A9

0x1FFF 75C8 - 0x1FFF 75C9

REFINT

)

= 3.3 V (± 10 mV)

0x1FFF 75AA - 0x1FFF 75AB

REFINT

3.20.3 V

battery voltage monitoring

BAT

This embedded hardware feature allows the application to measure the V voltage using the ADC VIN[14] input channel. As V outside the ADC input range, the VBAT pin is internally connected to a bridge divider by three. As a consequence, the converted digital value is one third the V

3.21 Digital-to-analog converter (DAC)

The 1-channel 12-bit buffered DAC converts a digital value into an analog voltage available on the channel output. The architecture of each channel is based on an integrated resistor string and an inverting amplifier. The digital circuitry is common for both channels.

DAC main features:

• 1 DAC output channel

• 8-bit or 12-bit output mode

• buffer offset calibration (factory and user trimming)

• left or right data alignment in 12-bit mode

• synchronized update capability

• noise-wave generation

• triangular-wave generation

• independent or simultaneous conversion for DAC channels

may be higher than V

BAT

voltage.

BAT

(a)

battery

, and thus

DDA

a. VDD on STM32WL55/54UxYx devices.

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Functional overview STM32WL55/54xx

• DMA capability for either DAC channel

• triggering with timer events, synchronized with DMA

• triggering with external events

Sample-and-hold low-power mode, with internal or external capacitor

3.22 Voltage reference buffer (VREFBUF)

The devices embed a voltage reference buffer that can be used as voltage reference for ADC, and also as voltage reference for external components through the VREF+ pin.

VREFBUF supports two voltages: 2.048 V and 2.5 V.

An external voltage reference can be provided through the VREF+ pin when VREFBUF is off.

3.23 Comparator (COMP)

The devices embed two rail-to-rail comparators with programmable reference voltage (internal or external), hysteresis and speed (low speed for low-power) and with selectable output polarity.

The reference voltage can be one of the following:

• external I/O

• internal reference voltage or submultiple (1/4, 1/2, 3/4)

All comparators can wake up from Stop mode, generate interrupts and breaks for the timers, and can be also combined into a window comparator.

3.24 True random number generator (RNG)

The devices embed a true RNG that delivers 32-bit random numbers generated by an integrated analog circuitry.

3.25 Advanced encryption standard hardware accelerator (AES)

The AES encrypts or decrypts data, using an algorithm and implementation fully compliant with the advanced encryption standard (AES) defined in FIPS (federal information processing standards) publication 197.

Multiple chaining modes are supported (ECB, CBC, CTR, GCM, GMAC, CCM), for key sizes of 128 or 256 bits. The AES supports DMA single transfers for incoming and outgoing data (two DMA channels required).

3.26 Public key accelerator (PKA)

The PKA is used to compute cryptographic public key primitives, specifically those related to RSA (Rivest, Shamir and Adleman), Diffie-Hellmann or ECC (elliptic curve cryptography) over GF(p) (Galois fields). These operations are executed in the Montgomery domain.

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STM32WL55/54xx Functional overview

3.27 Timer and watchdog

The devices include one advanced 16-bit timer, one general-purpose 32-bit timer, two 16-bit basic timers, three low-power timers, two watchdog timers and a SysTick timer.

The table below compares the features of the advanced control, general purpose and basic timers.

Table 14. Timer features

Counter

resolution

(bits)

16 Up

Counter

type

Up, down

and

up/down

Prescaler

Any integer

1 and 65536

Timer type

Advanced control

General purpose

Low power

Timer name

TIM1 16

TIM2 32 NA

TIM16

TIM17

LPTIM1 LPTIM2 LPTIM3

3.27.1 Advanced-control timer (TIM1)

The advanced-control timer TIM1 can be seen as a three-phase PWM multiplexed on six channels. Each channel has complementary PWM outputs with programmable inserted dead-times. Each channel can also be seen as complete general-purpose timers.

The four independent channels can be used for:

• input capture

• output compare

• PWM generation (edge or center-aligned modes) with full modulation capability

(0 - 100 %)

• one-pulse mode output

factor

between

DMA

request

generation

Yes

Capture/ compare channels

Complementary

outputs

In debug mode, the TIM1 counter can be frozen and the PWM outputs disabled to turn off any power switches driven by these outputs.

Many features are shared with those of the general-purpose timers (described in the next section) using the same architecture. TIM1 can then work together with TIM2 via the peripheral interconnect matrix, for synchronization or event chaining.

3.27.2 General-purpose timers (TIM2, TIM16, TIM17)

Each general-purpose timer can be used to generate PWM outputs, or act as a simple time base.

TIM2 main features:

• full-featured general-purpose timer

• four independent channels for input capture/output compare, PWM or one-pulse mode

output

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Functional overview STM32WL55/54xx

• counter that can be frozen in debug mode

• independent DMA request generation, support of quadrature encoders

TIM16 and TIM17 main features:

• general-purpose timers with mid-range features

• 16-bit auto-reload upcounters and 16-bit prescalers

• 1 channel and 1 complementary channel

• channels that can all be used for input capture/output compare, PWM or one-pulse

mode output

• counter that can be frozen in debug mode

• independent DMA request generation

3.27.3 Low-power timers (LPTIM1, LPTIM2 and LPTIM3)

These low-power timers have an independent clock and run in Stop mode if they are clocked by LSE, LSI, or by an external clock. They are able to wake up the system from Stop mode.

LPTIM1 is active in Stop 0, Stop 1 and Stop 2 modes.

LPTIM2 and LPTIM3 are active in Stop 0 and Stop 1 modes.

LPTIM1/2/3 main features:

• 16-bit up counter with 16-bit autoreload register

• 16-bit compare register

• configurable output: pulse, PWM

• continuous/one-shot mode

• selectable software/hardware input trigger

• selectable clock source

• internal clock sources: LSE, either LSI, HSI16 or APB clock

• external clock source over LPTIM input (works even with no internal clock source

running, used by pulse counter application)

• programmable digital glitch filter

• encoder mode (LPTIM1 only)

3.27.4 Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and a 8-bit prescaler. The IWDG is clocked from an independent 32 kHz internal RC (LSI). As the IWDG operates independently from the main clock, it can operate in Stop and Standby modes.

The IWDG can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. The IWDG is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.

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STM32WL55/54xx Functional overview

3.27.5 System window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free running. The WWDG can be used as a watchdog to reset the device when a problem occurs.

The WWDG is clocked from the main clock and has an early warning interrupt capability. The counter can be frozen in debug mode.

3.27.6 SysTick timer

This timer is dedicated to real-time operating systems, but can also be used as a standard down counter.

SysTick timer main features:

• 24-bit down counter

• autoreload capability

• maskable system interrupt generation when the counter reaches 0

• programmable clock source

3.28 Real-time clock (RTC), tamper and backup registers

The RTC is an independent BCD timer/counter. The RTC provides a time-of-day clock/calendar with programmable alarm interrupts.

As long as the supply voltage remains in the operating range, the RTC never stops, regardless of the device status (Run mode, low-power mode or under reset).

The RTC provides an automatic wakeup to manage all low-power modes.

The RTC is functional in VBAT mode.

Twenty 32-bit backup registers are retained in all low-power modes and also in VBAT mode. These registers can be used to store sensitive data as their content is protected by a tamper detection circuit.

Three tamper pins and four internal tampers are available for anti-tamper detection. The external tamper pins can be configured for edge or level detection with or without filtering.

3.29 Inter-integrated circuit interface (I2C)

The device embeds three I2Cs, with features implementation listed in the he table below.

The I

C bus interface handles communications between the microcontroller and the serial

C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.

The I2C peripheral supports:

• I

C bus specification and user manual rev. 5 compatibility:

– slave and master modes, multimaster capability

– Standard-mode (Sm), with a bitrate up to 100 Kbit/s

– Fast-mode (Fm), with a bitrate up to 400 Kbit/s

– Fast-mode plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os

– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses

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Functional overview STM32WL55/54xx

– programmable setup and hold times

– clock stretching (optional)

• SMBus (system management bus) specification rev 2.0 compatibility:

– hardware PEC (packet error checking) generation and verification with ACK

control

– address resolution protocol (ARP) support

– SMBus alert

• PMBus (power system management protocol) specification rev 1.1 compatibility

• independent clock: a choice of independent clock sources allowing the I

communication speed to be independent from the PCLK reprogramming (see Figure 8)

• wakeup from Stop mode on address match

• programmable analog and digital noise filters

• 1-byte buffer with DMA capability

I2C features

7-bit addressing mode X X X

10-bit addressing mode X X X

Standard-mode (up to 100 Kbit/s) X X X

Table 15. I2C implementation

(1)

I2C1

(2)

I2C2

(2)

I2C3

Fast-mode (up to 400 Kbit/s) X X X

Fast-mode Plus with 20mA output drive I/Os (up to 1 Mbit/s) X X X

Independent clock X X X

Wakeup from Stop mode X

SMBus/PMBus X X X

1. X = supported.

2. The register content is lost in Stop 2 mode.

3. Wakeup supported from Stop 0 and Stop 1 modes.

4. Wakeup supported from Stop 0, Stop 1 and Stop 2 modes.

(3)

(4)

3.30 Universal synchronous/asynchronous receiver transmitter (USART/UART)

The devices embed two universal synchronous receiver transmitters, USART1 and USART2 (see Table 16 for the implementation details).

Each USART provides asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode. Each USART has LIN Master/Slave capability and provides hardware management of the CTS and RTS signals, and RS485 driver enable.

The USART is able to communicate at speeds of up to 4 Mbit/s, and also provides Smart Card mode (ISO 7816 compliant) and SPI-like communication capability.

The USART supports synchronous operation (SPI mode), and can be used as an SPI master.

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STM32WL55/54xx Functional overview

The USART has a clock domain independent from the CPU clock, allowing the USART to wake up the MCU from Stop mode, using baudrates up to 200 kbaud.

The wakeup events from Stop mode are programmable and can be one of the following:

• start bit detection

• any received data frame

• a specific programmed data frame

The USART interface can be served by the DMA controller.

3.31 Low-power universal asynchronous receiver transmitter (LPUART)

The devices embed one low-power UART (LPUART1) that enables asynchronous serial communication with minimum power consumption. The LPUART supports half-duplex single-wire communication and modem operations (CTS/RTS), allowing multiprocessor communication.

The LPUART has a clock domain independent from the CPU clock, and can wake up the system from Stop mode using baudrates up to 220 Kbaud. The wakeup events from Stop mode are programmable and can be one of the following:

• start bit detection

• any received data frame

• a specific programmed data frame

Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while having an extremely low-energy consumption. Higher speed clock can be used to reach higher baudrates.

The LPUART interface can be served by the DMA controller.

USART modes/features

Hardware flow control for modem X X

Continuous communication using DMA X X

Multiprocessor communication X X

Synchronous mode (Master/Slave) X -

Smartcard mode X -

Single-wire half-duplex communication X X

IrDA SIR ENDEC block X -

LIN mode X -

Dual clock domain and wakeup from low-power mode X X

Receiver timeout interrupt X -

Modbus communication X -

Auto baud rate detection X -

Table 16. USART/LPUART features

(1)

USART1/2 LPUART1

DS13293 Rev 1 47/145

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Functional overview STM32WL55/54xx

Table 16. USART/LPUART features (continued)

USART modes/features

Driver enable X X

USART data length 7, 8 and 9 bits

Tx/Rx FIFO X X

Tx/Rx FIFO size 8

1. X = supported.

(1)

USART1/2 LPUART1

3.32 Serial peripheral interface (SPI)/integrated-interchip sound interface (I2S)

The SPI/I2S interface can be used to communicate with external devices using the SPI protocol or the I

S audio protocol. SPI or I2S mode is selectable by software. SPI Motorola®

mode is selected by default after a device reset.

The SPI protocol supports half-duplex, full-duplex and simplex synchronous, serial communication with external devices. The SPI interface can be configured as master and, in this case, it provides the communication clock (SCK) to the external slave device. The SPI interface can also operate in multimaster configuration.

The I

S protocol is also a synchronous serial communication interface. It can operate in slave or master mode with half-duplex communication. It can address four different audio standards including the Philips I

S standard, the MSB- and LSB-justified standards and the

PCM standard.

Features SPI1 SPI2S2 SUBGHZSPI

Enhanced NSSP and TI modes Yes

Hardware CRC calculation Yes Yes No

S support No Yes No

Data size configurable (bits) from 4 to 16

Rx/Tx FIFO size (bits) 32

Wakeup capability from LPSleep Yes

1. The SPI1 and SPI2S2 instances are general purpose type while the SUBGHZSPI instance is dedicated for

Sub-GHz radio control exclusively. Radio is controlled internally through SUBGHZSPI and, for debug purpose only, from the external.

Table 17. SPI and SPI/I2S implementation

(1)

3.33 Development support

Serial-wire JTAG debug port (SWJ-DP)

The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial-wire debug port, that enables either a serial-wire debug or a JTAG probe to be connected to the target.

The debug is performed using only two pins instead of the five required by the JTAG (JTAG pins can then be reused as GPIOs with alternate function). The JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

48/145 DS13293 Rev 1

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STM32WL55/54xx Pinouts, pin description and alternate functions

MSv48144V4

PB3

PB4

PB5

PB6

PB7

PB8

PA0

PA1

PA2

PA3

VDD

PA4

PA5

PA6

PA9

RFI_P

VR_PA

PA7

PA8

RFI_N

NRST

PH3-BOOT0

RFO_LP

RFO_HP

PA13

PA12

PA11

PA10

PB12

PB2

PB0-VDD_TCXO

VDDRF1V55

VDDRF

OSC_OUT

OSC_IN

VDDPA

VSSSMPS

VLXSMPS

VDD

VDDA

VBAT

VDDSMPS

VFBSMPS

PC15-OSC32_OUT

PA15

PA14

PC14-OSC32_IN

PC13

UFQFPN48

136

393740

484746

222421

131415

4 Pinouts, pin description and alternate functions

Figure 9. UFQFPN48 pinout

1. The above figure shows the package top view.

2. The exposed pad must be connected to the ground plain.

DS13293 Rev 1 49/145

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Pinouts, pin description and alternate functions STM32WL55/54xx

MSv48145V4

143987652

PA4

PA3

PC1

PB6

PB3

VLXSMPS

VSSSMPS

PA5

PA2

PC6

PC0

VDD

PB5

PB4

VFBSMPS

VDDSMPS

PA8

PA7

PA1

PC4

VSS

PB8

PB7

PA15

PB10

PB11

PA6

PC5

PC2

PB9

PB15

PA14

PC3

PC15-

OSC32

_OUT

VREF+

VDDA

RFI_P

VSSRF

PB0-

VDD_TCXO

PA0

PB14

PC14-

OSC32_IN

VDDRF

1V55

PB13

PC13

VSS

VDD

OSC_OUT

PB2

PA10

PA13

VBAT

VSS

PA11

PA12

PA9 PB12 PB1 VDDRF VDD

NRST

VSS

PH3-

BOOT0

VDD RFI_N

VSSRF

RFO_LP

VDDPA

VSSRF

RFO_HP

VR_PA

OSC_IN

Figure 10. UFBGA73 pinout

1. The above figure shows the package top view.

Table 18. Legend/abbreviations used in the pinout table

Name Abbreviation Definition

Pin name

Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name

S Supply pin

I Input only pin

Pin type

I/O Input / output pin

O Output only pin

I/O structure

RF Radio RF pin

TT 3 V tolerant I/O

_f I/O, Fm+ capable

FT 5 V tolerant I/O

_a I/O, with Analog switch function supplied by V

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DDA

Page 51

STM32WL55/54xx Pinouts, pin description and alternate functions

Table 18. Legend/abbreviations used in the pinout table (continued)

Name Abbreviation Definition

Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset.

Functions selected through GPIOx_AFR registers

Functions directly selected/enabled through peripheral registers

Table 19. STM32WL55/54xx pin definition

functions

Notes

Alternate functions

Additional

functions

Pin number

Pin name

WLCSP59

UFQFPN48

(function after

UFBGA73

reset)

Pin type

Notes

I/O structure

Alternate functions Additional functions

- E10 - VSS S - - - -

1D11C1 PB3 I/OFT_a-

JTDO/TRACESWO,

TIM2_CH2, SPI1_SCK,

RF_IRQ0, USART1_RTS,

DEBUG_RF_DTB1,

CM4_EVENTOUT

COMP1_INM, COMP2_INM,

ADC_IN2,

TAMP_IN3/WKUP3

NJTRST, I2C3_SDA,

2D9C2 PB4 I/OFT_fa-

SPI1_MISO, USART1_CTS,

DEBUG_RF_LDORDY,

TIM17_BKIN,

COMP1_INP, COMP2_INP,

ADC_IN3

CM4_EVENTOUT

LPTIM1_IN1, I2C1_SMBA,

SPI1_MOSI, RF_IRQ1,

3-D2 PB5 I/OFT_a-

USART1_CK, COMP2_OUT,

TIM16_BKIN,

CM4_EVENTOUT

- F7 E3 VSS S - - - -

- F11 E2 VDD S - - - -

4 - E1 PB6 I/O FT_f -

5-C3 PB7 I/OFT_f-

6-D3 PB8 I/OFT_f-

DS13293 Rev 1 51/145

LPTIM1_ETR, I2C1_SCL,

USART1_TX, TIM16_CH1N,

CM4_EVENTOUT

LPTIM1_IN2, TIM1_BKIN,

I2C1_SDA, USART1_RX,

TIM17_CH1N,

CM4_EVENTOUT

TIM1_CH2N, I2C1_SCL,

RF_IRQ2, TIM16_CH1,

CM4_EVENTOUT

Page 52

Pinouts, pin description and alternate functions STM32WL55/54xx

Table 19. STM32WL55/54xx pin definition (continued)

Pin number

Pin name

(function after

reset)

UFBGA73

WLCSP59

UFQFPN48

--C4 PB9 I/OFT_f-

- - F2 PC0 I/O FT_f -

- - F1 PC1 I/O FT_f -

--D4 PC2 I/OFT-

--D5 PC3 I/OFT-

- - F3 PC4 I/O FT - CM4_EVENTOUT -

Pin type

Notes

I/O structure

Alternate functions Additional functions

TIM1_CH3N, I2C1_SDA,

SPI2_NSS/I2S2_WS,

IR_OUT, TIM17_CH1,

CM4_EVENTOUT

LPTIM1_IN1, I2C3_SCL,

LPUART1_RX, LPTIM2_IN1,

CM4_EVENTOUT

LPTIM1_OUT,

SPI2_MOSI/I2S2_SD,

I2C3_SDA, LPUART1_TX,

CM4_EVENTOUT

LPTIM1_IN2, SPI2_MISO,

CM4_EVENTOUT

LPTIM1_ETR,

SPI2_MOSI/I2S2_SD,

LPTIM2_ETR,

CM4_EVENTOUT

- - E4 PC5 I/O FT - CM4_EVENTOUT -

- - G2 PC6 I/O FT - I2S2_MCK, CM4_EVENTOUT -

TIM2_CH1, I2C3_SMBA,

I2S_CKIN, USART2_CTS,

7H11D6 PA0 I/OFT_a-

TIM2_ETR, CM4_EVENTOUT

8 G10 G3 PA1 I/O FT_a -

9F9H2 PA2 I/OFT_a-

10 C8 H1 PA3 I/O FT_a -

- E6 G5 VSS S - - - -

USART2_RX, LPUART1_RX,

COMP1_OUT,

DEBUG_PWR_REGLP1S,

TIM2_CH2, LPTIM3_OUT,

I2C1_SMBA, SPI1_SCK,

USART2_RTS,

LPUART1_RTS,

DEBUG_PWR_REGLP2S,

CM4_EVENTOUT

LSCO, TIM2_CH3,

USART2_TX, LPUART1_TX,

COMP2_OUT,

DEBUG_PWR_LDORDY,

CM4_EVENTOUT

TIM2_CH4, I2S2_MCK,

CM4_EVENTOUT

TAMP_IN2/WKUP1

LSCO

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STM32WL55/54xx Pinouts, pin description and alternate functions

Table 19. STM32WL55/54xx pin definition (continued)

Pin number

Pin name

(function after

Notes

I/O structure

WLCSP59

UFQFPN48

reset)

Pin type

UFBGA73

11 K11 H 5 VDD S - - - -

12 J10 J1 PA4 I/O FT -

13 H9 J2 PA5 I/O FT -

14 G8 F4 PA6 I/O FT -

15 E8 H3 PA7 I/O FT_fa -

Alternate functions Additional functions

RTC_OUT2, LPTIM1_OUT,

SPI1_NSS, USART2_CK,

DEBUG_SUBGHZSPI_

NSSOUT, LPTIM2_OUT,

CM4_EVENTOUT

TIM2_CH1, TIM2_ETR,

SPI2_MISO, SPI1_SCK,

DEBUG_SUBGHZSPI_

SCKOUT, LPTIM2_ETR,

CM4_EVENTOUT

TIM1_BKIN, I2C2_SMBA,

SPI1_MISO, LPUART1_CTS,

DEBUG_SUBGHZSPI_

MISOOUT, TIM16_CH1,

CM4_EVENTOUT

TIM1_CH1N, I2C3_SCL,

SPI1_MOSI, COMP2_OUT,

DEBUG_SUBGHZSPI_

MOSIOUT, TIM17_CH1,

CM4_EVENTOUT

MCO, TIM1_CH1,

16 L10 J3 PA8 I/O FT_a -

SPI2_SCK/I2S2_CK,

USART1_CK, LPTIM2_OUT,

CM4_EVENTOUT

TIM1_CH2,

SPI2_NSS/I2S2_WS,

17 K9 E5 PA9 I/O FT_fa -

I2C1_SCL,

SPI2_SCK/I2S2_CK,

USART1_TX,

CM4_EVENTOUT

TIM2_CH3, I2C3_SCL,

- - H4 PB10 I/O FT_f -

SPI2_SCK/I2S2_CK,

LPUART1_RX, COMP1_OUT,

CM4_EVENTOUT

TIM2_CH4, I2C3_SDA,

--G4 PB11 I/OFT_f-

LPUART1_TX, COMP2_OUT,

CM4_EVENTOUT

18 J8 F5 NRST I/O FT - - -

19 H7 J5 PH3-BOOT0 I/O FT - CM4_EVENTOUT BOOT0

-L8- VDD S - - - -

DS13293 Rev 1 53/145

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Pinouts, pin description and alternate functions STM32WL55/54xx

Table 19. STM32WL55/54xx pin definition (continued)

Pin number

Pin name

(function after

reset)

UFBGA73

WLCSP59

UFQFPN48

- K7 - VSS S - - - -

- J6 H6 VSSRF S - - - -

- H5 G6 VSSRF S - - - -

20 L6 J6 RFI_P I RF - - -

21 K5 H7 RFI_N I RF - - -

- G4 G7 VSSRF S - - - -

- J4 - VSSRF S - - - -

22 L4 J8 RFO_LP O RF - - -

- - G8 VSSRF S - - - -

Pin type

Notes

I/O structure

Alternate functions Additional functions

23 K3 J9 RFO_HP O RF - - -

- H3 - VSSRF S - - - -

24 L2 H9 VR_PA S - - - -

25 H1 H8 VDDPA S - - - -

- K1 - VSSRF S - - - -

26 G2 G9 OSC_IN I RF - - -

27 F1 F8 OSC_OUT O RF - - -

- F3 - VSSRF S - - - -

28 E2 E8 VDDRF S - - - -

29 D1 F7 VDDRF1V55 S - - - -

- F5 D9 VSS S - - - -

- - E9 VDD S - - - -

30 B1 F6 PB0-VDD_TCXO I/O TT -

- - E7 PB1 I/O FT_a -

31 - D8 PB2 I/O FT_a -

32 - E6 PB12 I/O FT -

COMP1_OUT,

CM4_EVENTOUT

LPUART1_RTS_DE,

LPTIM2_IN1,

CM4_EVENTOUT

LPTIM1_OUT, I2C3_SMBA,

SPI1_NSS,

DEBUG_RF_SMPSRDY,

CM4_EVENTOUT

TIM1_BKIN, I2C3_SMBA,

SPI2_NSS/I2S2_WS,

LPUART1_RTS,

CM4_EVENTOUT

COMP2_INP,

ADC_IN5

COMP1_INP,

COMP2_INM,

ADC_IN4

54/145 DS13293 Rev 1

Page 55

STM32WL55/54xx Pinouts, pin description and alternate functions

Table 19. STM32WL55/54xx pin definition (continued)

Pin number

Pin name

(function after

Notes

I/O structure

WLCSP59

UFQFPN48

reset)

Pin type

UFBGA73

- - D7 PB13 I/O FT_fa -

- - C6 PB14 I/O FT_fa -

33 D3 C8 PA10 I/O FT_fa -

34 E4 B9 PA11 I/O FT_fa -

35 D5 A9 PA12 I/O FT_fa -

36 D7 B8 PA13 I/O FT_a -

- C2 B7 VSS S - - - -

-A2A7 VDD S - - - -

Alternate functions Additional functions

TIM1_CH1N, I2C3_SCL,

SPI2_SCK/I2S2_CK,

LPUART1_CTS,

ADC_IN0

CM4_EVENTOUT

TIM1_CH2N, I2S2_MCK,

I2C3_SDA, SPI2_MISO,

ADC_IN1

CM4_EVENTOUT

RTC_REFIN, TIM1_CH3,

I2C1_SDA,

SPI2_MOSI/I2S2_SD,

USART1_RX,

DEBUG_RF_HSE32RDY,

TIM17_BKIN,

COMP1_INM, COMP2_INM,

DAC_OUT1,

ADC_IN6

CM4_EVENTOUT

TIM1_CH4, TIM1_BKIN2,

LPTIM3_ETR, I2C2_SDA,

SPI1_MISO, USART1_CTS,

DEBUG_RF_NRESET,

COMP1_INM, COMP2_INM,

ADC_IN7

CM4_EVENTOUT

TIM1_ETR, LPTIM3_IN1,

I2C2_SCL, SPI1_MOSI,

RF_BUSY, USART1_RTS,

ADC_IN8

CM4_EVENTOUT

JTMS-SWDIO, I2C2_SMBA,

IR_OUT, CM4_EVENTOUT

ADC_IN9

37 - A8 VBAT S - - - -

TAMP_IN1/

38 - C7 PC13 I/O FT - CM4_EVENTOUT

RTC_OUT1/RTC_TS/

WKUP2

39 B3 B6 PC14-OSC32_IN I/O FT - CM4_EVENTOUT OSC32_IN

40 A4 C5

PC15-

OSC32_OUT

I/O FT - CM4_EVENTOUT OSC32_OUT

- - B5 VREF+ S - - - -

41 B5 A5 VDDA S - - - -

- C4 - VSS S - - - -

DS13293 Rev 1 55/145

Page 56

Pinouts, pin description and alternate functions STM32WL55/54xx

Table 19. STM32WL55/54xx pin definition (continued)

Pin number

Pin name

(function after

WLCSP59

UFQFPN48

reset)

UFBGA73

Pin type

I/O structure

42 C6 A4 PA14 I/O FT_a -

Notes

Alternate functions Additional functions

JTCK-SWCLK, LPTIM1_OUT,

I2C1_SMBA,

ADC_IN10

CM4_EVENTOUT

43 A8 B3 PA15 I/O FT_fa -

JTDI, TIM2_CH1, TIM2_ETR,

I2C2_SDA, SPI1_NSS,

COMP1_INM,

COMP2_INP,

CM4_EVENTOUT

TIM1_CH3N, I2C2_SCL,

- - B4 PB15 I/O FT_f

SPI2_MOSI/I2S2_SD,

CM4_EVENTOUT

44 A6 - VDD S - - - -

- B7 - VSS S - - - -

(1)

G6 - VSS S - - - -

45 B9 B2 VFBSMPS S - - - -

46 A10 A2 VDDSMPS S - - - -

47 B11 B1 VLXSMPS S - - - -

48 C10 A1 VSSSMPS S - - - -

1. Pin 49 is an exposed pad that must be connected to VSS.

ADC_IN11

56/145 DS13293 Rev 1

Page 57

Table 20. Alternate functions

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

STM32WL55/54xx Pinouts, pin description and alternate functions

DS13293 Rev 1 57/145

Port

PA0

PA1

PA2

PA3

PA4

PA5

PA6

Port A

PA7

PA8

PA9

PA1 0

PA11

SYS_

LSCO

RTC_

OUT2

MCO

RTC_

REFIN

TIM1/ TIM2/

LPTIM1

TIM2_

CH1

TIM2_

CH2

TIM2_

CH3

TIM2_

CH4

LPTIM1

_OUT

TIM2_

CH1

TIM1_

BKIN

TIM1_ CH1N

TIM1_

CH1

TIM1_

CH2

TIM1_

CH3

TIM1_

CH4

TIM1/

BKIN2

SPI2S2/

TIM2

TIM2_

ETR

TIM1_

TIM1/

LPTIM3

LPTIM3_

OUT

-- -- -

-- -

SPI2_

MISO

-- -

SPI2_

NSS/

I2S2_WS

LPTIM3_

ETR

I2C1/ I2C2/

I2C3

I2C3_ SMBA

I2C1_ SMBA

I2C2_ SMBA

I2C3_

SCL

I2C1_

SCL

I2C1_

SDA

I2C2_

SDA

SPI1/

SPI2S2

I2S_

CKIN

SPI1_

SCK

I2S2_

MCK

SPI1_

NSS

SPI1_

SCK

SPI1_ MISO

SPI1_ MOSI

SPI2_

SCK/

I2S2_CK

SPI2_

SCK/

I2S2_CK

SPI2_

MOSI/

I2S2_SD

SPI1_ MISO

-- -----

-- ----

USART1

LPUART1 - - -

USART2

USART2_

CTS

USART2_

RTS

USART2_TXLPUART1_

USART2_RXLPUART1_

USART2_

USART1_

CTS

----

LPUART1_

RTS

-----

LPUART1_

CTS

----- -

----- - -

-----

----

COMP1/ COMP2/

DEBUG

TIM1

COMP1_

--- -

---

--- - - -

---

COMP2_

TIM1_

BKIN

COMP2_

TIM1_ BKIN2

OUT

DEBUG_PWR

_REGLP1S

DEBUG_PWR

_REGLP2S

DEBUG_PWR

_LDORDY

DEBUG_

SUBGHZSPI_

NSSOUT

DEBUG_

SUBGHZSPI_

SCKOUT

DEBUG_

SUBGHZSPI_

MISOOUT

DEBUG_

SUBGHZSPI_

MOSIOUT

DEBUG_RF_

HSE32RDY

DEBUG_RF_

NRESET

TIM2/ TIM16/ TIM17/

LPTIM2

TIM2_ETR

LPTIM2_

OUT

LPTIM2_

ETR

TIM16_

CH1

TIM17_

CH1

LPTIM2_

OUT

TIM17_

BKIN

EVENOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

Page 58

58/145 DS13293 Rev 1

Table 20. Alternate functions (continued)

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Pinouts, pin description and alternate functions STM32WL55/54xx

Port

PA1 2

PA1 3

PA1 4

Port A (continued)

PA1 5

PB0

PB1

PB2

PB3

PB4

PB5

Port B

PB6

PB7

PB8

PB9

PB10

SYS_

JTMS-

SWDIO

JTCK-

SWCLK

JTDI

JTDO/

TRACE

SWO

NJTRST - - -

TIM1/ TIM2/

LPTIM1

TIM1_

LPTIM1_

TIM2_

---- -- - - ----

---- -- - -

LPTIM1_

TIM2_

LPTIM1_

TIM1_

CH2N

TIM1_

CH3N

TIM2_

TIM1/

ETR

-- -

OUT

CH1

OUT

CH2

IN1

ETR

IN2

CH3

SPI2S2/

TIM2

TIM2_

ETR

TIM1/

LPTIM3

LPTIM3_

-- -

IN1

TIM1_

BKIN

I2C1/ I2C2/

I2C3

I2C2_

SCL

I2C2_ SMBA

I2C1_ SMBA

I2C2_

SDA

I2C3_ SMBA

I2C3_

SDA

I2C1_ SMBA

I2C1_

SCL

I2C1_

SDA

I2C1_

SCL

I2C1_

SDA

I2C3_

SCL

SPI1/

SPI2S2

SPI1_ MOSI

SPI1_

SPI1_ MISO

SPI1_ MOSI

SPI2_

I2S2_WS

SPI2_

I2S2_CK

RF_BUSY

-- -IR_OUT---- - -

-- - ----- - -

NSS

SCK

NSS/

SCK/

RF_IRQ0

RF_IRQ1

- RF_IRQ2 - - - - - - -

USART1

LPUART1 - - -

USART2

USART1_

RTS

-- ----- - -

-- -----

USART1_

RTS

USART1_

--IR_OUT---- -

CTS

USART1_

----- - -

LPUART1_

RTS_DE

-----

----

----- -

LPUART1_

--- - -

---

COMP1/ COMP2/

TIM1

COMP1_

OUT

COMP2_

OUT

COMP1_

OUT

TIM2/

DEBUG

TIM16/ TIM17/

LPTIM2

LPTIM2_

IN1

DEBUG_RF_

SMPSRDY

DEBUG_RF_

DTB1

DEBUG_RF_

LDORDY

TIM17_

BKIN

TIM16_

BKIN

TIM16_

CH1N

TIM17_

CH1N

TIM16_

CH1

TIM17_

CH1

EVENOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

Page 59

Table 20. Alternate functions (continued)

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

STM32WL55/54xx Pinouts, pin description and alternate functions

DS13293 Rev 1 59/145

Port

SYS_

PB11

PB12

PB13

PB14

Port B (continued)

PB15

TIM1/ TIM2/

TIM1/

LPTIM1

TIM2_

CH4

TIM1_

BKIN

TIM1_

CH1N

TIM1_

CH2N

TIM1_

CH3N

SPI2S2/

TIM2

TIM1/

LPTIM3

TIM1_

BKIN

-I2S2_MCK

I2C1/ I2C2/

I2C3

I2C3_

SDA

I2C3_ SMBA

I2C3_

SCL

I2C3_

SDA

I2C2_

SCL

SPI1/

SPI2S2

-- -

SPI2_

NSS/

I2S2_WS

SPI2_

SCK/

I2S2_CK

SPI2_ MISO

SPI2_

MOSI/

I2S2_SD

USART1

LPUART1 - - -

USART2

LPUART1_

-- ----- - -

LPUART1_

RTS

LPUART1_

CTS

---

--- - - -

COMP1/ COMP2/

TIM1

COMP2_

OUT

DEBUG

TIM2/ TIM16/ TIM17/

LPTIM2

EVENOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

Page 60

60/145 DS13293 Rev 1

Table 20. Alternate functions (continued)

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Pinouts, pin description and alternate functions STM32WL55/54xx

Port

PC0

PC1

PC2

PC3

PC4

Port C

PC5

PC6

PC13

PC14

PC15

SYS_

TIM1/ TIM2/

LPTIM1

LPTIM1_

---- -- - - ----- - -

---- -

---- -- - - ----- - -

TIM1/

IN1

OUT

IN2

ETR

SPI2S2/

TIM2

TIM1/

LPTIM3

SPI2_

MOSI/

I2S2_SD

-- -

I2C1/ I2C2/

I2C3

I2C3_

SCL

I2C3_

SDA

SPI1/

SPI2S2

-- -

SPI2_ MISO

SPI2_

MOSI/

I2S2_SD

I2S2_

MCK

USART1

LPUART1 - - -

USART2

LPUART1_

-- ----- - -

-- ----- -

-- ----- - -

--- - -

--- - - -

COMP1/ COMP2/

TIM1

DEBUG

TIM2/ TIM16/ TIM17/

LPTIM2

LPTIM2_

IN1

LPTIM2_

ETR

EVENOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

CM4_

EVENTOUT

PH3

Port H

---- -- - - ----- - EVENTOUT

CM4_

Page 61

STM32WL55/54xx Electrical characteristics

MSv68045V1

MCU pin

C = 50 pF

MSv68046V1

MCU pin

5 Electrical characteristics

5.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS and, for parameter values based on characterization results, measurements are performed on the UFQFPN48 package.

5.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies, by tests in production on 100 % of the devices, with an ambient temperature at T by the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3).

5.1.2 Typical values

= 25 °C and TA = TAmax (given

Unless otherwise specified, typical data are based on TA = 25 °C, V Typical values are given only as design guidelines and are not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95 % of the devices have an error less than or equal to the value indicated

5.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

5.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 11.

5.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 12.

Figure 11. Pin loading conditions Figure 12. Pin input voltage

(mean ± 2).

= V

DDA

= V

BAT

= 3 V.

DS13293 Rev 1 61/145

135

Page 62

Electrical characteristics STM32WL55/54xx

MSv64325V5

Backup circuitry

(LSE, RTC and

backup registers)

Kernel logic

(CPU, digital

and memories

Level shifter

I/O

logic

LPR

GPIOs

1.55 to 3.6 V

n x 100 nF + 1 x 4.7 μF

n x VSS

n x VDD

VBAT

CORE

Power switch

ADC DAC

COMPs

VREFBUF

REF+

REF-

DDA

10 nF + 1 μF

VDDA

VSS

REF

100 nF

1 μF

SMPS

VDDSMPS

VLXSMPS

VFBSMPS

VSSSMPS

4.7 μF

Exposed pad

470 nF

To all modules (VSS/VSSRF)

LDO/SMPS

RFLDO

VDDRF1V5

REG PA

VDDPA (= VDDRF1V5 or VDDSMPS)

VDDRF

15 μH

BAT

Sub-GHz radio

OUT

5.1.6 Power supply scheme

Figure 13. Power supply scheme

Caution: Each power supply pair (such as V

Note: For the UFQFPN48 and WLCSP59 package, VREF+ is internally connected to VDDA.

62/145 DS13293 Rev 1

ceramic capacitors as shown in the above figure. These capacitors must be placed as close

DD/VSS or VDDA/VSS

) must be decoupled with filtering

as possible to (or below) the appropriate pins on the underside of the PCB to ensure the good functionality of the device.

Page 63

STM32WL55/54xx Electrical characteristics

MSv64326V2

VBAT

VDD

VDDA

VDDRF

VDDSMPS

DDVBAT

VBAT

DDA

VDD

VDDA

DDRF

VDDRF

DDSMPS

VDDSMPS

5.1.7 Current consumption measurement

Figure 14. Current consumption measurement scheme

5.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in the tables below, may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are available on demand.

Table 21. Voltage characteristics

Symbol Ratings Min Max Unit

External main supply voltage

DDX

- V

(including V

DDSMPS, VBAT, VREF+

, V

DDA

Input voltage on FT_xx pins

(2)

Input voltage on TT pins 3.9

DDRF

)

–0.3 3.9

min (VDD, V

- 0.3

Input voltage on any other pin 3.9

DDx

SSx-VSS

- V

REF+

1. All main power (VDD, VDDRF, VDDA, VBAT) and ground (VSS) pins must always be connected to the external power supply, in the permitted range.

power pins of the same domain

Variations between all the different

ground pins

Allowed voltage difference for

DDA

REF+

(5)

DDA

Variations between different V

|V

DDX

-50

-0.4V

(1)

DDA

, V

DDRF

, V

DDSMPS

) +

3.9

(3)(4)

DS13293 Rev 1 63/145

135

Page 64

Electrical characteristics STM32WL55/54xx

2. VIN maximum must always be respected. Refer to the next table for the maximum allowed injected current values.

3. This formula must be applied only on the power supplies related to the I/O structure described in Table 19:

STM32WL55/54xx pin definition.

4. To sustain a voltage higher than 4 V, the internal pull-up/pull-down resistors must be disabled.

5. Include VREF- pin.

Table 22. Current characteristics

Symbol Ratings Max Unit

(1)

130

100

IV

DD(PIN)

SS(PIN)

Total current into sum of all V

Total current out of sum of all V

Maximum current into each

VDD

Maximum current out of each

power lines (source)

ground lines (sink)

power pin (source)

ground pin (sink)

VSS

Output current sunk by any I/O and control pin, except FT_f 20

IO(PIN)

Output current sunk by any FT_f pin 20

Output current sourced by any I/O and control pin 20

I

Total output current sunk by sum of all I/Os and control pins

IO(PIN)

INJ(PIN)

|I

INJ(PIN)

1. All main power (VDD, VDDRF, VDDA, VBAT) and ground (VSS) pins must always be connected to the external power supplies, in the permitted range.

2. This current consumption must be correctly distributed over all I/Os and control pins.

3. Positive injection (when V specified maximum value.

4. A negative injection is induced by V maximum allowed input voltage values.

5. When several inputs are submitted to a current injection, the maximum |I injected currents (instantaneous values).

Total output current sourced by sum of all I/Os and control pins

Injected current on FT_xx, TT and RST pins, except PB0 –5 / +0

(3)

Injected current on PB0 -5/0

Total injected current (sum of all I/Os and control pins)

> VDD) is not possible on these I/Os and does not occur for input voltages lower than the

< VSS. I

must never be exceeded. Refer also to the previous table for the

INJ(PIN)

(2)

(5)

is the absolute sum of the negative

INJ(PIN)

100

(4)

Table 23. Thermal characteristics

Symbol Ratings Value Unit

STG

Storage temperature range -65 to +150

Maximum junction temperature 125

64/145 DS13293 Rev 1

°C

Page 65

STM32WL55/54xx Electrical characteristics

5.3 Operating conditions

5.3.1 Main performances

Table 24. Main performances at VDD = 3 V

Parameter Test conditions Typ Unit

VBAT (V

= 3V, VDD = 0 V) 0.005

BAT

Shutdown 0.031

Standby (32-Kbyte RAM retention) 0.360

CORE

Core current consumption

Stop 2, RTC enabled 1

Sleep (16 MHz) 770

LPRun (2 MHz) 220

Run, SMPS ON (48 MHz) 3450

Rx boosted LoRa 125 kHz, SMPS ON 4.82

434 to 490 MHz, 14 dBm, 3.3 V 21

Tx low power

868 to 915 MHz, 14 dBm, 3.3 V 26

434 to 490 MHz, 22 dBm, 3.3 V 120

Tx high power

868 to 915 MHz, 22 dBm, 3.3 V 107

5.3.2 General operating conditions

Table 25. General operating conditions

µA

Symbol Parameter Conditions Min Max Unit

HCLK

PCLK1

PCLK2

Internal AHB clock frequency -

Internal APB1 clock frequency -

Internal APB2 clock frequency -

Standard operating voltage - 1.8

0 48 MHzf

(1)

3.6

ADC or COMP used 1.62

DAC used 1.71

DDA

BAT

FBSMPS

DDRF

Analog supply voltage

VREFBUF used 2.4

ADC, DAC, COMP and VREFBUF not used

Backup operating voltage - 1.55 3.6

SMPS feedback voltage - 1.4 3.6

Minimum RF voltage - 1.8 3.6

TT I/O –0.3 V

I/O input voltage

All I/O except TT –0.3

min (V

3.6

+ 0.3

min between

, V

DDA

and 5.5 V

(2)(3)

) + 3.6 V

DS13293 Rev 1 65/145

135

Page 66

Electrical characteristics STM32WL55/54xx

Table 25. General operating conditions (continued)

Symbol Parameter Conditions Min Max Unit

Power dissipation at

= 85 °C for suffix 6 version

or TA = 105 °C for suffix 7

UFBGA73 - 392.0 mW

(4)

Ambient temperature for suffix 6 version

Maximum power dissipation

Low-power dissipation

–40

(5)

105

Ambient temperature for the suffix 7 version

dissipation

Low-power dissipation

–40

(5)

Suffix 6 version

Maximum power

Junction temperature range

1. When the reset is released, the functionality is guaranteed down to V

2. This formula has to be applied only on the power supplies related to the I/O structure described in Table 19:

STM32WL55/54xx pin definition. Maximum I/O input voltage is the smallest value between min (V

5.5 V.

3. For operation with voltage higher than min (V disabled.

4. If T

5. In low-power dissipation state, T

is lower, higher PD values are allowed as long as TJ does not exceed TJ max (see Table 101: Package thermal

characteristics).

can be extended to this range, as long as TJ does not exceed TJ max (see Table 101:

Package thermal characteristics).

Suffix 7 version 125

BOR0

, V

) + 0.3 V, the internal pull-up and pull-down resistors must be

DDA

–40

min.

105

125

105

, V

DDA

°C

) + 3.6 V and

66/145 DS13293 Rev 1

Page 67

STM32WL55/54xx Electrical characteristics

5.3.3 Sub-GHz radio characteristics

Electrical characteristics of the sub-GHz radio are given with the following conditions unless otherwise specified:

• V

• Temperature = 25 °C

• HSE32 = 32 MHz

• F

• All RF impedances matched using reference design

• Reference design implementing a 32 MHz crystal oscillator

• Transmit mode output power defined in 50  load

• FSK BER (bit error rate) = 0.1 %, 2-level FSK modulation without pre-filtering,

• LoRa PER (packet error rate) = 1 %, packet of 64 bytes, preamble of 8 bytes, error

• Sensitivities given using highest LNA gain step

• Power consumption measured with -140 dBm signal and AGC ON

• Blocking immunity, ACR and co-channel rejection, given for a single tone interferer and

• Bandwidth expressed on DSB (double-sided band)

= 3.3 V. The current consumption is measured as described in Figure 14.

includes current consumption of all supplies (V

DDRF

, V

DDSMPS

, VDD, V

DDA

, V

BAT

All peripherals except Sub-GHz radio are disabled and the system is in Standby mode.

= 434/868/915 MHz

BR = 4.8 Kbit/s, FDA = 5 kHz, BW_F = 20 kHz

correction code CR = 4/5, CRC on payload enabled, no reduced encoding, no implicit header

referenced to sensitivity +6 dB, blocking tests performed with unmodulated signal

Table 26. Operating range of RF pads

Pad Description Max Unit

RFI_P/RFI_N RF input power 0

RFO_LP/RFO_HP/VR_PA Voltage Standing Wave Ratio (VSWR) 10.1

dBm

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Electrical characteristics STM32WL55/54xx

Table 27. Sub-GHz radio power consumption

Symbol Mode Conditions Min Typ Max Unit

Deep-Sleep

mode (Sleep with cold

(1)(2)

start)

Sleep mode (with warm

(2)(3)

start)

Sleep, LDO

(4)

mode

Sleep, SMPS

(4)

mode

Standby mode (RC 13 MHz on)

Standby mode (HSE32)

Synthesizer mode

All blocks off - 50 -

Configuration retained - 140 -

Configuration retained + RC64k - 810 -

LDO, band-gap, RC 13 MHz on

Band-gap,

HSE32 off - 414 -

HSE32 on - 564 -

HSE32 off - 700 RC 13 MHz on, SMPS 40 mA max

HSE32 on - 950 -

RC 13 MHz on, HSE32 off - 0.7 -

SMPS mode 40 mA max settings - 1.05 -

LDO mode - 0.99 -

SMPS mode used with 40 mA drive capability - 2.66 -

LDO mode - 4.05 -

µA

FSK 4.8 Kbit/s - 4.47 -

Receive mode, SMPS mode used

SMPS 40 mA max

LoRa 125 kHz - 4.82 -

Rx boosted, FSK 4.8 Kbit/s - 5.12 -

RX boosted, LoRa 125 kHz - 5.46 -

FSK 4.8 Kbit/s - 8.18 -

Receive mode, LDO mode used

LoRa 125 kHz 8.90

FSK 4.8 Kbit/s 9.52 RX boosted

LoRa 125 kHz 10.22

1. Cold start is equivalent to device at POR or when the device wakes up from Sleep mode with all blocks off.

2. Only Sub-GHz radio power consumption.

3. Warm start only happens when the device wakes up from Sleep mode with its configuration retained,

4. System in Stop 0 mode range 2.

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STM32WL55/54xx Electrical characteristics

Table 28. Sub-GHz radio power consumption in transmit mode

Symbol Frequency band (MHz) PA match (conditions) Power output Typ Unit

+14 dBm, V

Low power (optimized for 14 dBm)

+10 dBm, V

+14 dBm, V

+10 dBm, V

868 to 915

+15 dBm, V

Low power (optimal settings)

(1)

+10 dBm, V

+15 dBm, V

+10 dBm, V

+14 dBm, V

Low power (optimized for 14 dBm)

+10 dBm, V

+14 dBm, V

+10 dBm, V

434 to 490

+15 dBm, V

+10 dBm, V

Low power (optimal settings)

+15 dBm, V

+10 dBm, V

868 to 915

Low-power PA, SMPS OFF +14 dBm, V

434 to 490 43.5

+22 dBm, V

High power (optimized for 22 dBm)

868 to 915

+20 dBm, V

+17 dBm, V

+14 dBm, V

+20 dBm, V

High power (optimal settings)

+17 dBm, V

+14 dBm, V

+22 dBm, V

High power (optimized for 22 dBm)

434 to 490

+20 dBm, V

+17 dBm, V

+14 dBm, V

+20 dBm, V

High power (optimal settings)

+17 dBm, V

+14 dBm, V

1. Optimal settings can be used to optimize power consumption when the output power is NOT 22 dBm (high power) or

14 dBm (low power). In that case, a dedicated firmware configuration associated to a dedicated board matching network (see AN5457 for details) corresponding to the custom output power, can be used.

= 3.3 V 23.5

DDRF

= 3.3 V 17.5

DDRF

= 1.8 V 41.5

DDRF

= 1.8 V 28.5

DDRF

= 3.3 V 25.5

DDRF

= 3.3 V 15

DDRF

= 1.8 V 51

DDRF

= 1.8 V 25

DDRF

= 3.3 V 22.5

DDRF

= 3.3 V 13.5

DDRF

= 1.8 39.5

DDRF

= 1.8 V 22.5

DDRF

= 3.3 V 24.5

DDRF

= 3.3 V 13.5

DDRF

= 1.8 V 43

DDRF

= 1.8 V 21.5

DDRF

= 3.3 V

DDRF

= 3.3 V 119

DDRF

= 3.3 V 107.5

DDRF

= 3.3 V 98

DDRF

= 3.3 V 92

DDRF

= 3.3 V 92.5

DDRF

= 3.3 V 58

DDRF

= 3.3 V 45.5

DDRF

= 3.3 V 110.5

DDRF

= 3.3 V 90

DDRF

= 3.3 V 71

DDRF

= 3.3 V 59

DDRF

= 3.3 V 72

DDRF

= 3.3 V 43.5

DDRF

= 3.3 V 38

DDRF

45.5

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Electrical characteristics STM32WL55/54xx

Table 29. Sub-GHz radio general specifications

Symbol Description Conditions Min Typ Max Unit

FR Frequency synthesizer range Low-power PA 150 - 960 MHz

FSTEP Frequency synthesizer step High-resolution mode HSE / 2

100 kHz offset - –100 -

PHN

(2)

(1)

Synthesizer phase noise (868 to 915 MHz)

(2)(5)

-095 - Hz

dBc/Hz1 MHz offset - –120 -

10 MHz offset - –135 -

TS_FS Synthesizer wakeup time From Standby, HSE32 mode - 40 -

TS_HO

TS_OS

OSC_

TRM

BR_F Bitrate, FSK

FDA Frequency deviation, FSK

Synthesizer hop time 10 MHz step - 40 -

(3)

Crystal oscillator wakeup time

From Standby, RC from HSE32 off

normal mode

-170 -

Crystal oscillator trimming range for crystal frequency error compensation

(4)

Min/max XTAL specifications ±15 ±30 - ppm

Programmable (min modulation index is 0.5)

Programmable (FDA + BR_F/2  250 kHz)

0.6 - 300

0.6 - 200 kHz

(5)

µs

Kbit/s

BR_L Bitrate, LoRa

Min for SF12, BW_L = 7.8 kHz Max for SF7, BW_L = 500 kHz

0.018 - 62.5

BW_L Signal BW, LoRa Programmable 7.8 - 500

SF Spreading factor for LoRa Programmable, chips/symbol = 2

1. Phase Noise specifications are given for the recommended PLL bandwidth to be used for the specific modulation/BR, optimized settings may be used for specific applications.

2. Phase Noise is not constant over frequency, due to the topology of the PLL. For two frequencies close to each other, the phase noise may change significantly

3. Wakeup time till crystal oscillator frequency is within ±10 ppm.

4. OSC_TRIM is the available trimming range to compensate for crystal initial frequency error and to allow crystal temperature compensation implementation. The total available trimming range is higher and allows the compensation for all device process variations

5. Maximum bit rate is assumed to scale with the RF frequency: for example 300 Kbit /s in the 869-to-915 MHz frequency band and only 50 Kbit/s at 150 MHz.

6. For RF frequencies below 400 MHz, there is a scaling between the frequency and supported bandwidth. Some bandwidths may not be available below 400 MHz.

5-12-

(6)

Kbit/s

kHz

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STM32WL55/54xx Electrical characteristics

Table 30. Sub-GHz radio receive mode specifications

Symbol Description Conditions Min Typ Max Unit

RXS_2FB

Sensitivity 2-FSK, RX boosted gain, split RF paths for RX and Tx, RF switch insertion loss excluded

BR = 0.6 Kbit/s, FDA = 0.8 kHz, BW = 4 kHz

BR = 1.2 Kbit/s, FDA = 5 kHz, BW = 20 kHz

BR = 4.8 Kbit/s, FDA = 5 kHz, BW = 20 kHz

BR = 38.4 Kbit/s, FDA = 40 kHz, BW = 160 kHz

BR = 250 Kbit/s, FDA = 125 kHz, BW = 500 kHz

- –125 -

- –123 -

-–117 -

- –108 -

- –103 -

BW = 10.4 kHz, SF = 7 - –135 -

BW = 10.4 kHz, SF = 12 - –148 -

dBm

RXS_LB

Sensitivity LoRa, RX boosted gain, split RF paths for RX and Tx, RF switch insertion loss excluded

BW = 125 kHz, SF = 7 - –125 -

BW = 125 kHz, SF = 12 - –138 -

BW = 250 kHz, SF = 7 - –122 -

BW = 250 kHz, SF = 12 - –135 -

BW = 500 kHz, SF = 7 - –118 -

BW = 500 kHz, SF = 12 - –130 -

RSX_2F

Sensitivity 2-FSK, RX power saving gain with direct tie connection between RX and Tx

BR = 4.8 Kbit/s, FDA = 5 kHz, BW = 20 kHz

-–115 -

Sensitivity LoRa, RX power

RXS_L

saving gain with direct tie

BW = 125 kHz, SF = 12 - –135 -

connection between RX and Tx

CCR_F Co-channel rejection, FSK - - –9 -

SF = 7 - 7 -

CCR_L Co-channel rejection, LoRa

SF = 12 - 19 -

ACR_F Adjacent channel rejection, FSK Offset = ±50 kHz - 44 -

Offset = ±1.5 x BW_L, BW = 125 kHz, SF = 7

-60 -

ACR_L Adjacent channel rejection, LoRa

BI_F Blocking immunity, FSK

Offset = ±1.5 x BW_L, BW = 125 kHz, SF = 12

Offset = ±1 MHz, BR = 4.8 Kbit/s, FDA = 5 kHz, BW = 20 kHz

Offset = ±2 MHz, BR = 4.8 Kbit/s, FDA = 5 kHz, BW = 20 kHz

Offset = ±10 MHz, BR = 4.8 Kbit/s, FDA = 5 kHz, BW = 20 kHz

-71 -

-67 -

-70 -

-76 -

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Electrical characteristics STM32WL55/54xx

Table 30. Sub-GHz radio receive mode specifications (continued)

Symbol Description Conditions Min Typ Max Unit

BI_L Blocking immunity, LoRa

Offset = ±1 MHz, BW = 125 kHz, SF = 12

Offset = ±2 MHz, BW = 125 kHz, SF = 12

Offset = ±10 MHz, BW = 125 kHz, SF = 12

-87 -

-91 -

-96 -

Unwanted tones are 1 MHz and

1.96 MHz above LO.

-–9 -

868 to 915 MHz band

IIP3 Third order input intercept point

Unwanted tones are 1 MHz and

1.96 MHz above LO.

- –15 -

433 MHz band

Without IQ calibration - 30 -

IMA Image attenuation

With IQ calibration - 54 -

BW_F DSB channel filter BW, FSK Programmable, typical values 4.8 - 467 kHz

TS_RX Receiver wakeup time FS to RWX - 41 - µs

Maximum tolerated frequency offset between transmitter and receiver, SF7 to SF12

FERR_L

Maximum tolerated frequency

All bandwidths, ±25 % of BW. The tighter limit between this line

-±25 - BW

and the three lines below applies.

SF12 –50 - 50

offset between transmitter and receiver, SF10 to SF12

SF10 –200 - 200

dBm

ppmSF11 –100 - 100

Table 31. Sub-GHz radio transmit mode specifications

Symbol Description Conditions Min Typ Max Unit

Highest power step setting for low-power PA (LP PA)

-+15

(1)

TXOP Max RF output power

TXDRP

RF output power drop versus supply voltage

TXPRNG RF output power range

TXACC

RF output power step accuracy

Highest power step setting for high-power PA (HP PA)

LP PA, under SMPS or LDO VDDop range from 1.8 to 3.7 V

HP PA, +22 dBm, V

= 2.7 V - 2 -

= 2.4 V - 3 -

= 1.8 V - 6 -

Programmable in 31 steps, typical value

--±2-dB

-+22-

-0.5-

TXOP-31 - TXOP dBm

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STM32WL55/54xx Electrical characteristics

Table 31. Sub-GHz radio transmit mode specifications (continued)

Symbol Description Conditions Min Typ Max Unit

TXRMP PA ramping time Programmable 10 - 3400

TS_TX TX wakeup time

1. For low-power PA, +15 dBm maximum RF output power can be reached with optimal settings.

Frequency synthesizer enabled

- 36 + PA ramping -

µs

Table 32. Sub-GHz radio power management specifications

Frequency

Symbol Description Conditions

(MHz)

470 490 868

TRPOR Required POR reset pulse duration For V

 1.8 V 50 100 - µs

VEOLL End-of-life low-threshold voltage - 1.81 1.89 1.96

VEOLH End-of-life high-threshold voltage - 1.86 1.94 2.1

VEOLD End-of-life hysteresis voltage VEOLH - VEOLL 50 53 56 mV

VREG Main regulated supply

Load transient for ILSMPS 100 µA to

LDTRSMPS

100 mA in 10 µs LDO running

LDO or SMPS over process, voltage and temperature range

1.47 1.55 1.62 V

High BW mode - 25 -

Low BW mode - 47 -

ILSMPS SMPS load current - - - 100 mA

IDDSMPS SMPS quiescent current

SMPS converter average efficiency

EFFSMPS

EFF = VREG x ILOAD / V

DDSMPS

x IDD

SMPS high power, V

SMPS low power, V

SMPS 100 mA max V ILSMPS = 6 mA

SMPS 100 mA max V ILSMPS = 50 mA

SMPS 100 mA max V ILSMPS = 6 mA

SMPS 100 mA max V ILSMPS = 50 mA

= 3.3 V - 538 -

= 3.3 V - 460 -

= 3.3 V,

= 1.8 V,

= 2.0 V,

-71-

-89-

-88-

-91-

Unit

µA

SMPS 100 mA max V ILSMPS = 100 mA

= 3.3 V,

-86-

Cout Shared between LDO and SMPS ±20 % tolerance - 470 - nF

Lout SMPS inductor - - 15 - µH

TSSMPS Sleep and Sleep, SMPS startup time For ILIM = 50 mA - 70 - µs

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Electrical characteristics STM32WL55/54xx

Table 32. Sub-GHz radio power management specifications (continued)

Frequency

Symbol Description Conditions

= 3.3 V,

ILOAD = 0 to 100 mA, current limiter off

(MHz)

470 490 868

-95-

Unit

IDDLDO LDO quiescent current

= 3.3 V, ILOAD = 100 mA,

current limiter on

= 3.3 V, ILOAD = 50 mA,

current limiter on

-380-

-280-

ILDO LDO load current - - 100 - mA

LDTRLDO

Load transient for ILDO 100 µA to 100 mA in 10 µs

--25-mV

TSLDO Sleep and Sleep, LDO startup time For ILIM = 50 mA - 60 - µs

VDIG Digital regulator target voltage - 1.14 1.2 1.26 V

(1)

ILM

1. The default current limiter value is set to 50 mA.

Current limiter max value - 25 50 200 mA

5.3.4 Operating conditions at power-up/power-down

Parameters given in the table below are derived from tests performed under the ambient temperature condition summarized in Table 25: General operating conditions.

Symbol Parameter Min Max Unit

VDD

VDDA

VDDRF

Table 33. Operating conditions at power-up/power-down

VDD rise time rate - 

fall time rate 10 

rise time rate 0 

DDA

fall time rate 10 

DDA

rise time rate - 

DDRF

fall time rate - 

DDRF

µAV

µs/V

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STM32WL55/54xx Electrical characteristics

5.3.5 Embedded reset and power-control block characteristics

Parameters given in the table below are derived from tests performed under the ambient temperature conditions summarized in Table 25: General operating conditions.

Table 34. Embedded reset and power-control block characteristics

Symbol Parameter Conditions

RSTTEMPO

BOR0

(2)

Reset temporization after BOR0 is detected V

Brownout reset threshold 0

rising - 250 400 s

Rising edge 1.72 1.76 1.80

Falling edge 1.70 1.74 1.78

(2)

Rising edge 2.06 2.10 2.14

BOR1

Brownout reset threshold 1

Falling edge 1.96 2.00 2.04

Rising edge 2.26 2.31 2.35

BOR2

Brownout reset threshold 2

Falling edge 2.16 2.20 2.24

(1)

Min Typ Max Unit

BOR3

BOR4

PVD0

PVD1

PVD2

PVD3

PVD4

PVD5

PVD6

hyst_BORH0

hyst_BOR_PVD

(BOR_PVD)

Brownout reset threshold 3

Brownout reset threshold 4

Programmable voltage detector threshold 0

PVD threshold 1

PVD threshold 2

PVD threshold 3

PVD threshold 4

PVD threshold 5

PVD threshold 6

Hysteresis voltage of BORH0

Hysteresis voltage of BORH (except BORH0) and PVD

(3)

BOR

(2)

(except BOR0) and PVD

consumption from V

Rising edge 2.56 2.61 2.66

Falling edge 2.47 2.52 2.57

Rising edge 2.85 2.90 2.95

Falling edge 2.76 2.81 2.86

Rising edge 1.88 1.95 2.02

Falling edge 1.83 1.90 1.97

Rising edge 2.26 2.31 2.36

Falling edge 2.15 2.20 2.25

Rising edge 2.41 2.46 2.51

Falling edge 2.31 2.36 2.41

Rising edge 2.56 2.61 2.66

Falling edge 2.47 2.52 2.57

Rising edge 2.69 2.74 2.79

Falling edge 2.59 2.64 2.69

Rising edge 2.85 2.91 2.96

Falling edge 2.75 2.81 2.86

Rising edge 2.92 2.98 3.04

Falling edge 2.84 2.90 2.96

Hysteresis in continuous mode

Hysteresis in other mode

-20-

-30-

- - 100 -

- - 1.1 1.6 µA

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Electrical characteristics STM32WL55/54xx

Table 34. Embedded reset and power-control block characteristics (continued)

Symbol Parameter Conditions

(1)

Min Typ Max Unit

PVM3

hyst_PVM3

(PVM3)

1. Continuous mode means Run and Sleep modes, or temperature sensor enable in LPRun and LPSleep modes.

2. Guaranteed by design.

3. BOR0 is enabled in all modes (except Shutdown) and its consumption is therefore included in the supply current characteristics tables.

peripheral voltage monitoring

DDA

Falling edge 1.6 1.64 1.68

PVM3 hysteresis - - 10 - mV

(2)

PVM3 consumption from V

--2-µA

5.3.6 Embedded voltage reference

Parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 25: General operating

conditions.

Rising edge 1.61 1.65 1.69

Symbol Parameter Conditions Min Typ Max Unit

Internal reference voltage –40 °C < TJ < +105 °C 1.182 1.212 1.232 V

ADC sampling time when reading

(1)

the internal reference voltage

Start time of reference voltage buffer when ADC is enable

REFINT

)

VDD when converted by ADC

IDD(V

REFINT

S_vrefint

start_vrefint

REFINTBUF

Table 35. Embedded internal voltage reference

-4

--812

buffer consumption from

- - 12.5 20

(2)

µs

µA

V

REFINT

Coeff

DDCoeff

REFINT_DIV1

REFINT_DIV2

REFINT_DIV3

1. The shortest sampling time can be determined in the application by multiple iterations.

2. Guaranteed by design.

Internal reference voltage spread over the temperature range

Temperature coefficient –40 °C < TJ < +105 °C - 30 50

Long term stability 1000 hours, T = 25 °C - 300 1000

Voltage coefficient 3.0 V < VDD < 3.6 V - 250 1200

1/4 reference voltage

1/2 reference voltage 49 50 51

3/4 reference voltage 74 75 76

= 3.3 V - 5 7.5

76/145 DS13293 Rev 1

24 25 26

(2)

ppm/°C

ppm

ppm/V

REFINT

Page 77

STM32WL55/54xx Electrical characteristics

MSv66005V3

1.185

1.19

1.195

1.2

1.205

1.21

1.215

1.22

1.225

1.23

1.235

-40 -20 0 20 40 60 80 100 120

°C

Mean Min Max

Figure 15. V

5.3.7 Supply current characteristics

The current consumption is a function of several parameters and factors such as operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.

versus temperature

REFINT

The current consumption is measured as described in Figure 14.

Typical and maximum current consumption

The device is put under the following conditions:

• All I/O pins are in analog input mode.

• All peripherals are disabled, except when explicitly mentioned.

• The Flash memory access time is adjusted with the minimum wait-states number,

depending on the f to Flash clock (HCLK3) frequency’ in the reference manual (RM0461).

• f

PCLK

= f

when the peripherals are enabled.

HCLK

= f

HCLK

HCLKS

Parameters given in the tables below (Table 36 to Table 55) are derived from tests performed under ambient temperature and supply voltage conditions summarized in

Table 25: General operating conditions.

frequency. Refer to the table ‘Number of wait states according

HCLK

for the Flash memory and shared peripherals.

DS13293 Rev 1 77/145

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78/145 DS13293 Rev 1

Table 36. Current consumption in Run and LPRun modes on CPU1, CoreMark code with data

running from Flash memory, ART enable (cache ON, prefetch OFF)

Conditions Typ Max

Symbol Parameter

= f

(Run)

(LPRun)

1. Guaranteed by characterization results, unless otherwise specified.

Supply current

in Run mode

Supply current

in LPRun mode

HCLK

All peripherals disabled

HCLK

All peripherals disabled

= f

MSI

Voltage

scaling

Range 2

SMPS

Range 2

Range 1

SMPS

Range 1

(1)

HCLK

(MHz)

25 °C 55 °C 85 °C 105 °C 25 °C 85 °C 105 °C

16 1.85 1.90 1.95 2.10 2.20 2.40 2.80

8 1.10 1.15 1.20 1.30 1.40 1.60 1.90

2 0.585 0.610 0.670 0.760 - - -

16 1.50 1.45 1.65 1.70 - - -

8 1.00 1.05 1.05 1.10 - - -

2 0.730 0.750 0.780 0.830 - - -

48 5.55 5.65 5.80 5.95 7.40 11.0 14.0

32 3.85 3.95 4.05 4.20 5.60 8.40 13.0

16 2.15 2.20 2.30 2.45 3.70 6.60 11.0

48 3.40 3.45 3.55 3.60 - - -

32 2.50 2.55 2.60 2.65 - - -

16 1.60 1.60 1.65 1.70 - - -

2 0.220 0.235 0.290 0.380 0.270 0.490 0.880

1 0.120 0.135 0.185 0.275 0.150 0.390 0.780

0.4 0.058 0.0715 0.120 0.210 0.084 0.330 0.710

Electrical characteristics STM32WL55/54xx

Unit

Page 79

DS13293 Rev 1 79/145

Table 37. Current consumption in Run and LPRun modes on CPU1 and CPU2, CoreMark code

Symbol Parameter

(Run)

(LPRun)

Supply current in

Run mode

Supply current in

LPRun mode

with data running from SRAM1

Conditions Typ

= f

HCLK

All peripherals disabled

HCLK

All peripherals disabled

= f

MSI

Volt age scaling

HCLK

(MHz)

25 °C 55 °C 85 °C 105 °C

Range 2 16 2.5 2.55 2.65 2.75

48 8.00 8.15 8.35 8.55

Range 1

32 5.80 5.90 6.05 6.25

48 4.75 4.85 4.95 5.00

SMPS

Range 1

32 3.50 3.60 3.65 3.75

16 2.20 2.25 2.30 2.40

20.350- - -

10.185- - -

0.4 0.0805 - - -

STM32WL55/54xx Electrical characteristics

Unit

Page 80

80/145 DS13293 Rev 1

Table 38. Current consumption in Run and LPRun modes on CPU1, CoreMark code

Symbol Parameter

= f

(Run)

(LPRun)

1. Guaranteed by characterization results, unless otherwise specified.

Supply current

in Run mode

Supply current

in LPRun mode

HCLK

All peripherals disabled

HCLK

All peripherals disabled

= f

MSI

with data running from SRAM1

Conditions Typ Max

Voltage

scaling

Range 2

SMPS

Range 2

Range 1

SMPS

Range 1

HCLK

(MHz)

25 °C 55 °C 85 °C 105 °C 25 °C 85 °C 105 °C

16 1.90 1.90 2.00 2.10 2.20 2.40 2.80

8 1.101.151.201.301.401.602.00

2-------

16 1.40 1.45 1.50 1.55 - - -

8 1.00 1.05 1.05 1.10 - - -

2 0.730 0.750 0.780 0.825 - - -

48 5.65 5.75 5.90 6.05 6.50 6.70 7.10

32 3.90 4.00 4.10 4.25 4.60 4.80 5.20

16 2.20 2.25 2.30 2.45 2.50 2.80 3.20

48 3.45 3.50 3.60 3.65 - - -

32 2.50 2.55 2.60 2.70 - - -

16 1.60 1.60 1.65 1.70 - - -

2 0.220 0.230 0.285 0.375 0.240 0.480 0.860

1 0.120 0.130 0.180 0.270 0.140 0.380 0.770

0.4 0.052 0.064 0.115 0.205 0.077 0.320 0.710

Electrical characteristics STM32WL55/54xx

(1)

Unit

Page 81

Table 39. Typical current consumption in Run and LPRun modes on CPU1, with different codes

STM32WL55/54xx Electrical characteristics

running from Flash memory, ART enable (cache ON, prefetch OFF)

DS13293 Rev 1 81/145

Symbol Parameter

IDD(Run)

Supply current in

Run mode

- Voltage scaling Code 25 °C 25 °C

= f

HCLK

MSI

All peripherals disabled

Conditions Typ

Reduced code 1.90

(1)

HCLK

Range 2

= 16 MHz

CoreMark

Dhrystone 2.1 1.85 115.63

Fibonacci 1.80 112.50

While(1) 1.60 100.00

Reduced code 1.45 90.63

(1)

HCLK

SMPS

Range 2

= 16 MHz

CoreMark

Dhrystone 2.1 1.40 87.50

Fibonacci 1.40 87.50

While(1) 1.30 81.25

Reduced code 5.70 118.75

(1)

HCLK

Range 1

= 48 MHz

CoreMark

Dhrystone 2.1 5.50 114.58

Fibonacci 5.40 112.50

While(1) 4.65 96.88

Reduced code 3.50 72.92

(1)

HCLK

SMPS

Range 1

= 48 MHz

CoreMark

Dhrystone 2.1 3.40 70.83

Fibonacci 3.30 68.75

While(1) 2.90 60.42

Typ

Unit

118.75

1.85 115.63

1.40 87.50

5.55 115.63

3.40 70.83

Unit

µA/MHz

Page 82

82/145 DS13293 Rev 1

Table 39. Typical current consumption in Run and LPRun modes on CPU1, with different codes

running from Flash memory, ART enable (cache ON, prefetch OFF) (continued)

Electrical characteristics STM32WL55/54xx

Conditions Typ

Symbol Parameter

- Voltage scaling Code 25 °C 25 °C

= f

IDD(LPRun)

1. CoreMark used for characterization results provided in Table 36 and Table 39.

Supply current in

LPRun mode

HCLK

All peripherals disabled

MSI

= 2 MHz

Typ

Unit

Reduced code 0.225

CoreMark

(1)

Dhrystone 2.1 0.220 110.00

0.220 110.00

112.50

Fibonacci 0.240 120.00

While(1) 0.175 87.50

Unit

µA/MHz

Page 83

Table 40. Typical current consumption in Run and LPRun modes on CPU1,

STM32WL55/54xx Electrical characteristics

with different codes running from SRAM1

DS13293 Rev 1 83/145

Symbol Parameter

IDD(Run)

Supply current

in Run mode

- Voltage scaling Code 25 °C 25 °C

= f

HCLK

MSI

All peripherals disabled

Conditions Typ

Reduced code 1.95

(1)

HCLK

Range 2

= 16 MHz

CoreMark

Dhrystone 2.1 1.90 118.75

Fibonacci 1.90 118.75

While(1) 1.75 109.38

Reduced code 1.45 90.63

Range 2

SMPS ON

HCLK

= 16 MHz

CoreMark

Dhrystone 2.1 1.45 90.63

Fibonacci 1.45 90.63

(1)

While(1) 1.35 84.38

Reduced code 5.90 122.92

(1)

HCLK

Range 1

= 48 MHz

CoreMark

Dhrystone 2.1 5.70 118.75

Fibonacci 5.65 117.71

While(1) 5.10 106.25

Reduced code 3.60 75.00

Range 1

SMPS ON

HCLK

= 48 MHz

CoreMark

Dhrystone 2.1 3.50 72.92

Fibonacci 3.45 71.88

(1)

While(1) 3.15 65.63

Typ

Unit

121.88

1.90 118.75

1.45 90.63

5.65 117.71

3.45 71.88

Unit

µA/MHz

Page 84

84/145 DS13293 Rev 1

Table 40. Typical current consumption in Run and LPRun modes on CPU1,

with different codes running from SRAM1 (continued)

Electrical characteristics STM32WL55/54xx

Conditions Typ

Symbol Parameter

- Voltage scaling Code 25 °C 25 °C

= f

Supply current

IDD(LPRun)

1. CoreMark used for characterization results provided in Table 36 and Table 39.

2. Flash memory in power-down mode.

(2)

in LPRun mode

HCLK

All peripherals disabled

MSI

= 2 MHz

Typ

Unit

Reduced code 0.225

CoreMark

(1)

Dhrystone 2.1 0.225 112.50

0.220 110.00

112.50

Fibonacci 0.225 112.50

While(1) 0.195 97.50

Unit

µA/MHz

Page 85

Symbol Parameter

(Sleep)

Supply current in Sleep mode

Table 41. Current consumption in Sleep and LPSleep modes on CPU1, Flash memory ON

Conditions Typ Max

= f

HCLK

MSI

All peripherals disabled

Volt age scaling

Range 2

Range 1

HCLK

(MHz)

25 °C 55 °C 85 °C 105 °C 25 °C 85 °C 105 °C

16 0.770 0.800 0.860 0.955 1.00 1.30 1.60

8 0.570 0.600 0.655 0.745 0.780 0.990 1.40

2 0.445 0.470 0.525 0.615 0.650 0.860 1.30

48 1.70 1.70 1.80 1.90 2.10 2.30 2.70

32 1.25 1.30 1.40 1.50 1.60 1.90 2.30

16 0.845 0.875 0.945 1.05 1.10 1.40 1.80

STM32WL55/54xx Electrical characteristics

(1)

Unit

DS13293 Rev 1 85/145

Supply current

(LPSleep)

in LPSleep

mode

1. Guaranteed by characterization results, unless otherwise specified.

= f

HCLK

MSI

All peripherals disabled

SMPS

Range 1

48 1.35 1.40 1.45 1.50 - - -

32 1.15 1.15 1.20 1.25 - - -

16 0.895 0.915 0.950 1.00 - - -

2 0.068 0.0805 0.130 0.220 0.095 0.330 0.720

1 0.044 0.0565 0.105 0.195 0.069 0.310 0.700

0.4 0.0225 0.040 0.0885 0.180 0.052 0.290 0.680

0.1 0.018 0.032 0.081 0.170 0.045 0.280 0.670

Page 86

86/145 DS13293 Rev 1

Table 42. Current consumption in Sleep and LPSleep modes on CPU1 and CPU2,

Symbol Parameter

Flash memory ON

Conditions Typ

- Voltage scaling f

(MHz) 25 °C

HCLK

16 0.790

Electrical characteristics STM32WL55/54xx

Unit

(Sleep)

(LPSleep)

Supply current in

Sleep mode

Supply current in

LPSleep mode

Table 43. Current consumption in LPSleep mode on CPU1, Flash memory in power-down

= f

HCLK

MSI

All peripherals disabled

= f

HCLK

MSI

All peripherals disabled

Conditions Typ Max

Symbol Parameter

-f

(MHz) 25 °C 55 °C 85 °C 105 °C 25 °C 85 °C 105 °C

HCLK

2 58.0 74.5 125 215 86.0 330 710

(LPSleep)

Supply current in

LPSleep mode

HCLK

All peripherals disabled

1 35.5 50.5 99.0 190 60.0 300 690

0.4 18.5 33.5 81.5 170 41.0 280 670

= f

0.1 11.0 26.5 74.5 165 36.0 280 660

1. Guaranteed by characterization results, unless otherwise specified.

Range 2

Range 1

SMPS Range 1

80.585

20.450

48 1.75

32 1.30

16 0.870

48 1.40

32 1.15

16 0.905

0.1 0.0165

(1)

Unit

µA

Page 87

Symbol Parameter

(LPSleep)

Supply current in

LPSleep mode

Table 44. Current consumption in LPSleep mode on CPU1 and CPU2,

Flash memory in power-down

Conditions Typ

-f

= f

HCLK

All peripherals disabled

(MHz) 25 °C

HCLK

259.5

136.0

0.4 21.5

0.1 12.5

STM32WL55/54xx Electrical characteristics

Unit

µA

Table 45. Current consumption in Stop 2 mode

Conditions Typ Max

Symbol Parameter

DS13293 Rev 1 87/145

(Stop 2)

(Stop 2 with

RTC)

1. Guaranteed based on test during characterization, unless otherwise specified.

2. LSI using LSIPRE = 1 configuration.

Supply current in Stop 2 mode RTC disabled

Supply current in Stop 2 mode RTC enabled, clocked by LSI

(2)

(1)

(V) 0 °C 25 °C 55 °C 85 °C 105 °C 0 °C 25 °C 85 °C 105 °C

1.8 0.545 0.830 2.45 8.45 13.5 1.20 2.20 24.0 66.0

2.4 0.525 0.850 2.60 8.80 14.0 - - - -

3.0 0.605 0.885 2.80 9.25 14.5 1.10 2.60 26.0 69.0

3.6 0.630 0.935 3.10 9.75 15.5 1.40 2.80 26.0 71.0

1.8 0.650 0.880 2.55 8.25 13.5 1.30 2.30 24.0 66.0

2.4 0.630 0.945 2.70 8.85 14.0 - - - -

3.0 0.715 1.00 2.90 9.70 15.0 1.40 2.80 26.0 69.0

3.6 0.750 1.10 3.15 10.5 15.5 1.50 3.00 26.0 71.0

Unit

µA

Page 88

88/145 DS13293 Rev 1

Table 46. Current consumption during wakeup from Stop 2 mode

Typ a t 2 5 ° C

Conditions

= 1.8 V VDD = 2.4 V VDD = 3.0 V VDD = 3.6 V

Wakeup clock: MSI 4 MHz, voltage range 2 2.93 3.22 3.45 4.79

Wakeup clock: MSI 2 MHz, voltage range 2 4.44 5.03 5.82 7.36

Wakeup clock: MSI 4 MHz, voltage range 1 3.03 3.14 3.51 4.66

Wakeup clock: MSI 16 MHz, voltage range 1 1.75 1.95 2.00 3.06

Wakeup clock: MSI 48 MHz, voltage range 1 1.75 1.40 1.89 2.80

Electrical characteristics STM32WL55/54xx

Unit

nAs

Table 47. Current consumption in Stop 1 mode

Conditions Typ Max

Symbol Parameter

(V) 0 °C 25 °C 55 °C 85 °C 105 °C 0 °C 25 °C 85 °C 105 °C

1.8 2.05 4.00 14.0 47.0 74.5 6.10 20.0 200 480

(Stop 1)

Supply current in Stop 1 mode RTC disabled

2.4 2.15 3.95 14.0 47.0 75.0 - - - -

3.0 2.15 4.15 14.0 47.5 75.5 5.90 20.0 200 490

3.6 2.25 4.20 14.0 48.0 76.5 6.20 20.0 200 490

1.8 2.15 4.10 14.0 47.0 75.0 6.30 20.0 200 480

(Stop 1with

RTC)

Supply current in Stop 1 mode RTC enabled, clocked by LSI

(2)

2.4 2.15 4.10 14.0 47.5 75.5 - - - -

3.0 2.25 4.20 14.0 47.5 76.0 6.40 21.0 200 490

3.6 2.30 4.15 14.5 48.5 77.0 6.70 21.0 200 490

1. Guaranteed based on test during characterization, unless otherwise specified.

2. LSI using LSIPRE = 1 configuration.

(1)

Unit

µA

Page 89

Table 48. Current consumption during wakeup from Stop 1 mode

Typ a t 2 5 ° C

Conditions

= 1.8 V VDD = 2.4 V VDD = 3.0 V VDD = 3.6 V

Wakeup clock: MSI 4 MHz, voltage range 2 1.05 1.15 1.09 1.18

Wakeup clock: MSI 2 MHz, voltage range 2 1.81 1.81 2.12 2.40

Wakeup clock: MSI 4 MHz, voltage range 1 0.766 1.23 1.34 1.49

Wakeup clock: MSI 16 MHz, voltage range 1 0.310 0.169 0.935 0.836

Wakeup clock: MSI 48 MHz, voltage range 1 0.0707 0.461 0.533 0.565

STM32WL55/54xx Electrical characteristics

Unit

nAs

Table 49. Current consumption in Stop 0 mode

Conditions Typ Max

Symbol Parameter

DS13293 Rev 1 89/145

(Stop 0)

1. Guaranteed based on test during characterization, unless otherwise specified.

Supply current in Stop 0 mode RTC disabled

Table 50. Current consumption during wakeup from Stop 0 mode

Conditions

Wakeup clock: MSI 4 MHz, voltage range 2 3.45 3.76 3.45 4.04

Wakeup clock: MSI 2 MHz, voltage range 2 3.05 3.20 3.74 3.35

Wakeup clock: MSI 4 MHz, voltage range 1 3.20 3.66 3.30 4.11

Wakeup clock: MSI 16 MHz, voltage range 1 1.07 1.25 1.71 1.80

Wakeup clock: MSI 48 MHz, voltage range 1 0.867 1.13 1.39 0.949

(1)

(V)

0 °C 25 °C 55 °C 85 °C 105 °C 0 °C 25 °C 85 °C 105 °C

1.8 335 345 365 415 455 480 500 740 1200

2.4360370395445485----

3.0 390 400 425 475 515 540 570 800 1200

3.6 425 435 460 515 550 580 600 840 1300

Typ a t 2 5 ° C

Unit

VDD = 1.8 V VDD = 2.4 V VDD = 3.0 V VDD = 3.6 V

nAs

Unit

µA

Page 90

90/145 DS13293 Rev 1

Table 51. Current consumption in Standby mode

Conditions Typ Max

Symbol Parameter

(V)

0 °C 25 °C 55 °C 85 °C 105 °C 0 °C 25 °C 85 °C 105 °C

1.8 0.009 0.027 0.245 1.00 2.40 - - - -

2.4 0.022 0.051 0.340 1.35 2.85 - - - -

3.0 0.046 0.071 0.470 1.75 3.40 - - - -

3.6 0.075 0.125 0.650 2.30 4.05 - - - -

1.8 0.130 0.205 0.820 2.90 5.55 0.200 0.550 8.20 24.0

2.4 0.140 0.225 0.915 3.25 6.05 - - - -

3.0 0.165 0.255 1.05 3.70 6.60 0.280 0.710 9.40 27.0

(Standby)

Supply current in Standby mode RTC disabled Backup registers retained

No retention

SRAM2 retained

3.6 0.190 0.300 1.20 4.25 7.25 0.330 0.770 10.0 28.0

1.8 0.215 0.295 0.895 3.10 5.30 - - - -

RTC clocked by LSI (PREDIV = 1)

RTC clocked by LSE

(2)

quartz

in low drive

(Standby

with RTC)

Supply current in Standby mode (backup registers and SRAM2 retained) RTC enabled

mode

1. Guaranteed by characterization results, unless otherwise specified.

2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.

Table 52. Current consumption during wakeup from Standby mode

2.4

3.0

3.6

1.8

2.4

3.0

3.6

0.230 0.325 0.990 3.45 5.95 - - - -

0.260 0.360 1.15 3.95 6.85 - - - -

0.305 0.425 1.30 4.55 7.85 - - - -

0.270 0.350 0.975 3.15 5.80 - - - -

0.295 0.390 1.10 3.50 6.25 - - - -

0.345 0.445 1.25 4.00 6.85 - - - -

0.415 0.535 1.45 4.60 7.55 - - - -

Typ at 25 °C

Symbol Conditions

= 1.8 V VDD = 2.4 V VDD = 3.0 V VDD = 3.6 V

IDD (wakeup from Standby)

Wakeup clock: MSI 4 MHz 23.5 81.3 111 114

Wakeup clock: MSI 8 MHz 15.2 15.7 17.3 19.6

Electrical characteristics STM32WL55/54xx

(1)

Unit

µA

Unit

nAs

Page 91

Symbol Parameter

Table 53. Current consumption in Shutdown mode

Conditions Typ Max

(V)

1.8 0.001 0.008 0.105 0.380 0.995 0.001 0.043 1.70 6.40

0 °C 25 °C 55 °C 85 °C 105 °C 0 °C 25 °C 85 °C 105 °C

STM32WL55/54xx Electrical characteristics

(1)

Unit

(Shutdown)

Supply current in Shutdown mode RTC disabled Backup registers retained

2.40.0080.0180.1350.4451.20----

3.0 0.018 0.031 0.180 0.545 1.45 0.078 0.150 2.40 8.50

3.6 0.041 0.062 0.260 0.690 1.80 0.110 0.190 2.90 9.90

1.80.0540.0650.1450.5451.35----

2.40.0900.1050.2000.6651.60----

3.00.1600.1750.2950.8601.95----

3.60.2500.2800.4401.152.45----

1.80.1400.1550.2700.6051.20----

2.40.1650.1850.3150.7051.40----

3.00.2050.2250.3800.8551.70----

DS13293 Rev 1 91/145

(Shutdown

with RTC)

Supply current in Shutdown mode (backup registers retained) RTC enabled

RTC clocked by

an external clock

RTC clocked by LSE quartz

(2)

low drive mode

3.60.2650.2950.5001.102.10----

1. Guaranteed by characterization results, unless otherwise specified.

2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.

µA

Page 92

92/145 DS13293 Rev 1

Table 54. Current consumption in VBAT mode

Conditions Typ Max

Symbol Parameter

BAT

(V)

0 °C 25 °C 55 °C 85 °C 105 °C 105 °C

1.8 1.00 3.00 19.0 95.0 180 1.00

2.4 1.00 3.00 22.0 110 200 1.00

3.0 1.00 5.00 31.0 150 270 1.00

3.6 3.00 11.0 50.0 220 380 3.00

1.8 140 150 180 275 390 140

2.4 155 170 200 310 435 155

(1)

3.0 185 200 235 375 545 185

(VBAT)

RTC disabled

Backup domain supply current

RTC enabled and clocked by LSE quartz

3.6 230 245 295 485 710 230

1. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.

Table 55. Current under Reset condition

Conditions Typ

Symbol

(V) 25 °C

1.8 V 600

(RST)

2.4 V 650

3.0 V 700

3.6 V 780

Electrical characteristics STM32WL55/54xx

Unit

µA

Page 93

STM32WL55/54xx Electrical characteristics

DDfSW

C××=

I/O system current consumption

The current consumption of the I/O system has two components: a static and a dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 75: I/O static characteristics.

For the output pins, any external pull-down or external load must also be considered to estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs.

Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,

as a result of external electromagnetic noise. To avoid current consumption related to floating pins, these pins must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption measured previously (see

Table 56: Peripheral current consumption, the I/Os used by an application also contribute to

the current consumption. When an I/O pin switches, it uses the current from the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin:

where

• I

• V

• f

• C is the total capacitance seen by the I/O pin: C = C

• C

is the current sunk by a switching I/O to charge/discharge the capacitive load.

is the I/O supply voltage.

is the I/O switching frequency.

+ C

EXT .

is the PCB board capacitance plus any connected external device pin

EXT

capacitance.

The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.

DS13293 Rev 1 93/145

135

Page 94

Electrical characteristics STM32WL55/54xx

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in the table below. The device is placed under the following conditions:

• All I/O pins are in analog mode.

• The given value is calculated by measuring the difference of the current consumptions:

– when the peripheral is clocked on

– when the peripheral is clocked off

• Ambient operating temperature and supply voltage conditions summarized in Table 21:

Voltage characteristics.

• The power consumption of the digital part of the on-chip peripherals is given in the table below. The power consumption of the analog part of the peripherals (where applicable) is indicated in each related section of the datasheet.

Peripheral Range 1 Range 2 LPRun and LPSleep Unit

CRC1 0.42 0.38 1.00

DMA1 2.29 1.88 1.45

Table 56. Peripheral current consumption

AHB1

AHB2

AHB3

DMA2 2.50 1.94 1.50

DMAMUX1 3.96 3.38 2.50

All AHB1 peripherals 9.17 7.50 9.30

GPIOA 0.01 0.12 0.20

GPIOB 0.01 0.12 0.15

GPIOC 0.01 0.12 0.15

GPIOH 0.01 0.06 0.10

All AHB2 peripherals 0.62 0.56 0.40

AES1 2.50 2.13 1.80

FLASH 7.92 6.56 11.3

PKA 3.33 2.75 2.15

RNG1 1.04 N/A N/A

RNG1 independent clock domain 0.62 N/A N/A

SRAM1 0.62 0.38 0.55

SRAM2 0.42 0.37 0.50

All AHB3 peripherals

DAC 0.83 0.69 0.50

I2C1 1.67 1.37 1.05

(1)

16.0 13.4 16.0

µA/MHz

APB1

I2C1 independent clock domain 2.29 1.94 1.40

I2C2 1.67 1.37 1.05

I2C2 independent clock domain 2.50 2.00 1.60

I2C3 1.67 1.37 0.90

94/145 DS13293 Rev 1

µA/MHz

Page 95

STM32WL55/54xx Electrical characteristics

Table 56. Peripheral current consumption (continued)

Peripheral Range 1 Range 2 LPRun and LPSleep Unit

I2C3 independent clock domain 2.29 1.87 1.30

LPTIM1 1.67 1.44 1.50

LPTIM1 independent clock domain 2.50 2.19 1.45

LPTIM2 1.67 1.37 0.90

LPTIM2 independent clock domain 2.50 2.12 1.55

LPTIM3 0.83 0.69 0.65

LPTIM3 independent clock domain 2.29 1.94 0.65

LPUART1 2.08 1.81 3.55

APB1

LPUART1 independent clock domain

RTCAPB 2.08 1.81 1.50

SPI2 1.46 1.19 0.90

TIM2 4.58 3.81 2.95

USART2 1.88 1.56 1.35

USART2 independent clock domain 4.58 3.75 3.05

2.50 2.06 1.35

µA/MHz

WWDG1 0.42 0.31 0.05

All APB1 peripherals

ADC 1.25 1.00 0.70

ADC independent clock domain 0.21 0.13 0.30

SPI1 1.25 1.06 0.90

TIM1 6.25 5.19 8.30

APB2

APB3

All peripherals

1. Without independent clocks.

TIM16 2.29 1.94 1.35

TIM17 2.29 1.87 1.25

USART1 1.67 1.38 1.00

USART1 independent clock domain 4.17 3.38 2.90

All APB2 peripherals

SUBGHZSPI 1.46 1.25 1.10

(1)

19.6 16.1 20.2

15.8 13.0 15.8

62.9 52.3 59.7

5.3.8 Wakeup time from low-power modes and voltage scaling transition times

µA/MHz

µA/MHzAll APB3 peripherals 1.46 1.25 1.10

The wakeup times given in the table below, are the latency between the event and the execution of the first user instruction.

The device goes in low-power mode after the WFE (wait for event) instruction.

DS13293 Rev 1 95/145

135

Page 96

Electrical characteristics STM32WL55/54xx

Table 57. Low-power mode wakeup timings

(1)

Symbol Parameter Conditions Typ Max Unit

WUSLEEP

WULPSLEEP

Wakeup time from Sleep to Run mode

Wakeup time from LPSleep to LPRun mode

- 0.188 0.222

Wakeup in Flash with memory in power-down during LPSleep mode (FPDS = 1 in PWR_CR1) and with clock MSI = 2 MHz

3.81 4.38

Wakeup clock MSI = 48 MHz 2.14 2.90

Wakeup clock MSI = 16 MHz 2.78 3.58

Wakeup clock HSI16 = 16 MHz 1.99 -

To Run mode (Range 1)

Wakeup clock HSI16 = 16 MHz with HSIKERON enabled

1.01 1.13

WUSTOP0

Wakeup time from Stop 0 mode in Flash memory

(2)

Wakeup clock MSI = 4 MHz 6.79 8.21

Wakeup clock MSI = 2 MHz 10.4 12.2

To LPRun mode Wakeup clock MSI = 2 MHz 10.5 12.3

Wakeup clock MSI = 48 MHz 5.15 6.55

Wakeup clock MSI = 16 MHz 5.73 7.14

Wakeup clock HSI16 = 16 MHz 5.71 7.10

To Run mode (Range 1)

Wakeup clock HSI16 = 16 MHz with HSIKERON enabled

4.57 6.52

WUSTOP1

Wakeup time from Stop 1 mode in Flash memory

(2)

Wakeup clock MSI = 4 MHz 8.43 9.93

µs

Wakeup clock MSI = 2 MHz 11.9 13.7

To LPRun mode Wakeup clock MSI = 2 MHz 10.6 13.9

Wakeup clock MSI = 48 MHz 5.56 6.85

Wakeup clock MSI = 16 MHz 6.32 7.59

Wakeup clock HSI16 = 16 MHz 6.28 7.51

Wakeup clock HSI16 = 16 MHz with HSIKERON enabled

6.26 7.53

WUSTOP2

Wakeup time from Stop 2 mode in Flash memory

(2)

To Run mode (Range 1)

Wakeup clock MSI = 4 MHz 9.69 10.9

Wakeup clock MSI = 2 MHz 14.0 15.4

WUSTBY

WUSHUTD

1. Guaranteed by characterization results (VDD = 3 V, T = 25 °C).

2. Wakeup time is equivalent when code is executed from SRAM1 compared to Flash memory. It is also equivalent when

going to Range 2 rather than Range 1.

Wakeup time from Standby to Run mode

Wakeup time from Shutdown to Run mode

Range 1

Range 1 Wakeup clock MSI = 4 MHz 264 316

Wakeup clock MSI = 4 MHz 34.3 39.2

Wakeup clock MSI = 8 MHz 22.4 25.6

µs

96/145 DS13293 Rev 1

Page 97

STM32WL55/54xx Electrical characteristics

Table 58. Regulator modes transition times

(1)

Symbol Parameter Conditions Typ Max Unit

WULPRUN

VOST

1. Guaranteed by characterization results (VDD = 3 V, T = 25 °C).

2. Time until REGLPF flag is cleared in PWR_SR2.

3. Time until VOSF flag is cleared in PWR_SR2.

Transition time from LPRun to Run

(2)

mode

Regulator transition time from Range 2 to Range 1

Regulator transition time from Range 1 to Range 2

(3)

Code run with MSI = 2 MHz 19.6 -

21.9 32.2

Code run with HSI16

23.1 33.9

5.3.9 External clock source characteristics

High-speed external user clock generated from an external source

The high-speed external (HSE32) clock can be supplied with a 32 MHz crystal oscillator or by a TCXO (temperature controlled crystal oscillator).

Crystal oscillator

The devices include internal programmable capacitances that can be used to tune the crystal frequency in order to compensate the PCB parasitic one.

µs

Characteristics in the tables below, are measured over recommended operating conditions, unless otherwise specified. Typical values are referred to T

Symbol Parameter Conditions Min Typ Max Unit

nom

TOL

Shunt

motion

ESR

1. 32 MHz XTAL is specified for two specific references: NX2016SA and NX1612SA.

2. Load capacitance can be managed by internal programmable capacitances at calibration phase. No need to add external

foot capacitances. The values indicated take into account the combination of the two foot capacitances.

Oscillator frequency - - 32 - MHz

Frequency accuracy

Load capacitance

Load

Crystal shunt capacitance - 0.3 0.6 2

Crystal motional capacitance - 1.3 1.89 2.5 fF

Crystal equivalent series resistance

Drive level - - - 100 µW

Table 59. HSE32 crystal requirements

Initial - - ±10

Aging over 10 years - - ±10

(2)

-9.51010.5

- - 30 60 

= 25 °C and VDD = 3 V.

(1)

ppmOver temperature (-20 to 70 °C) - - ±10

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Electrical characteristics STM32WL55/54xx

Table 60. HSE32 oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

stabilized,

SUA(HSE)

SUR(HSE)

DDRF(HSE)

XOT

g(HSE)

XOT

fp(HSE)

Startup time for 80% amplitude stabilization

Startup time for HSEREADY signal

HSE32 current consumption

SUBGHZ_HSEINTRIMR granularity

SUBGHZ_HSEINTRIMR frequency pulling

DDRF

SUBGHZ_HSEINTRIMR = 0x12,

-40 to +105 °C temperature range

stabilized,

DDRF

SUBGHZ_HSEINTRIMR = 0x12,

-40 to +105 °C temperature range

HSEGMC = 000, SUBGHZ_HSEINTRIMR = 0x12

-1000-

- 180 -

-50-µA

-15

±15 ±30 -

Capacitor bank

XOT

nb(HSE)

st(HSE)

SUBGHZ_HSEINTRIMR number of tuning bits

SUBGHZ_HSEINTRIMR setting time

-6-bit

--0.1ms

For more information about the trimming methodology of the oscillator, refer to the application note HSE trimming for STM32 wireless MCUs (AN5042).

µs

ppm

TCXO regulator

Symbol Parameter Conditions Min Typ Max Unit

TCXO

Regulated voltage range for TCXO voltage supply

ILTCXO Load current for TCXO regulator - - 1.5 4 mA

TSVTCXO Startup time for TCXO regulator

IDDTCXO

ATC XO

1. In order to minimize spurious injection, the capacitance value must be calculated such that an amplitude of

0.4 to 0.5 Vpk-pk on OSC_IN is obtained. For TCXO output voltage of 0.8 Vpk-pk, 10 pF can be used.

Current consumption for TCXO regulator

Amplitude voltage for external TCXO applied to OSC_IN pin

Table 61. HSE32 TCXO regulator characteristics

> V

DDOP

From enable to regulated voltage within 25 mV from target

Quiescent current - - 70 µA

Relative to load current - 1.6 2 %

Provided through a 220  resistor in series with a capacitance (voltage divider)

+ 200 mV 1.6 1.7 3.3 V

TCXO

(1)

- - 50 µs

0.4 0.6 1.2 Vpk-pk

Low-speed external user clock generated from an external source

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator. The information provided in this section is based on design simulation results obtained with typical external components specified in the table below. In the application,

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STM32WL55/54xx Electrical characteristics

MS30253V2

OSC32_IN

OSC32_OUT

Drive

programmable

amplifier

LSE

32.768 kHz resonator

Resonator with integrated capacitors

the resonator and the load capacitors have to be placed as close as possible to the oscillator pins to minimize output distortion and startup stabilization time.

Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Table 62. Low-speed external user clock characteristics

Symbol Parameter Conditions Min Typ Max Unit

LSEDRV[1:0] = 00 - Low drive capability - 250 -

(1)

DD(LSE)

LSE current consumption

LSEDRV[1:0] = 01 - Medium-low drive capability - 315 -

LSEDRV[1:0] = 10 - Medium-high drive capability - 500 -

LSEDRV[1:0] = 11 - High drive capability - 630 -

LSEDRV[1:0] = 00 - Low drive capability - - 0.50

mcritmax

Maximum critical crystal g

LSEDRV[1:0] = 01 - Medium-low drive capability - - 0.75

LSEDRV[1:0] = 10 - Medium-high drive capability - - 1.70

LSEDRV[1:0] = 11 - High drive capability - - 2.70

1. Guaranteed by design.

2. t

(2)

SU(LSE)

reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer.

Startup time VDD stabilized - 2 - s

is the startup time measured from the moment it is enabled (by software) until a stable 32.768 kHz oscillation is

For more information on the crystal selection, refer to application note Oscillator design guide for STM8AF/AL/S, STM32 MCUs and MPUs (AN2867).

Figure 16. Typical application with a 32.768 kHz crystal

µA/V

Note: No external resistors are required between OSC32_IN and OSC32_OUT, and it is forbidden

to add one.

In bypass mode, the LSE oscillator is switched off and the input pin is a standard GPIO.

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Electrical characteristics STM32WL55/54xx

MS19215V2

LSEH

f(LSE)

90%

10%

LSE

r(LSE)

LSEL

w(LSEH)

w(LSEL)

The external clock signal has to respect the I/O characteristics detailed in Section 5.3.16:

I/O port characteristics.The recommend clock input waveform is shown in the figure below.

Figure 17. Low-speed external clock source AC timing diagram

Table 63. Low-speed external user clock characteristics

(1)

– Bypass mode

Symbol Parameter Conditions Min Typ Max Unit

LSE_ext

LSEH

LSEL

w(LSEH)

w(LSEL)

User external clock source frequency

OSC32_IN input pin highlevel voltage

OSC32_IN input pin lowlevel voltage

OSC32_IN high or low time - 250 - - ns

- 21.2 32.768 44.4 kHz

-V

0.7 x

DDx

-V

- 0.3 x V

DDx

Includes initial accuracy,

tolLSE

Frequency tolerance

stability over temperature,

–500 - +500 ppm

aging and frequency pulling

1. Guaranteed by design.

5.3.10 Internal clock source characteristics

Parameters given in the table below are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 25: General operating

conditions. The provided curves are characterization results, not tested in production.

High-speed internal (HSI16) RC oscillator

Symbol Parameter Conditions Min Typ Max Unit

HSI16

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HSI16 frequency V

Table 64. HSI16 oscillator characteristics

(1)

= 3.0 V, TA = 30 °C 15.88 - 16.08 MHz