ST MICROELECTRONICS STM32WL55CCU6 Datasheet

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STM32WL55xx STM32WL54xx

UFQFPN48 (7 x 7 mm)

UFBGA73 (5 x 5 mm)

WLCSP59

Multiprotocol LPWAN dual core 32-bit Arm® Cortex®-M4/M0+

LoRa

Features

Radio

• Frequency range: 150 MHz to 960 MHz

• Modulation: LoRa

BPSK

• RX sensitivity: (at 1.2 Kbit/s), (at 10.4 kHz, spreading factor 12)

• Transmitter high output power, programmable up to +22 dBm

• Transmitter low output power, programmable up to +15 dBm

• Compliant with the following radio frequency regulations such as ETSI EN 300 220, EN 300 113, EN 301 166, FCC CFR 47 Part 15, 24, 90, 101 and the Japanese ARIB STD-T30, T-67, T-108

• Compatible with standardized or proprietary protocols such as LoRaWAN W-MBus and more (fully open wireless system-on-chip)

Ultra-low-power platform

• 1.8 V to 3.6 V power supply

•

–40 °C to +105 °C temperature range

• Shutdown mode: 31 nA (V

• Standby (+ RTC) mode:

360 nA (V

• Stop2 (+ RTC) mode: 1.07 µA (V

• Active-mode MCU: < 72 µA/MHz (CoreMark

• Active-mode RX: 4.82 mA

• Active-mode TX: 15 mA at 10 dBm and 87 mA

at 20 dBm (LoRa

Core

• 32-bit Arm® Cortex®-M4 CPU

, (G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM

, (G)FSK, (G)MSK and

–123 dBm for 2-FSK –148 dBm for LoRa

= 3 V)

125 kHz)

, Sigfox™,

= 3 V)

Datasheet - production data

– Adaptive real-time accelerator (ART

Accelerator) allowing 0-wait-state execution from Flash memory, frequency up to 48 MHz, MPU and DSP instructions

– 1.25 DMIPS/MHz (Dhrystone 2.1)

• 32-bit Arm

Cortex®-M0+ CPU

– Frequency up to 48 MHz, MPU – 0.95 DMIPS/MHz (Dhrystone 2.1)

Security and identification

• Hardware encryption AES 256-bit

• True random number generator (RNG)

• Sector protection against read/write operations

(PCROP, RDP, WRP)

• CRC calculation unit

• Unique device identifier (64-bit UID compliant

with IEEE 802-2001 standard)

• 96-bit unique die identifier

• Hardware public key accelerator (PKA)

• Key management services

• Secure sub-GHz MAC layer

• Secure firmware update (SFU)

• Secure firmware install (SFI)

)

Supply and reset management

• High-efficiency embedded SMPS step-down converter

• SMPS to LDO smart switch

• Ultra-safe, low-power BOR (brownout reset)

with 5 selectable thresholds

• Ultra-low-power POR/PDR

November 2020 DS13293 Rev 1 1/145

This is information on a product in full production.

www.st.com

STM32WL55/54xx

• Programmable voltage detector (PVD)

• V

mode with RTC and 20x32-byte backup

BAT

registers

Clock sources

• 32 MHz crystal oscillator

• TCXO support: programmable supply voltage

• 32 kHz oscillator for RTC with calibration

• High-speed internal 16 MHz factory trimmed

RC (± 1 %)

• Internal low-power 32 kHz RC

• Internal multi-speed low-power 100 kHz to

48 MHz RC

• PLL for CPU, ADC and audio clocks

Memories

• 256-Kbyte Flash memory

• 64-Kbyte RAM

• 20x32-bit backup register

• Bootloader supporting USART and SPI

interfaces

• OTA (over-the-air) firmware update capable

• Sector protection against read/write operations

System peripherals

• Mailbox and semaphores for communication between Cortex firmware

-M4 and Cortex®-M0+

Controllers

• 2x DMA controller (7 channels each) supporting ADC, DAC, SPI, I2C, LPUART, USART, AES and timers

• 2x USART (ISO 7816, IrDA, SPI)

• 1x LPUART (low-power)

• 2x SPI 16 Mbit/s (1 over 2 supporting I2S)

• 3x I2C (SMBus/PMBus™)

• 2x 16-bit 1-channel timer

• 1x 16-bit 4-channel timer (supporting

motor control)

• 1x 32-bit 4-channel timer

• 3x 16-bit ultra-low-power timer

• 1x RTC with 32-bit sub-second wakeup

counter

• 1x independent SysTick

• 1x independent watchdog

• 1x window watchdog

Rich analog peripherals (down to 1.62 V)

• 12-bit ADC 2.5 Msps, up to 16 bits with hardware oversampling, conversion range up to 3.6 V

• 12-bit DAC, low-power sample-and-hold

• 2x ultra-low-power comparators

Table 1. Device summary

Reference Part number

STM32WL55xx STM32WL55CC, STM32WL55JC, STM32WL55UC

STM32WL54xx STM32WL54CC, STM32WL54JC, STM32WL54UC

Up to 43 I/Os, most 5 V-tolerant

Development support

• Serial-wire debug (SWD), JTAG

• Dual CPU cross trigger capabilities

All packages ECOPACK2 compliant

2/145 DS13293 Rev 1

STM32WL55/54xx Contents

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.2 Arm Cortex-M cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.3 Adaptive real-time memory accelerator (ART Accelerator) . . . . . . . . . . . 15

3.4 Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.5 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.5.1 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.5.2 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.6 Security memory management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.7 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.8 Global security controller (GTZC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.9 Sub-GHz radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.9.2 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.9.3 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.9.4 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.9.5 RF-PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.9.6 Intermediate frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.10 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.10.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.10.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.10.3 Linear voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.10.4 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.11 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.11.1 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.12 Peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.13 Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.14 Hardware semaphore (HSEM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.15 Inter-processor communication controller (IPCC) . . . . . . . . . . . . . . . . . . 38

DS13293 Rev 1 3/145

Contents STM32WL55/54xx

3.16 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.17 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.18 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.18.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 39

3.18.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 39

3.19 Cyclic redundancy check (CRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.20 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.20.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.20.2 Internal voltage reference (V

3.20.3 V

battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

BAT

) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

REFINT

3.21 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.22 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.23 Comparator (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.24 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.25 Advanced encryption standard hardware accelerator (AES) . . . . . . . . . . 42

3.26 Public key accelerator (PKA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.27 Timer and watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.27.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.27.2 General-purpose timers (TIM2, TIM16, TIM17) . . . . . . . . . . . . . . . . . . . 43

3.27.3 Low-power timers (LPTIM1, LPTIM2 and LPTIM3) . . . . . . . . . . . . . . . . 44

3.27.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.27.5 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.27.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.28 Real-time clock (RTC), tamper and backup registers . . . . . . . . . . . . . . . 45

3.29 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.30 Universal synchronous/asynchronous receiver transmitter

(USART/UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.31 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 47

3.32 Serial peripheral interface (SPI)/integrated-interchip sound

interface (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.33 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4 Pinouts, pin description and alternate functions . . . . . . . . . . . . . . . . . 49

5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

4/145 DS13293 Rev 1

STM32WL55/54xx Contents

5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.3.1 Main performances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.3.2 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.3.3 Sub-GHz radio characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.3.4 Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . 74

5.3.5 Embedded reset and power-control block characteristics . . . . . . . . . . . 75

5.3.6 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

5.3.7 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

5.3.8 Wakeup time from low-power modes and voltage scaling

transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

5.3.9 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

5.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 100

5.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

5.3.12 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

5.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

5.3.14 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

5.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

5.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

5.3.17 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

5.3.18 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

5.3.19 Analog-to-digital converter characteristics . . . . . . . . . . . . . . . . . . . . . . 116

5.3.20 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

5.3.21 V

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

BAT

5.3.22 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 122

5.3.23 Digital-to-analog converter characteristics . . . . . . . . . . . . . . . . . . . . . . 124

5.3.24 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

5.3.25 Timers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

5.3.26 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 130

DS13293 Rev 1 5/145

Contents STM32WL55/54xx

6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

6.1 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

6.2 WLCSP59 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

6.3 UFBGA73 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

6.4 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

6/145 DS13293 Rev 1

STM32WL55/54xx List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2. Main features and peripheral count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 3. Access status versus RDP level and execution mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 4. Sub-GHz radio transmit high output power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 5. FSK mode intermediate frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 6. LoRa mode intermediate frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 7. Functionalities depending on system operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 8. Low-power mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 9. MCU and sub-GHz radio operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 10. Peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 11. DMA1 and DMA2 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 12. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 13. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 14. Timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 15. I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 16. USART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 17. SPI and SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 18. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 19. STM32WL55/54xx pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 20. Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 21. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 22. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 23. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 24. Main performances at VDD = 3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 25. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 26. Operating range of RF pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 27. Sub-GHz radio power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 28. Sub-GHz radio power consumption in transmit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 29. Sub-GHz radio general specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 30. Sub-GHz radio receive mode specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 31. Sub-GHz radio transmit mode specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 32. Sub-GHz radio power management specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 33. Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 34. Embedded reset and power-control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 35. Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 36. Current consumption in Run and LPRun modes on CPU1, CoreMark code with data

running from Flash memory, ART enable (cache ON, prefetch OFF) . . . . . . . . . . . . . . . . 78

Table 37. Current consumption in Run and LPRun modes on CPU1 and CPU2, CoreMark code

with data running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 38. Current consumption in Run and LPRun modes on CPU1, CoreMark code

with data running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 39. Typical current consumption in Run and LPRun modes on CPU1, with different codes

running from Flash memory, ART enable (cache ON, prefetch OFF) . . . . . . . . . . . . . . . . 81

Table 40. Typical current consumption in Run and LPRun modes on CPU1,

with different codes running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 41. Current consumption in Sleep and LPSleep modes on CPU1, Flash memory ON . . . . . . 85

Table 42. Current consumption in Sleep and LPSleep modes on CPU1 and CPU2,

Flash memory ON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

DS13293 Rev 1 7/145

List of tables STM32WL55/54xx

Table 43. Current consumption in LPSleep mode on CPU1, Flash memory in power-down . . . . . . . 86

Table 44. Current consumption in LPSleep mode on CPU1 and CPU2,

Flash memory in power-down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 45. Current consumption in Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 46. Current consumption during wakeup from Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 47. Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 48. Current consumption during wakeup from Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 49. Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 50. Current consumption during wakeup from Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 51. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 52. Current consumption during wakeup from Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 53. Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 54. Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 55. Current under Reset condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 56. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 57. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 58. Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 59. HSE32 crystal requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 60. HSE32 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 61. HSE32 TCXO regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 62. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 63. Low-speed external user clock characteristics – Bypass mode . . . . . . . . . . . . . . . . . . . . 100

Table 64. HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 65. MSI oscillator characteristics

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102

Table 66. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 67. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Table 68. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Table 69. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 70. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 71. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 72. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 73. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 74. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Table 75. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table 76. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 77. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 78. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Table 79. Analog switches booster characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Table 80. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Table 81. Maximum ADC R

values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

AIN

Table 82. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Table 83. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Table 84. V Table 85. V

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

BAT

charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

BAT

Table 86. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 87. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Table 88. DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Table 89. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Table 90. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 91. IWDG min/max timeout period at 32 kHz (LSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Table 92. Minimum I2CCLK frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Table 93. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

8/145 DS13293 Rev 1

STM32WL55/54xx List of tables

Table 94. USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Table 95. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Table 96. Dynamic JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Table 97. Dynamic SWD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Table 98. UFQFPN48 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Table 99. UFBGA73 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Table 100. UFBGA recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . 141

Table 101. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Table 102. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

DS13293 Rev 1 9/145

List of figures STM32WL55/54xx

List of figures

Figure 1. STM32WL55/54xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 2. sub-GHz radio system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 3. High output power PA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 4. Low output power PA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 5. Power-up/power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 6. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 7. Supply configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 8. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 9. UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 10. UFBGA73 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 11. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 12. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 13. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 14. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 15. VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 16. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 17. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 18. HSI16 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Figure 19. Typical current consumption vs. MSI frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Figure 20. I/O input characteristics - V

Figure 21. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 22. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 23. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 24. VREFOUT_TEMP when VRS = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Figure 25. VREFOUT_TEMP when VRS = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 26. 12-bit buffered/non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Figure 27. SPI timing diagram - Slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Figure 28. SPI timing diagram - Slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Figure 29. SPI timing diagram - Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Figure 30. UFQFPN48 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Figure 31. UFQFPN48 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Figure 32. UFQFPN48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Figure 33. UFBGA73 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Figure 34. UFBGA73 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Figure 35. UFBGA73 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

and V

on all I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

10/145 DS13293 Rev 1

STM32WL55/54xx Introduction

1 Introduction

This document provides information on the STM32WL55/54xx microcontrollers.

®(a)

For information on the Arm

Cortex

-M4 Technical Reference Manual and to the Cortex®-M0+ Technical Reference

Cortex®-M4 and Cortex®-M0+ cores, refer respectively to the

Manual available from the www.arm.com website.

For information on LoRa

modulation, refer to the Semtech website

(https://www.semtech.com/technology/lora).

2 Description

The STM32WL55/54xx long-range wireless and ultra-low-power devices embed a powerful

and ultra-low-power LPWAN-compliant radio solution, enabling the following modulations:

LoRa

, (G)FSK, (G)MSK, and BPSK.

The LoRa

These devices are designed to be extremely low-power and are based on the

high-performance Arm

48 MHz. This core implements a full set of DSP instructions. It is complemented by an Arm

Cortex

modulation is available in STM32WLx5xx only.

Cortex®-M4 32-bit RISC core operating at a frequency of up to

-M0+ microcontroller. Both cores implement an independent memory protection unit

(MPU) that enhances the application security.

The devices embed high-speed memories (256-Kbyte Flash memory, 64-Kbyte SRAM), and

an extensive range of enhanced I/Os and peripherals.

The devices also embed several protection mechanisms for embedded Flash memory and

SRAM: readout protection, write protection and proprietary code readout protection.

In addition, the STM32WL55/54xx devices support the following secure services running on

Arm

Cortex-M0+: unique boot entry capable, secure sub-GHz MAC layer, secure firmware

update, secure firmware install and storage and management of secure keys.

These devices offer a 12-bit ADC, a 12-bit DAC low-power sample-and-hold, two

ultra-low-power comparators associated with a high-accuracy reference voltage generator.

The devices embed a low-power RTC with a 32-bit sub-second wakeup counter, one 16-bit

single-channel timer, two 16-bit four-channel timers (supporting motor control), one 32-bit

four-channel timer and three 16-bit ultra-low-power timers.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

DS13293 Rev 1 11/145

Description STM32WL55/54xx

These devices also embed two DMA controllers (7 channels each) allowing any transfer

combination between memory (Flash memory, SRAM1 and SRAM2) and peripheral, using

the DMAMUX1 for flexible DMA channel mapping.

The devices also feature the standard and advanced communication interfaces listed below:

• inter-processor communication controller (mailbox) and semaphores for communication between the two Arm

Cortex®-M cores

• two USART (supporting LIN, smartcard, IrDA, modem control and ISO7816)

• one low-power UART (LPUART)

• three I2C (SMBus/PMBus)

• two SPIs (up to 16 MHz, one supporting I

The operating temperature/voltage ranges are

–40 °C to +105 °C (+85 °C with radio)

(a)

from a 1.8 V to 3.6 V power supply. A comprehensive set of power-saving modes allows the design of low-power applications.

The devices integrate a high-efficiency SMPS step-down converter and independent power supplies for ADC, DAC and comparator analog inputs.

A V

dedicated supply allows the LSE 32.768 kHz oscillator, the RTC and the backup

BAT

registers to be backed up. The devices can maintain these functions even if the main V not present, through a CR2032-like battery, a supercap or a small rechargeable battery.

Feature

CPU Arm

Maximum CPU frequency (MHz) 48

Flash memory density (Kbytes) 256

SRAM density (Kbytes)

Radio

Radio PA

SRAM1 32

SRAM2 32

LoRa

(G)FSK

BPSK

Low output power (up to 15 dBm)

High output power (up to 22 dBm)

Table 2. Main features and peripheral count

STM32WL55Cx

STM32WL54Cx

Available on STM32WL55xx devices.

Not available on STM32WL54xx devices

STM32WL55Jx

STM32WL54Jx

Cortex-M4 and Cortex-M0

Yes(G)MSK

Yes

STM32WL55Ux

STM32WL54Ux

General purpose 4

Timer

a. Devices with suffix 6 operate up to 85 °C. Devices with suffix 7 can operate up to 105 °C except radio.

12/145 DS13293 Rev 1

Low-power 3

SysTick 1

STM32WL55/54xx Description

Table 2. Main features and peripheral count (continued)

Feature

STM32WL55Cx

STM32WL54Cx

STM32WL55Jx

STM32WL54Jx

SPI/I2S 2 (1 supporting I2S)

Communication interface

USART 2

LPUART 1

Independent 1

Watchdog

Window 1

RTC (with wakeup counter) 1

DMA (7 channels) 2

Mailbox and semaphores 1

AES 256 bits 1

RNG 1

PKA 1

P C R O P, R DP, WR P 1

CRC 1

64-bit UID compliant with IEEE 802-2001 standard

Security

96-bit die ID 1

STM32WL55Ux

STM32WL54Ux

Storage and management of secure

keys

Secure sub-GHz MAC layer

Secure firmware update 1

Secure firmware install 1

Tamper pins 3 3 2

Wakeup pins 3 3 2

GPIOs 29 43 22

ADC (number of channels, ext + int) 1 (9 + 4) 1 (12 + 4) 1 (8 + 4)

DAC (number of channels) 1 (1)

Internal VREFBUF No Yes No

Analog comparator 2

Operating voltage 1.8 to 3.6 V

Ambient operating temperature –40 °C to +85 °C

Junction temperature –40 °C to +105 °C

Package

UFQFPN48

(7x7 mm)

UFBGA73

(5x5 mm)

WLCSP59

DS13293 Rev 1 13/145

Description STM32WL55/54xx

MSv66957V1

DMA1 (7 channels)

NVIC

TIM17

EXTI

TIM16

GPIO

ports A,B,C,H

PWR

SRAM1

RTC

TAMP

IWDG

LSE

32 kHz

HSE32 32 MHz

MSI 5 %

0.1-48MHz

HSI 1 % 16 MHz

PLL

Power supply

POR/PDR/BOR/PVD/PVM

ADC (12 bits ULP,

2 Msps, 12 channels)

Temperature sensor

APB1 and APB 2

Backup domain

JTAG/SWD

Flash interface arbiter

ART Accelerator

256-Kbyte

Flash memory

Sub-GHz

radio

RNG

LSI

32 kHz

LPTIM2

LPTIM1

CRC

RCC

SYSCFG/

COMP/VREF

HSEM

WWDG

SPI2S2

I2C3

LPUART1

SPI1

USART1

TIM2

MPU

SRAM2

backup memory

Cortex-M4

(DSP)

≤ 48 MHz

DMAMUX

DMA2 (7 channels)

LDO/SMPS

LPTIM3

TIM1

I2C1

I2C2

USART2

DAC

(12 bits)

AES

PKA

AHB1 and AHB2

TZSC

IPCC

NVIC

MPU

Cortex-M0+

≤ 48 MHz

SUBGHZ

SPI

CTI

TZIC

AHB3

Figure 1. STM32WL55/54xx block diagram

14/145 DS13293 Rev 1

STM32WL55/54xx Functional overview

3 Functional overview

3.1 Architecture

The devices embed a sub-GHz RF subsystem that interfaces with a generic microcontroller subsystem using an Arm Cortex-M4 (called CPU1) and an Arm Cortex-M0+ (called CPU2).

An RF low-layer stack is needed and is to be run on CPU1 or CPU2, whereas the host application code is preferably run on CPU1.

The RF subsystem communication is done through an internal SPI interface.

All secure code must be run by CPU2.

3.2 Arm Cortex-M cores

With its embedded Arm cores, the STM32WL55/54xx devices are compatible with all Arm tools and software.

Figure 1 shows the general block diagram of the STM32WL55/54xx devices.

Arm Cortex-M4

The Arm Cortex-M4 is a processor for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.

The Arm Cortex-M4 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an Arm core in the memory size usually associated with 8- and 16-bit devices.

This processor supports a set of DSP instructions that allow efficient signal processing and complex algorithm execution.

Arm Cortex-M0+

The Arm Cortex-M0+ is an entry-level processor for embedded systems. It has been developed to provide lowest power consumption in the Cortex-M family, while delivering good computation performance and response to interrupts.

The Arm Cortex-M0+ 32-bit RISC processor features good code-efficiency with ultra-low power consumption in the memory size usually associated with 8-bit and 16-bit devices.

3.3 Adaptive real-time memory accelerator (ART Accelerator)

The ART Accelerator is a memory accelerator that is optimized for STM32 industry-standard Arm Cortex-M4 processor. The ART Accelerator balances the inherent performance advantage of the Arm Cortex-M4 over Flash memory technologies, that normally require the processor to wait for the Flash memory at higher frequencies.

To release the processor near 60 DMIPS performance at 48 MHz, the ART Accelerator implements an instruction prefetch queue and branch cache, that increases the program execution speed from the 64-bit Flash memory. Based on CoreMark benchmark, the

DS13293 Rev 1 15/145

Functional overview STM32WL55/54xx

performance achieved thanks to the ART Accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 48 MHz.

3.4 Memory protection unit (MPU)

The memory protection unit (MPU) is used to manage the CPU1 and CPU2 accesses to memory, to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to eight protected areas that can in turn be divided up into eight subareas. The protection area sizes are between 32 bytes and the whole 4 Gbytes of addressable memory.

The MPU is especially helpful for applications where some critical or certified code must be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

3.5 Memories

3.5.1 Embedded Flash memory

The Flash memory interface manages the accesses from CPU1 AHB ICode/DCode and CPU2 AHB Sbus to the Flash memory. It implements the access, the erase and program Flash memory operations, and the read and write protection.

The main features of the Flash memory are listed below:

• Memory organization: 1 bank

– main memory: up to 256 Kbytes

– page size: 2 Kbytes

• 72-bit wide data read (64 bits plus 8 ECC bits)

• 72-bit wide data write (64 bits plus 8 ECC bits)

• Page erase and mass erase

Flexible protections can be configured thanks to option bytes:

• Readout protection (RDP) to protect the whole memory. Three levels are available:

– Level 0: no readout protection

– Level 1: memory readout protection. The Flash memory cannot be read from or

written to if either debug features are connected, boot in SRAM or bootloader is selected.

– Level 2: chip readout protection. Debug features (JTAG and serial wire), boot in

SRAM and bootloader selection are disabled (JTAG fuse). This selection can only be reverted by the secure CPU2.

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STM32WL55/54xx Functional overview

Table 3. Access status versus RDP level and execution mode

Area

Main memory

System memory

Option bytes

Backup registers

SRAM2

1. The option byte can be modified by the sub-GHz radio.

2. Erased when RDP changes from Level 1 to Level 0.

RDP level

Read Write Erase Read Write Erase

1 Yes Yes Yes No No No

2 Yes Yes Yes NA NA NA

1Yes No No Yes No No

2 Yes No No NA NA NA

1 Yes Yes Yes Yes Yes Yes

2Yes No

1Yes Yes NA

2YesYesNANANANA

1 Yes Yes Yes

2 Yes Yes Yes NA NA NA

User execution

(1)

• Write protection (WRP): the protected area is protected against erasing and

programming. Two areas can be selected, with 4-Kbyte granularity.

• Proprietary code readout protection (PCROP): two parts of the Flash memory can be

protected against read and write from third parties. The protected area is execute-only: it can only be reached by the STM32 CPU1/2, as an instruction code, while all other accesses (DMA, debug and CPU1/2 data read, write and erase) are strictly prohibited. Two areas can be selected, with 2-Kbyte granularity. An additional option bit (PCROP_RDP) is used to select if the PCROP area is erased or not when the RDP protection is changed from Level 1 to Level 0.

(1)

(2)

Debug, boot from SRAM or boot from

system memory (loader)

NA NA NA

No No NA

No No No

(2)

A section of the Flash memory can be secured for CPU2, and, in that case, cannot be accessed by CPU1.

The whole non-volatile memory embeds the error correction code (ECC) feature supporting:

• single error detection and correction

• double error detection

• address of the ECC fail can be read in the FLASH_ECCR register

The embedded Flash memory is shared between CPU1 and CPU2 on a time sharing basis. A dedicated hardware mechanism allows both CPUs to suspend write/erase operations.

3.5.2 Embedded SRAM

The devices feature up to 64 Kbytes of embedded SRAM, split in two blocks:

• SRAM1: up to 32 Kbytes mapped at address 0x2000 0000

• SRAM2: up to 32 Kbytes located at address 0x2000 8000 (contiguous to SRAM1), also

mirrored at 0x1000 0000, with hardware parity check (this SRAM can be retained in Standby mode)

The SRAMs can be accessed in read/write with 0 wait states for all CPU1/2 clock speeds.

DS13293 Rev 1 17/145

Functional overview STM32WL55/54xx

3.6 Security memory management

The devices contain many security blocks both for the sub-GHz MAC layer and the Host application, such as:

• securable RNG

• customer keys storage

• secure Flash memory partition for CPU2 only access

• secure SRAM partition, that can be accessed only by CPU2

• securable sub-GHz radio sub-system

• securable DMA channels

• securable AES: 128-and 256-bit AES, supporting ECB, CBC, CTR, GCM, GMAC and

CCM chaining modes

• securable PKA:

– modular arithmetic including exponentiation with maximum modulo size of

3136 bits

– elliptic curves over prime field scalar multiplication, ECDSA signature, ECDSA

verification with maximum modulo size of 521 bits

• cyclic redundancy check calculation unit (CRC)

3.7 Boot modes

At startup, BOOT0 pin and BOOT1 option bit are used to select one of the following boot options:

• Boot from user Flash memory

• Boot from boot system memory (where embedded bootloader is located)

• Boot from embedded SRAM

• Boot from system memory (where the embedded SFI is located)

The bootloader makes possible to download code from USART or SPI.

3.8 Global security controller (GTZC)

The GTZC includes the following sub-blocks:

• TZSC: security controller

This sub-block defines the secure/privileged state of slave peripherals. It also controls the unprivileged area size for the watermark memory peripheral controller (MPCWM).

• TZIC: security illegal access controller

This sub-block gathers all illegal access events in the system and generates a secure interrupt towards the secure CPU2 NVIC.

These sub-blocks are used to configure the system security and privilege such as:

• on-chip Flash memory and RAM with programmable privileged protection on both

secure and non-secure memory areas

• AHB and APB peripherals with programmable security and/or privileged access

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STM32WL55/54xx Functional overview

MSv62614V1

Sub-GHz radio

Sub-GHz

RF frontend

Radio control

SUBGHZSPI

hse32

Interrups

RFO_LP

RFO_HP

RFI_P

RFI_N

FSK

modem

LoRa

modem

(note)

Data

and

control

HSE32

OSC_IN

OSC_OUT

BUSY

HSERDY

HSEON

HSEBYPPWR

Note: LoRa modem is only available on STM32WL55xx devices.

VR_PA

VDDPA

PB0_VDDTCXO

3.9 Sub-GHz radio

3.9.1 Introduction

The sub-GHz radio is an ultra-low-power sub-GHz radio operating in the 150 - 960 MHz ISM band. LoRa, (G)FSK/(G)MSK modulation in transmit and receive, and (D)BPSK in transmit only, allow an optimal trade-off between range, data rate and power consumption. This subGHz radio is compliant with the LoRaWAN ETSI EN 300 220, EN 300 113, EN 301 166, FCC CFR 47 part 15, 24, 90, 101 and the ARIB STD-T30, T-67, T-108.

The sub-GHz radio consists of:

• an analog front-end transceiver, capable of outputting up to + 15 dBm maximum power

on its RFO_LP pin and up to + 22 dBm maximum power on RFO_HP pin

• a digital modem bank providing the following modulation schemes:

– LoRa Rx/Tx with bandwidth (BW) from 7.8 - 500 kHz, spreading factor (SF)

5 - 12, bit rate (BR) from 0.013 to 17.4 Kbit/s (real bitrate)

– FSK and GFSK Rx/Tx with BR from 0.6 to 300 Kbit/s

– (G)MSK Tx with BR from 0 to 10 Kbit/s

– BPSK and DBPSK TX only with bitrate for 100 and 600 bit/s

• a digital control including all data processing and sub-GHz radio configuration control

• a high-speed clock generation

specification v1.0 and radio regulations such as

3.9.2 General description

The sub-GHz radio provides an internal processing unit to handle communication with the system CPU. Communication is handled by commands sent over the SPI interface, and a set of interrupts is used to signal events. BUSY information signals operation activity and is used to indicate when the sub-GHz radio commands cannot be received.

The block diagram of the sub-GHz radio system is shown in the figure below.

Figure 2. sub-GHz radio system block diagram

DS13293 Rev 1 19/145

Functional overview STM32WL55/54xx

MSv62616V2

VLXSMPS

VFBSMPS (1.55V)

VDDPA

VR_PA (up to 3.1V)

RFO_HP

LDO/SMPS

REG

HP PA

VLXSMPS

VFBSMPS (1.55V)

VDDPA

VR_PA (up to 3.1V)

RFO_HP

LDO/SMPS

REG

HP PA

VDDSMPS (1.8 to 3.6V) VDDSMPS (1.8 to 3.6V)

LDO mode

SMPS mode

Note: Use of the SMPS is optional. When SMPS is not used, the BOM can be reduced by removing the coil between VLXSMPS and VFBSMPS pins.

3.9.3 Transmitter

The transmit chain comprises the modulated output from the modem, that directly modulates the RF-PLL. An optional pre-filtering of the bit stream can be enabled to reduce the power in the adjacent channel also dependent on the selected modulation scheme. The modulated signal from the RF-PLL directly drives the high output power PA (HP PA) or low output power PA (LP PA).

Transmitter high output power

Transmit high output power up to + 22 dBm, is supported through the RFO_HP RF pin.

For this, the REG PA must be supplied directly from V

on VDDSMPS pin, as shown in the

figure below.

The output power range is programmable in 32 steps of ~ 1 dB. The power amplifier ramping timing is also programmable.This allows adaptation to meet radio regulation requirements.

Figure 3. High output power PA

The table below gives the maximum transmit output power versus the V

DDPA

Table 4. Sub-GHz radio transmit high output power

supply (V) Transmit output power (dBm)

3.3 + 22

20/145 DS13293 Rev 1

2.7 + 20

2.4 + 19

1.8 + 16

supply level.

DDPA

STM32WL55/54xx Functional overview

MSv62617V2

Note: Use of the SMPS is optional. When SMPS is not used, the BOM can be reduced by removing the coil between VLXSMPS and VFBSMPS pins.

VLXSMPS

VFBSMPS (1.55V)

VDDPA

VR_PA (up to 1.35V)

RFO_LP

LDO/SMPS

REG

LP PA

LDO mode SMPS mode

VDDSMPS (1.8 to 3.6V)

VLXSMPS

VFBSMPS (1.55V)

VDDPA

VR_PA (up to 1.35V)

RFO_LP

LDO/SMPS

REG

LP PA

VDDSMPS (1.8 to 3.6V)

Transmitter low output power

The transmit low output power up to + 15 dBm on full VDD range (1.8 to 3.6 V), is supported through the RFO_LP RF pin. For this, the REG PA must be supplied from the regulated V

FBSMPS

The output power range is programmable in 32 steps of ~1 dB. The power amplifier ramping timing is also programmable.This allows adaptation to meet radio regulation requirements.

supply at 1.55 V, as shown in the figure below.

Figure 4. Low output power PA

3.9.4 Receiver

3.9.5 RF-PLL

The receive chain comprises a differential low-noise amplifier (LNA), a down-converter to low-IF by mixer operation in quadrature configuration. The I and Q signals are low pass filtered and a  ADC converts them into the digital domain. In the digital modem, the signals are decimated, further down converted and channel filtered. The demodulation is done according to the selected modulation scheme.

The down mixing to low-IF is done by mixing the receive signal with the local RF-PLL located in the negative frequency, where -f frequency, f is located at f

is the received signal and fif is the intermediate frequency). The wanted signal

= flo + fif.

= -frf + -fif. (where flo is the local RF-PLL

The receiver features automatic I and Q calibration, that improves image rejection. The calibration is done automatically at startup before using the receiver, and can be requested by command.

The receiver supports LoRa, (G)MSK and (G)FSK modulations.

The RF-PLL is used as the frequency synthesizer for the generation of the local oscillator frequency (f

) for both transmit and receive chains. The RF-PLL uses auto calibration and

DS13293 Rev 1 21/145

Functional overview STM32WL55/54xx

uses the 32 MHz HSE32 reference. The sub-GHz radio covers all continuous frequencies in the range between 150 to 960 MHz.

3.9.6 Intermediate frequencies

The sub-GHz radio receiver operates mostly in low-IF configuration, except for specific highbandwidth settings.

Table 5. FSK mode intermediate frequencies

Setting name Bandwidth (kHz) f

RX_BW_467 467.0

RX_BW_234 234.3

RX_BW_117 117.3

RX_BW_58 58.6

RX_BW_29 29.3

RX_BW_14 14.6

RX_BW_7 7.3

RX_BW_373 373.6

RX_BW_187 187.2

RX_BW_93 93.8

RX_BW_46 46.9

RX_BW_23 23.4

RX_BW_11 11.7

RX_BW_5 5.8

RX_BW_312 312.0

RX_BW_156 156.2

RX_BW_78 78.2

(kHz)

250

200

RX_BW_39 39.0

RX_BW_19 19.5

RX_BW_9 9.7

RX_BW_4 4.8

Table 6. LoRa mode intermediate frequencies

Setting name Bandwidth (kHz) f

LORA_BW_500 500 0

LORA_BW_250 250

LORA_BW_62 62.5

LORA_BW_41 41.67 167

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167

(kHz)

250LORA_BW_125 125

STM32WL55/54xx Functional overview

Table 6. LoRa mode intermediate frequencies (continued)

Setting name Bandwidth (kHz) f

LORA_BW_31 31.25 250

LORA_BW_20 20.83 167

LORA_BW_15 15.63 250

LORA_BW_10 10.42 167

LORA_BW_7 7.81 250

3.10 Power supply management

The devices embed two different regulators: one LDO and one DC/DC (SMPS). The SMPS can be optionally switched-on by software to improve the power efficiency. As LDO and SMPS operate in parallel, the SMPS switch-on is transparent to the user and only the power efficiency is affected.

3.10.1 Power supply schemes

The devices require a V independent supplies (V peripherals:

• V

= 1.8 V to 3.6 V

is the external power supply for the I/Os, the system analog blocks such as reset,

power management, internal clocks and low-power regulator. It is provided externally through VDD pins.

• V

DDSMPS

= 1.8 V to 3.6 V

is the external power supply for the SMPS step-down converter. It is provided externally through VDDSMPS supply pin and must be connected to the same supply as V

• V

FBSMPS

= 1.45 V to 1.62 V (1.55 V typical)

is the external power supply for the main system regulator. It is provided externally through VFBSMPS pin and is supplied through the SMPS step-down converter.

• V

= 0 V to 3.6 V (DAC minimum voltage is 1.71 V without buffer and 1.8 V with

DDA

buffer. COMP and ADC minimum voltage is 1.62 V. VREFBUF minimum voltage is

2.4 V)

is the external analog power supply for A/D converters, D/A converters, voltage

DDA

reference buffer, and comparators. The V voltage (see power-up and power-down limitations below) and must preferably be connected to V

• V

DDRF

= 1.8 V to 3.6 V

is an external power supply for the radio. It is provided externally through the

VDDRF pin and must be connected to the same supply as V

• V

DDRF1V5

= 1.45 V to 1.62 V

is an external power supply for the radio. It is provided externally through the

operating voltage supply between 1.8 V and 3.6 V. Several

DDSMPS

, V

FBSMPS

when these peripherals are not used.

, V

DDA

, V

) can be provided for specific

DDRF

voltage level is independent from the V

(kHz)

DS13293 Rev 1 23/145

Functional overview STM32WL55/54xx

MSv68044V1

0.3

BOR0

3.6

Operating modePower-on Power-down time

DDA

Invalid supply area V

DDA

< V

+ 300 mV

DDA

independent from V

VDDRF1V5 pin and must be connected externally to VFBSMPS.

• V

• VREF-, VREF

= 1.55 V to 3.6 V

BAT

is the power supply for RTC, TAMP, external clock 32 kHz oscillator and backup

BAT

registers (through power switch) when V

is the input reference voltage for ADC and DAC. It is also the output of the

REF+

is not present.

internal voltage reference buffer when enabled.

– When V

can be grounded when ADC/DAC is not active. The internal voltage reference

REF+

DDA

< 2 V, V  2 V, V

must be equal to V

REF+

must be between 2 V and V

REF+

DDA

buffer supports the following output voltages, configured with VRS bit in the VREFBUF_CSR register:

–V

around 2.048 V: this requires V

REF+

around 2.5 V: this requires V

REF+

DDA

 2.4 V.

DDA

 2.8 V.

During power up and power down, the following power sequence is required:

1. When V

During power down, V

< 1 V other power supplies (V

can temporarily become lower then other supplies only if the

) must remain below V

DDA

+ 300 mV.

energy provided to the device remains below 1 mJ. This allows external decoupling capacitors to be discharged with different time constants during this transient phase.

2. When V

An embedded linear voltage regulator is used to supply the internal digital power V V

is the power supply for digital peripherals, SRAM1 and SRAM2. The Flash memory

CORE

is supplied by V part V

DDI

> 1 V, all other power supplies (V

CORE

and VDD. V

is split in two parts: V

CORE

) become independent.

DDA

part and an interruptible

DDO

CORE

Figure 5.

Note: VDD, V

sequence.

DDRF

and V

DDSMPS

must be wired together, so they can follow the same voltage

Power-up/power-down sequence

24/145 DS13293 Rev 1

STM32WL55/54xx Functional overview

MSv50973V1

LDO/SMPS

LXSMPS

FBSMPS

BKP

DDO

DDI

BAT

MAIN

POR

mode

FW mode

RFLDO

DDSMPS

DDRF1V5

LPR

MSv50974V1

LDO/SMPS

LDO/SMPS supply LDO supply

LDO

MR LPR

DDRF1V5

FBSMPS

LXSMPS

DDSMPS

LDO/SMPS

LDO

MR LPR

DDRF1V5

FBSMPS

LXSMPS

DDSMPS

Figure 6. Power supply overview

The different supply configurations are shown in the figure below.

Figure 7. Supply configurations

DS13293 Rev 1 25/145

Functional overview STM32WL55/54xx

The LDO or SMPS step-down converter operating mode can be configured by one of the following:

• by the MCU using the SMPSEN setting in PWR control register 5 (PWR_CR5), that depends upon the MCU system operating mode (Run, Stop, Standby or Shutdown).

• by the sub-GHz radio using SetRegulatorMode() command and the sub-GHz radio operating mode (Sleep, Calibrate, Standby, Standby with HSE32 or Active).

After any POR and NRST reset, the LDO mode is selected. The SMPS selection has priority over LDO selection.

While the sub-GHz radio is in Standby with HSE32 or in Active mode, the supply mode is not altered until the sub-GHz radio enters Standby or Sleep mode. The sub-GHz radio activity may add a delay for entering the MCU software requested supply mode.

The LDO or SMPS supply mode can be checked with the SMPSRDY flag in power status register 2 (PWR_SR2).

Note: When the radio is active, the supply mode is not changed until after the radio activity is

finished.

During Stop 1, Stop 2 and Standby modes, when the sub-GHz radio is not active, the LDO or SMPS step-down converter is switched off. When exiting low-power modes (except Shutdown), the SMPS step-down converter is set by hardware to the mode selected by the SMPSEN bit in PWR control register 5 (PWR_CR5). SMPSEN is retained in Stop and Standby modes.

Independently from the MCU software selected supply operating mode, the sub-GHz radio allows the supply mode selection while the sub-GHz radio is active (thanks to the sub-GHz radio SetRegulatorMode()command).

The maximum load current delivered by the SMPS can be selected by the sub- GHz radio SUBGHZ_SMPSC2R register.

The inrush current of the LDO and SMPS step-down converter can be controlled via the sub- GHz radio SUBGHZ_PCR register. This information is retained in all but the sub-GHz radio Deep-sleep mode.

The SMPS needs a clock to be functional. If for any reason this clock stops, the device may be destroyed. To avoid this situation, a clock detection is used to, in case of a clock failure, switch off the SMPS and enable the LDO. The SMPS clock detection is enabled by the subGHz radio SUBGHZ_SMPSC0R.CLKDE. By default, the SMPS clock detection is disabled and must be enabled before enabling the SMPS.

Danger: Before enabling the SMPS, the SMPS clock detection must be

enabled in the sub-GHz radio SUBGHZ_SMPSC0R.CLKDE.

3.10.2 Power supply supervisor

The devices integrate a power-on reset/power-down reset, coupled with a Brownout reset (BOR) circuitry.

BOR0 level cannot be disabled. Other BOR levels can be enabled by user option. When enabled, BOR is active in all power modes except in Shutdown

26/145 DS13293 Rev 1

STM32WL55/54xx Functional overview

Five BOR thresholds can be selected through option bytes.

During power-on, BOR keeps the device under reset until the supply voltage V the specified V

• When V

threshold:

BORx

drops below the selected threshold, a device reset is generated.

is above the V

can start.

The devices feature an embedded PVD (programmable voltage detector) that monitors the V

power supply and compares it with the V

when V

drops below the V

PVD

threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state.

The PVD is enabled by software and can be configured to monitor the V needed for the sub-GHz radio operation. For this, the PVD must select its lowest threshold, and the PVD and the wakeup must be enabled by the EWPVD bit in PWR_CR3 register. Only a voltage drop below the PVD level generates a wakeup event.

In addition, the devices embed a PVM (peripheral voltage monitor) that compares the independent supply voltage V functional supply range.

Finally, a radio end-of-life monitor provides information on the V low to operate the sub-GHz radio. When reaching the EOL level, the software must stop all radio activity in a safe way.

3.10.3 Linear voltage regulator

reaches

upper limit, the device reset is released and the system

BORx

threshold. An interrupt can be generated

threshold and/or when VDD is higher than the V

with a fixed threshold to ensure that the peripheral is in its

DDA

PVD

supply when V

PVD

supply level

is too

Two embedded linear voltage regulators supply all the digital circuitries, except for the Standby circuitry and the Backup domain. The main regulator (MR) output voltage (V can be programmed by software to two different power ranges (range 1 and range 2), to optimize the consumption depending on the system maximum operating frequency.

The voltage regulators are always enabled after a reset. Depending on the application modes, the V

supply is provided either by the main regulator or by the low-power

CORE

regulator (LPR).

When MR is used, a dynamic voltage scaling is proposed to optimize power as follows:

• range 1: high-performance range

The system clock frequency can be up to 48 MHz. The Flash memory access time for read access is minimum. Write and erase operations are possible.

• range 2: low-power range

The system clock frequency can be up to 16 MHz.The Flash memory access time for a read access is increased as compared to range 1. Write and erase operations are possible.

Note: MR is supplied by VDD during power-on or at wakeup from Stop1, Stop2, Standby or

Shutdown mode. MR is powered by LDO/SMPS after these transition phases.

3.10.4 VBAT operation

The VBAT pin is used to power the device V from an external battery, an external super-capacitor, or from V

domain (RTC, LSE and backup registers)

BAT

when no external battery

CORE

)

DS13293 Rev 1 27/145

Functional overview STM32WL55/54xx

nor an external super-capacitor are present. Three anti-tamper detection pins are available in VBAT mode.

VBAT operation is automatically activated when V

An internal V

battery charging circuit is embedded and can be activated when VDD is

BAT

present.

Note: When the microcontroller is supplied only from V

alarm/events do not exit it from VBAT operation.

3.11 Low-power modes

The devices support several low-power modes to achieve the best compromise between low-power consumption, short startup time, available peripherals and available wakeup sources.

By default, the microcontroller is in Run mode, range 1, after a system or a power-on reset. It is up to the user to select one of the low-power modes described below:

• Sleep mode: CPU clock off, all peripherals including CPU core peripherals (among them NVIC, SysTick) can run and wake up the CPU when an interrupt or an event occurs.

• Low-power run mode (LPRun): when the system clock frequency is reduced below 2 MHz. The code is executed from the SRAM or from the Flash memory. The regulator is in low-power mode to minimize the operating current.

• Low-power sleep mode (LPSleep): entered from the LPRun mode.

• Stop 0 and Stop 1 modes: the content of SRAM1, SRAM2 and of all registers is

retained. All clocks in the V disabled. LSI and LSE can be kept running.

RTC can remain active (Stop mode with RTC, Stop mode without RTC). The sub-GHz radio may remain active independently from the CPUs.

Some peripherals with the wakeup capability can enable HSI16 RC during the Stop mode to detect their wakeup condition.

Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller wakeup time but a higher consumption compared with Stop 2.

In Stop 0 mode, the main regulator remains on, resulting in the fastest wakeup time but with much higher consumption. The active peripherals and wakeup sources are the same as in Stop 1 mode that uses the low-power regulator.

The system clock, when exiting Stop 0 or Stop 1 mode, can be either MSI up to 48 MHz or HSI16, depending on the software configuration.

• Stop 2 mode: part of the V and some peripherals preserve their contents (see Table 7).

All clocks in the V

domain are stopped. PLL, MSI, HSI16 and HSE32 are disabled.

CORE

LSI and LSE can be kept running.

RTC can remain active (Stop 2 mode with RTC, Stop 2 mode without RTC). The subGHz radio may also remain active independent from the CPUs.

Some peripherals with the wakeup capability can enable HSI16 RC during the Stop 2 mode to detect their wakeup condition (see Tab le 7).

The system clock when exiting from Stop 2 mode, can be either MSI up to 48 MHz or

domain are stopped. PLL, MSI, HSI16 and HSE32 are

CORE

domain is powered off. Only SRAM1, SRAM2, CPUs

CORE

is not present.

, external interrupts and RTC

BAT

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STM32WL55/54xx Functional overview

HSI16, depending on the software configuration.

• Standby mode: V

domain is powered off. However, it is possible to preserve the

CORE

SRAM2 content as detailed below:

– Standby mode with SRAM2 retention when the RRS bit is set in the PWR control

– Standby mode when the RRS bit is cleared in the PWR control register 3

(PWR_CR3). In this case the main regulator and the low-power regulator are powered off.

All clocks in the V

domain are stopped. PLL, MSI, HSI16 and HSE32 are disabled.

CORE

LSI and LSE can be kept running.

Th RTC can remain active (Standby mode with RTC, Standby mode without RTC). The sub-GHz radio and the PVD may also remain active when enabled independent from the CPUs. In Standby mode, the PVD selects its lowest level.

The system clock, when exiting Standby modes, is MSI at 4 MHz.

• Shutdown mode: V

domain is powered off. All clocks in the V

CORE

domain are

CORE

stopped. PLL, MSI, HSI16, LSI and HSE32 are disabled. LSE can be kept running. The system clock when exiting the Shutdown mode, is MSI at 4 MHz. In this mode, the supply voltage monitoring is disabled and the product behavior is not guaranteed in case of a power voltage drop.

The table below summarizes the peripheral features over all available modes. Wakeup capability is detailed in gray cells.

Table 7. Functionalities depending on system operating mode

Stop 0 Stop 1 Stop 2 Standby Shutdown

Peripheral

Run

Sleep

LPRun

LPSleep

Wakeup capability

CPU1 Y R Y R R -R-R---- --

CPU2 Y R Y R R

Sub-GHz radio system O O O O O

(2)

Flash memory (256 Kbytes)

(2)O(3)

(3)

-R-R---- --

OOOOOOO- --

R -R-R-R-R -R

Flash memory interface Y Y Y Y R -R-R---- --

SRAM1 Y O

SRAM2 Y O

(2)

Backup registers Y Y Y Y R

Brownout reset (BOR) Y Y Y Y Y

Programmable voltage detector (PVD)

OOOOO

(2)

R -R-R---- --

R -R-R-O

-R-R-R-R -R

YYYYYYY- --

OOOOOO

(1)

Wakeup capability

(4)

-- --

(5)O(5)

- --

VBAT

Wakeup capability

DS13293 Rev 1 29/145

Functional overview STM32WL55/54xx

Table 7. Functionalities depending on system operating mode

Peripheral

Peripheral voltage monitor (PVM3)

DMAx (x = 1, 2) O O O O R

DMAMUX1 O O O O R

High-speed internal (HSI16) O O O O O

High-speed external (HSE32) O O O

Low-speed internal (LSI) O O O O O

Low-speed external (LSE) O O O O O

Multi-speed internal (MSI) O O O O O

Clock security system (CSS) O O O O R

Clock security system on LSE O O O O O

Run

Sleep

LPRun

LPSleep

OOOOO

(7)O(7)O(7)

(1)

(continued)

Stop 0 Stop 1 Stop 2 Standby Shutdown

Wakeup capability

OOOOO- -- --

-R------ --

(6)

-O

(7)

-O

(6)

-O

(7)

-O

---- --

(7)

-O

-- --

-O-O-O-- --

-O-O-O-O -O

-O-O---- --

-R------ --

OOOOOOO- --

VBAT

RTC/auto wakeup O O O O O

Number of tamper pins 3 3 3 3 3

USARTx (x= 1, 2) O O O O O

Low-power UART (LPUART1) O O O O O

I2Cx (x = 1, 2) O O O O O

I2C3 O O O O O

SPI1 O O O O R

SUBGHZSPI O O O O R

SPI2S2 O O O O R

ADC O O O O R

DAC O O O O R

VREFBUF O O O O O

COMPx (x = 1, 2) O O O O O

Temperature sensor O O O O R

TIMx (x = 1, 2, 16, 17) O O O O R

LPTIM1 O O O O O

LPTIMx (x = 2, 3) O O O O O

Independent watchdog (IWDG)

OOOOOOOOOOOO- --

OOOOOOOO OO

O3O3O3O3 O3

(8)O(8)O(8)O(8)

(8)O(8)O(8)O(8)O(8)O(8)

(9)O(9)O(9)O(9)

(9)O(9)O(9)O(9)O(9)O(9)

- ---- --

- -- --

- ---- --

- -- --

-R------ --

-O-R---- --

OOOOO- -- --

-R------ --

OOOOO- -- --

OOO- ---- --

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+ 115 hidden pages

ST MICROELECTRONICS STM32WL55CCU6 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Table 1. Device summary

1 Introduction

2 Description

Table 2. Main features and peripheral count

Figure 1. STM32WL55/54xx block diagram

3 Functional overview

3.1 Architecture

3.2 Arm Cortex-M cores

Arm Cortex-M4

Arm Cortex-M0+

3.3 Adaptive real-time memory accelerator (ART Accelerator)

3.4 Memory protection unit (MPU)

3.5 Memories

3.5.1 Embedded Flash memory

Table 3. Access status versus RDP level and execution mode

3.5.2 Embedded SRAM

3.6 Security memory management

3.7 Boot modes

3.8 Global security controller (GTZC)

3.9 Sub-GHz radio

3.9.1 Introduction

3.9.2 General description

Figure 2. sub-GHz radio system block diagram

3.9.3 Transmitter

Transmitter high output power

Figure 3. High output power PA

Table 4. Sub-GHz radio transmit high output power

Transmitter low output power

Figure 4. Low output power PA

3.9.4 Receiver

3.9.5 RF-PLL

3.9.6 Intermediate frequencies

Table 5. FSK mode intermediate frequencies

Table 6. LoRa mode intermediate frequencies

3.10 Power supply management

3.10.1 Power supply schemes

Figure 6. Power supply overview

Figure 7. Supply configurations

3.10.2 Power supply supervisor

3.10.3 Linear voltage regulator

3.10.4 VBAT operation

3.11 Low-power modes

Table 7. Functionalities depending on system operating mode