STMicroelectronics STM32WB15CC Datasheet

STM32WB15CC

Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4 with FPU, Bluetooth® 5.2 radio solution

Datasheet - production data

Features

Includes ST state-of-the-art patented technology

Radio

–2.4 GHz

–RF transceiver supporting Bluetooth® 5.2 specification

–RX sensitivity: -95.5 dBm (Bluetooth® Low Energy at 1 Mbps)

–Programmable output power up to +5.5 dBm with 1 dB steps

–Integrated balun to reduce BOM

–Support for 2 Mbps

–Dedicated Arm® 32-bit Cortex® M0+ CPU for real-time Radio layer

–Accurate RSSI to enable power control

–Suitable for systems requiring compliance with radio frequency regulations ETSI EN 300 328, EN 300 440, FCC CFR47 Part 15 and ARIB STD-T66

–Support for external PA

–Available integrated passive device (IPD) companion chip for optimized matching solution (MLPF-WB-01E3)

Ultra-low-power platform

–1.71 to 3.6 V power supply

–– 40 °C to 85 / 105 °C temperature ranges

–12 nA shutdown mode

–610 nA Standby mode + RTC + 48 KB RAM

–Active-mode MCU: 33 µA / MHz when RF and SMPS on

–Radio: Rx 4.5 mA / Tx at 0 dBm 5.2 mA

UFQFPN48 7 x 7 mm

solder pad

Core: Arm® 32-bit Cortex®-M4 CPU with FPU, adaptive real-time accelerator (ART Accelerator) allowing 0-wait-state execution from Flash memory, frequency up to 64 MHz, MPU, 80 DMIPS and DSP instructions

Performance benchmark

–1.25 DMIPS/MHz (Drystone 2.1)

Supply and reset management

–High efficiency embedded SMPS step-down converter with intelligent bypass mode

–Ultra-safe, low-power BOR (brownout reset) with five selectable thresholds

–Ultra-low-power POR/PDR

–Programmable voltage detector (PVD)

–VBAT mode with RTC and backup registers

Clock sources

–32 MHz crystal oscillator with integrated trimming capacitors (Radio and CPU clock)

–32 kHz crystal oscillator for RTC (LSE)

–Internal low-power 32 kHz RC (LSI1)

–Internal low-drift 32 kHz RC (LSI2)

–Internal multispeed 100 kHz to 48 MHz oscillator, factory-trimmed

–High speed internal 16 MHz factory trimmed RC

–1x PLL for system clock and ADC

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This is information on a product in full production.

www.st.com

STM32WB15CC

Memories

–320 KB Flash memory with sector protection (PCROP) against R/W operations, enabling radio stack and application

–48 KB SRAM, including 36 KB with hardware parity check

–20x32-bit backup register

–Boot loader supporting USART, SPI, I2C interfaces

–1 Kbyte (128 double words) OTP

Rich analog peripherals (down to 1.62 V)

–12-bit ADC 2.5 Msps, 190 µA/Msps

–1x ultra-low-power comparator

System peripherals

–Inter processor communication controller (IPCC) for communication with Bluetooth® Low Energy

–HW semaphores for resources sharing between CPUs

–1x DMA controller (7x channels) supporting ADC, SPI, I2C, USART, AES, timers

–1x USART (ISO 7816, IrDA, SPI Master, Modbus and Smartcard mode)

–1x LPUART (low power)

–1x SPI 32 Mbit/s

–1x I2C (SMBus/PMBus)

–Touch sensing controller, up to eight sensors

–1x 16-bit, four channels advanced timer

–1x 32-bit, four channels timer

–2x 16-bit ultra-low-power timer

–1x independent Systick

–1x independent watchdog

–1x window watchdog

Security and ID

–Secure firmware installation (SFI) for Bluetooth® Low Energy SW stack

–2x hardware encryption AES maximum

256-bit for the application and the Bluetooth® Low Energy

–HW public key authority (PKA)

–Cryptographic algorithms: RSA, Diffie-Helman, ECC over GF(p)

–True random number generator (RNG)

–Sector protection against R/W operation (PCROP)

–CRC calculation unit

–Die information: 96-bit unique ID

–IEEE 64-bit unique ID. Possibility to derive Bluetooth® Low Energy 48-bit EUI

Up to 37 fast I/Os, 35 of them 5 V-tolerant

Development support

–Serial wire debug (SWD), JTAG for the application processor

–Application cross trigger

All packages are ECOPACK2 compliant

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Contents

1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 9
2	Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		10
3	Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		13
	3.1	Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
	3.2	Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
	3.3	Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14

3.3.1 Adaptive real-time memory accelerator (ART Accelerator) . . . . . . . . . . 14 3.3.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.4	Security and safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		16
3.5	Boot modes and FW update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		16
3.6	RF subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		16
	3.6.1	RF front-end block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
	3.6.2	BLE general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
	3.6.3	RF pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
	3.6.4	Typical RF application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19

3.7 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

	3.7.1	Power supply distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
	3.7.2	Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	21
	3.7.3	Linear voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
	3.7.4	Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
	3.7.5	Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
	3.7.6	Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	31
3.8	VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		31
3.9	Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		31
3.10	Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		33
3.11	General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . .		35
3.12	Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . .		36
3.13	Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		36
	3.13.1	Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . .	36

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3.13.2 Extended interrupts and events controller (EXTI) . . . . . . . . . . . . . . . . . 37

3.14 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.14.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.14.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.15 Comparator (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.16 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.17 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.18 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.18.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.18.2 General-purpose timer (TIM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.18.3 Low-power timer (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . 40 3.18.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.18.5 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.18.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.19 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 41 3.20 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.21Universal synchronous/asynchronous receiver transmitter (USART) . . . 43

3.22Low-power universal asynchronous receiver transmitter (LPUART) . . . . 43

3.23 Serial peripheral interface (SPI1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.24 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.24.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 44

4	Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			45
5	Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			54
6	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			55
	6.1	Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		55
		6.1.1	Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	55
		6.1.2	Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	55
		6.1.3	Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	55
		6.1.4	Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	55
		6.1.5	Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	55
		6.1.6	Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	56
		6.1.7	Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . .	57

6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

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6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

6.3.1 Summary of main performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.3.2 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.3.3 RF BLE characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.3.4 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 65 6.3.5 Embedded reset and power control block characteristics . . . . . . . . . . . 66 6.3.6 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.3.7 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

6.3.8Wakeup time from Low-power modes and voltage scaling

transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.3.9 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.3.12 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.3.14 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.3.17 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 6.3.18 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.3.19 Analog-to-Digital converter characteristics . . . . . . . . . . . . . . . . . . . . . 101 6.3.20 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 6.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

6.3.22 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.3.23 SMPS step-down converter characteristics . . . . . . . . . . . . . . . . . . . . . 108

6.3.24 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.3.25 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 109

7	Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			114
	7.1	UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		.114
	7.2	Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		.117
		7.2.1	Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	117
		7.2.2	Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . .	117
8	Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			119
9	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			120

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List of tables	STM32WB15CC

List of tables

Table 1. STM32WB15CC device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 2. Access status vs. readout protection level and execution modes . . . . . . . . . . . . . . . . . . . 15 Table 3. RF pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 4. Typical external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 5. Power supply typical components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 6. Functionalities depending on system operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 7. STM32WB15CC modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 8. STM32WB15CC CPU1 peripherals interconnect matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 9. DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 10. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 11. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 12. Timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 13. I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 14. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 15. STM32WB15CC pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 16. Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 17. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 18. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 19. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 20. Main performance at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 21. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 22. RF transmitter BLE characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 23. RF transmitter BLE characteristics (1 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 24. RF transmitter BLE characteristics (2 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 25. RF receiver BLE characteristics (1 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 26. RF receiver BLE characteristics (2 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 27. RF BLE power consumption for VDD = 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 28. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 29. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 30. Embedded internal voltage reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 31. Current consumption in Run and Low-power run modes, code with data processing

running from Flash memory, ART enable (Cache ON Prefetch OFF), VDD = 3.3 V . . . . . 69 Table 32. Current consumption in Run and Low-power run modes, code with data processing

running from SRAM1, VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 33. Typical current consumption in Run and Low-power run modes, with different codes

running from Flash memory, ART enable (Cache ON Prefetch OFF), VDD= 3.3 V . . . . . . 71 Table 34. Typical current consumption in Run and Low-power run modes,

with different codes running from SRAM1, VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 35. Current consumption in Sleep and Low-power sleep modes, Flash memory ON . . . . . . . 73 Table 36. Current consumption in Low-power sleep modes, Flash memory in Power down . . . . . . . 73 Table 37. Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 38. Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 39. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 40. Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 41. Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 42. Current under Reset condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 43. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 44. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

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STM32WB15CC	List of tables

Table 45. Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 46. Wakeup time using LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 47. HSE crystal requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 48. HSE clock source requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 49. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 50. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 51. Low-speed external user clock characteristics – Bypass mode . . . . . . . . . . . . . . . . . . . . . 86 Table 52. HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 53. MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

Table 54. LSI1 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 55. LSI2 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 56. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 57. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table 58. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table 59. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 60. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Table 61. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Table 62. Electrical sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 63. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 64. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 65. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 66. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 67. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table 68. Analog switches booster characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 69. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Table 70. Maximum ADC RAIN values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Table 71. ADC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 72. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table 73. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 74. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 75. VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 76. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 77. IWDG min/max timeout period at 32 kHz (LSI1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 78. Minimum I2CCLK frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 79. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 80. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 81. JTAG characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Table 82. SWD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Table 83. UFQFPN48 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 84. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Table 85. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

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List of figures	STM32WB15CC

List of figures

Figure 1. STM32WB15CC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 2. STM32WB15CC RF front-end block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 3. External components for the RF part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 4. Power distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 5. Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 6. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 7. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 8. STM32WB15CCU UFQFPN48 pinout (1) (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 9. STM32WB15CCU UFQFPN48E pinout (1) (2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 10. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 11. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 12. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 13. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 14. VREFINT vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 15. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 16. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 17. HSI16 frequency vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 18. Typical current consumption vs. MSI frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Figure 19. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Figure 20. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Figure 21. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Figure 22. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Figure 23. SPI timing diagram - Slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Figure 24. SPI timing diagram - Slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Figure 25. SPI timing diagram - Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Figure 26. UFQFPN48 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Figure 27. UFQFPN48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Figure 28. UFQFPN48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

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STM32WB15CC	Introduction

1 Introduction

This document provides the ordering information and mechanical device characteristics of the STM32WB15CC microcontroller, based on Arm® cores(a). Throughout the whole document TBD indicates a value to be defined.

This document must be read in conjunction with the reference manual (RM0473), available from the STMicroelectronics website www.st.com.

For information on the Arm® Cortex®-M4 and Cortex®-M0+ cores, refer, respectively, to the Cortex®-M4 Technical Reference Manual and to the Cortex®-M0+ Technical Reference Manual, both available on the www.arm.com website.

For information on Bluetooth® refer to www.bluetooth.com.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

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Description	STM32WB15CC

2 Description

The STM32WB15CC multiprotocol wireless and ultra-low-power device embeds a powerful and ultra-low-power radio compliant with the Bluetooth® Low Energy SIG specification v5.2. It contains a dedicated Arm® Cortex® -M0+ for performing all the real-time low layer operation.

The device is designed to be extremely low-power and is based on the high-performance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to 64 MHz. This core features a Floating point unit (FPU) single precision that supports all Arm® single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) that enhances application security.

Enhanced inter-processor communication is provided by the IPCC with six bidirectional channels. The HSEM provides hardware semaphores used to share common resources between the two processors.

The device embeds high-speed memories (320 Kbyte of Flash memory, 48 Kbytes of SRAM) and an extensive range of enhanced I/Os and peripherals.

Direct data transfer between memory and peripherals and from memory to memory is supported by seven DMA channels with a full flexible channel mapping by the DMAMUX peripheral.

The device feature several mechanisms for embedded Flash memory and SRAM: readout protection, write protection and proprietary code readout protection. Portions of the memory can be secured for Cortex® -M0+ exclusive access.

The AES encryption engine, PKA and RNG enable upper layer cryptography. The device offers a fast 12-bit ADC and one ultra-low-power comparator.

The device embeds a low-power RTC, one advanced 16-bit timer, one general-purpose 32-bit timer, and two 16-bit low-power timers.

In addition, up to eight capacitive sensing channels are available.

The STM32WB15CC also features standard and advanced communication interfaces, namely one USART (ISO 7816, IrDA, Modbus and Smartcard mode), one

lowpower UART (LPUART), one I2C (SMBus/PMBus), one SPI up to 32 MHz.

The STM32WB15CC operates in the -40 to +85 °C (+105 °C junction) and -40 to +105 °C (+125 °C junction) temperature ranges from a 1.71 to 3.6 V power supply. A comprehensive set of power-saving modes enables the design of low-power applications.

The STM32WB15CC integrates a high efficiency SMPS step-down converter with automatic bypass mode capability when the VDD falls below VBORx (x=1, 2, 3, 4) voltage level (default is 2.0 V). It includes independent power supplies for analog input for ADC and comparator.

A VBAT dedicated supply allows the device to back up the LSE 32.768 kHz oscillator, the RTC and the backup registers, thus enabling the STM32WB15CC to supply these functions even if the main VDD is not present through a CR2032-like battery, a Supercap or a small rechargeable battery.

The STM32WB15CC offers one package, 48 pins.

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		Table 1. STM32WB15CC device features and peripheral counts
	Feature		STM32WB15CCUxE		STM32WB15CCU
	Flash memory density			320 KB
	SRAM density			48 KB
	BLE			V5.2 (2 Mbps)
		Advanced		1 (16 bits)
	Timers	General		1 (32 bits)
		Low power		2 (16 bits)
		SysTick		1
		SPI		1
	Comm	I2C		1
	interface	USART(1)		1
		LPUART		1
	RTC			1
	Tamper pin			1
	Wakeup pin			2
	GPIOs		37		30
	Capacitive sensing		8		3
	SMPS		No		Yes
	12-bit ADC			13 channels
	Number of channels		(including 3 internal)
	Internal Vref			Yes
	Analog comparator			1
	Max CPU frequency			64 MHz
	Operating temperature		Ambient operating temperature:-40 to +85 °C and -40 to +105 °C
			Junction temperature: -40 to +105 °C and -40 to +125 °C
	Operating voltage			1.71 to 3.6 V
	Package		UFQFPN48 7 x 7 mm
			0.5 mm pitch, solder pad

1. USART peripheral can be used as SPI master.

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Description	STM32WB15CC

Figure 1. STM32WB15CC block diagram

					APB asynchronous
				<![if ! IE]> <![endif]>AHB asynchronous		RCC2
<![if ! IE]> <![endif]>CTI		NVIC	<![if ! IE]> <![endif]>AHB Lite		BLE IP	LSI2
						32 kHz
	Cortex-M0+				BLE RF IP	HSE2
						32 MHz
					32 KB SRAM2a	WKUP
						BLE
							LSE
	<![if ! IE]> <![endif]>320 KB Flash	<![if ! IE]> <![endif]>shared memory			4 KB SRAM2b	RTC2	32 kHz
<![if ! IE]> <![endif]>JTAG/SWD			<![if ! IE]> <![endif]>Arbiter + ART				LSI1
					PKA + RAM	I-WDG	32 kHz
					HSEM	TAMP
				<![if ! IE]> <![endif]>(shared)
					RNG
		NVIC		<![if ! IE]> <![endif]>lite			HSI 1%
				<![if ! IE]> <![endif]>AHB	IPCC	PLL1
	Cortex-M4						16 MHz
							MSI up to
	(DSP)				RCC + CSS
							48 MHz
<![if ! IE]> <![endif]>CTI
	FPU	MPU			PWR	Power supply POR/
						PDR/BOR/PVD/AVD
					EXTI
			<![if ! IE]> <![endif]>Lite		AES2
			<![if ! IE]> <![endif]>AHB
DMA1 - 7 channels						WWDG
					12 KB SRAM1
	DMAMUX						DBG
	GPIO ports			Temp (oC) sensor			SPI1
	A, B, C, E, H				ADC1 12-bit ULP
	CRC
					2.5 Msps / 13 ch		I2C1
	TSC
					APB
						LPUART1
	LPTIM1				TIM1	USART1
	LPTIM2				TIM2	SYSCFG/COMP
							MS53541V3

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STM32WB15CC	Functional overview

3 Functional overview

3.1Architecture

The STM32WB15CC multiprotocol wireless device embeds a BLE RF subsystem that interfaces with a generic microcontroller subsystem using an Arm® Cortex®-M4 CPU (called CPU1) on which the host application resides.

The RF subsystem is composed of an RF analog front end, BLE block as well as of a dedicated Arm® Cortex®-M0+ microcontroller (called CPU2), plus proprietary peripherals. The RF subsystem performs all of the BLE stack, reducing the interaction with the CPU1 to high level exchanges.

Some functions are shared between the RF subsystem CPU (CPU2) and the Host CPU (CPU1):

Flash memories

SRAM1, SRAM2a and SRAM2b (all can be retained in Standby mode)

Security peripherals (RNG, PKA)

Clock RCC

Power control (PWR)

The communication and the sharing of peripherals between the RF subsystem and the Cortex®-M4 CPU is performed through a dedicated inter processor communication controller (IPCC) and semaphore mechanism (HSEM).

3.2Arm® Cortex®-M4 core with FPU

The Arm® Cortex®-M4 with FPU is a processor for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.

The Arm® Cortex®-M4 with FPU 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an Arm® core in the memory size usually associated with 8- and 16-bit devices.

The processor supports a set of DSP instructions enabling efficient signal processing and complex algorithm execution.

Its single precision FPU speeds up software development by using metalanguage development tools, while avoiding saturation.

With its embedded Arm® core, the STM32WB15CC is compatible with all Arm® tools and software.

Figure 1 shows the general block diagram of the device.

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Functional overview	STM32WB15CC

3.3Memories

3.3.1Adaptive real-time memory accelerator (ART Accelerator)

The ART Accelerator is a memory accelerator optimized for STM32 industry-standard Arm® Cortex®-M4 processors. It balances the inherent performance advantage of the Arm® Cortex®-M4 over Flash memory technologies, which normally require the processor to wait for the Flash memory at higher frequencies.

To release the processor near 80 DMIPS performance at 64 MHz, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 64-bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 64 MHz.

3.3.2Memory protection unit

The memory protection unit (MPU) is used to manage the CPU1 accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to eight protected areas, which can be divided up into eight subareas. The protection area sizes are between 32 bytes and the whole

4 Gbytes of addressable memory.

The MPU is especially helpful for applications where some critical or certified code must be protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-time operating system). If a program accesses a memory location prohibited by the MPU, the RTOS detects it and takes action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

3.3.3Embedded Flash memory

The STM32WB15CC device features 320 Kbytes of embedded Flash memory available for storing programs and data, as well as some customer keys.

Flexible protections can be configured thanks to option bytes:

Readout protection (RDP) to protect the whole memory. Three levels are available:

–Level 0: no readout protection

–Level 1: memory readout protection: the Flash memory cannot be read from or written to if either debug features are connected, boot in SRAM or bootloader is selected

–Level 2: chip readout protection: debug features (Cortex®-M4 and Cortex®-M0+ JTAG and serial wire), boot in SRAM and bootloader selection are disabled (JTAG fuse). This selection is irreversible.

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STM32WB15CC										Functional overview
	Table 2. Access status vs. readout protection level and execution modes
		Protection		User execution					Debug, boot from SRAM or boot
	Area								from system memory (loader)
		level
			Read		Write		Erase		Read	Write	Erase
	Main	1	Yes		Yes		Yes		No	No	No
	memory	2	Yes		Yes		Yes		N/A	N/A	N/A
	System	1	Yes		No		No		Yes	No	No
	memory	2	Yes		No		No		N/A	N/A	N/A
	Option	1	Yes		Yes		Yes		Yes	Yes	Yes
	bytes	2	Yes		(1)		No	(1)	N/A	N/A	N/A
					No
	Backup	1	Yes		Yes		N/A(2)		No	No	N/A(2)
	registers	2	Yes		Yes		N/A		N/A	N/A	N/A
	SRAM2a	1	Yes		Yes		Yes(2)		No	No	No(2)
	SRAM2b	2	Yes		Yes		Yes		N/A	N/A	N/A

1.The option byte can be modified by the RF subsystem.

2.Erased when RDP changes from Level 1 to Level 0.

Write protection (WRP): the protected area is protected against erasing and programming. Two areas can be selected, with 4-Kbyte granularity.

Proprietary code readout protection (PCROP): two parts of the Flash memory can be protected against read and write from third parties. The protected area is execute-only: it can only be reached by the STM32 CPU, as an instruction code, while all other accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited. Two areas can be selected, with 2-Kbyte granularity. An additional option bit (PCROP_RDP) makes possible to select if the PCROP area is erased or not when the RDP protection is changed from Level 1 to Level 0.

A section of the Flash memory is secured for the RF subsystem CPU2, and cannot be accessed by the host CPU1.

The whole non-volatile memory embeds the error correction code (ECC) feature supporting:

single error detection and correction

double error detection

the address of the ECC fail can be read in the ECC register

The embedded Flash memory is shared between CPU1 and CPU2 on a time sharing basis. A dedicated HW mechanism allows both CPUs to perform Write/Erase operations.

3.3.4Embedded SRAM

The STM32WB15CC device features 48 Kbytes of embedded SRAM, split in three blocks:

SRAM1: 12 Kbytes mapped at address 0x2000 0000

SRAM2a: 32 Kbytes located at address 0x2003 0000 also mirrored at 0x1000 0000, with hardware parity check

SRAM2b: 4 Kbytes located at address 0x2003 8000 (contiguous with SRAM2a) and mirrored at 0x1000 8000 with hardware parity check

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Functional overview	STM32WB15CC

SRAM2a and SRAM2b can be write-protected, with 1-Kbyte granularity. A section of the SRAM2a and SRAM2b is secured for the RF sub-system and cannot be accessed by the host CPU1.

The SRAMs can be accessed in read/write with 0 wait states for all CPU1 and CPU2 clock speeds.

3.4Security and safety

The STM32WB15CC contains many security blocks both for the BLE and the Host application.

It includes:

Secure Flash memory partition for RF subsystem-only access

Secure SRAM partition, that can be accessed only by the RF subsystem

True random number generator (RNG)

Advance encryption standard hardware accelerator (AES-256bit, supporting chaining modes ECB, CBC, CTR, GCM, GMAC, CCM)

Private key acceleration (PKA) including:

–Modular arithmetic including exponentiation with maximum modulo size of 3136 bits

–Elliptic curves over prime field scalar multiplication, ECDSA signature, ECDSA verification with maximum modulo size of 521 bits

Cyclic redundancy check calculation unit (CRC)

A specific mechanism is in place to ensure that all the code executed by the RF subsystem CPU2 can be secure, whatever the Host application.

3.5Boot modes and FW update

At startup, BOOT0 pin and BOOT1 option bit are used to select one of three boot options:

Boot from user Flash

Boot from system memory

Boot from embedded SRAM

The device always boots on CPU1 core. The embedded bootloader code makes it possible to boot from various peripherals:

UART

I2C

SPI

Secure Firmware update from system boot is provided.

3.6RF subsystem

The STM32WB15CC embed an ultra-low power multi-standard radio Bluetooth® Low Energy (BLE), compliant with Bluetooth® specification v5.2. The BLE features 1 Mbps and 2 Mbps transfer rates, supports multiple roles simultaneously acting at the same time as

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STM32WB15CC	Functional overview

BLE sensor and hub device, embeds Elliptic Curve Diffie-Hellman (ECDH) key agreement protocol, thus ensuring a secure connection.

The BLE stack runs on an embedded Arm® Cortex®-M0+ core (CPU2). The stack is stored on the embedded Flash memory, which is also shared with the Arm® Cortex®-M4 (CPU1) application, making it possible in-field stack update.

3.6.1RF front-end block diagram

The RF front-end is based on a direct modulation of the carrier in Tx, and uses a low IF architecture in Rx mode.

Thanks to an internal transformer at RF pins, the circuit directly interfaces the antenna (single ended connection, impedance close to 50 Ω). The natural bandpass behavior of the internal transformer, simplifies outside circuitry aimed for harmonic filtering and out of band interferer rejection.

In Transmit mode, the maximum output power is user selectable through the programmable LDO voltage of the power amplifier. A linearized, smoothed analog control offers clean power ramp-up.

In receive mode the circuit can be used in standard high performance or in reduced power consumption (user programmable). The Automatic gain control (AGC) is able to reduce the chain gain at both RF and IF locations, for optimized interference rejection. Thanks to the use of complex filtering and highly accurate I/Q architecture, high sensitivity and excellent linearity can be achieved.

The bill of material is reduced thanks to the high degree of integration. The radio frequency source is synthesized form an external 32 MHz crystal that does not need any external trimming capacitor network thanks to a dual network of user programmable integrated capacitors.

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Figure 2. STM32WB15CC RF front-end block diagram

	Timer and Power		AGC	<![if ! IE]> <![endif]>control	<![if ! IE]> <![endif]>AGC
	control
RF_TX_
MOD_	RF control			<![if ! IE]> <![endif]>ADC
EXT_PA					G
Interrupt			BLE		BP
							LNA
Wakeup		modulator
	BLE			filter
				<![if ! IE]> <![endif]>ADC
AHB	controller		BLE		G
APB		demodulator						RF1
			<![if ! IE]> <![endif]>Modulator	PLL
							<![if ! IE]> <![endif]>PA	See
					<![if ! IE]> <![endif]>ramp PA generator			note
Adjust		Adjust
	HSE							Trimmed
								bias
				SMPS	LDO	LDO	LDO	Max PA
								level
			VDDSMPS	VSSSMPS	VLXSMPS	VFBSMPS		VDDRF
OSC_IN		OSC_OUT
	32 MHz
Note: UFQFPN48: VSS through exposed pad, and VSSRF pin must be connected to ground plane
								MS53542V2

3.6.2BLE general description

The BLE block is a master/slave processor, compliant with Bluetooth specification 5.2 standard (2 Mbps).

It integrates a 2.4 GHz RF transceiver and a powerful Cortex®-M0+ core, on which a complete power-optimized stack for Bluetooth Low Energy protocol runs, providing master / slave role support

GAP: central, peripheral, observer or broadcaster roles

ATT/GATT: client and server

SM: privacy, authentication and authorization

L2CAP

Link layer: AES-128 encryption and decryption

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In addition, according to Bluetooth specification v5.2, the BLE block provides:

Multiple roles simultaneous support

Master/slave and multiple roles simultaneously

LE data packet length extension (making it possible to reach 800 kbps at application level)

LE privacy 1.2

LE secure connections

Flexible Internet connectivity options

High data rate (2 Mbps)

The device allows the applications to meet the tight peak current requirements imposed by the use of standard coin cell batteries. When the high efficiency embedded SMPS

step-down converter is used, the RF front end consumption (Itmax) is only TBD mA at the highest output power (TBD dBm).

Ultra-low-power sleep modes and very short transition time between operating modes result in very low average current consumption during real operating conditions, resulting in longer battery life.

The BLE block integrates a full bandpass balun, thus reducing the need for external components.

The link between the Cortex®-M4 application processor (CPU1) running the application, and the BLE stack running on the dedicated Cortex®-M0+ (CPU2) is performed through a normalized API, using a dedicated IPCC.

3.6.3RF pin description

The RF block contains dedicated pins, listed in Table 3.

	:		Table 3. RF pin list
	Name	Type	Description
	RF1		RF Input/output, must be connected to the antenna through a low-pass matching network
	OSC_OUT		32 MHz main oscillator, also used as HSE source
		I/O
	OSC_IN
	RF_TX_		External PA transmit control
	MOD_EXT_PA
	VDDRF	VDD	Dedicated supply, must be connected to VDD
	VSSRF(1)	VSS	To be connected to GND

1. On packages with exposed pad, this pad must be connected to GND plane for correct RF operation.

3.6.4Typical RF application schematic

The schematic in Figure 3 and the external components listed in Table 3 are purely indicative. For more details refer to the “Reference design” provided in separate documents.

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Figure 3. External components for the RF part

	OSC_IN
	X1	32 MHz
	OSC_OUT
		VDD
	VDDRF
STM32WB		C1	Antenna
	VSSRF
microcontroller
	(including exposed pad)
		Lf1
		Cf1	Cf2
	RF1	Antenna filter
		Lf2
			MS53575V1

Table 4. Typical external components

Component	Description	Value
C1	Decoupling capacitance for RF	100 nF // 100 pF
X1	32 MHz crystal(1)	32 MHz
Antenna filter	Antenna filter and matching network	Refer to AN5165, on www.st.com
Antenna	2.4 GHz band antenna	-

1. e.g. NDK reference: NX2016SA 32 MHz EXS00A-CS06654.

Note:	For more details refer to AN5165 “Development of RF hardware using STM32WB
	microcontrollers” available on www.st.com.

3.7Power supply management

3.7.1Power supply distribution

The device integrate an SMPS step-down converter to improve low power performance when the VDD voltage is high enough. This converter has an intelligent mode that automatically enters in bypass mode when the VDD voltage falls below a specific BORx (x = 1, 2, 3 or 4) voltage.

By default, at Reset the SMPS is in bypass mode.

The device can be operated without the SMPS by just wiring its output to VDD. This is the case for applications where the voltage is low, or where the power consumption is not critical.

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Figure 4. Power distribution

VDD			VDD
VDDSMPS			VDDSMPS
		SMPS		SMPS
VLXSMPS	SMPS mode or		VLXSMPS	(not used)
L1	BYPASS mode
		LPR			LPR
VFBSMPS			VFBSMPS
C2
RFR		MR	RFR		MR
SMPS configuration			LDO configuration
					MS41409V4

Table 5. Power supply typical components

	Component	Description		Value
	C2	SMPS output capacitor(1)		4.7 µF
	L1(2)	SMPS inductance	For 8 MHz(3)	2.2 µH
			For 4 MHz(4)	10 µH

1.e.g. GRM155R60J475KE19.

2.An extra 10 nH inductor in series with L1 is needed to improve the receiver performance, e.g Murata LQG15WZ10NJ02D

3.e.g. Wurth 74479774222.

4.e.g. Murata LQM21FN100M70L.

The SMPS can also be switched on or set in bypass mode at any time by the application software, for example when very accurate ADC measurement are needed.

3.7.2Power supply schemes

The device has different voltage supplies (see Figure 6) and can operate within the following voltage ranges:

VDD = 1.71 to 3.6 V: external power supply for I/Os (VDDIO), the internal regulator and system functions such as RF, SMPS, reset, power management and internal clocks. It

is provided externally through VDD pins. VDDRF and VDDSMPS must be always connected to VDD pins.

VDDA = 1.62 (ADC/COMPs) to 3.6 V: external analog power supply for ADC and comparator. The VDDA voltage level can be independent from the VDD voltage. When not used VDDA must be connected to VDD.

During power up/down, the following power sequence requirements must be respected:

When VDD is below 1 V the other power supply (VDDA), must remain below VDD + 300 mV

When VDD is above 1 V all power supplies are independent.

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Figure 5. Power-up/down sequence

V
3.6	(1)
	VDDX
	VDD
VBOR0
1
0.3
Power-on	Operating mode	Power-down	time
Invalid supply area	VDDX < VDD + 300 mV	VDDX independent from VDD
			MSv47490V1

1. VDDX refers to VDDA.

During the power down phase, VDD can temporarily become lower than other supplies only if the energy provided to the MCU remains below 1 mJ. This allows the external decoupling capacitors to be discharged with different time constants during the power down transient phase.

Note:	VDD, VDDRF and VDDSMPS must be wired together, so they can follow the same voltage
	sequence.

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				Figure 6. Power supply overview
				Interruptible domain (VDD12I)	On domain (VDD12O)

	<![if ! IE]> <![endif]>shifter	IO	(CPU1, CPU2,	RCC, PwrCtrl,
				SysConfig, EXTI,
IOs	<![if ! IE]> <![endif]>Level	logic	peripherals)	LPTIM, LPUSART
			Power	Power
			switch	switch
VSS			VSS	VSS
VFBSMPS			MR
VLXSMPS
	SMPS
VDDSMPS			RFR
VSSSMPS
	LPR
VDDRF	RF domain
				Backup domain
			Radio	VBKP12	SRAM1,
					SRAM2b,
					SRAM2a

VSSRF

Power switch

VSS

VSS

(including exposed pad)

Wakeup domain (VDDIO)

VDD

HSI, HSE,

Power switch

PLL, LSI1,

VSW

VBAT

LSI2, IWDG,

RF

VSS

Switch domain (VSW)

LSE, RTC,

VBAT

IO

backup

IOs

logic

registers

VSS

VDDA

V

SS

Analog domain

ADC

=

VREF+

=

VREF-

VSS

MS53544V2

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3.7.3Linear voltage regulator

Three embedded linear voltage regulators supply most of the digital and RF circuitries, the main regulator (MR), the low-power regulator (LPR) and the RF regulator (RFR).

The MR is used in the Run and Sleep modes and in the Stop 0 mode.

The LPR is used in Low-Power Run, Low-Power Sleep and Stop 1 modes. It is also used to supply the SRAMs in Standby with retention.

The RFR is used to supply the RF analog part, its activity is automatically managed by the RF subsystem.

All the regulators are in power-down in Standby and Shutdown modes: the regulator output is in high impedance, and the kernel circuitry is powered down, inducing zero consumption.

The ultralow-power STM32WB15CC supports dynamic voltage scaling to optimize its power consumption in run mode. The voltage from the main regulator that supplies the logic (VCORE) can be adjusted according to the system’s maximum operating frequency.

VCORE can also be supplied by the low-power regulator, the main regulator being switched off. The system is then in Low-power run mode. In this case the CPU is running at up to

2 MHz, and peripherals with independent clock can be clocked by HSI16 (in this mode the RF subsystem is not available).

3.7.4Power supply supervisor

An integrated ultra-low-power brown-out reset (BOR) is active in all modes except Shutdown ensuring proper operation after power-on and during power down. The device remains in reset mode when the monitored supply voltage VDD is below a specified threshold, without the need for an external reset circuit.

The lowest BOR level is 1.71 V at power on, and other higher thresholds can be selected through option bytes.The device features an embedded programmable voltage detector (PVD) that monitors the VDD power supply and compares it with the VPVD threshold. An interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

In addition, the device embeds a peripheral voltage monitor (PVM) that compares the independent supply voltage VDDA with a fixed threshold to ensure that the peripheral is in its functional supply range.

Any BOR level can also be used to automatically switch the SMPS step-down converter in bypass mode when the VDD voltage drops below a given voltage level. The mode of operation is selectable by register bit, the BOR level is selectable by option byte.

3.7.5Low-power modes

This ultra-low-power device supports several low-power modes to achieve the best compromise between low-power consumption, short startup time, available peripherals and available wakeup sources.

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By default, the microcontroller is in Run mode, after a system or a power on Reset. It is up to the user to select one of the low-power modes described below:

Sleep

In Sleep mode, only the CPU1 is stopped. All peripherals, including the RF subsystem, continue to operate and can wake up the CPU when an interrupt/event occurs.

Low-power run

This mode is achieved with VCORE supplied by the low-power regulator to minimize the regulator operating current. The code can be executed from SRAM or from the Flash memory, and the CPU1 frequency is limited to 2 MHz. The peripherals with independent clock can be clocked by HSI16. The RF subsystem is not available in this mode and must be OFF.

Low-power sleep

This mode is entered from the low-power run mode. Only the CPU1 clock is stopped. When wakeup is triggered by an event or an interrupt, the system reverts to the low-power run mode. The RF subsystem is not available in this mode and must be OFF.

Stop 0 and Stop 1

Stop modes achieve the lowest power consumption while retaining the content of all the SRAM and registers. The LSE (or LSI) is still running.

The RTC can remain active (Stop mode with RTC, Stop mode without RTC).

Some peripherals with wakeup capability can enable the HSI16 RC during Stop modes to detect their wakeup condition.

Two modes are available: Stop 0 and Stop 1.

Stop 1 offers several active peripherals and wakeup sources. In Stop 0 mode the main regulator remains ON, allowing a very fast wakeup time but with higher consumption. In these modes the RF subsystem can wait for incoming events in all Stop modes.

The system clock when exiting from Stop 0 or Stop1 modes can be either MSI up to 48 MHz or HSI16 if the RF subsystem is disabled. If the RF subsystem is used the exits must be set to HSI16 only.

Standby

The Standby mode is used to achieve the lowest power consumption with BOR. The internal regulator is switched off so that the VCORE domain is powered off.

The RTC can remain active (Standby mode with RTC).

The brown-out reset (BOR) always remains active in Standby mode.

The state of each I/O during standby mode can be selected by software: I/O with internal pull-up, internal pull-down or floating.

After entering Standby mode, register content is lost except for registers in the Backup domain and Standby circuitry. Optionally, SRAMs can be retained in Standby mode, supplied by the low-power regulator (Standby with 48 KB SRAM retention mode).

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE, or from the RF system wakeup).

The system clock after wakeup is 16 MHz, derived from the HSI16

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In this mode the RF can be used.

Shutdown

The Shutdown mode allows to achieve the ultimate lowest power consumption. The internal regulator is switched off so that the VCORE domain is powered off.

The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).

The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode, therefore the switch to Backup domain is not supported.

SRAM1, SRAM2a, SRAM2b and register contents are lost except for registers in the Backup domain.

The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic wakeup, timestamp, tamper).

The system clock after wakeup is 4 MHz, derived from the MSI. In this mode the RF is no longer operational.

When the RF subsystem is active, it changes the power state according to its needs (Run, Stop, Standby). This operation is transparent for the CPU1 host application and managed by a dedicated HW state machine. At any given time the effective power state reached is the higher one needed by both the CPU1 and RF sub-system.

Table 6 summarizes the peripheral features over all available modes. Wakeup capability is detailed in gray cells.

Table 6. Functionalities depending on system operating mode(1)

<![if ! IE]> <![endif]>power-Lowsleep

Stop0

Stop1

Standby

Shutdow

<![if ! IE]> <![endif]>power-Low run

Peripheral

<![if ! IE]> <![endif]>Run

<![if ! IE]> <![endif]>Sleep

-

<![if ! IE]> <![endif]>capabilityWakeup

-

<![if ! IE]> <![endif]>capabilityWakeup

-

<![if ! IE]> <![endif]>capabilityWakeup

-

<![if ! IE]> <![endif]>capabilityWakeup

<![if ! IE]> <![endif]>VBAT

CPU1

Y

-

Y

-

-

-

-

-

-

-

-

-

-

CPU2

Y

-

Y

-

-

-

-

-

-

-

-

-

-

Radio-system (BLE)

Y

Y

-

-

-

Y

-

Y

-

Y(2)

-

-

-

Flash memory

Y

Y

O

O

R

-

R

-

R

-

R

-

R

SRAM1

Y

O(3)

Y

O(3)

R

-

R

-

O(2)

-

-

-

-

SRAM2a

Y

O(3)

Y

O(3)

R

-

R

-

O(2)

-

-

-

-

SRAM2b

Y

O(3)

Y

O(3)

R

-

R

-

O(2)

-

-

-

-

Backup registers

Y

Y

Y

Y

R

-

R

-

R

-

R

-

R

Brown-out reset (BOR)

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

-

-

-

Brown-out SMPS

Y

Y

Y

Y

Y

Y

-

-

-

-

-

-

-

force bypass (BOR)

Programmable voltage detector

O

O

O

O

O

O

O

O

-

-

-

-

-

(PVD)

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Table 6. Functionalities depending on system operating mode(1) (continued)

					<![if ! IE]> <![endif]>Low-power sleep	Stop0		Stop1		Standby		Shutdow
				<![if ! IE]> <![endif]>Low-power run
	Peripheral	<![if ! IE]> <![endif]>Run	<![if ! IE]> <![endif]>Sleep			-	<![if ! IE]> <![endif]>Wakeup capability	-	<![if ! IE]> <![endif]>Wakeup capability	-	<![if ! IE]> <![endif]>Wakeup capability	-	<![if ! IE]> <![endif]>Wakeup capability	<![if ! IE]> <![endif]>VBAT
	Peripheral voltage monitor	O	O	O	O	O	O	O	O	-	-	-	-	-
	(PVMx; x=3)
	DMAx (x=1)	O	O	O	O	-	-	-	-	-	-	-	-	-
	High speed internal (HSI16)	O	O	O	O	O(4)	-	O(4)	-	-	-	-	-	-
	High speed external (HSE)	O	O	O	O	-	-	-	-	-	-	-	-	-
	Low speed internal (LSI)	O	O	O	O	O	-	O	-	O	-	-	-	-
	Low speed external (LSE)	O	O	O	O	O	-	O	-	O	-	O	-	O
	Multi-speed internal (MSI)	O	O	O	O	-	-	-	-	-	-	-	-	-
	Clock security system (CSS)	O	O	O	O	-	-	-	-	-	-	-	-	-
	Clock security system on LSE	O	O	O	O	O	O	O	O	O	O	-	-	-
	RTC / Auto wakeup	O	O	O	O	O	O	O	O	O	O	O	O	O
	Number of RTC tamper pins	1	1	1	1	1	O	1	O	1	O	1	O	1
	USART1	O	O	O	O	O(5)	O(5)	O(5)	O(5)	-	-	-	-	-
	Low-power UART (LPUART)	O	O	O	O	O(5)	O(5)	O(5)	O(5)	-	-	-	-	-
	I2C1	O	O	O	O	O(6)	O(6)	O(6)	O(6)	-	-	-	-	-
	SPIx (x=1)	O	O	O	O	-	-	-	-	-	-	-	-	-
	ADC1	O	O	O	O	-	-	-	-	-	-	-	-	-
	COMPx (x=1)	O	O	O	O	O	O	O	O	-	-	-	-	-
	Temperature sensor	O	O	O	O	-	-	-	-	-	-	-	-	-
	Timers (TIMx)	O	O	O	O	-	-	-	-	-	-	-	-	-
	Low-power timer 1 (LPTIM1)	O	O	O	O	O	O	O	O	-	-	-	-	-
	Low-power timer 2 (LPTIM2)	O	O	O	O	O	O	O	O	-	-	-	-	-
	Independent watchdog (IWDG)	O	O	O	O	O	O	O	O	O	O	-	-	-
	Window watchdog (WWDG)	O	O	O	O	-	-	-	-	-	-	-	-	-
	SysTick timer	O	O	O	O	-	-	-	-	-	-	-	-	-
	Touch sensing controller (TSC)	O	O	O	O	-	-	-	-	-	-	-	-	-
	True random number generator	O	O	-	-	-	-	-	-	-	-	-	-	-
	(RNG)
	AES hardware accelerator	O	O	O	O	-	-	-	-	-	-	-	-	-
	CRC calculation unit	O	O	O	O	-	-	-	-	-	-	-	-	-

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Table 6. Functionalities depending on system operating mode(1) (continued)

					<![if ! IE]> <![endif]>Low-power sleep	Stop0		Stop1		Standby		Shutdow
				<![if ! IE]> <![endif]>Low-power run
	Peripheral	<![if ! IE]> <![endif]>Run	<![if ! IE]> <![endif]>Sleep			-	<![if ! IE]> <![endif]>Wakeup capability	-	<![if ! IE]> <![endif]>Wakeup capability	-	<![if ! IE]> <![endif]>Wakeup capability	-	<![if ! IE]> <![endif]>Wakeup capability	<![if ! IE]> <![endif]>VBAT
IPCC		O	-	O	-	-	-	-	-	-	-	-	-	-
HSEM		O	-	O	-	-	-	-	-	-	-	-	-	-
PKA		O	O	O	O	-	-	-	-	-	-	-	-	-
GPIOs		O	O	O	O	O	O	O	O	(7)	2	(9)	2	-
											pins		pins
											(8)		(9)

1.Legend: Y = Yes (enabled). O = Optional (disabled by default, can be enabled by software). R = data retained. - = Not available. Gray cells indicate Wakeup capability.

2.The SRAM1, SRAM2a and SRAM2b content needs to be retained via the PWR_CR3.RRS bit.

3.The SRAM clock can be gated on or off.

4.Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not need it anymore.

5.UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event.

6.I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.

7.I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.

8.The I/Os with wakeup from Standby/Shutdown capability are PA0 and PA2.

9.I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode.

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Table 7. STM32WB15CC modes overview

	Mode	Regulator	CPU1	Flash	SRAM	Clocks	DMA and Peripherals	Wakeup source	Consumption(1)	Wakeup time
	Run	MR	Yes	ON(2)	ON	Any	All	N/A	91 µA/MHz	N/A
				ON(2)		Any
	LPRun	LPR	Yes		ON	except	All except RF and RNG	N/A	90 µA/MHz	TBD µs
						PLL
	Sleep	MR	No	ON(2)	ON(3)	Any	All	Any interrupt	28 µA/MHz	TBD cycles
								or event
				ON(2)	ON(3)	Any		Any interrupt
	LPSleep	LPR	No			except	All except RF and RNG		27 µA/MHz	TBD cycles
								or event
						PLL
							RF, BOR, PVD, PVM, RTC,	Reset pin, all I/Os, RF,
								BOR, PVD, PVM,
						LSE, LSI,	IWDG, COMPx (x=1),
								RTC, IWDG, COMPx
	Stop 0	MR	No	OFF	ON	HSE(4),	USART1(6), LPUART1(6),		100 µA	TBD µs
						HSI16(5)	I2C1(7), LPTIMx (x=1, 2), SMPS	(x=1), USART1,
							All other peripherals are frozen.	LPUART1, I2C1,
								LPTIMx (x=1, 2)
							RF, BOR, PVD, PVM, RTC,	Reset pin, all I/Os
								RF, BOR, PVD, PVM,
						LSE, LSI,	IWDG, COMPx (x=1),		3.05 µA w/o RTC
								RTC, IWDG, COMPx
	Stop 1	LPR	No	OFF	ON	HSE(4),	USART1(6), LPUART1(6),			TBD µs
						HSI16(5)	I2C1(7), LPTIMx (x=1, 2)	(x=1), USART1,	3.35 µA w RTC
							All other peripherals are frozen.	LPUART1, I2C1,
								LPTIMx (x=1, 2)
		LPR			SRAMs		RF, BOR, RTC, IWDG	RF, Reset pin	0.335 µA w/o RTC
					ON		All other peripherals are		0.61 µA w RTC
	Standby		No	OFF		LSE, LSI	powered off.	Two I/Os (WKUPx)(8)		TBD µs
									0.243 µA w/o RTC
		OFF			OFF		I/O configuration can be floating,	BOR, RTC, IWDG
									0.518 µA w RTC
							pull-up or pull-down
							RTC
							All other peripherals are	Two I/Os (WKUPx)(8),	0.012 µA w/o RTC	-
	Shutdown	OFF	No	OFF	OFF	LSE	powered off.
								RTC	0.210 µA w/ RTC
							I/O configuration can be floating,
							pull-up or pull-down(9)

1. Typical current at VDD = 1.8 V, 25 °C. for STOPx, SHUTDOWN and Standby, else VDD = 3.3 V, 25 °C.

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<![endif]>overview Functional

<![if ! IE]> <![endif]>30/121	2.	The Flash memory controller can be placed in power-down mode if the RF subsystem is not in use and all the program is run from the SRAM.	<![if ! IE]> <![endif]>Functional
	3.	The SRAM1 and SRAM2 clocks can be gated off independently.
	4.	HSE (32 MHz) automatically used when RF activity is needed by the RF subsystem.
	5.	HSI16 (16 MHz) automatically used by some peripherals.	<![if ! IE]> <![endif]>overview
	8.	I/Os with wakeup from Standby/Shutdown capability: PA0, PA2.
	6.	U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, Address match or Received frame event.
	7.	I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.
	9.	I/Os can be configured with internal pull-up, pull-down or floating but the configuration is lost immediately when exiting the Shutdown mode.

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