STMicroelectronics STM32WB10CC Datasheet

Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4

UFQFPN48

7 x 7 mm

solder pad

Features

 Includes ST state-of-the-art patented

technology

 Radio

– 2.4 GHz – RF transceiver supporting Bluetooth

specification

– RX sensitivity: -95.5 dBm (Bluetooth

Energy at 1 Mbps)

– Programmable output power up to +4 dBm

with 1 dB steps – Integrated balun to reduce BOM – Support for 1 Mbps – Dedicated Arm

for real-time Radio layer – Accurate RSSI to enable power control – Suitable for systems requiring compliance

with radio frequency regulations ETSI EN

300 328, EN 300 440, FCC CFR47 Part 15

and ARIB STD-T66 – Support for external PA – Available integrated passive device (IPD)

companion chip for optimized matching

solution (MLPF-WB-01E3)

 Ultra-low-power platform

– 2.0 to 3.6 V power supply – – 10 °C to +85 °C temperature range – 18 nA shutdown mode – 700 nA Standby mode + RTC + 48 KB

RAM – Radio: Rx 7.7 mA / Tx at 0 dBm 8.7 mA

 Core: Arm

adaptive real-time accelerator (ART Accelerator) allowing 0-wait-state execution from Flash memory, frequency up to 64 MHz, MPU, 80 DMIPS and DSP instructions

 Performance benchmark

– 1.25 DMIPS/MHz (Drystone 2.1)

32-bit Cortex® M0+ CPU

32-bit Cortex®-M4 CPU with FPU,

STM32WB10CC

with FPU, Bluetooth

5.2

Low

 Supply and reset management

– Ultra-safe, low-power BOR (brownout

reset) with five selectable thresholds – Ultra-low-power POR/PDR – Programmable voltage detector (PVD) –V

 Clock sources

– 32 MHz crystal oscillator with integrated

– 32 kHz crystal oscillator for RTC (LSE) – Internal low-power 32 kHz RC (LSI1) – Internal low-drift 32 kHz (stability

– Internal multispeed 100 kHz to 48 MHz

– High speed internal 16 MHz factory

– 1x PLL for system clock and ADC

 Memories

– 320 KB Flash memory with sector

– 48 KB SRAM, including 36 KB with

– 20x32-bit backup register – Boot loader supporting USART, SPI, I2C

– 1 Kbyte (128 double words) OTP

 Rich analog peripherals (down to 2.0 V)

– 12-bit ADC 2.5 Msps, 190 µA/Msps

mode with RTC and backup registers

BAT

trimming capacitors (Radio and CPU clock)

±500 ppm) RC (LSI2)

oscillator, factory-trimmed

trimmed RC (±1%)

protection (PCROP) against R/W

operations, enabling radio stack and

application

hardware parity check

interfaces

5.2 radio solution

Datasheet - production data

February 2021 DS13259 Rev 1 1/110

This is information on a product in full production.

www.st.com

STM32WB10CC

 System peripherals

– Inter processor communication controller

(IPCC) for communication with Bluetooth Low Energy

– HW semaphores for resources sharing

between CPUs

– 1x DMA controller (7x channels) supporting

ADC, SPI, I2C, USART, AES, timers

– 1x USART (ISO 7816, IrDA, SPI Master,

Modbus and Smartcard mode) – 1x SPI 32 Mbit/s – 1x I2C (SMBus/PMBus) – Touch sensing controller, up to eight

sensors – 1x 16-bit, four channels advanced timer – 1x 32-bit, four channels timer – 2x 16-bit ultra-low-power timer – 1x independent Systick – 1x independent watchdog – 1x window watchdog

 Security and ID

– Secure firmware installation (SFI) for

Bluetooth

Low Energy SW stack

– 2x hardware encryption AES maximum

256-bit for the application and the Bluetooth

Low Energy – HW public key authority (PKA) – Cryptographic algorithms: RSA, 

Diffie-Helman, ECC over GF(p) – True random number generator (RNG) – Sector protection against R/W operation

(PCROP) – CRC calculation unit – Die information: 96-bit unique ID – IEEE 64-bit unique ID. Possibility to derive

Bluetooth

Low Energy 48-bit EUI

 Up to 30 fast I/Os, 28 of them 5 V-tolerant

 Development support

– Serial wire debug (SWD), JTAG for the

application processor – Application cross trigger

 Package is ECOPACK2 compliant

2/110 DS13259 Rev 1

STM32WB10CC Contents

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.2 Arm

3.3 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.4 Security and safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.3.1 Adaptive real-time memory accelerator (ART Accelerator) . . . . . . . . . . 14

3.3.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.3.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.5 Boot modes and FW update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.6 RF subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.6.1 RF front-end block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.6.2 BLE general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.6.3 RF pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.6.4 Typical RF application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.7 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.7.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.7.2 Linear voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.7.3 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.7.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.7.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.8 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.9 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.10 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.11 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.12 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.13 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.13.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 35

3.13.2 Extended interrupts and events controller (EXTI) . . . . . . . . . . . . . . . . . 36

DS13259 Rev 1 3/110

Contents STM32WB10CC

3.14 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.14.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.14.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.15 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.16 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.17 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.17.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.17.2 General-purpose timer (TIM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.17.3 Low-power timer (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . 39

3.17.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.17.5 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.17.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.18 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 40

3.19 Inter-integrated circuit interface (I

C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.20 Universal synchronous/asynchronous receiver transmitter (USART) . . . 42

3.21 Serial peripheral interface (SPI1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.22 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.22.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 43

4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6.3.1 Summary of main performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6.3.2 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

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STM32WB10CC Contents

6.3.3 RF BLE characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6.3.4 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 60

6.3.5 Embedded reset and power control block characteristics . . . . . . . . . . . 60

6.3.6 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

6.3.7 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

6.3.8 Wakeup time from Low-power modes and voltage scaling

transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6.3.9 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

6.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

6.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

6.3.12 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

6.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

6.3.14 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

6.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

6.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

6.3.17 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

6.3.18 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

6.3.19 Analog-to-Digital converter characteristics . . . . . . . . . . . . . . . . . . . . . . 91

6.3.20 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

6.3.21 V

6.3.22 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

6.3.23 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . . 98

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

BAT

7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

7.1 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

7.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

7.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

7.2.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 106

8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

DS13259 Rev 1 5/110

List of tables STM32WB10CC

List of tables

Table 1. STM32WB10CC device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 2. Access status vs. readout protection level and execution modes . . . . . . . . . . . . . . . . . . . 15

Table 3. RF pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 4. Typical external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 5. Functionalities depending on system operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 6. STM32WB10CC modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 7. STM32WB10CC CPU1 peripherals interconnect matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 8. DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 9. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 10. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 11. Timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 12. I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 13. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 14. STM32WB10CC pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 15. Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 16. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 17. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 18. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 19. Main performance at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 20. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 21. RF transmitter BLE characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 22. RF transmitter BLE characteristics (1 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 23. RF receiver BLE characteristics (1 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 24. RF BLE power consumption for VDD = 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 25. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 26. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 27. Embedded internal voltage reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 28. Current consumption in Run and Low-power run modes, code with data processing

running from Flash memory, ART enable (Cache ON Prefetch OFF), VDD = 3.3 V . . . . . 63

Table 29. Current consumption in Run and Low-power run modes, code with data processing

running from SRAM1, VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 30. Typical current consumption in Run and Low-power run modes, with different codes

running from Flash memory, ART enable (Cache ON Prefetch OFF), VDD= 3.3 V . . . . . . 64

Table 31. Typical current consumption in Run and Low-power run modes,

with different codes running from SRAM1, VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 32. Current consumption in Sleep and Low-power sleep modes, Flash memory ON . . . . . . . 65

Table 33. Current consumption in Low-power sleep modes, Flash memory in Power down . . . . . . . 65

Table 34. Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 35. Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 36. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 37. Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 38. Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 39. Current under Reset condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 40. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 41. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 42. Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 43. HSE crystal requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 44. HSE clock source requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

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STM32WB10CC List of tables

Table 45. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 46. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 47. Low-speed external user clock characteristics, bypass mode . . . . . . . . . . . . . . . . . . . . . . 75

Table 48. HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 49. MSI oscillator characteristics

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Table 50. LSI1 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 51. LSI2 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 52. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 53. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 54. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 55. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 56. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 57. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 58. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 59. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 60. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 61. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 62. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 63. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 64. Analog switches booster characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 65. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 66. Maximum ADC R

values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

AIN

Table 67. ADC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 68. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 69. V Table 70. V

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

BAT

charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

BAT

Table 71. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 72. IWDG min/max timeout period at 32 kHz (LSI1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 73. Minimum I2CCLK frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 74. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 75. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 76. JTAG characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 77. SWD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 78. UFQFPN48 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 79. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Table 80. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

DS13259 Rev 1 7/110

List of figures STM32WB10CC

List of figures

Figure 1. STM32WB10CC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 2. STM32WB10CC RF front-end block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 3. External components for the RF part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 4. Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 5. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 6. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 7. STM32WB10CCU UFQFPN48 pinout

Figure 8. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 9. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 10. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 11. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 12. VREFINT vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 13. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 14. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 15. HSI16 frequency vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 16. Typical current consumption vs. MSI frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 17. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 18. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 19. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 20. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 21. SPI timing diagram - Slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 22. SPI timing diagram - Slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Figure 23. SPI timing diagram - Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Figure 24. UFQFPN48 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Figure 25. UFQFPN48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Figure 26. UFQFPN48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

(1) (2)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8/110 DS13259 Rev 1

STM32WB10CC Introduction

1 Introduction

This document provides the ordering information and mechanical device characteristics of

the STM32WB10CC microcontroller, based on Arm

cores

(a)

. Throughout the whole

document TBD indicates a value to be defined.

This document must be read in conjunction with the reference manual (RM0478), available

from the STMicroelectronics website www.st.com.

For information on the Arm® Cortex®-M4 and Cortex®-M0+ cores, refer, respectively, to the

Cortex

-M4 Technical Reference Manual and to the Cortex®-M0+ Technical Reference

Manual, both available on the www.arm.com website.

For information on Bluetooth® refer to www.bluetooth.com.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

DS13259 Rev 1 9/110

Description STM32WB10CC

2 Description

The STM32WB10CC multiprotocol wireless and ultra-low-power device embeds a powerful

and ultra-low-power radio compliant with the Bluetooth

It contains a dedicated Arm

Cortex® -M0+ for performing all the real-time low layer

Low Energy SIG specification v5.0.

operation.

The device is designed to be extremely low-power and is based on the high-performance

Arm

Cortex®-M4 32-bit RISC core operating at a frequency of up to 64 MHz. This core

features a Floating point unit (FPU) single precision that supports all Arm

®

single-precision data-processing instructions and data types. It also implements a full set of

DSP instructions and a memory protection unit (MPU) that enhances application security.

Enhanced inter-processor communication is provided by the IPCC with six bidirectional

channels. The HSEM provides hardware semaphores used to share common resources

between the two processors.

The device embeds high-speed memories (320 Kbyte of Flash memory, 48 Kbytes of

SRAM) and an extensive range of enhanced I/Os and peripherals.

Direct data transfer between memory and peripherals and from memory to memory is

supported by seven DMA channels with a full flexible channel mapping by the DMAMUX

peripheral.

The device features several mechanisms for embedded Flash memory and SRAM: readout

protection, write protection and proprietary code readout protection. Portions of the memory

can be secured for Cortex

-M0+ exclusive access.

The AES encryption engine, PKA and RNG enable upper layer cryptography.

The device offers a fast 12-bit ADC.

The device embeds a low-power RTC, one advanced 16-bit timer, one general-purpose

32-bit timer, and two 16-bit low-power timers.

In addition, up to three capacitive sensing channels are available.

The STM32WB10CC also features standard and advanced communication interfaces,

namely one USART (ISO 7816, IrDA, Modbus and Smartcard mode), one I2C

(SMBus/PMBus), one SPI up to 32

MHz.

The STM32WB10CC operates in the -10 to +85 °C (+105 °C junction) temperature range

from a 2.0 to 3.6

V power supply. A comprehensive set of power-saving modes enables the

design of low-power applications.

The device includes independent power supplies for analog input for ADC.

A V

dedicated supply allows the device to back up the LSE 32.768 kHz oscillator, the

BAT

RTC and the backup registers, thus enabling the STM32WB10CC to supply these functions

even if the main V

is not present through a CR2032-like battery, a Supercap or a small

rechargeable battery.

The STM32WB10CC is available in a 48-pin UFQFPN package.

10/110 DS13259 Rev 1

STM32WB10CC Description

Table 1. STM32WB10CC device features and peripheral counts

Feature STM32WB10CC

Flash memory density 320K bytes

SRAM density 48 Kbytes

BLE V5.2 (1 Mbps)

Advanced 1 (16-bit)

Timers

Communication interface

RTC 1

Tamper pin 1

Wakeup pin 2

GPIOs 30

Capacitive sensing 3

12-bit ADC Number of channels

Internal V

ref

Max CPU frequency 64 MHz

General purpose 1 (32-bit)

Low power 2 (16-bit)

SysTick 1

SPI 1

I2C 1

USART

(1)

13 channels

(including 3 internal)

Yes

Operating temperature

Ambient operating temperature:-10 to +85 °C

Junction temperature: -10 to 105 °C

Operating voltage 2.0 to 3.6 V

Package

1. USART peripheral can be used as SPI.

7 mm x 7 mm, 0.5 mm pitch, solder pad

UFQFPN48

DS13259 Rev 1 11/110

Description STM32WB10CC

MS53573V2

NVICETM

TIM2

PWR

TIM1

GPIO ports

A, B, C, E, H

EXTI

12 KB SRAM1

RTC2

I-WDG

LSE

32 kHz

HSE2

32 MHz

MSI up to

48 MHz

HSI 1% 16 MHz

PLL1

Power supply POR/

PDR/BOR/PVD/AVD

ADC1 12-bit ULP

2.5 Msps / 13 ch

NVIC

JTAG/SWD

AHB Lite

IPCC

Arbiter + ART

320 KB Flash

shared memory

BLE IP

RNG

LSI1

32 kHz

BLE RF IP

LPTIM2

LPTIM1

AES2

DBG

AHB lite (shared)

WKUP

BLE

AHB asynchronous

CRC

RCC + CSS

SYSCFG

APB asynchronous

RCC2

TSC

HSEM

WWDG

USART1

SPI1

I2C1

PKA + RAM

LSI2

32 kHz

MPU

Cortex-M0+

32 KB SRAM2a

Cortex-M4

(DSP)

4 KB SRAM2b

FPU

CTI CTI

TAMP

DMAMUX

AHB Lite

Temp (

C) sensor

DMA1 - 7 channels

APB

Figure 1. STM32WB10CC block diagram

12/110 DS13259 Rev 1

STM32WB10CC Functional overview

3 Functional overview

3.1 Architecture

The STM32WB10CC multiprotocol wireless device embeds a BLE RF subsystem that

interfaces with a generic microcontroller subsystem using an Arm

CPU1) on which the host application resides.

The RF subsystem is composed of an RF analog front end, BLE block as well as of a

dedicated Arm

The RF subsystem performs all of the BLE stack, reducing the interaction with the CPU1 to

high level exchanges.

Some functions are shared between the RF subsystem CPU (CPU2) and the Host CPU

(CPU1):

 Flash memories

 SRAM1, SRAM2a and SRAM2b (all can be retained in Standby mode)

 Security peripherals (RNG, PKA)

 Clock RCC

 Power control (PWR)

The communication and the sharing of peripherals between the RF subsystem and the

Cortex

controller (IPCC) and semaphore mechanism (HSEM).

Cortex®-M0+ microcontroller (called CPU2), plus proprietary peripherals.

-M4 CPU is performed through a dedicated inter processor communication

3.2 Arm® Cortex®-M4 core with FPU

The Arm® Cortex®-M4 with FPU is a processor for embedded systems. It has been

developed to provide a low-cost platform that meets the needs of MCU implementation, with

a reduced pin count and low-power consumption, while delivering outstanding

computational performance and an advanced response to interrupts.

Cortex®-M4 CPU (called

The Arm® Cortex®-M4 with FPU 32-bit RISC processor features exceptional 

code-efficiency, delivering the high-performance expected from an Arm® core in the

memory size usually associated with 8- and 16-bit devices.

The processor supports a set of DSP instructions enabling efficient signal processing and

complex algorithm execution.

Its single precision FPU speeds up software development by using metalanguage

development tools, while avoiding saturation.

With its embedded Arm® core, the STM32WB10CC is compatible with all Arm® tools and

software.

Figure 1 shows the general block diagram of the device.

DS13259 Rev 1 13/110

Functional overview STM32WB10CC

3.3 Memories

3.3.1 Adaptive real-time memory accelerator (ART Accelerator)

The ART Accelerator is a memory accelerator optimized for STM32 industry-standard Arm®

Cortex

for the Flash memory at higher frequencies.

To release the processor near 80 DMIPS performance at 64 MHz, the accelerator

implements an instruction prefetch queue and branch cache, which increases program

execution speed from the 64-bit Flash memory. Based on CoreMark benchmark, the

performance achieved thanks to the ART accelerator is equivalent to 0 wait state program

execution from Flash memory at a CPU frequency up to 64 MHz.

3.3.2 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU1 accesses to memory to

prevent one task to accidentally corrupt the memory or resources used by any other active

task. This memory area is organized into up to eight protected areas, which can be divided

up into eight subareas. The protection area sizes are between 32 bytes and the whole

-M4 processors. It balances the inherent performance advantage of the Arm®

-M4 over Flash memory technologies, which normally require the processor to wait

Gbytes of addressable memory.

The MPU is especially helpful for applications where some critical or certified code must be

protected against the misbehavior of other tasks. It is usually managed by an RTOS

(real-time operating system). If a program accesses a memory location prohibited by the

MPU, the RTOS detects it and takes action. In an RTOS environment, the kernel can

dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

3.3.3 Embedded Flash memory

The STM32WB10CC device features 320 Kbytes of embedded Flash memory available for

storing programs and data, as well as some customer keys.

Flexible protections can be configured thanks to option bytes:

 Readout protection (RDP) to protect the whole memory. Three levels are available:

– Level 0: no readout protection

– Level 1: memory readout protection: the Flash memory cannot be read from or

written to if either debug features are connected, boot in SRAM or bootloader is selected

– Level 2: chip readout protection: debug features (Cortex

JTAG and serial wire), boot in SRAM and bootloader selection are disabled (JTAG fuse). This selection is irreversible.



-M4 and Cortex®-M0+

14/110 DS13259 Rev 1

STM32WB10CC Functional overview

Table 2. Access status vs. readout protection level and execution modes

Area

Main

memory

System

memory

Option

bytes

Backup

registers

SRAM2a SRAM2b

1. The option byte can be modified by the RF subsystem.

2. Erased when RDP changes from Level 1 to Level 0.

Protection

level

1 Yes Yes Yes No No No

2 Yes Yes Yes N/A N/A N/A

1 Yes No No Yes No No

2 Yes No No N/A N/A N/A

1 Yes Yes Yes Yes Yes Yes

2YesNo

1YesYesN/A

2 Yes Yes N/A N/A N/A N/A

1 Yes Yes Yes

2 Yes Yes Yes N/A N/A N/A

User execution

Read Write Erase Read Write Erase

(1)

Debug, boot from SRAM or boot

from system memory (loader)

N/A N/A N/A

(2)

No No N/A

No No No

(2)

 Write protection (WRP): the protected area is protected against erasing and

programming. Two areas can be selected, with 4-Kbyte granularity.

 Proprietary code readout protection (PCROP): two parts of the Flash memory can be

protected against read and write from third parties. The protected area is execute-only: it can only be reached by the STM32 CPU, as an instruction code, while all other accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited. Two areas can be selected, with 2-Kbyte granularity. An additional option bit (PCROP_RDP) makes possible to select if the PCROP area is erased or not when the RDP protection is changed from Level 1 to Level 0.

A section of the Flash memory is secured for the RF subsystem CPU2, and cannot be

accessed by the host CPU1.

The whole non-volatile memory embeds the error correction code (ECC) feature supporting:

 single error detection and correction

 double error detection

 the address of the ECC fail can be read in the ECC register

The embedded Flash memory is shared between CPU1 and CPU2 on a time sharing basis.

A dedicated HW mechanism allows both CPUs to perform Write/Erase operations.

3.3.4 Embedded SRAM

The STM32WB10CC device features 48 Kbytes of embedded SRAM, split in three blocks:

 SRAM1: 12 Kbytes mapped at address 0x2000 0000

 SRAM2a: 32 Kbytes located at address 0x2003 0000 also mirrored at 0x1000 0000,

with hardware parity check

 SRAM2b: 4 Kbytes located at address 0x2003 8000 (contiguous with SRAM2a) and

mirrored at 0x1000 8000 with hardware parity check

DS13259 Rev 1 15/110

Functional overview STM32WB10CC

SRAM2a and SRAM2b can be write-protected, with 1-Kbyte granularity. A section of the

SRAM2a and SRAM2b is secured for the RF sub-system and cannot be accessed by the

host CPU1.

The SRAMs can be accessed in read/write with 0 wait states for all CPU1 and CPU2 clock

speeds.

3.4 Security and safety

The STM32WB10CC contains many security blocks both for the BLE and the Host

application.

It includes:

 Secure Flash memory partition for RF subsystem-only access

 Secure SRAM partition, that can be accessed only by the RF subsystem

 True random number generator (RNG)

 Advance encryption standard hardware accelerator (AES-256bit, supporting chaining

modes ECB, CBC, CTR, GCM, GMAC, CCM)

 Private key acceleration (PKA) including:

– Modular arithmetic including exponentiation with maximum modulo size of 3136

bits

– Elliptic curves over prime field scalar multiplication, ECDSA signature, ECDSA

verification with maximum modulo size of 521 bits

 Cyclic redundancy check calculation unit (CRC)

A specific mechanism is in place to ensure that all the code executed by the RF subsystem

CPU2 can be secure, whatever the Host application.

3.5 Boot modes and FW update

At startup, BOOT0 pin and BOOT1 option bit are used to select one of three boot options:

 Boot from user Flash

 Boot from system memory

 Boot from embedded SRAM

The device always boots on CPU1 core. The embedded bootloader code makes it possible

to boot from various peripherals:

 UART

 I2C

 SPI

Secure Firmware update from system boot is provided.

3.6 RF subsystem

The STM32WB10CC embeds an ultra-low power multi-standard radio Bluetooth® Low

Energy (BLE), compliant with Bluetooth

transfer rate, supports multiple roles simultaneously acting at the same time as BLE sensor

specification v5.2. The BLE features 1 Mbps

16/110 DS13259 Rev 1

STM32WB10CC Functional overview

and hub device, embeds Elliptic Curve Diffie-Hellman (ECDH) key agreement protocol, thus

ensuring a secure connection.

The BLE stack runs on an embedded Arm® Cortex®-M0+ core (CPU2). The stack is stored

on the embedded Flash memory, which is also shared with the Arm

application, making it possible in-field stack update.

3.6.1 RF front-end block diagram

The RF front-end is based on a direct modulation of the carrier in Tx, and uses a low IF

architecture in Rx mode.

Thanks to an internal transformer at RF pins, the circuit directly interfaces the antenna

(single ended connection, impedance close to 50 ). The natural bandpass behavior of the

internal transformer, simplifies outside circuitry aimed for harmonic filtering and out of band

interferer rejection.

In Transmit mode, the maximum output power is user selectable through the programmable

LDO voltage of the power amplifier. A linearized, smoothed analog control offers clean

power ramp-up.

In receive mode the circuit can be used in standard high performance or in reduced power

consumption (user programmable). The Automatic gain control (AGC) is able to reduce the

chain gain at both RF and IF locations, for optimized interference rejection. Thanks to the

use of complex filtering and highly accurate I/Q architecture, high sensitivity and excellent

linearity can be achieved.

The bill of material is reduced thanks to the high degree of integration. The radio frequency

source is synthesized form an external 32 MHz crystal that does not need any external

trimming capacitor network thanks to a dual network of user programmable integrated

capacitors.

Cortex®-M4 (CPU1)

DS13259 Rev 1 17/110

Functional overview STM32WB10CC

MS53574V1

Note: UFQFPN48: V

through exposed pad, and V

SSRF

pin must be connected to ground plane

filter

ADC

PLL

Modulator

RF1

Adjust

32 MHz

OSC_OUTOSC_IN

PA ramp

generator

AGC

control

BLE

modulator

BLE

demodulator

BLE

controller

RF control

AGC

Timer and Power

control

LDO LDO LDO

Trimmed

bias

DDRF

Max PA

level

Adjust

HSE

LNA

Wakeup

Interrupt

AHB

APB

See note

RF_TX_

MOD_

EXT_PA

Figure 2. STM32WB10CC RF front-end block diagram

3.6.2 BLE general description

The BLE block is a master/slave processor, compliant with Bluetooth specification 5.2

standard (1

It integrates a 2.4 GHz RF transceiver and a powerful Cortex®-M0+ core, on which a

complete power-optimized stack for Bluetooth Low Energy protocol runs, providing

master

Mbps).

/ slave role support

 GAP: central, peripheral, observer or broadcaster roles

 ATT/GATT: client and server

 SM: privacy, authentication and authorization

 L2CAP

 Link layer: AES-128 encryption and decryption

18/110 DS13259 Rev 1

STM32WB10CC Functional overview

In addition, according to Bluetooth specification v5.2, the BLE block provides:

 Multiple roles simultaneous support

 Master/slave and multiple roles simultaneously

 LE data packet length extension (making it possible to reach 800 kbps at application

level)

 LE privacy 1.2

 LE secure connections

 Flexible Internet connectivity options

The device allows the applications to meet the tight peak current requirements imposed by

the use of standard coin cell batteries.

Ultra-low-power sleep modes and very short transition time between operating modes result

in very low average current consumption during real operating conditions, resulting in longer

battery life.

The BLE block integrates a full bandpass balun, thus reducing the need for external

components.

The link between the Cortex®-M4 application processor (CPU1) running the application, and

the BLE stack running on the dedicated Cortex

-M0+ (CPU2) is performed through a

normalized API, using a dedicated IPCC.

3.6.3 RF pin description

The RF block contains dedicated pins, listed in Table 3.

Name Type Description

RF1

OSC_OUT

OSC_IN

RF_TX_

MOD_EXT_PA

VDDRF V

VSSRF

1. The exposed pad must be connected to GND plane for correct RF operation.

(1)

RF Input/output, must be connected to the antenna through a low-pass matching network

32 MHz main oscillator, also used as HSE source

I/O

External PA transmit control

Dedicated supply, must be connected to V

VSSTo be connected to GND

Table 3. RF pin list

3.6.4 Typical RF application schematic

The schematic in Figure 3 and the external components listed in Table 3 are purely

indicative. For more details refer to the “Reference design” provided in separate documents.

DS13259 Rev 1 19/110

Functional overview STM32WB10CC

MS53575V1

STM32WB

microcontroller

OSC_IN

OSC_OUT

VDDRF

VSSRF

RF1

Antenna

Cf1 Cf2

Lf1

Lf2

Antenna filter

(including exposed pad)

32 MHz

Figure 3. External components for the RF part

Component Description Value

C1 Decoupling capacitance for RF 100 nF // 100 pF

X1 32 MHz crystal

Antenna filter Antenna filter and matching network Refer to AN5165, on www.st.com

Antenna 2.4 GHz band antenna -

1. e.g. NDK reference: NX2016SA 32 MHz EXS00A-CS06654.

Table 4. Typical external components

(1)

32 MHz

Note: For more details refer to AN5165 “Development of RF hardware using STM32WB

microcontrollers” available on www.st.com.

3.7 Power supply management

3.7.1 Power supply schemes

The device has different voltage supplies (see Figure 5) and can operate within the following

voltage ranges:

 V

system functions such as RF, reset, power management and internal clocks. It is provided externally through VDD pins. V

 V

DDA

be independent from the V

= 2.0 to 3.6 V: external power supply for I/Os (V

= 2.0 to 3.6 V: external analog power supply for ADC. The V

must be always connected to VDD pins.

voltage. When not used V

DDRF

), the internal regulator and

DDIO

must be connected to VDD.

DDA

voltage level can

DDA

20/110 DS13259 Rev 1

STM32WB10CC Functional overview

MSv47490V1

0.3

BOR0

3.6

Operating modePower-on Power-down time

DDX

(1)

Invalid supply area V

DDX

< V

+ 300 mV

DDX

independent from V

During power up/down, the following power sequence requirements must be respected:

 When VDD is below 1 V the other power supply (V

+ 300 mV

 When V

is above 1 V all power supplies are independent.

), must remain below

DDA

Figure 4. Power-up/down sequence

1. V

refers to V

DDX

DDA

During the power down phase, VDD can temporarily become lower than other supplies only

if the energy provided to the MCU remains below 1 mJ. This allows the external decoupling

capacitors to be discharged with different time constants during the power down transient

phase.

Note: VDD and V

must be wired together, so they can follow the same voltage sequence.

DDRF

DS13259 Rev 1 21/110

Functional overview STM32WB10CC

MS53576V2

VBAT

IOs

Wakeup domain (V

DDIO

)

Analog domain

Interruptible domain (V

DD12I

)

Switch domain (V

)

(CPU1, CPU2,

peripherals)

Level shifter

Power switch

BAT

ADC

DDA

REF-

HSI, HSE,

PLL,

LSI1, LSI2,

IWDG, RF

IOs

logic

REF+

LSE, RTC,

backup registers

logic

Backup domain

Power switch

BKP12

SRAM1,

SRAM2a,

SRAM2b

Power switch

On domain (V

DD12O

)

Power switch

SysConfig, EXTI,

RCC, PwrCtrl,

LPTIM, USART1

LPR

RFR

RF domain

Radio

DDRF

SSRF

(including exposed pad)

Figure 5. Power supply overview

22/110 DS13259 Rev 1

STM32WB10CC Functional overview

3.7.2 Linear voltage regulator

Three embedded linear voltage regulators supply most of the digital and RF circuitries, the

main regulator (MR), the low-power regulator (LPR) and the RF regulator (RFR).

 The MR is used in the Run and Sleep modes and in the Stop 0 mode.

 The LPR is used in Low-Power Run, Low-Power Sleep and Stop 1 modes. It is also

used to supply the SRAMs in Standby with retention.

 The RFR is used to supply the RF analog part, its activity is automatically managed by

the RF subsystem.

All the regulators are in power-down in Standby and Shutdown modes: the regulator output

is in high impedance, and the kernel circuitry is powered down, inducing zero consumption.

The ultralow-power STM32WB10CC supports dynamic voltage scaling to optimize its power

consumption in run mode. The voltage from the main regulator that supplies the logic

(VCORE) can be adjusted according to the system’s maximum operating frequency.

VCORE can also be supplied by the low-power regulator, the main regulator being switched

off. The system is then in Low-power run mode. In this case the CPU is running at up to

MHz, and peripherals with independent clock can be clocked by HSI16 (in this mode the

RF subsystem is not available).

3.7.3 Power supply supervisor

An integrated ultra-low-power brown-out reset (BOR) is active in all modes except

Shutdown ensuring proper operation after power-on and during power down. The device

remains in reset mode when the monitored supply voltage V

threshold, without the need for an external reset circuit.

The lowest BOR level is 2.0 V at power on, and other higher thresholds can be selected

through option bytes.The device features an embedded programmable voltage detector

(PVD) that monitors the V

interrupt can be generated when V

higher than the V

threshold. The interrupt service routine can then generate a warning

PVD

message and/or put the MCU into a safe state. The PVD is enabled by software.

3.7.4 Low-power modes

This ultra-low-power device supports several low-power modes to achieve the best

compromise between low-power consumption, short startup time, available peripherals and

available wakeup sources.

By default, the microcontroller is in Run mode, after a system or a power on Reset. It is up to

the user to select one of the low-power modes described below:

 Sleep

In Sleep mode, only the CPU1 is stopped. All peripherals, including the RF subsystem, continue to operate and can wake up the CPU when an interrupt/event occurs.

 Low-power run

This mode is achieved with VCORE supplied by the low-power regulator to minimize the regulator operating current. The code can be executed from SRAM or from the Flash memory, and the CPU1 frequency is limited to 2 MHz. The peripherals with

power supply and compares it with the V

drops below the V

threshold and/or when VDD is

PVD

is below a specified

threshold. An

PVD

DS13259 Rev 1 23/110

Functional overview STM32WB10CC

independent clock can be clocked by HSI16. The RF subsystem is not available in this mode and must be OFF.

 Low-power sleep

This mode is entered from the low-power run mode. Only the CPU1 clock is stopped. When wakeup is triggered by an event or an interrupt, the system reverts to the  low-power run mode. The RF subsystem is not available in this mode and must be OFF.

 Stop 0 and Stop 1

Stop modes achieve the lowest power consumption while retaining the content of all the SRAM and registers. The LSE (or LSI) is still running.

The RTC can remain active (Stop mode with RTC, Stop mode without RTC).

Some peripherals with wakeup capability can enable the HSI16 RC during Stop modes to detect their wakeup condition.

Two modes are available: Stop 0 and Stop 1.

Stop 1 offers several active peripherals and wakeup sources. In Stop 0 mode the main regulator remains ON, allowing a very fast wakeup time but with higher consumption.

In these modes the RF subsystem can wait for incoming events in all Stop modes.

The system clock when exiting from Stop 0 Stop1 modes can be either MSI up to 48 MHz or HSI16 if the RF subsystem is disabled. If the RF subsystem is used the exits must be set to HSI16 only.

 Standby

The Standby mode is used to achieve the lowest power consumption with BOR. The internal regulator is switched off so that the VCORE domain is powered off.

The RTC can remain active (Standby mode with RTC).

The brown-out reset (BOR) always remains active in Standby mode.

The state of each I/O during standby mode can be selected by software: I/O with internal pull-up, internal pull-down or floating.

After entering Standby mode, register content is lost except for registers in the Backup domain and Standby circuitry. Optionally, SRAMs can be retained in Standby mode, supplied by the low-power regulator (Standby with 48 KB SRAM retention mode).

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE, or from the RF system wakeup).

The system clock after wakeup is 16 MHz, derived from the HSI16

24/110 DS13259 Rev 1

STM32WB10CC Functional overview

In this mode the RF can be used.

 Shutdown

The Shutdown mode allows to achieve the ultimate lowest power consumption. The internal regulator is switched off so that the VCORE domain is powered off.

The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).

The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode, therefore the switch to Backup domain is not supported.

SRAM1, SRAM2a, SRAM2b and register contents are lost except for registers in the Backup domain.

The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic wakeup, timestamp, tamper).

The system clock after wakeup is 4 MHz, derived from the MSI.

In this mode the RF is no longer operational.

When the RF subsystem is active, it changes the power state according to its needs (Run,

Stop, Standby). This operation is transparent for the CPU1 host application and managed by

a dedicated HW state machine. At any given time the effective power state reached is the

higher one needed by both the CPU1 and RF sub-system.

Tabl e 5 summarizes the peripheral features over all available modes. Wakeup capability is

detailed in gray cells.

Table 5. Functionalities depending on system operating mode

(1)

Stop0 Stop1 Standby Shutdow

Peripheral

Run

Sleep

Low-power run

Low-power sleep

Wakeup capability

VBAT

Wakeup capability

CPU1 Y - Y - - --------

CPU2 Y - Y - -

Radio-system (BLE) Y Y - - -

Flash memory Y Y O O R

SRAM1 Y O

SRAM2a Y O

SRAM2b Y O

(3)

Backup registers Y Y Y Y R

Brown-out reset (BOR) Y Y Y Y Y

Programmable voltage detector (PVD)

OOO O O

--------

Y-Y-Y

(2)

- --

-R-R-R-R

R -R-O

(2)

----

(2)

----

(2)

----

-R-R-R-R

YYYYY- --

OOO- ----

DMAx (x=1) O O O O - --------

High speed internal (HSI16) O O O O O

(4)

-O

------

DS13259 Rev 1 25/110

Functional overview STM32WB10CC

Table 5. Functionalities depending on system operating mode

(1)

(continued)

Stop0 Stop1 Standby Shutdow

Peripheral

Run

Sleep

Low-power run

Low-power sleep

Wakeup capability

VBAT

Wakeup capability

High speed external (HSE) O O O O - --------

Low speed internal (LSI) O O O O O

Low speed external (LSE) O O O O O

Multi-speed internal (MSI) O O O O -

Clock security system (CSS) O O O O -

Clock security system on LSE O O O O O

RTC / Auto wakeup O O O O O

Number of RTC tamper pins 1 1 1 1 1

USART1 O O O O O

I2C1 O O O O O

-O-O----

-O-O-O-O

--------

OOOOO- --

OOOOOOOO

O1O1O1O1

(5)O(5)O(5)O(5)

(6)O(6)O(6)O(6)

- ----

SPIx (x=1) O O O O -

ADC1 O O O O -

Temperature sensor O O O O -

Timers (TIMx) O O O O -

Low-power timer 1 (LPTIM1) O O O O O

Low-power timer 2 (LPTIM2) O O O O O

Independent watchdog (IWDG) O O O O O

Window watchdog (WWDG) O O O O -

SysTick timer O O O O -

Touch sensing controller (TSC) O O O O -

True random number generator (RNG)

OO - - -

--------

OOO- ----

OOOOO- --

--------

AES hardware accelerator O O O O - --------

CRC calculation unit O O O O -

IPCC O - O - -

HSEM O - O - -

PKA O O O O -

GPIOs O O O O O

--------

OOO

(7)

pins

(8)

(9)

pins

(9)

26/110 DS13259 Rev 1

STM32WB10CC Functional overview

1. Legend: Y = Yes (enabled). O = Optional (disabled by default, can be enabled by software).  R = data retained. - = Not available. Gray cells indicate Wakeup capability.

2. The SRAM1, SRAM2a and SRAM2b content needs to be retained via the PWR_CR3.RRS bit.

3. The SRAM clock can be gated on or off.

4. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not need it anymore.

5. UART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event.

6. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.

7. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.

8. The I/Os with wakeup from Standby/Shutdown capability are PA0 and PA2.

9. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode.

DS13259 Rev 1 27/110

28/110 DS13259 Rev 1

Table 6. STM32WB10CC modes overview

Mode Regulator CPU1 Flash SRAM Clocks DMA and Peripherals Wakeup source Consumption

Run MR Yes ON

LPRun LPR Yes ON

Sleep MR No ON

(2)

ON Any All N/A 91 µA/MHz N/A

Any

except

All except RF and RNG N/A 90 µA/MHz TBD µs

PLL

(3)

Any All

Any interrupt

or event

28 µA/MHz TBD cycles

(1)

Functional overview STM32WB10CC

Wakeup time

LPSleep LPR No ON

(2)

Stop 0 MR No OFF ON

Stop 1 LPR No OFF ON

SRAMs

Standby

LPR

No OFF

OFF OFF

(3)

Any

except

PLL

LSE, LSI,

(4)

HSE

(5)

HSI16

LSE, LSI,

(4)

HSE

(5)

HSI16

LSE, LSI

All except RF and RNG

RF, BOR, PVD, RTC, IWDG,

USART1

(6)

, I2C1

LPTIMx (x=1, 2)

(7)

All other peripherals are frozen.

RF, BOR, PVD, RTC, IWDG,

USART1

(6)

, I2C1

LPTIMx (x=1, 2)

(7)

All other peripherals are frozen.

RF, BOR, RTC, IWDG

All other peripherals are

powered off.

I/O configuration can be floating,

pull-up or pull-down

Any interrupt

or event

Reset pin, all I/Os, RF,

BOR, PVD, RTC,

IWDG, USART1, I2C1,

LPTIMx (x=1, 2)

Reset pin, all I/Os

RF, BOR, PVD, RTC,

IWDG, USART1, I2C1,

LPTIMx (x=1, 2)

RF, Reset pin

Two I/Os (WKUPx)

(8)

BOR, RTC, IWDG

3.05 µA w/o RTC

3.45 µA w RTC

0.345 µA w/o RTC

0.70 µA w RTC

0.245 µA w/o RTC

0.600 µA w RTC

RTC

All other peripherals are

Shutdown OFF No OFF OFF LSE

I/O configuration can be floating,

1. Typical current at VDD = 2.4 V, 25 °C. for STOPx, SHUTDOWN and Standby, else VDD = 3.3 V, 25 °C.

2. The Flash memory controller can be placed in power-down mode if the RF subsystem is not in use and all the program is run from the SRAM.

3. The SRAM1 and SRAM2 clocks can be gated off independently.

4. HSE (32 MHz) automatically used when RF activity is needed by the RF subsystem.

powered off.

pull-up or pull-down

(9)

Two I/Os (WKUPx)

RTC

(8)

0.018 µA w/o RTC

0.425 µA w/ RTC

27 µA/MHz TBD cycles

100 µA TBD µs

TBD µs

5. HSI16 (16 MHz) automatically used by some peripherals.

6. U(S)ART reception is functional in Stop mode, and generates a wakeup interrupt on Start, Address match or Received frame event.

7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.

8. I/Os with wakeup from Standby/Shutdown capability: PA0, PA2.

9. I/Os can be configured with internal pull-up, pull-down or floating but the configuration is lost immediately when exiting the Shutdown mode.

DS13259 Rev 1 29/110

STM32WB10CC Functional overview

Functional overview STM32WB10CC

3.7.5 Reset mode

To improve the consumption under reset, the I/Os state under and after reset is “analog state” (the I/O Schmitt trigger is disabled). In addition, the internal reset pull-up is deactivated when the reset source is internal.

3.8 VBAT operation

The VBAT pin allows to power the device VBAT domain (RTC, LSE and Backup registers) from an external battery, an external supercapacitor, or from V

when no external battery

nor an external supercapacitor are present. One anti-tamper detection pin is available in VBAT mode.

VBAT operation is automatically activated when VDD is not present.

An internal VBAT battery charging circuit is embedded and can be activated when VDD is present.

Note: When the microcontroller is supplied only from VBAT, external interrupts and RTC

alarm/events do not exit it from VBAT operation.

3.9 Interconnect matrix

Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU1 resources and, consequently, reducing power supply consumption. In addition, these hardware connections result in fast and predictable latency.

Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power run and Sleep, Stop 0 and Stop 1 modes.

Table 7. STM32WB10CC CPU1 peripherals interconnect matrix

Source Destination Action

TIMx Timers synchronization or chaining Y Y Y Y -

TIMx

ADC1 TIM1 Timer triggered by analog watchdog Y Y Y Y -

RTC

All clock sources (internal and external)

ADC1 Conversion triggers Y Y Y Y -

DMA Memory to memory transfer trigger Y Y Y Y -

LPTIMERx

TIM2

Low-power timer triggered by RTC alarms or tampers

Clock source used as input channel for RC measurement and trimming

Run

Sleep

Low-power

Low-power run

YYYYY

YYYY -

Stop 0 / Stop 1

30/110 DS13259 Rev 1

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