ST MICROELECTRONICS STM32L562ZET6Q Datasheet

STM32L562xx
UFQFPN48 (7 x 7 mm)
UFBGA132 (7 x 7 mm)
WLCSP81 (4.36 x 4.07 mm)
(*): Silhouette shown above.
LQFP48 (7 x 7 mm)
LQFP64 (10 x 10 mm
)
LQFP100
(*)
(14 x14 mm)
LQFP144 (20 x 20mm)
FBGA
Ultra-low-power Arm® Cortex®-M33 32-bit MCU+TrustZone®+FPU,
Datasheet - production data
Features
Ultra-low-power with FlexPowerControl
1.71 V to 3.6 V power supply
-40 °C to 85/125 °C temperature range
Batch acquisition mode (BAM)
187 nA in VBAT mode: supply for RTC and
32x32-bit backup registers
17 nA Shutdown mode (5 wakeup pins)
108 nA Standby mode (5 wakeup pins)
222 nA Standby mode with RTC
3.16 μA Stop 2 with RTC
106 μA/MHz Run mode (LDO mode)
62 μA/MHz Run mode @ 3 V
(SMPS step-down converter mode)
5 µs wakeup from Stop mode
Brownout reset (BOR) in all modes except
Shutdown
Core
Memories
Up to 512-Kbyte Flash, two banks read-while­write
256 Kbytes of SRAM including 64 Kbytes with hardware parity check
External memory interface supporting SRAM, PSRAM, NOR, NAND and FRAM memories
OCTOSPI memory interface
Arm® 32-bit Cortex®-M33 CPU with
TrustZone
ART Accelerator
8-Kbyte instruction cache allowing 0-wait-state execution from Flash memory and external memories; frequency up to 110 MHz, MPU, 165 DMIPS and DSP instructions
Performance benckmark
1.5 DMIPS/MHz (Drystone 2.1)
442 CoreMark
Energy benchmark
370 ULPMark-CP® score
54 ULPMark-PP
27400 SecureMark-TLS
February 2020 DS12736 Rev 2 1/323
This is information on a product in full production.
®
and FPU
®
(4.02 CoreMark®/MHz)
®
score
®
score
Security
Arm® TrustZone® and securable I/Os, memories and peripherals
Flexible life cycle scheme with RDP (readout protection)
Root of trust thanks to unique boot entry and hide protection area (HDP)
SFI (secure firmware installation) thanks to embedded RSS (root secure services)
Secure firmware upgrade support with TF-M
AES coprocessor
Public key accelerator
On-the-fly decryption of Octo-SPI external
memories
HASH hardware accelerator
www.st.com
STM32L562xx
Active tamper and protection against temperature, voltage and frequency attacks
True random number generator NIST SP800­90B compliant
96-bit unique ID
512-byte OTP (one-time programmable) for
user data
General-purpose input/outputs
Up to 114 fast I/Os with interrupt capability most 5 V-tolerant and up to 14 I/Os with independent supply down to 1.08 V
Power management
Embedded regulator (LDO) with three configurable range output to supply the digital circuitry
Embedded SMPS step-down converter
External SMPS support
Clock management
4 to 48 MHz crystal oscillator
32 kHz crystal oscillator for RTC (LSE)
Internal 16 MHz factory-trimmed RC (±1%)
Internal low-power 32 kHz RC (±5%)
Internal multispeed 100 kHz to 48 MHz
oscillator, auto-trimmed by LSE (better than ±0.25% accuracy)
Internal 48 MHz with clock recovery
3 PLLs for system clock, USB, audio, ADC
Up to 19 communication peripherals
1x USB Type-C™/ USB power delivery controller
1x USB 2.0 full-speed crystal less solution, LPM and BCD
2x SAIs (serial audio interface)
4x I2C FM+(1 Mbit/s), SMBus/PMBus™
6x USARTs (ISO 7816, LIN, IrDA, modem)
3x SPIs (7x SPIs with USART and OCTOSPI in
SPI mode)
1x FDCAN controller
1x SDMMC interface
2 DMA controllers
14 DMA channels
Up to 22 capacitive sensing channels
Support touch key, linear and rotary touch sensors
Rich analog peripherals (independent supply)
2x 12-bit ADC 5 Msps, up to 16-bit with hardware oversampling, 200 µA/Msps
2x 12-bit DAC outputs, low-power sample and hold
2x operational amplifiers with built-in PGA
2x ultra-low-power comparators
4x digital filters for sigma delta modulator
Up to 16 timers and 2 watchdogs
16x timers: 2 x 16-bit advanced motor-control, 2 x 32-bit and 5 x 16-bit general purpose, 2x 16-bit basic, 3x low-power 16-bit timers (available in Stop mode), 2x watchdogs, 2x SysTick timer
RTC with hardware calendar, alarms and calibration

Table 1. Device summary

Reference Part numbers
STM32L562xx
2/323 DS12736 Rev 2
STM32L562CE, STM32L562ME, STM32L562QE, STM32L562RE, STM32L562VE, STM32L562ZE
CRC calculation unit
Debug
Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell™ (ETM)
STM32L562xx Contents
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1 Arm® Cortex®-M33 core with TrustZone® and FPU . . . . . . . . . . . . . . . . . 20
3.2 Art Accelerator – instruction cache (ICACHE) . . . . . . . . . . . . . . . . . . . . . 20
3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.6 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.7 Global TrustZone controller (GTZC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.8 TrustZone security architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.8.1 TrustZone peripheral classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.9 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.9.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.9.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.9.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.9.4 SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.9.5 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.9.6 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.9.7 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.9.8 PWR TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.10 Peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.11 Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.12 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.13 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.14 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.15 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.16 DMA request router (DMAMUX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.17 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.17.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 57
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Contents STM32L562xx
3.17.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 57
3.18 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 58
3.19 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 58
3.20 Octo-SPI interface (OCTOSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.21 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.21.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.21.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.21.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.22 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.23 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.24 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.25 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.26 Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 64
3.27 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.28 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.29 Advanced encryption standard hardware accelerator (AES) . . . . . . . . . . 66
3.30 HASH hardware accelerator (HASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.31 Public key accelerator PKA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.32 On-the-fly decryption engine (OTFDEC) . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.33 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.33.1 Advanced-control timer (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.33.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16,
TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.33.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.33.4 Low-power timers (LPTIM1, LPTIM2 and LPTIM3) . . . . . . . . . . . . . . . . 70
3.33.5 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.33.6 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.33.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.34 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.35 Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.36 Inter-integrated circuit interface (I
2
C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.37 Universal synchronous/asynchronous receiver transmitter (USART) . . . 75
3.38 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 76
3.39 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.40 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4/323 DS12736 Rev 2
STM32L562xx Contents
3.41 Secure digital input/output and MultiMediaCards Interface (SDMMC) . . . 77
3.42 Controller area network (FDCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.43 Universal serial bus (USB FS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.44 USB Type-C™ / USB Power Delivery controller (UCPD) . . . . . . . . . . . . . 78
3.45 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.45.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.45.2 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 143
5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
5.3.2 SMPS step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
5.3.3 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 148
5.3.4 Embedded reset and power control block characteristics . . . . . . . . . . 148
5.3.5 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
5.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
5.3.7 Wakeup time from low-power modes and voltage scaling
transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
5.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 199
5.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 204
5.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
5.3.11 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
5.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
5.3.13 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
5.3.14 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
5.3.15 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
DS12736 Rev 2 5/323
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Contents STM32L562xx
5.3.16 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
5.3.17 Extended interrupt and event controller input (EXTI) characteristics . . 223
5.3.18 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
5.3.19 Analog-to-digital converter characteristics . . . . . . . . . . . . . . . . . . . . . . 225
5.3.20 Digital-to-Analog converter characteristics . . . . . . . . . . . . . . . . . . . . . 238
5.3.21 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 243
5.3.22 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
5.3.23 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 246
5.3.24 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
5.3.25 V
5.3.26 Temperature and VDD thresholds monitoring . . . . . . . . . . . . . . . . . . . 251
5.3.27 DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
5.3.28 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
5.3.29 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 255
5.3.30 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
5.3.31 OCTOSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
5.3.32 SD/SDIO/MMC card host interfaces (SDMMC) . . . . . . . . . . . . . . . . . . 289
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
BAT
5.3.33 UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
6.1 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
6.2 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
6.3 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
6.4 WLCSP81 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
6.5 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
6.6 UFBGA132 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
6.7 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311
6.8 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
6.8.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
6.8.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 316
7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
6/323 DS12736 Rev 2
STM32L562xx List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table 2. STM32L562xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 3. Boot modes when TrustZone is disabled (TZEN=0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 4. Boot modes when TrustZone is enabled (TZEN=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 5. Boot space versus RDP protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 6. Example of memory map security attribution vs SAU configuration regions . . . . . . . . . . . 27
Table 7. Securable peripherals by TZSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 8. TrustZone-aware peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 9. SMPS external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 10. STM32L562xx modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 11. Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 12. STM32L562xx peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 13. DMA1 and DMA2 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 14. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 15. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 16. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 17. I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 18. USART/UART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 19. SAI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 20. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 21. STM32L562xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 22. Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 23. Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 24. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 25. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 26. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 27. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 28. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 29. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 30. Embedded internal voltage reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 31. Current consumption in Run and Low-power run modes,code with data processing
running from Flash in single Bank, ICACHE ON in 2-way . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 32. Current consumption in Run and Low-power run modes,cod
running from Flash in single Bank, ICACHE ON in 1-way . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 33. Current consumption in Run and Low-power run modes, code with data processing
running from Flash in single Bank, ICACHE Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 34. Current consumption in Run and Low-power run modes, code with data processing
running from Flash in single bank, ICACHE ON in 2-way and power
supplied by internal SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 35. Current consumption in Run and Low-power run modes, code with data processing
running from Flash in single bank, ICACHE ON in 1-way and power
supplied by internal SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 36. Current consumption in Run and Low-power run modes, code with data processing
running from Flash in single bank, ICACHE Disabled and power
supplied by internal SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 37. Current consumption in Run and Low-power run modes, code with data processing
running from Flash in dual bank, ICACHE ON in 2-way . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 38. Current consumption in Run and Low-power run modes, code with data processing
e with data processing
DS12736 Rev 2 7/323
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List of tables STM32L562xx
running from Flash in dual bank, ICACHE ON in 1-way . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 39. Current consumption in Run and Low-power run modes, code with data processing
running from Flash in dual bank, ICACHE Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 40. Current consumption in Run and Low-power run modes, code with data processing
running from Flash in dual bank, ICACHE ON in 2-way and power
supplied by internal SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 41. Current consumption in Run and Low-power run modes, code with data processing
running from Flash in dual bank, ICACHE ON in 1-way and power
supplied by internal SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 42. Current consumption in Run and Low-power run modes, code with data processing
running from Flash in dual bank, ICACHE Disabled and power
supplied by internal SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 43. Current consumption in Run and Low-power run modes,
code with data processing running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 44. Current consumption in Run and Low-power run modes,
code with data processing running from SRAM1 and
power supplied by internal SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 45. Current consumption in Run and Low-power run modes,
code with data processing running from SRAM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 46. Current consumption in Run and Low-power run modes,
code with data processing running from SRAM2 and
power supplied by internal SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 47. Typical current consumption in Run and Low-power run modes,
with different codes running from Flash, ICACHE ON (2-way). . . . . . . . . . . . . . . . . . . . . 169
Table 48. Typical current consumption in Run and Low-power run modes with SMPS,
with different codes running from Flash, ICACHE ON (2-way). . . . . . . . . . . . . . . . . . . . . 170
Table 49. Typical current consumption in Run and Low-power run modes,
with different codes running from Flash, ICACHE ON (1-way). . . . . . . . . . . . . . . . . . . . . 171
Table 50. Typical current consumption in Run and Low-power run modes with SMPS,
with different codes running from Flash, ICACHE ON (1-way). . . . . . . . . . . . . . . . . . . . . 172
Table 51. Typical current consumption in Run and Low-power run modes,
with different codes running from Flash, ICACHE disabled . . . . . . . . . . . . . . . . . . . . . . . 173
Table 52. Typical current consumption in Run and Low-power run modes with internal SMPS,
with different codes running from Flash, ICACHE disabled . . . . . . . . . . . . . . . . . . . . . . . 174
Table 53. Typical current consumption in Run and Low-power run modes,
with different codes running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 54. Typical current consumption in Run and Low-power run modes with internal SMPS,
with different codes running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Table 55. Typical current consumption in Run and Low-power run modes,
with different codes running from SRAM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 56. Typical current consumption in Run and Low-power run modes with internal SMPS,
with different codes running from SRAM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 57. Current consumption in Sleep and Low-power sleep mode, Flash ON . . . . . . . . . . . . . . 179
Table 58. Current consumption in Low-power sleep mode, Flash in power-down . . . . . . . . . . . . . . 180
Table 59. Current consumption in Sleep and Low-power sleep mode,
Flash ON and power supplied by internal SMPS step down converter . . . . . . . . . . . . . . 181
Table 60. Current consumption in Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 61. Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 62. Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 63. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 64. Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 65. Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
8/323 DS12736 Rev 2
STM32L562xx List of tables
Table 66. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 67. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 68. Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 69. Wakeup time using USART/LPUART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 70. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 71. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Table 72. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Table 73. LSE oscillator characteristics (f
= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
LSE
Table 74. HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Table 75.
MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
Table 76. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 77. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Table 78. PLL, PLLSAI1, PLLSAI2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Table 79. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 80. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 81. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Table 82. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Table 83. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Table 84. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 85. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 86. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Table 87. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Table 88. I/O AC characteristics (All I/Os except FT_c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Table 89. FT_c I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Table 90. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Table 91. EXTI input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Table 92. Analog switches booster characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Table 93. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Table 94. Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Table 95. ADC accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Table 96. ADC accuracy - limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Table 97. ADC accuracy - limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Table 98. ADC accuracy - limited test conditions 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Table 99. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Table 100. DAC accuracy ranges 0/1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Table 101. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Table 102. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Table 103. OPAMP characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Table 104. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Table 105. V Table 106. V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
BAT
charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
BAT
Table 107. Temp and VDD monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Table 108. DFSDM measured timing 1.71 to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Table 109. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Table 110. IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Table 111. WWDG min/max timeout value at 110 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Table 112. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Table 113. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Table 114. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Table 115. USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Table 116. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 266
Table 117. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings. . . . . . . . . . . 266
DS12736 Rev 2 9/323
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List of tables STM32L562xx
Table 118. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 267
Table 119. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 268
Table 120. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Table 121. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 269
Table 122. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Table 123. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 271
Table 124. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Table 125. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Table 126. Synchronous non-multiplexed NOR/PSRAM read timings. . . . . . . . . . . . . . . . . . . . . . . . 277
Table 127. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Table 128. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Table 129. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Table 130. OCTOSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Table 131. OCTOSPI characteristics in DTR mode (no DQS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Table 132. OCTOSPI characteristics in DTR mode (with DQS)/Octal and HyperBus . . . . . . . . . . . . 285
Table 133. Dynamics characteristics: delay block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Table 134. Dynamics characteristics: SD / eMMC characteristics, VDD=2.7V to 3.6 V . . . . . . . . . . . 289
Table 135. Dynamics characteristics: eMMC characteristics VDD=1.71 V to 1.9 V. . . . . . . . . . . . . . 290
Table 136. UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Table 137. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Table 138. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Table 139. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Table 140. WLCSP - 81 balls, 4.36 x 4.07 mm, 0.4 mm pitch, wafer level chip scale
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Table 141. WLCSP81 recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Table 142. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Table 143. UFBGA132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Table 144. UFBGA132 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 309
Table 145. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Table 146. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Table 147. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
10/323 DS12736 Rev 2
STM32L562xx List of figures
List of figures
Figure 1. STM32L562xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 2. STM32L562xx power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 3. STM32L562xxxxP power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 4. STM32L562xxxxQ power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 5. Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 6. SMPS step down converter power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 7. STM32L562xx clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 8. Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 9. Voltage reference buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 10. STM32L562xx LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 11. STM32L562xxxxP LQFP48 external SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 12. STM32L562xx UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 13. STM32L562xxxxP UFQFPN48 external SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 14. STM32L562xx LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 15. STM32L562xxxxQ LQFP64 SMPS step down converter pinout. . . . . . . . . . . . . . . . . . . . . 82
Figure 16. STM32L562xxxxP LQFP64 external SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 17. STM32L562xxxxQ WLCSP81 SMPS step down converter ballout . . . . . . . . . . . . . . . . . . 83
Figure 18. STM32L562xxxxP WLCSP81 external SMPS ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 19. STM32L562xx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 20. STM32L562xxxxQ LQFP100 SMPS step down converter pinout. . . . . . . . . . . . . . . . . . . . 85
Figure 21. STM32L562xx UFBGA132 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 22. STM32L562xxxxQ UFBGA132 SMPS step down converter ballout. . . . . . . . . . . . . . . . . . 86
Figure 23. STM32L562xx LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 24. STM32L562xxxxQ LQFP144 SMPS step down converter pinout. . . . . . . . . . . . . . . . . . . . 88
Figure 25. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 26. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 27. STM32L552xx and STM32L562xx power supply overview . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 28. STM32L552xxxP and STM32L562xxxP power supply overview . . . . . . . . . . . . . . . . . . . 141
Figure 29. STM32L552xxxQ and STM32L562xxxQ power supply overview. . . . . . . . . . . . . . . . . . . 142
Figure 30. Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 31. External components for SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 32. VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 33. High-speed external clock source AC timing diagram .
Figure 34. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 35. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 36. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Figure 37. HSI16 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 38. Typical current consumption versus MSI frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 39. HSI48 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 40. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Figure 41. I/O AC characteristics definition
Figure 42. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Figure 43. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Figure 44. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Figure 45. 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Figure 46. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Figure 47. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Figure 48. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
. . . . . . . . . . . . . . . . . . . . . . . . . . 199
DS12736 Rev 2 11/323
13
List of figures STM32L562xx
Figure 49. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Figure 50. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Figure 51. USART master mode timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Figure 52. USART slave mode timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Figure 53. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 265
Figure 54. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 267
Figure 55. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 268
Figure 56. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 270
Figure 57. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Figure 58. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Figure 59. Synchronous non-multiplexed NOR/PSRAM read timings. . . . . . . . . . . . . . . . . . . . . . . . 276
Figure 60. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Figure 61. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Figure 62. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Figure 63. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 281
Figure 64. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 281
Figure 65. OCTOSPI timing diagram - SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Figure 66. OCTOSPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Figure 67. OCTOSPI HyperBus clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Figure 68. OCTOSPI HyperBus read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Figure 69. OCTOSPI HyperBus read with double latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Figure 70. OCTOSPI HyperBus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Figure 71. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Figure 72. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Figure 73. DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Figure 74. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 293
Figure 75. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Figure 76. Example of LQFP48 package marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . 295
Figure 77. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Figure 78. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Figure 79. Example of UFQFPN48 package marking (package top view). . . . . . . . . . . . . . . . . . . . . 298
Figure 80. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 299
Figure 81. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package
recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Figure 82. Example of LQFP64 package marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . 301
Figure 83. WLCSP - 81 balls, 4.36 x 4.07 mm, 0.4 mm pitch, wafer level chip scale
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Figure 84. WLCSP - 81 balls, 4.36 x 4.07 mm, 0.4 mm pitch, wafer level chip scale
recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Figure 85. Example of WLCSP81 package marking (package top view . . . . . . . . . . . . . . . . . . . . . . 304
Figure 86. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . 305
Figure 87. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat
recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Figure 88. Example of LQFP100 package marking (package top view) . . . . . . . . . . . . . . . . . . . . . . 307
Figure 89. UFBGA132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Figure 90. UFBGA132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Figure 91. Example of UFBGA132 package marking (package top view) . . . . . . . . . . . . . . . . . . . . 310
12/323 DS12736 Rev 2
STM32L562xx List of figures
Figure 92. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . 311
Figure 93. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package
recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Figure 94. Example of LQFP144 package marking (package top view) . . . . . . . . . . . . . . . . . . . . . . 314
DS12736 Rev 2 13/323
13
Introduction STM32L562xx

1 Introduction

This document provides the ordering information and mechanical device characteristics of
the STM32L562xx microcontrollers.
This document should be read in conjunction with the STM32L552xx and STM32L562xx
reference manual (RM0438).
For information on the Arm
Reference Manual, available from the www.arm.com website.
®(a)
Cortex®-M33 core, refer to the Cortex®-M33 Technical
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
14/323 DS12736 Rev 2
STM32L562xx Description

2 Description

The STM32L562xx devices are an ultra-low-power microcontrollers family (STM32L5
Series) based on the high-performance Arm
at a frequency of up to 110
The Cortex®-M33 core features a single-precision floating-point unit (FPU), which supports
all the Arm
Cortex
®
single-precision data-processing instructions and all the data types. The
®
-M33 core also implements a full set of DSP (digital signal processing) instructions
MHz.
®
Cortex®-M33 32-bit RISC core. They operate
and a memory protection unit (MPU) which enhances the application’s security.
These devices embed high-speed memories (512 Kbytes of Flash memory and 256 Kbytes
of SRAM), a flexible external memory controller (FSMC) for static memories (for devices
with packages of 100 pins and more), an Octo-SPI Flash memories interface (available on
all packages) and an extensive range of enhanced I/Os and peripherals connected to two
APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.
The STM32L5 Series devices offer security foundation compliant with the trusted based
security architecture (TBSA) requirements from Arm. They embed the necessary security
features to implement a secure boot, secure data storage, secure firmware installation and
secure firmware upgrade. Flexible life cycle is managed thanks to multiple levels of readout
protection. Firmware hardware isolation is supported thanks to securable peripherals,
memories and I/Os, and also to the possibility to configure the peripherals and memories as
“privilege”.
The STM32L562xx devices embed several protection mechanisms for embedded Flash
memory and SRAM: readout protection, write protection, secure and hidden protection
areas.
The STM32L562xx devices embed several peripherals reinforcing security:
- One AES coprocessor
- One public key accelerator (PKA), DPA resistant
- One on-the-fly decryption engine for Octo-SPI external memories
- One HASH hardware accelerator
- One true random number generator
The STM32L5 Series devices offer active tamper detection and protection against transient
and environmental perturbation attacks thanks to several internal monitoring which generate
secret data erase in case of attack. This helps to fit the PCI requirements for point of sales
applications. These devices offer two fast 12-bit ADC (5 Msps), two comparators, two
operational amplifiers, two DAC channels, an internal voltage reference buffer, a low-power
RTC, two general-purpose 32-bit timer, two 16-bit PWM timers dedicated to motor control,
seven general-purpose 16-bit timers, and two 16-bit low-power timers. The devices support
four digital filters for external sigma delta modulators (DFSDM). In addition, up to 22
capacitive sensing channels are available.
STM32L5 Series also feature standard and advanced communication interfaces such as:
- Four I2Cs
- Three SPIs
- Three USARTs, two UARTs and one low-power UART
DS12736 Rev 2 15/323
79
Description STM32L562xx
- Two SAIs
- One SDMMC
- One FDCAN
- USB device FS
- USB Type-C / USB power delivery controller
The STM32L562xx devices embed an AES, PKA and OTFDEC hardware accelerator.
The devices operate in the -40 to +85 °C (+105 °C junction) and -40 to +125 °C (+130 °C
junction) temperature ranges from a 1.71 to 3.6
V power supply. A comprehensive set of
power-saving modes allows the design of low-power applications.
Some independent power supplies are supported like an analog independent supply input
for ADC, DAC, OPAMPs and comparators, a 3.3
14 I/Os, which can be supplied independently down to 1.08
V dedicated supply input for USB and up to
V. A VBAT input allows to
backup the RTC and backup the registers.
The STM32L562xx devices offer seven packages from 48-pin to 144-pin.

Table 2. STM32L562xx features and peripheral counts

Peripherals
STM32L562CE/
STM32L562CExxP
Flash memory (Kbyte) 512
SRAM
External memory controller for static memories (FSMC)
OCTOSPI 1
Timers
System (Kbyte) 256 (192+64)
Backup (byte) 128
Advanced control 2 (16-bit)
General purpose
Basic 2 (16-bit)
Low power 3 (16-bit)
SysTick timer 1
Watchdog timers (independent, window)
STM32L562RE/
STM32L562RExxQ
STM32L562RExxP/
No Yes
STM32L562MExxQ
STM32L562MExxP/
5 (16-bit) 2 (32-bit)
2
STM32L562VE/
STM32L562VExxQ
STM32L562QE/
STM32L562QExxP/
STM32L562QExxQ
STM32L562ZE/
STM32L562ZExxQ
16/323 DS12736 Rev 2
STM32L562xx Description
Table 2. STM32L562xx features and peripheral counts (continued)
Peripherals
STM32L562CE/
STM32L562CExxP
STM32L562RE/
STM32L562RExxQ
STM32L562RExxP/
STM32L562MExxQ
STM32L562MExxP/
STM32L562VE/
STM32L562VExxQ
STM32L562QE/
STM32L562QExxQ
STM32L562QExxP/
STM32L562ZE/
SPI 3
I2C 4
(1)
Communication interfaces
USART
/UART UART LPUART
SAI 2
3/2 (2)
2 1
FDCAN 1
USB FS Yes
SDMMC No
Digital filters for sigma­delta modulators
Yes/No/ Yes
Yes (4 filters)
Yes
Number of channels 8
Real time clock (RTC) Yes
Tamper pins 3 4/3 3 5/4 5 8/7
True random number generator Yes
AES Yes
PKA Yes
STM32L562ZExxQ
HASH (SHA-256) Yes
On-the-fly decryption for OCTOSPI 1
OCTOSPI memory encryption 1
GPIOs Wakeup pins Nb of I/Os down to 1.08 V
Capacitive sensing Number of channels
38/36
3 0
52/50/47
4/3/3
0
54/51
3 6
5 10/10/9 10 19/18 22 22/21
12-bit ADC 2
ADC
Number of channels
9
16/16/15 16/15 16/14 16 16/14
12-bit DAC 1
DAC
Number of channels
2
DS12736 Rev 2 17/323
83/79
5/4
0
110/108/105
5
13/
13/10
115 /111
5/4
14/13
79
Description STM32L562xx
Table 2. STM32L562xx features and peripheral counts (continued)
Peripherals
Internal voltage reference buffer
STM32L562CE/
STM32L562CExxP
STM32L562RE/
STM32L562RExxQ
STM32L562RExxP/
STM32L562MExxQ
STM32L562MExxP/
Yes
STM32L562VE/
STM32L562VExxQ
STM32L562QE/
STM32L562QExxQ
STM32L562QExxP/
STM32L562ZE/
Analog comparator 2
Operational amplifiers 2
Max. CPU frequency 110 MHz
Operating voltage 1.71 to 3.6 V
Operating temperature
Package
1. USART3 is not available on STM32L562CExxP devices.
2. For the LQFP100 package, only FSMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select.
UFQFPN48
Ambient operating temperature: -40 to 85 °C / -40 to 125 °C
Junction temperature: -40 to 105 °C / -40 to 130 °C
LQFP48,
LQFP64 WLCSP81 LQFP100
(2)
UFBGA132 LQFP144
STM32L562ZExxQ
18/323 DS12736 Rev 2
STM32L562xx Description
MSv49330V6
USB FS
CH1
CH2
DAC1
Flash up to 512KB
Flexible static memory controller (FSMC): SRAM,
PSRAM, NOR Flash,FRAM, NAND Flash
114 AF
PA[15:0]
3 compl. channels (TIM1_CH[1:3]N),
4 channels (TIM1_CH[1:4]), ETR, BKIN,
BKIN2 as AF
RX, TX, CK,CTS,
RTS as AF
MOSI, MISO,
SCK, NSS as AF
APB260 M Hz
APB1 30MHz
MOSI, MISO, SCK, NSS as AF
OUT1
RTC_TS
OSC32_IN
OSC32_OUT
VDDA, VSSA
VDD, VSS, NRST
smcard irDA
16b
D[7:0], D[3:1]dir CMD, CMDdir,CK, CKin D0dir, D2dir
VBAT = 1.55 to 3.6 V
SCL, SDA, SMBA as AF
JTAG & SW
ARM Cortex-M33 110 MHz TrustZone FPU
NVIC
ETM
MPU
TRACECLK
TRACED[3:0]
CLK, NE[4:1], NL, NBL[1:0], A[25:0], D[15:0], NOE, NWE, NWAIT, NCE, INT as AF
DP
DM
FIFO
@ VDDA
BOR
Supply
supervision
PVD, PVM
Int
reset
XTAL 32 kHz
RTC
FCLK
Standby
interface
IWDG
@VBAT
@ VDD
@VDD
AWU
PCLKx
VDD = 1.71 to 3.6 V
VSS
Voltage regulator LDO and SMPS
3.3 to 1.2 V
VDD
Power management
@ VDD
RTC_TAMP[8:1]
Backup register
AHB bus-matrix
2 channels, 1 compl. channel,
BKIN as AF
TIM2
TIM3
TIM4
TIM5
USART2
USART3
I2C1/SMBUS
SPI1
TIM17
USART1
EXT IT. WKUP
TIM16
TIM8 / PWM
TIM15
SDMMC1
TIM1 / PWM
TIM6
TIM7
WWDG
GPIO PORT H
GPIO PORT F
GPIO PORT G
GPIO PORT D
GPIO PORT E
GPIO PORT B
GPIO PORT C
GPIO PORT A
DMA1
DMA2
APB1 110 MHz (max)
SRAM 192 KB
SRAM 64 KB
NJTRST, JTDI,
JTCK/SWCLK
JTDO/SWD, JTDO
C-BUS
S-BUS
PB[15:0]
PC[15:0]
PD[15:0]
PE[15:0]
PF[15:0]
PG[15:0]
PH[1:0]
16b
16b
16b
16b
3 compl. Channels (TIM1_CH[1:3]N),
4 channels (TIM1_CH[1:4]), ETR, BKIN,
BKIN2 as AF
1 channel, 1 compl. channel,
BKIN as AF
1 channel, 1 compl. channel,
BKIN as AF
OUT2
16b
16b
SCL, SDA, SMBA as AF
SCL, SDA, SMBA as AF
MOSI, MISO, SCK, NSS as AF
RX, TX, CTS, RTS as AF
RX, TX, CTS, RTS as AF
RX, TX, CK, CTS, RTS as AF
RX, TX, CK, CTS, RTS as AF
smcard
irDA
smcard
irDA
32b
16b
16b
32b
4 channels, ETR as AF
4 channels, ETR as AF
4 channels, ETR as AF
4 channels, ETR as AF
AHB/APB1
OSC_IN
OSC_OUT
HCLKx
XTAL OSC
4- 16MHz
16xIN
VREF+
USAR T 2MBps
Temperature sensor
MCLK_A, SD_A, FS_A, SCK_A, EXTCLK
MCLK_B, SD_B, FS_B, SCK_B as AF
SAI1
MCLK_A, SD_A, FS_A, SCK_A, EXTCLK
MCLK_B, SD_B, FS_B, SCK_B as AF
SAI2
SDCKIN[7:0], SDDATIN[7:0],
SDCKOUT,SDTRIG as AF
DFSDM
Touch sensing controller
8 groups of sensing channels as AF
OUT, INN, INP
LPUART1
LPTIM1
LPTIM2
RX, TX, CTS, RTS as AF
IN1, IN2, OUT, ETR as AF
IN1, OUT, ETR as AF
RC HSI
RC LSI
PLL 1&2&3
MSI
Octo SPI1 memory interface
IO[7:0], CLK, NCLK, NCS. DQS
@ VDDUSB
COMP1
INP, INN, OUT
COMP2
INP, INN, OUT
@ VDDA
RTC_OUT
VDDIO, VDDUSB
FIFO
PHY
AHB1 110 MHz
CRC
OUT, INN, INP
I2C2/SMBUS
I2C3/SMBUS
OpAmp1
SPI3
SPI2
UART5
UART4
APB2 110MHz
AHB2 110 MHz
OpAmp2
@VDDA
RNG
AES
VREF Buffer
@ VDDA
@ VDD
HASH
FIFO
TX, RX as AF
FDCAN1
SCL, SDA, SMBA as AF
I2C4/SMBUS
ITF
ADC1
@ VDDA
SYSCFG
Icache 8KB
ADC2
LPTIM3
IN1, OUT, ETR as AF
UCPD1
DP
DM
@ VDDUSB
PHY
CRS
PKA32
DMAMUX1
AHB1 110 MHz
AHB/APB2
32-bits AHB bus
VDD power domain
VDDUSB power domain
VBAT power domain
VDDIO2 power domain
VDDA power domain
OTFDEC
GTZC
Reset
and clock
control
UCPD1

Figure 1. STM32L562xx block diagram

1. AF: alternate function on I/O pins.
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3 Functional overview

3.1 Arm® Cortex®-M33 core with TrustZone® and FPU

The Cortex®-M33 with TrustZone and FPU is a highly energy efficient processor designed for microcontrollers and deeply embedded applications, especially those requiring efficient security.
The Cortex®-M33 processor delivers a high computational performance with low-power consumption and an advanced response to interrupts. it features:
Arm® TrustZone® technology, using the ARMv8-M main extension supporting secure and non-secure states
Memory protection units (MPUs), 8 regions for secure and 8 regions for non secure
Configurable secure attribute unit (SAU) supporting up to 8 memory regions
Floating-point arithmetic functionality with support for single precision arithmetic
The processor supports a set of DSP instructions that allows an efficient signal processing and a complex algorithm execution.
The Cortex®-M33 processor supports the following bus interfaces:
System AHB bus: The System AHB (S-AHB) bus interface is used for any instruction fetch and data access to the memory-mapped SRAM, peripheral, external RAM and external device, or Vendor_SYS regions of the ARMv8-M memory map.
Code AHB bus The Code AHB (C-AHB) bus interface is used for any instruction fetch and data access to the code region of the ARMv8-M memory map.
Figure 1 shows the general block diagram of the STM32L562xx family devices.

3.2 Art Accelerator – instruction cache (ICACHE)

The instruction cache (ICACHE) is introduced on C-AHB code bus of Cortex®-M33 processor to improve performance when fetching instruction (or data) from both internal and external memories.
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STM32L562xx Functional overview
ICACHE offers the following features:
Multi-bus interface: – slave port receiving the memory requests from the Cortex
®
-M33 C-AHB code
execution port – master1 port performing refill requests to internal memories (FLASH and SRAMs) – master2 port performing refill requests to external memories (external
FLASH/RAMs through Octo-SPI/FMC interfaces) – a second slave port dedicated to ICACHE registers access.
Close to zero wait states instructions/data access performance: – 0 wait-state on cache hit – hit-under-miss capability, allowing to serve new processor requests while a line
refill (due to a previous cache miss) is still ongoing – critical-word-first refill policy, minimizing processor stalls on cache miss – hit ratio improved by 2-ways set-associative architecture and pLRU-t replacement
policy (pseudo-least-recently-used, based on binary tree), algorithm with best
complexity/performance balance – dual master ports allowing to decouple internal and external memory traffics, on
Fast and Slow buses, respectively; also minimizing impact on interrupt latency – optimal cache line refill thanks to AHB burst transactions (of the cache line size). – performance monitoring by means of a hit counter and a miss counter.
Extension of cacheable region beyond Code memory space, by means of address remapping logic that allows to define up to 4 cacheable external regions
Power consumption reduced intrinsically (most accesses to cache memory rather to bigger main memories); even improved by configuring ICACHE as direct mapped (rather than the default 2-ways set-associative mode)
TrustZone
®
security support
Maintenance operation for software management of cache coherency
Error management: detection of unexpected cacheable write access, with optional
interrupt raising.

3.3 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to the memory and to prevent one task to accidentally corrupt the memory or the resources used by any other active task. This memory area is organized into up to 8 regions for secure and 8 regions for non secure state.
The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (real­time operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
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Functional overview STM32L562xx

3.4 Embedded Flash memory

The devices feature 512 Kbytes of embedded Flash memory which is available for storing programs and data.
The Flash interface features:
Single or dual bank operating modes
Read-while-write (RWW) in dual bank mode
This feature allows to perform a read operation from one bank while an erase or program operation is performed to the other bank. The dual bank boot is also supported. Each bank contains 128 pages of 2 or 4 memory also embeds 512 bytes OTP (one-time programmable) for user data.
Flexible protections can be configured thanks to the option bytes:
Readout protection (RDP) to protect the whole memory. Four levels of protection are
available: – Level 0: no readout protection – Level 0.5: available only when TrustZone is enabled
All read/write operations (if no write protection is set) from/to the non-secure Flash memory are possible. The Debug access to secure area is prohibited. Debug access to non-secure area remains possible.
– Level 1: memory readout protection; the Flash memory cannot be read from or written
to if either the debug features are connected or the boot in RAM or bootloader are selected. If TrustZone is enabled, the non-secure debug is possible and the boot in SRAM is not possible.
– Level 2: chip readout protection; the debug features (Cortex
wire), the boot in RAM and the bootloader selection are disabled (JTAG fuse). This selection is irreversible.
Write protection (WRP): the protected area is protected against erasing and programming:
In single bank mode, four areas can be selected with 4-Kbyte granularity. – In dual bank mode, two areas per bank can be selected with 2-Kbyte granularity.
Kbytes (depending on the read access width). The Flash
®
-M33 JTAG and serial
The whole non-volatile memory embeds the error correction code (ECC) feature supporting:
Single error detection and correction
Double error detection
The address of the ECC fail can be read in the ECC register.
TrustZone security
When the TrustZone security is enabled, the whole Flash is secure after reset and the following protections are available:
Non-volatile watermark-based secure Flash area: the secure area can be accessed only in secure mode.
In single bank mode, four areas can be selected with a page granularity. – In dual bank mode, one area per bank can be selected with a page granularity.
Secure hidden protection area: it is part of the Flash secure area and it can be protected to deny an access to this area by any data read, write and instruction fetch.
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For example, a software code in the secure Flash memory hidden protection area can be executed only once and deny any further access to this area until next system reset.
Volatile block-based secure Flash area. In a block-based secure area, each page can be programmed on-the-fly as secure or non-secure.

3.5 Embedded SRAM

The devices feature 256 Kbytes of embedded SRAM. This SRAM is split into three blocks:
192 Kbytes mapped at address 0x2000 0000 (SRAM1).
64 Kbytes located at address 0x0A03 0000 with hardware parity check (SRAM2).
This memory is also mapped at address 0x2003 0000 offering a contiguous address space with the SRAM1. This block is accessed through the C-bus for maximum performance. Either 64 Kbytes or upper 4 Kbytes of SRAM2 can be retained in Standby mode. The SRAM2 can be write-protected with 1 Kbyte granularity.
The memory can be accessed in read/write at CPU clock speed with 0 wait states.
TrustZone security
When the TrustZone security is enabled, all SRAMs are secure after reset. The SRAM can be programmed as non-secure by block based using the MPCBB (memory protection controller block based) in GTZC controller. The granularity of SRAM secure block based is a page of 256 bytes.

3.6 Boot modes

At startup, a BOOT0 pin, nBOOT0 and NSBOOTADDx[24:0] / SECBOOTADD0[24:0] option bytes are used to select the boot memory address which includes:
Boot from any address in user Flash
Boot from system memory bootloader
Boot from any address in embedded SRAM
Boot from Root Security service (RSS)
The BOOT0 value may come from the PH3-BOOT0 pin or from an option bit depending on the value of a user option bit to free the GPIO pad if needed.
The boot loader is located in the system memory. It is used to reprogram the Flash memory by using USART, I2C, SPI, FDCAN or USB FS in device mode through the DFU (device firmware upgrade).
The bootloader is available on all devices. Refer to the application note STM32 microcontroller system memory boot mode (AN2606) for more details.
The root secure services (RSS) are embedded in a Flash memory area named secure information block, programmed during ST production.
The RSS enables for example the secure firmware installation (SFI) thanks to the RSS extension firmware (RSSe SFI).
This feature allows the customers to protect the confidentiality of the firmware to be provisioned into the STM32 device when the production is subcontracted to a third party.
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Functional overview STM32L562xx
The RSS is available on all devices, after enabling the TrustZone through the TZEN option bit.
Refer to the application note Overview secure firmware install (SFI) (AN4992) for more details.
Refer to Tab le 3 and Tab le 4 for boot modes when TrustZone is disabled and enabled respectively.

Table 3. Boot modes when TrustZone is disabled (TZEN=0)

nBOOT0
FLASH_
OPTR[27]
BOOT0
pin PH3
nSWBOOT0
FLASH_
OPTR[26]
Boot address option-
bytes selection
- 0 1 NSBOOTADD0[24:0]
- 1 1 NSBOOTADD1[24:0]
1 - 0 NSBOOTADD0[24:0]
0 - 0 NSBOOTADD1[24:0]
When TrustZone is enabled by setting the TZEN option bit, the boot space must be in secure area. The SECBOOTADD0[24:0] option bytes are used to select the boot secure memory address.
A unique boot entry option can be selected by setting the BOOT_LOCK option bit, allowing to boot always at the address selected by SECBOOTADD0[24:0] option bytes. All other boot options are ignored.
Boot area
Boot address defined by user option bytes NSBOOTADD0[24:0]
Boot address defined by user option bytes NSBOOTADD1[24:0]
Boot address defined by user option bytes NSBOOTADD0[24:0]
Boot address defined by user option bytes NSBOOTADD1[24:0]
ST programmed
default value
Flash: 0x0800 0000
System bootloader: 0x0BF9 0000
Flash: 0x0800 0000
System bootloader: 0x0BF9 0000
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STM32L562xx Functional overview

Table 4. Boot modes when TrustZone is enabled (TZEN=1)

BOOT_
LOCK
nBOOT0
FLASH_
OPTR[27]
BOOT0
PH3
pin
nSWBOOT0
FLASH_
OPTR[26]
RSS
command
-0 1 0
- 1 1 0 N/A RSS: 0x0FF8 0000
0
1- 0 0
0- 0 0 N/A
-- -
0N/A
1- - - -
Boot address
option-bytes
selection
SECBOOTAD
D0[24:0]
SECBOOTAD
D0[24:0]
SECBOOTAD
D0[24:0]
Boot area
Secure boot address defined by user option bytes
SECBOOTADD0[24:0]
Secure boot address defined by user option bytes SECBOOTADD0[24:0]
RSS: RSS: 0x0FF8 0000
RSS: RSS: 0x0FF8 0000
Secure boot address defined by user option bytes SECBOOTADD0[24:0]
ST programmed default value
Flash: 0x0C00 0000
RSS: 0x0FF8 0000
Flash: 0x0C00 0000
RSS: 0x0FF8 0000
RSS: 0x0FF8 0000
Flash: 0x0C00 0000
The boot address option bytes enables the possibility to program any boot memory address. However, the allowed address space depends on Flash read protection RDP level.
If the programmed boot memory address is out of the allowed memory mapped area when RDP level is 0.5 or more, the default boot fetch address is forced to:
0x0800 0000 (when TZEN = 0)
RSS (when TZEN = 1)
Refer to Tab le 5.
RDP TZEN = 1 TZEN = 0
0 Any boot address Any boot address

Table 5. Boot space versus RDP protection

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Table 5. Boot space versus RDP protection (continued)
RDP TZEN = 1 TZEN = 0
0.5
1 Any boot address
Boot address only in: – RSS – or secure Flash: 0x0C00 0000 -
0x0C07 FFFF
2
Otherwise boot address forced to RSS
N/A
If boot is configured for NSBOOTADD0 and NSBOOTADD0 in the range 0x0800 0000 ­0x0807 FFFF: boot at the address stored in NSBOOTADD0
If boot is configured for NSBOOTADD1 and NSBOOTADD1 in the range 0x0800 0000 ­0x0807 FFFF: boot at the address stored in NSBOOTADD1
Otherwise boot address is forced at 0x0800 0000

3.7 Global TrustZone controller (GTZC)

The GTZC includes three different sub-blocks:
TZSC: TrustZone® security controller This sub-block defines the secure/privilege state of slave/master peripherals. It also controls the non-secure area size for the watermark memory peripheral controller (MPCWM). The TZSC block informs some peripherals (such as RCC or GPIOs) about the secure status of each securable peripheral, by sharing with RCC and I/O logic.
1. MPCBB: block-based memory protection controller This sub-block controls secure states of all blocks (256-byte pages) of the associated SRAM.
2. TZIC: TrustZone illegal access controller This sub-block gathers all illegal access events in the system and generates a secure interrupt towards NVIC.
These sub-blocks are used to configure TrustZone and privileged attributes within the full system.
The GTZC main features are:
3 independent 32-bit AHB interface for TZSC, MPCBB and TZIC
MPCBB and TZIC accessible only with secure transactions
Secure and non-secure access supported for priv/non-priv part of TZSC
Register set to define security settings:
Secure blocks for internal SRAM – Non-secure regions for external memories – Secure/privilege access mode for securable and TZ-aware peripherals
Secure/privilege access mode for securable legacy masters.

3.8 TrustZone security architecture

The security architecture is based on Arm® TrustZone® with the ARMv8-M Main Extension.
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The TrustZone security is activated by the TZEN option bit in the FLASH_OPTR register. When the TrustZone is enabled, the SAU (security attribution unit) and IDAU
(implementation defined attribution unit) defines the access permissions based on secure and non-secure state.
SAU: Up to 8 SAU configurable regions are available for security attribution.
IDAU: It provides a first memory partition as non-secure or non-secure callable
attributes. It is then combined with the results from the SAU security attribution and the higher security state is selected.
Based on IDAU security attribution, the Flash, system SRAMs and peripherals memory space is aliased twice for secure and non-secure state. However, the external memories space is not aliased.
Tab le 6 shows an example of typical SAU regions configuration based on IDAU regions.
The user can split and choose the secure, non-secure or NSC regions for external memories as needed.

Table 6. Example of memory map security attribution vs SAU configuration regions

(1) (2)
Region
description
Code - external memories
Code - Flash and SRAM
Code - external memories
SRAM
Peripherals
External memories
1. NSC = non-secure callable.
2. Different colors highlights the different configurations
Pink: Non-secure
Green: NSC (non-secure callable) Lighter green: Secure or non-secure or NSC
Address range
0x0000_0000
0x07FF_FFFF
0x0800_0000
0x0BFF_FFFF
0x0C00_0000
0x0FFF_FFFF
0x1000_0000
0x17FF_FFFF
0x1800_0000
0x1FFF_FFFF
0x2000_0000
0x2FFF_FFFF
0x3000_0000
0x3FFF_FFFF
0x4000_0000
0x4FFF_FFFF
0x5000_0000
0x5FFF_FFFF
0x6000_0000
0xDFFF_FFFF
IDAU security
attribution
Non-secure
Non-secure Non-secure Non-secure
NSC Secure or NSC Secure or NSC
Non-secure
Non-secure
NSC Secure or NSC Secure or NSC
Non-secure Non-secure Non-secure
NSC Secure or NSC Secure or NSC
Non-secure
SAU security
attribution typical
configuration
Secure or non-
secure or NSC
Non-secure
Secure or non-
secure or NSC
Final security
attribution
Secure or non-
secure or NSC
Secure or non-
secure or NSC
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Functional overview STM32L562xx

3.8.1 TrustZone peripheral classification

When the TrustZone security is active, a peripheral can be either Securable or TrustZone­aware type as follows:
Securable: a peripheral is protected by an AHB/APB firewall gate that is controlled from TZSC controller to define security properties.
TrustZone-aware: a peripheral connected directly to AHB or APB bus and is implementing a specific TrustZone behavior such as a subset of registers being secure.
The tables below summarize the list of Securable and TrustZone aware peripherals within the system.
Table 7. Securable peripherals by TZSC
Bus Peripheral
AHB3
AHB 2
AHB1
APB2
OCTOSPI1 registers
FMC registers
SDMMC1
RNG
HASH
AES
ADC
ICACHE registers
TSC
CRC
DFSDM1
SAI2
SAI1
TIM17
TIM16
TIM15
USART1
TIM8
SPI1
TIM1
COMP
VREFBUF
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STM32L562xx Functional overview
Table 7. Securable peripherals by TZSC (continued)
Bus Peripheral
UCPD1
USB FS
FDCAN1
LPTIM3
LPTIM2
I2C4
LPUART1
LPTIM1
OPAMP
DAC1
CRS
I2C3
I2C2
APB1
I2C1
UART5
UART4
USART3
USART2
SPI3
SPI2
IWDG
WWDG
TIM7
TIM6
TIM5
TIM4
TIM3
TIM2
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Table 8. TrustZone-aware peripherals
Bus Peripheral
GPIOH
GPIOG
GPIOF
AHB2
AHB2 OTFDEC1
AHB1
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
MPCBB2
MPCBB1
MPCWM2
MPCWM1
TZIC
TZSC
EXTI
Flash memory
RCC
DMAMUX1
DMA2
DMA1
APB2 SYSCFG
APB1
PWR
RTC
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