ST MICROELECTRONICS STM32L562ZET6Q Datasheet

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STM32L562xx

UFQFPN48 (7 x 7 mm)

UFBGA132 (7 x 7 mm)

WLCSP81 (4.36 x 4.07 mm)

(*): Silhouette shown above.

LQFP48 (7 x 7 mm)

LQFP64 (10 x 10 mm

)

LQFP100

(*)

(14 x14 mm)

LQFP144 (20 x 20mm)

FBGA

Ultra-low-power Arm® Cortex®-M33 32-bit MCU+TrustZone®+FPU,

165DMIPS, up to 512KB Flash, 256KB SRAM, SMPS, AES+PKA

Datasheet - production data

Features

Ultra-low-power with FlexPowerControl

• 1.71 V to 3.6 V power supply

• -40 °C to 85/125 °C temperature range

• Batch acquisition mode (BAM)

• 187 nA in VBAT mode: supply for RTC and

32x32-bit backup registers

• 17 nA Shutdown mode (5 wakeup pins)

• 108 nA Standby mode (5 wakeup pins)

• 222 nA Standby mode with RTC

• 3.16 μA Stop 2 with RTC

• 106 μA/MHz Run mode (LDO mode)

• 62 μA/MHz Run mode @ 3 V

(SMPS step-down converter mode)

• 5 µs wakeup from Stop mode

• Brownout reset (BOR) in all modes except

Shutdown

Core

Memories

• Up to 512-Kbyte Flash, two banks read-whilewrite

• 256 Kbytes of SRAM including 64 Kbytes with hardware parity check

• External memory interface supporting SRAM, PSRAM, NOR, NAND and FRAM memories

• OCTOSPI memory interface

• Arm® 32-bit Cortex®-M33 CPU with

TrustZone

ART Accelerator

• 8-Kbyte instruction cache allowing 0-wait-state execution from Flash memory and external memories; frequency up to 110 MHz, MPU, 165 DMIPS and DSP instructions

Performance benckmark

• 1.5 DMIPS/MHz (Drystone 2.1)

• 442 CoreMark

Energy benchmark

• 370 ULPMark-CP® score

• 54 ULPMark-PP

• 27400 SecureMark-TLS

February 2020 DS12736 Rev 2 1/323

This is information on a product in full production.

and FPU

(4.02 CoreMark®/MHz)

score

Security

• Arm® TrustZone® and securable I/Os, memories and peripherals

• Flexible life cycle scheme with RDP (readout protection)

• Root of trust thanks to unique boot entry and hide protection area (HDP)

• SFI (secure firmware installation) thanks to embedded RSS (root secure services)

• Secure firmware upgrade support with TF-M

• AES coprocessor

• Public key accelerator

• On-the-fly decryption of Octo-SPI external

memories

• HASH hardware accelerator

www.st.com

STM32L562xx

• Active tamper and protection against temperature, voltage and frequency attacks

• True random number generator NIST SP80090B compliant

• 96-bit unique ID

• 512-byte OTP (one-time programmable) for

user data

General-purpose input/outputs

• Up to 114 fast I/Os with interrupt capability most 5 V-tolerant and up to 14 I/Os with independent supply down to 1.08 V

Power management

• Embedded regulator (LDO) with three configurable range output to supply the digital circuitry

• Embedded SMPS step-down converter

• External SMPS support

Clock management

• 4 to 48 MHz crystal oscillator

• 32 kHz crystal oscillator for RTC (LSE)

• Internal 16 MHz factory-trimmed RC (±1%)

• Internal low-power 32 kHz RC (±5%)

• Internal multispeed 100 kHz to 48 MHz

oscillator, auto-trimmed by LSE (better than ±0.25% accuracy)

• Internal 48 MHz with clock recovery

• 3 PLLs for system clock, USB, audio, ADC

Up to 19 communication peripherals

• 1x USB Type-C™/ USB power delivery controller

• 1x USB 2.0 full-speed crystal less solution, LPM and BCD

• 2x SAIs (serial audio interface)

• 4x I2C FM+(1 Mbit/s), SMBus/PMBus™

• 6x USARTs (ISO 7816, LIN, IrDA, modem)

• 3x SPIs (7x SPIs with USART and OCTOSPI in

SPI mode)

• 1x FDCAN controller

• 1x SDMMC interface

2 DMA controllers

• 14 DMA channels

Up to 22 capacitive sensing channels

• Support touch key, linear and rotary touch sensors

Rich analog peripherals (independent supply)

• 2x 12-bit ADC 5 Msps, up to 16-bit with hardware oversampling, 200 µA/Msps

• 2x 12-bit DAC outputs, low-power sample and hold

• 2x operational amplifiers with built-in PGA

• 2x ultra-low-power comparators

• 4x digital filters for sigma delta modulator

Up to 16 timers and 2 watchdogs

• 16x timers: 2 x 16-bit advanced motor-control, 2 x 32-bit and 5 x 16-bit general purpose, 2x 16-bit basic, 3x low-power 16-bit timers (available in Stop mode), 2x watchdogs, 2x SysTick timer

• RTC with hardware calendar, alarms and calibration

Table 1. Device summary

Reference Part numbers

STM32L562xx

2/323 DS12736 Rev 2

STM32L562CE, STM32L562ME, STM32L562QE, STM32L562RE, STM32L562VE, STM32L562ZE

CRC calculation unit

Debug

• Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell™ (ETM)

STM32L562xx Contents

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.1 Arm® Cortex®-M33 core with TrustZone® and FPU . . . . . . . . . . . . . . . . . 20

3.2 Art Accelerator – instruction cache (ICACHE) . . . . . . . . . . . . . . . . . . . . . 20

3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.6 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.7 Global TrustZone controller (GTZC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.8 TrustZone security architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.8.1 TrustZone peripheral classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.9 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.9.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.9.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.9.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.9.4 SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.9.5 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.9.6 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.9.7 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.9.8 PWR TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.10 Peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.11 Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.12 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.13 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.14 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.15 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.16 DMA request router (DMAMUX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.17 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.17.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 57

DS12736 Rev 2 3/323

Contents STM32L562xx

3.17.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 57

3.18 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 58

3.19 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 58

3.20 Octo-SPI interface (OCTOSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.21 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

3.21.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

3.21.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 62

3.21.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

3.22 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

3.23 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

3.24 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

3.25 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

3.26 Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 64

3.27 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

3.28 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

3.29 Advanced encryption standard hardware accelerator (AES) . . . . . . . . . . 66

3.30 HASH hardware accelerator (HASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3.31 Public key accelerator PKA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3.32 On-the-fly decryption engine (OTFDEC) . . . . . . . . . . . . . . . . . . . . . . . . . 68

3.33 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

3.33.1 Advanced-control timer (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . 69

3.33.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16,

TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

3.33.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

3.33.4 Low-power timers (LPTIM1, LPTIM2 and LPTIM3) . . . . . . . . . . . . . . . . 70

3.33.5 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

3.33.6 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

3.33.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

3.34 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

3.35 Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

3.36 Inter-integrated circuit interface (I

C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

3.37 Universal synchronous/asynchronous receiver transmitter (USART) . . . 75

3.38 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 76

3.39 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

3.40 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

4/323 DS12736 Rev 2

STM32L562xx Contents

3.41 Secure digital input/output and MultiMediaCards Interface (SDMMC) . . . 77

3.42 Controller area network (FDCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

3.43 Universal serial bus (USB FS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

3.44 USB Type-C™ / USB Power Delivery controller (UCPD) . . . . . . . . . . . . . 78

3.45 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

3.45.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 79

3.45.2 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 143

5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

5.3.2 SMPS step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

5.3.3 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 148

5.3.4 Embedded reset and power control block characteristics . . . . . . . . . . 148

5.3.5 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

5.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

5.3.7 Wakeup time from low-power modes and voltage scaling

transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

5.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 199

5.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 204

5.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

5.3.11 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

5.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

5.3.13 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

5.3.14 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

5.3.15 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

DS12736 Rev 2 5/323

Contents STM32L562xx

5.3.16 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

5.3.17 Extended interrupt and event controller input (EXTI) characteristics . . 223

5.3.18 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

5.3.19 Analog-to-digital converter characteristics . . . . . . . . . . . . . . . . . . . . . . 225

5.3.20 Digital-to-Analog converter characteristics . . . . . . . . . . . . . . . . . . . . . 238

5.3.21 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 243

5.3.22 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

5.3.23 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 246

5.3.24 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

5.3.25 V

5.3.26 Temperature and VDD thresholds monitoring . . . . . . . . . . . . . . . . . . . 251

5.3.27 DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

5.3.28 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

5.3.29 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 255

5.3.30 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

5.3.31 OCTOSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

5.3.32 SD/SDIO/MMC card host interfaces (SDMMC) . . . . . . . . . . . . . . . . . . 289

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

BAT

5.3.33 UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

6.1 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

6.2 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

6.3 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

6.4 WLCSP81 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

6.5 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

6.6 UFBGA132 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

6.7 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311

6.8 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

6.8.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316

6.8.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 316

7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

6/323 DS12736 Rev 2

STM32L562xx List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2. STM32L562xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 3. Boot modes when TrustZone is disabled (TZEN=0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 4. Boot modes when TrustZone is enabled (TZEN=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 5. Boot space versus RDP protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 6. Example of memory map security attribution vs SAU configuration regions . . . . . . . . . . . 27

Table 7. Securable peripherals by TZSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 8. TrustZone-aware peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 9. SMPS external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 10. STM32L562xx modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 11. Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 12. STM32L562xx peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 13. DMA1 and DMA2 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 14. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 15. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 16. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 17. I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 18. USART/UART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 19. SAI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 20. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 21. STM32L562xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 22. Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Table 23. Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Table 24. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Table 25. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Table 26. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Table 27. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Table 28. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Table 29. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 148

Table 30. Embedded internal voltage reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Table 31. Current consumption in Run and Low-power run modes,code with data processing

running from Flash in single Bank, ICACHE ON in 2-way . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 32. Current consumption in Run and Low-power run modes,cod

running from Flash in single Bank, ICACHE ON in 1-way . . . . . . . . . . . . . . . . . . . . . . . . 154

Table 33. Current consumption in Run and Low-power run modes, code with data processing

running from Flash in single Bank, ICACHE Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Table 34. Current consumption in Run and Low-power run modes, code with data processing

running from Flash in single bank, ICACHE ON in 2-way and power

supplied by internal SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Table 35. Current consumption in Run and Low-power run modes, code with data processing

running from Flash in single bank, ICACHE ON in 1-way and power

supplied by internal SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Table 36. Current consumption in Run and Low-power run modes, code with data processing

running from Flash in single bank, ICACHE Disabled and power

supplied by internal SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Table 37. Current consumption in Run and Low-power run modes, code with data processing

running from Flash in dual bank, ICACHE ON in 2-way . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Table 38. Current consumption in Run and Low-power run modes, code with data processing

e with data processing

DS12736 Rev 2 7/323

List of tables STM32L562xx

running from Flash in dual bank, ICACHE ON in 1-way . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Table 39. Current consumption in Run and Low-power run modes, code with data processing

running from Flash in dual bank, ICACHE Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Table 40. Current consumption in Run and Low-power run modes, code with data processing

running from Flash in dual bank, ICACHE ON in 2-way and power

supplied by internal SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Table 41. Current consumption in Run and Low-power run modes, code with data processing

running from Flash in dual bank, ICACHE ON in 1-way and power

supplied by internal SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Table 42. Current consumption in Run and Low-power run modes, code with data processing

running from Flash in dual bank, ICACHE Disabled and power

supplied by internal SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Table 43. Current consumption in Run and Low-power run modes,

code with data processing running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Table 44. Current consumption in Run and Low-power run modes,

code with data processing running from SRAM1 and

power supplied by internal SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Table 45. Current consumption in Run and Low-power run modes,

code with data processing running from SRAM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Table 46. Current consumption in Run and Low-power run modes,

code with data processing running from SRAM2 and

power supplied by internal SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Table 47. Typical current consumption in Run and Low-power run modes,

with different codes running from Flash, ICACHE ON (2-way). . . . . . . . . . . . . . . . . . . . . 169

Table 48. Typical current consumption in Run and Low-power run modes with SMPS,

with different codes running from Flash, ICACHE ON (2-way). . . . . . . . . . . . . . . . . . . . . 170

Table 49. Typical current consumption in Run and Low-power run modes,

with different codes running from Flash, ICACHE ON (1-way). . . . . . . . . . . . . . . . . . . . . 171

Table 50. Typical current consumption in Run and Low-power run modes with SMPS,

with different codes running from Flash, ICACHE ON (1-way). . . . . . . . . . . . . . . . . . . . . 172

Table 51. Typical current consumption in Run and Low-power run modes,

with different codes running from Flash, ICACHE disabled . . . . . . . . . . . . . . . . . . . . . . . 173

Table 52. Typical current consumption in Run and Low-power run modes with internal SMPS,

with different codes running from Flash, ICACHE disabled . . . . . . . . . . . . . . . . . . . . . . . 174

Table 53. Typical current consumption in Run and Low-power run modes,

with different codes running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Table 54. Typical current consumption in Run and Low-power run modes with internal SMPS,

with different codes running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Table 55. Typical current consumption in Run and Low-power run modes,

with different codes running from SRAM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Table 56. Typical current consumption in Run and Low-power run modes with internal SMPS,

with different codes running from SRAM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Table 57. Current consumption in Sleep and Low-power sleep mode, Flash ON . . . . . . . . . . . . . . 179

Table 58. Current consumption in Low-power sleep mode, Flash in power-down . . . . . . . . . . . . . . 180

Table 59. Current consumption in Sleep and Low-power sleep mode,

Flash ON and power supplied by internal SMPS step down converter . . . . . . . . . . . . . . 181

Table 60. Current consumption in Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Table 61. Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Table 62. Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Table 63. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Table 64. Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Table 65. Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

8/323 DS12736 Rev 2

STM32L562xx List of tables

Table 66. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Table 67. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Table 68. Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Table 69. Wakeup time using USART/LPUART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Table 70. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

Table 71. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Table 72. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Table 73. LSE oscillator characteristics (f

= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

LSE

Table 74. HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Table 75.

MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206

Table 76. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Table 77. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Table 78. PLL, PLLSAI1, PLLSAI2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Table 79. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Table 80. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Table 81. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Table 82. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Table 83. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Table 84. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

Table 85. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

Table 86. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Table 87. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

Table 88. I/O AC characteristics (All I/Os except FT_c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

Table 89. FT_c I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

Table 90. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

Table 91. EXTI input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

Table 92. Analog switches booster characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Table 93. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Table 94. Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

Table 95. ADC accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

Table 96. ADC accuracy - limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

Table 97. ADC accuracy - limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

Table 98. ADC accuracy - limited test conditions 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Table 99. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

Table 100. DAC accuracy ranges 0/1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

Table 101. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

Table 102. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Table 103. OPAMP characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Table 104. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

Table 105. V Table 106. V

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

BAT

charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

BAT

Table 107. Temp and VDD monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

Table 108. DFSDM measured timing 1.71 to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

Table 109. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

Table 110. IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

Table 111. WWDG min/max timeout value at 110 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

Table 112. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Table 113. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

Table 114. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

Table 115. USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

Table 116. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 266

Table 117. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings. . . . . . . . . . . 266

DS12736 Rev 2 9/323

List of tables STM32L562xx

Table 118. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 267

Table 119. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 268

Table 120. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 269

Table 121. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 269

Table 122. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 271

Table 123. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 271

Table 124. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

Table 125. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

Table 126. Synchronous non-multiplexed NOR/PSRAM read timings. . . . . . . . . . . . . . . . . . . . . . . . 277

Table 127. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

Table 128. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

Table 129. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 282

Table 130. OCTOSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

Table 131. OCTOSPI characteristics in DTR mode (no DQS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

Table 132. OCTOSPI characteristics in DTR mode (with DQS)/Octal and HyperBus . . . . . . . . . . . . 285

Table 133. Dynamics characteristics: delay block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

Table 134. Dynamics characteristics: SD / eMMC characteristics, VDD=2.7V to 3.6 V . . . . . . . . . . . 289

Table 135. Dynamics characteristics: eMMC characteristics VDD=1.71 V to 1.9 V. . . . . . . . . . . . . . 290

Table 136. UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

Table 137. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

Table 138. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

Table 139. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

Table 140. WLCSP - 81 balls, 4.36 x 4.07 mm, 0.4 mm pitch, wafer level chip scale

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

Table 141. WLCSP81 recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

Table 142. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

Table 143. UFBGA132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

Table 144. UFBGA132 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 309

Table 145. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

Table 146. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

Table 147. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

10/323 DS12736 Rev 2

STM32L562xx List of figures

List of figures

Figure 1. STM32L562xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 2. STM32L562xx power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 3. STM32L562xxxxP power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 4. STM32L562xxxxQ power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 5. Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 6. SMPS step down converter power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 7. STM32L562xx clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 8. Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 9. Voltage reference buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 10. STM32L562xx LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 11. STM32L562xxxxP LQFP48 external SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 12. STM32L562xx UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 13. STM32L562xxxxP UFQFPN48 external SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 14. STM32L562xx LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 15. STM32L562xxxxQ LQFP64 SMPS step down converter pinout. . . . . . . . . . . . . . . . . . . . . 82

Figure 16. STM32L562xxxxP LQFP64 external SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 17. STM32L562xxxxQ WLCSP81 SMPS step down converter ballout . . . . . . . . . . . . . . . . . . 83

Figure 18. STM32L562xxxxP WLCSP81 external SMPS ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 19. STM32L562xx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 20. STM32L562xxxxQ LQFP100 SMPS step down converter pinout. . . . . . . . . . . . . . . . . . . . 85

Figure 21. STM32L562xx UFBGA132 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 22. STM32L562xxxxQ UFBGA132 SMPS step down converter ballout. . . . . . . . . . . . . . . . . . 86

Figure 23. STM32L562xx LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 24. STM32L562xxxxQ LQFP144 SMPS step down converter pinout. . . . . . . . . . . . . . . . . . . . 88

Figure 25. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Figure 26. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Figure 27. STM32L552xx and STM32L562xx power supply overview . . . . . . . . . . . . . . . . . . . . . . . 140

Figure 28. STM32L552xxxP and STM32L562xxxP power supply overview . . . . . . . . . . . . . . . . . . . 141

Figure 29. STM32L552xxxQ and STM32L562xxxQ power supply overview. . . . . . . . . . . . . . . . . . . 142

Figure 30. Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Figure 31. External components for SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Figure 32. VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Figure 33. High-speed external clock source AC timing diagram .

Figure 34. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Figure 35. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Figure 36. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Figure 37. HSI16 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Figure 38. Typical current consumption versus MSI frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

Figure 39. HSI48 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Figure 40. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Figure 41. I/O AC characteristics definition

Figure 42. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

Figure 43. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

Figure 44. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

Figure 45. 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

Figure 46. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

Figure 47. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

Figure 48. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

. . . . . . . . . . . . . . . . . . . . . . . . . . 199

DS12736 Rev 2 11/323

List of figures STM32L562xx

Figure 49. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

Figure 50. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

Figure 51. USART master mode timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

Figure 52. USART slave mode timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

Figure 53. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 265

Figure 54. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 267

Figure 55. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 268

Figure 56. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 270

Figure 57. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

Figure 58. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

Figure 59. Synchronous non-multiplexed NOR/PSRAM read timings. . . . . . . . . . . . . . . . . . . . . . . . 276

Figure 60. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

Figure 61. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

Figure 62. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

Figure 63. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 281

Figure 64. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 281

Figure 65. OCTOSPI timing diagram - SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

Figure 66. OCTOSPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

Figure 67. OCTOSPI HyperBus clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

Figure 68. OCTOSPI HyperBus read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

Figure 69. OCTOSPI HyperBus read with double latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

Figure 70. OCTOSPI HyperBus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

Figure 71. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

Figure 72. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

Figure 73. DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

Figure 74. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 293

Figure 75. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package

recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294

Figure 76. Example of LQFP48 package marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . 295

Figure 77. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat

package outline. . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

Figure 78. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat

package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

Figure 79. Example of UFQFPN48 package marking (package top view). . . . . . . . . . . . . . . . . . . . . 298

Figure 80. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 299

Figure 81. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package

recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

Figure 82. Example of LQFP64 package marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . 301

Figure 83. WLCSP - 81 balls, 4.36 x 4.07 mm, 0.4 mm pitch, wafer level chip scale

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

Figure 84. WLCSP - 81 balls, 4.36 x 4.07 mm, 0.4 mm pitch, wafer level chip scale

recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

Figure 85. Example of WLCSP81 package marking (package top view . . . . . . . . . . . . . . . . . . . . . . 304

Figure 86. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . 305

Figure 87. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat

recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

Figure 88. Example of LQFP100 package marking (package top view) . . . . . . . . . . . . . . . . . . . . . . 307

Figure 89. UFBGA132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

Figure 90. UFBGA132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array

package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

Figure 91. Example of UFBGA132 package marking (package top view) . . . . . . . . . . . . . . . . . . . . 310

12/323 DS12736 Rev 2

STM32L562xx List of figures

Figure 92. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . 311

Figure 93. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package

recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

Figure 94. Example of LQFP144 package marking (package top view) . . . . . . . . . . . . . . . . . . . . . . 314

DS12736 Rev 2 13/323

Introduction STM32L562xx

1 Introduction

This document provides the ordering information and mechanical device characteristics of

the STM32L562xx microcontrollers.

This document should be read in conjunction with the STM32L552xx and STM32L562xx

reference manual (RM0438).

For information on the Arm

Reference Manual, available from the www.arm.com website.

®(a)

Cortex®-M33 core, refer to the Cortex®-M33 Technical

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

14/323 DS12736 Rev 2

STM32L562xx Description

2 Description

The STM32L562xx devices are an ultra-low-power microcontrollers family (STM32L5

Series) based on the high-performance Arm

at a frequency of up to 110

The Cortex®-M33 core features a single-precision floating-point unit (FPU), which supports

all the Arm

Cortex

single-precision data-processing instructions and all the data types. The

-M33 core also implements a full set of DSP (digital signal processing) instructions

MHz.

Cortex®-M33 32-bit RISC core. They operate

and a memory protection unit (MPU) which enhances the application’s security.

These devices embed high-speed memories (512 Kbytes of Flash memory and 256 Kbytes

of SRAM), a flexible external memory controller (FSMC) for static memories (for devices

with packages of 100 pins and more), an Octo-SPI Flash memories interface (available on

all packages) and an extensive range of enhanced I/Os and peripherals connected to two

APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.

The STM32L5 Series devices offer security foundation compliant with the trusted based

security architecture (TBSA) requirements from Arm. They embed the necessary security

features to implement a secure boot, secure data storage, secure firmware installation and

secure firmware upgrade. Flexible life cycle is managed thanks to multiple levels of readout

protection. Firmware hardware isolation is supported thanks to securable peripherals,

memories and I/Os, and also to the possibility to configure the peripherals and memories as

“privilege”.

The STM32L562xx devices embed several protection mechanisms for embedded Flash

memory and SRAM: readout protection, write protection, secure and hidden protection

areas.

The STM32L562xx devices embed several peripherals reinforcing security:

- One AES coprocessor

- One public key accelerator (PKA), DPA resistant

- One on-the-fly decryption engine for Octo-SPI external memories

- One HASH hardware accelerator

- One true random number generator

The STM32L5 Series devices offer active tamper detection and protection against transient

and environmental perturbation attacks thanks to several internal monitoring which generate

secret data erase in case of attack. This helps to fit the PCI requirements for point of sales

applications. These devices offer two fast 12-bit ADC (5 Msps), two comparators, two

operational amplifiers, two DAC channels, an internal voltage reference buffer, a low-power

RTC, two general-purpose 32-bit timer, two 16-bit PWM timers dedicated to motor control,

seven general-purpose 16-bit timers, and two 16-bit low-power timers. The devices support

four digital filters for external sigma delta modulators (DFSDM). In addition, up to 22

capacitive sensing channels are available.

STM32L5 Series also feature standard and advanced communication interfaces such as:

- Four I2Cs

- Three SPIs

- Three USARTs, two UARTs and one low-power UART

DS12736 Rev 2 15/323

Description STM32L562xx

- Two SAIs

- One SDMMC

- One FDCAN

- USB device FS

- USB Type-C / USB power delivery controller

The STM32L562xx devices embed an AES, PKA and OTFDEC hardware accelerator.

The devices operate in the -40 to +85 °C (+105 °C junction) and -40 to +125 °C (+130 °C

junction) temperature ranges from a 1.71 to 3.6

V power supply. A comprehensive set of

power-saving modes allows the design of low-power applications.

Some independent power supplies are supported like an analog independent supply input

for ADC, DAC, OPAMPs and comparators, a 3.3

14 I/Os, which can be supplied independently down to 1.08

V dedicated supply input for USB and up to

V. A VBAT input allows to

backup the RTC and backup the registers.

The STM32L562xx devices offer seven packages from 48-pin to 144-pin.

Table 2. STM32L562xx features and peripheral counts

Peripherals

STM32L562CE/

STM32L562CExxP

Flash memory (Kbyte) 512

SRAM

External memory controller for static memories (FSMC)

OCTOSPI 1

Timers

System (Kbyte) 256 (192+64)

Backup (byte) 128

Advanced control 2 (16-bit)

General purpose

Basic 2 (16-bit)

Low power 3 (16-bit)

SysTick timer 1

Watchdog timers (independent, window)

STM32L562RE/

STM32L562RExxQ

STM32L562RExxP/

No Yes

STM32L562MExxQ

STM32L562MExxP/

5 (16-bit) 2 (32-bit)

STM32L562VE/

STM32L562VExxQ

STM32L562QE/

STM32L562QExxP/

STM32L562QExxQ

STM32L562ZE/

STM32L562ZExxQ

16/323 DS12736 Rev 2

STM32L562xx Description

Table 2. STM32L562xx features and peripheral counts (continued)

Peripherals

STM32L562CE/

STM32L562CExxP

STM32L562RE/

STM32L562RExxQ

STM32L562RExxP/

STM32L562MExxQ

STM32L562MExxP/

STM32L562VE/

STM32L562VExxQ

STM32L562QE/

STM32L562QExxQ

STM32L562QExxP/

STM32L562ZE/

SPI 3

I2C 4

(1)

Communication interfaces

USART

/UART UART LPUART

SAI 2

3/2 (2)

2 1

FDCAN 1

USB FS Yes

SDMMC No

Digital filters for sigmadelta modulators

Yes/No/ Yes

Yes (4 filters)

Yes

Number of channels 8

Real time clock (RTC) Yes

Tamper pins 3 4/3 3 5/4 5 8/7

True random number generator Yes

AES Yes

PKA Yes

STM32L562ZExxQ

HASH (SHA-256) Yes

On-the-fly decryption for OCTOSPI 1

OCTOSPI memory encryption 1

GPIOs Wakeup pins Nb of I/Os down to 1.08 V

Capacitive sensing Number of channels

38/36

3 0

52/50/47

4/3/3

54/51

3 6

5 10/10/9 10 19/18 22 22/21

12-bit ADC 2

ADC

Number of channels

16/16/15 16/15 16/14 16 16/14

12-bit DAC 1

DAC

Number of channels

DS12736 Rev 2 17/323

83/79

5/4

110/108/105

13/

13/10

115 /111

5/4

14/13

Description STM32L562xx

Table 2. STM32L562xx features and peripheral counts (continued)

Peripherals

Internal voltage reference buffer

STM32L562CE/

STM32L562CExxP

STM32L562RE/

STM32L562RExxQ

STM32L562RExxP/

STM32L562MExxQ

STM32L562MExxP/

Yes

STM32L562VE/

STM32L562VExxQ

STM32L562QE/

STM32L562QExxQ

STM32L562QExxP/

STM32L562ZE/

Analog comparator 2

Operational amplifiers 2

Max. CPU frequency 110 MHz

Operating voltage 1.71 to 3.6 V

Operating temperature

Package

1. USART3 is not available on STM32L562CExxP devices.

2. For the LQFP100 package, only FSMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select.

UFQFPN48

Ambient operating temperature: -40 to 85 °C / -40 to 125 °C

Junction temperature: -40 to 105 °C / -40 to 130 °C

LQFP48,

LQFP64 WLCSP81 LQFP100

(2)

UFBGA132 LQFP144

STM32L562ZExxQ

18/323 DS12736 Rev 2

STM32L562xx Description

MSv49330V6

USB FS

CH1

CH2

DAC1

Flash up to 512KB

Flexible static memory controller (FSMC): SRAM,

PSRAM, NOR Flash,FRAM, NAND Flash

114 AF

PA[15:0]

3 compl. channels (TIM1_CH[1:3]N),

4 channels (TIM1_CH[1:4]), ETR, BKIN,

BKIN2 as AF

RX, TX, CK,CTS,

RTS as AF

MOSI, MISO,

SCK, NSS as AF

APB260 M Hz

APB1 30MHz

MOSI, MISO, SCK, NSS as AF

OUT1

RTC_TS

OSC32_IN

OSC32_OUT

VDDA, VSSA

VDD, VSS, NRST

smcard irDA

16b

D[7:0], D[3:1]dir CMD, CMDdir,CK, CKin D0dir, D2dir

VBAT = 1.55 to 3.6 V

SCL, SDA, SMBA as AF

JTAG & SW

ARM Cortex-M33 110 MHz TrustZone FPU

NVIC

ETM

MPU

TRACECLK

TRACED[3:0]

CLK, NE[4:1], NL, NBL[1:0], A[25:0], D[15:0], NOE, NWE, NWAIT, NCE, INT as AF

FIFO

@ VDDA

BOR

Supply

supervision

PVD, PVM

Int

reset

XTAL 32 kHz

RTC

FCLK

Standby

interface

IWDG

@VBAT

@ VDD

@VDD

AWU

PCLKx

VDD = 1.71 to 3.6 V

VSS

Voltage regulator LDO and SMPS

3.3 to 1.2 V

VDD

Power management

@ VDD

RTC_TAMP[8:1]

Backup register

AHB bus-matrix

2 channels, 1 compl. channel,

BKIN as AF

TIM2

TIM3

TIM4

TIM5

USART2

USART3

I2C1/SMBUS

SPI1

TIM17

USART1

EXT IT. WKUP

TIM16

TIM8 / PWM

TIM15

SDMMC1

TIM1 / PWM

TIM6

TIM7

WWDG

GPIO PORT H

GPIO PORT F

GPIO PORT G

GPIO PORT D

GPIO PORT E

GPIO PORT B

GPIO PORT C

GPIO PORT A

DMA1

DMA2

APB1 110 MHz (max)

SRAM 192 KB

SRAM 64 KB

NJTRST, JTDI,

JTCK/SWCLK

JTDO/SWD, JTDO

C-BUS

S-BUS

PB[15:0]

PC[15:0]

PD[15:0]

PE[15:0]

PF[15:0]

PG[15:0]

PH[1:0]

16b

3 compl. Channels (TIM1_CH[1:3]N),

4 channels (TIM1_CH[1:4]), ETR, BKIN,

BKIN2 as AF

1 channel, 1 compl. channel,

BKIN as AF

1 channel, 1 compl. channel,

BKIN as AF

OUT2

16b

SCL, SDA, SMBA as AF

MOSI, MISO, SCK, NSS as AF

RX, TX, CTS, RTS as AF

RX, TX, CK, CTS, RTS as AF

smcard

irDA

smcard

irDA

32b

16b

32b

4 channels, ETR as AF

AHB/APB1

OSC_IN

OSC_OUT

HCLKx

XTAL OSC

4- 16MHz

16xIN

VREF+

USAR T 2MBps

Temperature sensor

MCLK_A, SD_A, FS_A, SCK_A, EXTCLK

MCLK_B, SD_B, FS_B, SCK_B as AF

SAI1

MCLK_A, SD_A, FS_A, SCK_A, EXTCLK

MCLK_B, SD_B, FS_B, SCK_B as AF

SAI2

SDCKIN[7:0], SDDATIN[7:0],

SDCKOUT,SDTRIG as AF

DFSDM

Touch sensing controller

8 groups of sensing channels as AF

OUT, INN, INP

LPUART1

LPTIM1

LPTIM2

RX, TX, CTS, RTS as AF

IN1, IN2, OUT, ETR as AF

IN1, OUT, ETR as AF

RC HSI

RC LSI

PLL 1&2&3

MSI

Octo SPI1 memory interface

IO[7:0], CLK, NCLK, NCS. DQS

@ VDDUSB

COMP1

INP, INN, OUT

COMP2

INP, INN, OUT

@ VDDA

RTC_OUT

VDDIO, VDDUSB

FIFO

PHY

AHB1 110 MHz

CRC

OUT, INN, INP

I2C2/SMBUS

I2C3/SMBUS

OpAmp1

SPI3

SPI2

UART5

UART4

APB2 110MHz

AHB2 110 MHz

OpAmp2

@VDDA

RNG

AES

VREF Buffer

@ VDDA

@ VDD

HASH

FIFO

TX, RX as AF

FDCAN1

SCL, SDA, SMBA as AF

I2C4/SMBUS

ITF

ADC1

@ VDDA

SYSCFG

Icache 8KB

ADC2

LPTIM3

IN1, OUT, ETR as AF

UCPD1

@ VDDUSB

PHY

CRS

PKA32

DMAMUX1

AHB1 110 MHz

AHB/APB2

32-bits AHB bus

VDD power domain

VDDUSB power domain

VBAT power domain

VDDIO2 power domain

VDDA power domain

OTFDEC

GTZC

Reset

and clock

control

UCPD1

Figure 1. STM32L562xx block diagram

1. AF: alternate function on I/O pins.

DS12736 Rev 2 19/323

Functional overview STM32L562xx

3 Functional overview

3.1 Arm® Cortex®-M33 core with TrustZone® and FPU

The Cortex®-M33 with TrustZone and FPU is a highly energy efficient processor designed for microcontrollers and deeply embedded applications, especially those requiring efficient security.

The Cortex®-M33 processor delivers a high computational performance with low-power consumption and an advanced response to interrupts. it features:

• Arm® TrustZone® technology, using the ARMv8-M main extension supporting secure and non-secure states

• Memory protection units (MPUs), 8 regions for secure and 8 regions for non secure

• Configurable secure attribute unit (SAU) supporting up to 8 memory regions

• Floating-point arithmetic functionality with support for single precision arithmetic

The processor supports a set of DSP instructions that allows an efficient signal processing and a complex algorithm execution.

The Cortex®-M33 processor supports the following bus interfaces:

• System AHB bus: The System AHB (S-AHB) bus interface is used for any instruction fetch and data access to the memory-mapped SRAM, peripheral, external RAM and external device, or Vendor_SYS regions of the ARMv8-M memory map.

• Code AHB bus The Code AHB (C-AHB) bus interface is used for any instruction fetch and data access to the code region of the ARMv8-M memory map.

Figure 1 shows the general block diagram of the STM32L562xx family devices.

3.2 Art Accelerator – instruction cache (ICACHE)

The instruction cache (ICACHE) is introduced on C-AHB code bus of Cortex®-M33 processor to improve performance when fetching instruction (or data) from both internal and external memories.

20/323 DS12736 Rev 2

STM32L562xx Functional overview

ICACHE offers the following features:

• Multi-bus interface: – slave port receiving the memory requests from the Cortex

-M33 C-AHB code

execution port – master1 port performing refill requests to internal memories (FLASH and SRAMs) – master2 port performing refill requests to external memories (external

FLASH/RAMs through Octo-SPI/FMC interfaces) – a second slave port dedicated to ICACHE registers access.

• Close to zero wait states instructions/data access performance: – 0 wait-state on cache hit – hit-under-miss capability, allowing to serve new processor requests while a line

refill (due to a previous cache miss) is still ongoing – critical-word-first refill policy, minimizing processor stalls on cache miss – hit ratio improved by 2-ways set-associative architecture and pLRU-t replacement

policy (pseudo-least-recently-used, based on binary tree), algorithm with best

complexity/performance balance – dual master ports allowing to decouple internal and external memory traffics, on

Fast and Slow buses, respectively; also minimizing impact on interrupt latency – optimal cache line refill thanks to AHB burst transactions (of the cache line size). – performance monitoring by means of a hit counter and a miss counter.

• Extension of cacheable region beyond Code memory space, by means of address remapping logic that allows to define up to 4 cacheable external regions

• Power consumption reduced intrinsically (most accesses to cache memory rather to bigger main memories); even improved by configuring ICACHE as direct mapped (rather than the default 2-ways set-associative mode)

• TrustZone

security support

• Maintenance operation for software management of cache coherency

• Error management: detection of unexpected cacheable write access, with optional

interrupt raising.

3.3 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to the memory and to prevent one task to accidentally corrupt the memory or the resources used by any other active task. This memory area is organized into up to 8 regions for secure and 8 regions for non secure state.

The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

DS12736 Rev 2 21/323

Functional overview STM32L562xx

3.4 Embedded Flash memory

The devices feature 512 Kbytes of embedded Flash memory which is available for storing programs and data.

The Flash interface features:

• Single or dual bank operating modes

• Read-while-write (RWW) in dual bank mode

This feature allows to perform a read operation from one bank while an erase or program operation is performed to the other bank. The dual bank boot is also supported. Each bank contains 128 pages of 2 or 4 memory also embeds 512 bytes OTP (one-time programmable) for user data.

Flexible protections can be configured thanks to the option bytes:

• Readout protection (RDP) to protect the whole memory. Four levels of protection are

available: – Level 0: no readout protection – Level 0.5: available only when TrustZone is enabled

All read/write operations (if no write protection is set) from/to the non-secure Flash memory are possible. The Debug access to secure area is prohibited. Debug access to non-secure area remains possible.

– Level 1: memory readout protection; the Flash memory cannot be read from or written

to if either the debug features are connected or the boot in RAM or bootloader are selected. If TrustZone is enabled, the non-secure debug is possible and the boot in SRAM is not possible.

– Level 2: chip readout protection; the debug features (Cortex

wire), the boot in RAM and the bootloader selection are disabled (JTAG fuse). This selection is irreversible.

• Write protection (WRP): the protected area is protected against erasing and programming:

– In single bank mode, four areas can be selected with 4-Kbyte granularity. – In dual bank mode, two areas per bank can be selected with 2-Kbyte granularity.

Kbytes (depending on the read access width). The Flash

-M33 JTAG and serial

The whole non-volatile memory embeds the error correction code (ECC) feature supporting:

• Single error detection and correction

• Double error detection

• The address of the ECC fail can be read in the ECC register.

TrustZone security

When the TrustZone security is enabled, the whole Flash is secure after reset and the following protections are available:

• Non-volatile watermark-based secure Flash area: the secure area can be accessed only in secure mode.

– In single bank mode, four areas can be selected with a page granularity. – In dual bank mode, one area per bank can be selected with a page granularity.

• Secure hidden protection area: it is part of the Flash secure area and it can be protected to deny an access to this area by any data read, write and instruction fetch.

22/323 DS12736 Rev 2

STM32L562xx Functional overview

For example, a software code in the secure Flash memory hidden protection area can be executed only once and deny any further access to this area until next system reset.

• Volatile block-based secure Flash area. In a block-based secure area, each page can be programmed on-the-fly as secure or non-secure.

3.5 Embedded SRAM

The devices feature 256 Kbytes of embedded SRAM. This SRAM is split into three blocks:

• 192 Kbytes mapped at address 0x2000 0000 (SRAM1).

• 64 Kbytes located at address 0x0A03 0000 with hardware parity check (SRAM2).

This memory is also mapped at address 0x2003 0000 offering a contiguous address space with the SRAM1. This block is accessed through the C-bus for maximum performance. Either 64 Kbytes or upper 4 Kbytes of SRAM2 can be retained in Standby mode. The SRAM2 can be write-protected with 1 Kbyte granularity.

The memory can be accessed in read/write at CPU clock speed with 0 wait states.

TrustZone security

When the TrustZone security is enabled, all SRAMs are secure after reset. The SRAM can be programmed as non-secure by block based using the MPCBB (memory protection controller block based) in GTZC controller. The granularity of SRAM secure block based is a page of 256 bytes.

3.6 Boot modes

At startup, a BOOT0 pin, nBOOT0 and NSBOOTADDx[24:0] / SECBOOTADD0[24:0] option bytes are used to select the boot memory address which includes:

• Boot from any address in user Flash

• Boot from system memory bootloader

• Boot from any address in embedded SRAM

• Boot from Root Security service (RSS)

The BOOT0 value may come from the PH3-BOOT0 pin or from an option bit depending on the value of a user option bit to free the GPIO pad if needed.

The boot loader is located in the system memory. It is used to reprogram the Flash memory by using USART, I2C, SPI, FDCAN or USB FS in device mode through the DFU (device firmware upgrade).

The bootloader is available on all devices. Refer to the application note STM32 microcontroller system memory boot mode (AN2606) for more details.

The root secure services (RSS) are embedded in a Flash memory area named secure information block, programmed during ST production.

The RSS enables for example the secure firmware installation (SFI) thanks to the RSS extension firmware (RSSe SFI).

This feature allows the customers to protect the confidentiality of the firmware to be provisioned into the STM32 device when the production is subcontracted to a third party.

DS12736 Rev 2 23/323

Functional overview STM32L562xx

The RSS is available on all devices, after enabling the TrustZone through the TZEN option bit.

Refer to the application note Overview secure firmware install (SFI) (AN4992) for more details.

Refer to Tab le 3 and Tab le 4 for boot modes when TrustZone is disabled and enabled respectively.

Table 3. Boot modes when TrustZone is disabled (TZEN=0)

nBOOT0

FLASH_

OPTR[27]

BOOT0

pin PH3

nSWBOOT0

FLASH_

OPTR[26]

Boot address option-

bytes selection

- 0 1 NSBOOTADD0[24:0]

- 1 1 NSBOOTADD1[24:0]

1 - 0 NSBOOTADD0[24:0]

0 - 0 NSBOOTADD1[24:0]

When TrustZone is enabled by setting the TZEN option bit, the boot space must be in secure area. The SECBOOTADD0[24:0] option bytes are used to select the boot secure memory address.

A unique boot entry option can be selected by setting the BOOT_LOCK option bit, allowing to boot always at the address selected by SECBOOTADD0[24:0] option bytes. All other boot options are ignored.

Boot area

Boot address defined by user option bytes NSBOOTADD0[24:0]

Boot address defined by user option bytes NSBOOTADD1[24:0]

Boot address defined by user option bytes NSBOOTADD0[24:0]

Boot address defined by user option bytes NSBOOTADD1[24:0]

ST programmed

default value

Flash: 0x0800 0000

System bootloader: 0x0BF9 0000

Flash: 0x0800 0000

System bootloader: 0x0BF9 0000

24/323 DS12736 Rev 2

STM32L562xx Functional overview

Table 4. Boot modes when TrustZone is enabled (TZEN=1)

BOOT_

LOCK

nBOOT0

FLASH_

OPTR[27]

BOOT0

PH3

nSWBOOT0

FLASH_

OPTR[26]

RSS

command

-0 1 0

- 1 1 0 N/A RSS: 0x0FF8 0000

1- 0 0

0- 0 0 N/A

-- -

≠ 0N/A

1- - - -

Boot address

option-bytes

selection

SECBOOTAD

D0[24:0]

SECBOOTAD

D0[24:0]

SECBOOTAD

D0[24:0]

Boot area

Secure boot address defined by user option bytes

SECBOOTADD0[24:0]

Secure boot address defined by user option bytes SECBOOTADD0[24:0]

RSS: RSS: 0x0FF8 0000

Secure boot address defined by user option bytes SECBOOTADD0[24:0]

ST programmed default value

Flash: 0x0C00 0000

RSS: 0x0FF8 0000

Flash: 0x0C00 0000

RSS: 0x0FF8 0000

Flash: 0x0C00 0000

The boot address option bytes enables the possibility to program any boot memory address. However, the allowed address space depends on Flash read protection RDP level.

If the programmed boot memory address is out of the allowed memory mapped area when RDP level is 0.5 or more, the default boot fetch address is forced to:

• 0x0800 0000 (when TZEN = 0)

• RSS (when TZEN = 1)

Refer to Tab le 5.

RDP TZEN = 1 TZEN = 0

0 Any boot address Any boot address

Table 5. Boot space versus RDP protection

DS12736 Rev 2 25/323

Functional overview STM32L562xx

Table 5. Boot space versus RDP protection (continued)

RDP TZEN = 1 TZEN = 0

0.5

1 Any boot address

Boot address only in: – RSS – or secure Flash: 0x0C00 0000 -

0x0C07 FFFF

Otherwise boot address forced to RSS

N/A

If boot is configured for NSBOOTADD0 and NSBOOTADD0 in the range 0x0800 0000 0x0807 FFFF: boot at the address stored in NSBOOTADD0

If boot is configured for NSBOOTADD1 and NSBOOTADD1 in the range 0x0800 0000 0x0807 FFFF: boot at the address stored in NSBOOTADD1

Otherwise boot address is forced at 0x0800 0000

3.7 Global TrustZone controller (GTZC)

The GTZC includes three different sub-blocks:

• TZSC: TrustZone® security controller This sub-block defines the secure/privilege state of slave/master peripherals. It also controls the non-secure area size for the watermark memory peripheral controller (MPCWM). The TZSC block informs some peripherals (such as RCC or GPIOs) about the secure status of each securable peripheral, by sharing with RCC and I/O logic.

1. MPCBB: block-based memory protection controller This sub-block controls secure states of all blocks (256-byte pages) of the associated SRAM.

2. TZIC: TrustZone illegal access controller This sub-block gathers all illegal access events in the system and generates a secure interrupt towards NVIC.

These sub-blocks are used to configure TrustZone and privileged attributes within the full system.

The GTZC main features are:

• 3 independent 32-bit AHB interface for TZSC, MPCBB and TZIC

• MPCBB and TZIC accessible only with secure transactions

• Secure and non-secure access supported for priv/non-priv part of TZSC

• Register set to define security settings:

– Secure blocks for internal SRAM – Non-secure regions for external memories – Secure/privilege access mode for securable and TZ-aware peripherals

• Secure/privilege access mode for securable legacy masters.

3.8 TrustZone security architecture

The security architecture is based on Arm® TrustZone® with the ARMv8-M Main Extension.

26/323 DS12736 Rev 2

STM32L562xx Functional overview

The TrustZone security is activated by the TZEN option bit in the FLASH_OPTR register. When the TrustZone is enabled, the SAU (security attribution unit) and IDAU

(implementation defined attribution unit) defines the access permissions based on secure and non-secure state.

• SAU: Up to 8 SAU configurable regions are available for security attribution.

• IDAU: It provides a first memory partition as non-secure or non-secure callable

attributes. It is then combined with the results from the SAU security attribution and the higher security state is selected.

Based on IDAU security attribution, the Flash, system SRAMs and peripherals memory space is aliased twice for secure and non-secure state. However, the external memories space is not aliased.

Tab le 6 shows an example of typical SAU regions configuration based on IDAU regions.

The user can split and choose the secure, non-secure or NSC regions for external memories as needed.

Table 6. Example of memory map security attribution vs SAU configuration regions

(1) (2)

Region

description

Code - external memories

Code - Flash and SRAM

Code - external memories

SRAM

Peripherals

External memories

1. NSC = non-secure callable.

2. Different colors highlights the different configurations

Pink: Non-secure

Green: NSC (non-secure callable) Lighter green: Secure or non-secure or NSC

Address range

0x0000_0000

0x07FF_FFFF

0x0800_0000

0x0BFF_FFFF

0x0C00_0000

0x0FFF_FFFF

0x1000_0000

0x17FF_FFFF

0x1800_0000

0x1FFF_FFFF

0x2000_0000

0x2FFF_FFFF

0x3000_0000

0x3FFF_FFFF

0x4000_0000

0x4FFF_FFFF

0x5000_0000

0x5FFF_FFFF

0x6000_0000

0xDFFF_FFFF

IDAU security

attribution

Non-secure

Non-secure Non-secure Non-secure

NSC Secure or NSC Secure or NSC

Non-secure

NSC Secure or NSC Secure or NSC

Non-secure Non-secure Non-secure

NSC Secure or NSC Secure or NSC

Non-secure

SAU security

attribution typical

configuration

Secure or non-

secure or NSC

Non-secure

Secure or non-

secure or NSC

Final security

attribution

Secure or non-

secure or NSC

Secure or non-

secure or NSC

DS12736 Rev 2 27/323

Functional overview STM32L562xx

3.8.1 TrustZone peripheral classification

When the TrustZone security is active, a peripheral can be either Securable or TrustZoneaware type as follows:

• Securable: a peripheral is protected by an AHB/APB firewall gate that is controlled from TZSC controller to define security properties.

• TrustZone-aware: a peripheral connected directly to AHB or APB bus and is implementing a specific TrustZone behavior such as a subset of registers being secure.

The tables below summarize the list of Securable and TrustZone aware peripherals within the system.

Table 7. Securable peripherals by TZSC

Bus Peripheral

AHB3

AHB 2

AHB1

APB2

OCTOSPI1 registers

FMC registers

SDMMC1

RNG

HASH

AES

ADC

ICACHE registers

TSC

CRC

DFSDM1

SAI2

SAI1

TIM17

TIM16

TIM15

USART1

TIM8

SPI1

TIM1

COMP

VREFBUF

28/323 DS12736 Rev 2

STM32L562xx Functional overview

Table 7. Securable peripherals by TZSC (continued)

Bus Peripheral

UCPD1

USB FS

FDCAN1

LPTIM3

LPTIM2

I2C4

LPUART1

LPTIM1

OPAMP

DAC1

CRS

I2C3

I2C2

APB1

I2C1

UART5

UART4

USART3

USART2

SPI3

SPI2

IWDG

WWDG

TIM7

TIM6

TIM5

TIM4

TIM3

TIM2

DS12736 Rev 2 29/323

Functional overview STM32L562xx

Table 8. TrustZone-aware peripherals

Bus Peripheral

GPIOH

GPIOG

GPIOF

AHB2

AHB2 OTFDEC1

AHB1

GPIOE

GPIOD

GPIOC

GPIOB

GPIOA

MPCBB2

MPCBB1

MPCWM2

MPCWM1

TZIC

TZSC

EXTI

Flash memory

RCC

DMAMUX1

DMA2

DMA1

APB2 SYSCFG

APB1

PWR

RTC

30/323 DS12736 Rev 2

STM32L562xx Functional overview

Default TrustZone security state

The default system security state is:

• CPU: –Cortex

• Memory map: – SAU: is fully secure after reset. Consequently, all memory map is fully secure. Up

• Flash: – Flash security area is defined by watermark user options. – Flash block based area is non-secure after reset.

• SRAMs: – All SRAMs are secure after reset. MPCBB (memory protection block based

• External memories: – FSMC, OCTOSPI banks are secure after reset. MPCWMx (memory protection

• Peripherals – Securable peripherals are non-secure after reset. – TrustZone-aware peripherals (except the GPIO) are non-secure after reset. Their

-M33 is in secure state after reset. The boot address must be in secure

address.

to 8 SAU configurable regions are available for security attribution.

controller) is secure.

watermark based controller) are secure

secure configuration registers are secure.

Note: Refer to Ta bl e 7 and Ta b le 8 for a list of Securable and TrustZone-aware peripherals.

• All GPIO are secure after reset.

• Interrupts:

– NVIC: All interrupts are secure after reset. NVIC is banked for secure and non-

secure state.

– TZIC: All illegal access interrupts are disabled after reset.

DS12736 Rev 2 31/323

Functional overview STM32L562xx

3.9 Power supply management

The power controller (PWR) main features are:

• Power supplies and supply domains – Core domains (VCORE) – VDD domain – Backup domain (VBAT) – Analog domain (VDDA) – VDDIO2 domain – VDDUSB for USB transceiver

• System supply voltage regulation – SMPS step down converter – Voltage regulator (LDO)

• Power supply supervision – POR/PDR monitor –BOR monitor –PVD monitor – PVM monitor (VDDA, VDDUSB, VDDIO2) – Temperature thresholds monitor – Upper VDD voltage threshold monitor

• Power management – Operating modes – Voltage scaling control – Low-power modes

• VBAT battery charging

• TrustZone security

3.9.1 Power supply schemes

The devices require a 1.71 V to 3.6 V V supplies can be provided for specific peripherals:

• VDD = 1.71 V to 3.6 V V

is the external power supply for the I/Os, the internal regulator and the system

analog such as reset, power management and internal clocks. It is provided externally through the VDD pins.

• V

= 1.62 V (ADCs/COMPs) / 1.8 V (DACs/OPAMPs) to 2.4 V (VREFBUF) to 3.6 V

DDA

is the external analog power supply for A/D converters, D/A converters, voltage

DDA

reference buffer, operational amplifiers and comparators. The V independent from the V

voltage and should preferably be connected to VDD when

these peripherals are not used.

32/323 DS12736 Rev 2

operating voltage supply. Several independent

voltage level is

DDA

STM32L562xx Functional overview

• VDDSMPS = 1.71 V to 3.6 V VDDSMPS is the external power supply for the SMPS step down converter. It is provided externally through VDDSMPS supply pin, and shall be connected to the same supply as VDD.

• VLXSMPS is the switched SMPS step down converter output.

• V15SMPS are the power supply for the system regulator. It is provided externally

through the SMPS step down converter VLXSMPS output.

Note: The SMPS power supply pins are available only on a specific package with SMPS step

down converter option.

• VDD12 = 1.05 to 1.32 V VDD12 is the external power supply bypassing the internal regulator when connected to an external SMPS. It is provided externally through VDD12 pins and only available on packages with the external SMPS supply option. VDD12 does not require any external decoupling capacitance and cannot support any external load.

• VDDUSB = 3.0 V to 3.6 V VDDUSB is the external independent power supply for USB transceivers. The VDDUSB voltage level is independent from the VDD voltage and should preferably be connected to VDD when the USB is not used.

• VDDIO2 = 1.08 V to 3.6 V

• VDDIO2 is the external power supply for 14 I/Os (port G[15:2]). The VDDIO2 voltage

level is independent from the VDD voltage and should preferably be connected to VDD when PG[15:2] are not used.

• V

= 1.55 V to 3.6 V

BAT

is the power supply for RTC, external clock 32 kHz oscillator and backup registers

BAT

(through power switch) when V

REF-, VREF+

is the input reference voltage for ADCs and DACs. It is also the output of the

REF+

is not present.

internal voltage reference buffer when enabled. When V When V V

REF+

DDA

< 2 V V ≥ 2 V V

must be equal to V

REF+

must be between 2 V and V

REF+

DDA

can be grounded when ADC and DAC are not active.

The internal voltage reference buffer supports two output voltages, which are configured with VRS bit in the VREFBUF_CSR register:

–V –V

around 2.048 V. This requires V

REF+

around 2.5 V. This requires V

REF+

equal to or higher than 2.4 V.

DDA

equal to or higher than 2.8 V.

DDA

VREF- and VREF+ pins are not available on all packages. When not available, they are bonded to VSSA and VDDA, respectively. When the VREF+ is double-bonded with VDDA in a package, the internal voltage reference buffer is not available and must be kept disabled (refer to datasheet for packages pinout description). V

must always be equal to V

REF-

An embedded linear voltage-regulator is used to supply the internal digital power V V supplied by V

is the power supply for digital peripherals, SRAM1 and SRAM2. The Flash is

CORE

and VDD.

SSA

CORE

DS12736 Rev 2 33/323

Functional overview STM32L562xx

MSv49301V1

DDA

domain

Backup domain

Standby circuitry (Wakeup logic, IWDG)

Voltage regulator

Low voltage detector

LSE crystal 32 K osc BKP registers RCC BDCR register RTC

I/O ring

CORE

domain

Temp. sensor

Reset block

3 x PLL, HSI, MSI

Flash memory

USB transceivers

DDUSB

DDIO2

DDIO1

I/O ring

PG[15:2]

DDIO2

DDA

SSA

DDIO2

domain

CORE

BAT

Core

SRAM1 SRAM2

Digital

peripherals

2 x D/A converters

3 x A/D converters

2 x comparators

2 x operational amplifiers

Voltage reference buffer

Figure 2. STM32L562xx power supply overview

34/323 DS12736 Rev 2

STM32L562xx Functional overview

MSv49336V1

DDA

domain

Backup domain

Standby circuitry (Wakeup logic, IWDG)

Voltage regulator

Low voltage detector

LSE crystal 32 K osc BKP registers RCC BDCR register RTC

I/O ring

CORE

domain

Temp. sensor

Reset block

3 x PLL, HSI, MSI

Flash memory

USB transceivers

DDUSB

DDIO2

DDIO1

I/O ring

PG[15:2]

DDIO2

DDA

SSA

DDIO2

domain

CORE

BAT

Core

SRAM1 SRAM2

Digital

peripherals

2 x D/A converters

3 x A/D converters

2 x comparators

2 x operational amplifiers

Voltage reference buffer

2x V

DD12

Figure 3. STM32L562xxxxP power supply overview

DS12736 Rev 2 35/323

Functional overview STM32L562xx

MSv49332V1

DDA

domain

Backup domain

2 x D/A converters

2 x A/D converters

Standby circuitry (Wakeup logic, IWDG)

Voltage regulator

Low voltage detector

LSE crystal 32 K osc BKP registers RCC BDCR register RTC

2 x comparators

2 x operational amplifiers

Voltage reference buffer

I/O ring

CORE

domain

Temp. sensor

Reset block

3 x PLL, HSI, MSI

Flash memory

USB transceivers

DDUSB

DDIO2

DDIO1

I/O ring

DDIO2

DDA

SSA

DDIO2

domain

CORE

BAT

Core

SRAM1 SRAM2

Digital

peripherals

SMPS

LPR

LXSMPS

SSSMPS

2 x V

15SMPS

DDSMPS

Figure 4. STM32L562xxxxQ power supply overview

36/323 DS12736 Rev 2

During power-up and power-down phases, the following power sequence requirements must be respected:

• When V below VDD +300 mV.

• When V

• During the power-down phase, V

only if the energy provided to the MCU remains below 1 mJ; this allows external decoupling capacitors to be discharged with different time constants during the powerdown transient phase.

is below 1 V, other power supplies (V

is above 1 V, all power supplies are independent.

, V

DDA

can temporarily become lower than other supplies

DDIO2

and V

DDUSB

) must remain

STM32L562xx Functional overview

MSv47490V1

0.3

BOR0

3.6

Operating modePower-on Power-down time

DDX

(1)

Invalid supply area V

DDX

< V

+ 300 mV

DDX

independent from V

Figure 5. Power-up/down sequence

1. V

refers to any power supply among V

DDX

DDA

, V

DDIO2

and V

DDUSB.

3.9.2 Power supply supervisor

The devices have an integrated ultra-low-power Brownout reset (BOR) active in all modes (except for Shutdown mode). The BOR ensures proper operation of the devices after poweron and during power down. The devices remain in reset mode when the monitored supply voltage V

is below a specified threshold, without the need for an external reset circuit.

The lowest BOR level is 1.71 V at power on, and other higher thresholds can be selected through option bytes.The devices feature an embedded programmable voltage detector (PVD) that monitors the V

power supply and compares it to the VPVD threshold.

An interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

In addition, the devices embed a peripheral voltage monitor which compares the independent supply voltages V

DDA

, V

DDUSB

, V

with a fixed threshold in order to ensure

DDIO2

that the peripheral is in its functional supply range.

3.9.3 Voltage regulator

Two embedded linear voltage regulators supply most of the digital circuitries: the main regulator (MR) and the low-power regulator (LPR).

• The MR is used in the Run and Sleep modes and in the Stop 0 mode.

• The LPR is used in Low-power run, Low-power sleep, Stop 1 and Stop 2 modes. It is

also used to supply the 64 Kbytes or only 4 Kbytes of SRAM2 in standby with SRAM2 retention.

• Both regulators are in power-down while they are in standby and Shutdown modes: the regulator output is in high impedance, and the kernel circuitry is powered down thus inducing zero consumption.

DS12736 Rev 2 37/323

Functional overview STM32L562xx

The ultra-low-power STM32L562xx devices support dynamic voltage scaling to optimize its power consumption in Run mode. The voltage from the main regulator that supplies the logic (VCORE) can be adjusted according to the system’s maximum operating frequency.

The main regulator operates in the following ranges:

• Range 0 with the CPU running at up to 110 MHz.

• Range 1 with the CPU running at up to 80 MHz.

• Range 2 with a maximum CPU frequency of 26 MHz. All peripheral clocks are also

limited to 26 MHz.

The VCORE can be supplied by the low-power regulator, the main regulator being switched off. The system is then in Low-power run mode.

• Low-power run mode with the CPU running at up to 2 MHz. Peripherals with independent clock can be clocked by the HSI16.

3.9.4 SMPS step down converter

The built-in SMPS step down converter is a highly power-efficient DC/DC non-linear switching regulator that improves low-power performance when the VDD voltage is high enough. This SMPS step down converter automatically enters in bypass mode when the VDD voltage falls below 2

Note: There is no automatic SMPS bypass in Range 2.

V in Range 0 and Range 1.

The SMPS step down converter can be configured in:

• High-power mode (HPM): achieving a high efficiency at high current load. It is the default selected mode after POR reset.

• Low power mode achieving very high efficiency at low load

• Bypass mode

The SMPS step down converter can be switched in bypass mode at any time by the application software.

Note: The SMPS step down converter is available only on specific package.

SMPS step down converter power supply scheme

The SMPS step down converter requires an external coil with typical value of 4.7 μH to be connected between the VLXSMPS and the V15SMPS pins and a 4.7μF capacitor to be connected between the V15SMPS to VSSSMPS pins. It can be switched OFF by selecting the Bypass mode by software. Thus, only main regulator is used by the application.

38/323 DS12736 Rev 2

STM32L562xx Functional overview

MSv49346V1

Main

regulator

VDDSMPS

VLXSMPS

SMPS

Step Down

Converter

VSSSMPS

V15SMPS

CORE

V15SMPS

VDD

VSS

Figure 6. SMPS step down converter power supply scheme

If the selected package is with the SMPS step down converter option but it is never used by the application, it is recommend to set the SMPS power supply pins as follows:

• V

DDSMPS

• V

15SMPS

Component Description Value

and V

LXSMPS

connected to VSS

connected to VDD

Table 9. SMPS external components

C SMPS output capacitor

L SMPS inductance

(2)

(1)

4.7 µF

4.7 µH

1. For example GRM155R60J475ME87J and GRM21BR71E475KA73L.

2. For example TDK MLP2016H4R7MT.

SMPS step down converter fast startup

After POR reset, the SMPS step down converter starts in High-power mode and in Low startup mode. The low-startup feature is selected to limit the inrush current after power-on reset.

However, it is possible to configure a faster startup on the fly and it is applied for next startup either after a system reset or wakeup from low-power mode except Shutdown and VBAT modes. The fast startup is selected by setting the SMPSFSTEN bit in the PWR_CR4 register.

DS12736 Rev 2 39/323

40/323 DS12736 Rev 2

3.9.5 Low-power modes

The ultra-low-power STM32L562xx devices support seven low-power modes to achieve the best compromise between low-power consumption, short startup time, available peripherals and available wake-up sources. modes overview.

Functional overview STM32L562xx

Tabl e 11 shows the related STM32L562xx

Table 10. STM32L562xx modes overview

Mode

Regulator and SMPS

mode

(1)

CPU Flash SRAM Clocks DMA and Peripherals

Ranges 0/1

SMPS HP mode

Run

Yes ON

Range 2

SMPS LP mode

LPRun LPR Yes ON

Ranges 0/1

SMPS HP mode

Sleep

No ON

Range 2

SMPS LP mode

Ranges 0/1

Sleep

No ON

Range 2 All except USB_FS, RNG

LPSleep LPR No ON

(3)

ON Any

(4)

(5)

except PLL

Any

(2)

Wakeup source

All

N/A

All except USB_FS, RNG

All except USB_FS, RNG N/A

All

Any interrupt or event

All except USB_FS, RNG

All

Any interrupt or event

All except USB_FS, RNG Any interrupt or event

Table 10. STM32L562xx modes overview (continued)

STM32L562xx Functional overview

DS12736 Rev 2 41/323

Mode

Stop 0

Regulator and SMPS

(6)

Ranges 0/1/2 No Off ON

mode

(1)

CPU Flash SRAM Clocks DMA and Peripherals

Stop 1 LPR No Off ON

Stop 2 LPR No Off ON

LSE

LSI

LSE

LSI

LSE

LSI

(2)

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1,2)

DAC1

OPAMPx (x=1,2)

USARTx (x=1...5)

LPUART1

I2Cx (x=1...4)

(7)

(8)

LPTIMx (x=1,2)

***

All other peripherals are frozen

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1,2)

DAC1

OPAMPx (x=1,2)

USARTx (x=1...5)

LPUART1

I2Cx (x=1...4)

(7)

(8)

LPTIMx (x=1,2)

***

All other peripherals are frozen

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1..2)

(8)

I2C3

LPUART1

(7)

LPTIMx (x= 1,3)

***

All other peripherals are frozen

Wakeup source

Reset pin, all I/Os

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1..2)

USARTx (x=1...5)

LPUART1

I2Cx (x=1...4)

(7)

(8)

LPTIMx (x=1,2)

USB_FS

(9)

Reset pin, all I/Os

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1..2)

USARTx (x=1...5)

LPUART1

I2Cx (x=1...4)

(7)

(8)

LPTIMx (x=1,2)

USB_FS

(9)

Reset pin, all I/Os

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1..2)

(8)

I2C3

LPUART1

(7)

LPTIMx (x= 1,3)

(7)

42/323 DS12736 Rev 2

Table 10. STM32L562xx modes overview (continued)

Functional overview STM32L562xx

Mode

Regulator and SMPS

mode

(1)

LPR

CPU Flash SRAM Clocks DMA and Peripherals

SRAM2 ON

BOR, RTC, IWDG

(2)

***

All other peripherals are powered

off ***

Standby

OFF

Powered

Off

Powered

Off

LSE

LSI

I/O configuration can be floating,

pull-up or pull-down

RTC

***

Shutdown OFF

1. LPR means Main regulator is OFF and Low-power regulator is ON.

2. All peripherals can be active or clock gated to save power consumption.

3. The Flash memory can be put in power-down and its clock can be gated off when executing from SRAM.

4. The SRAM1 and SRAM2 clocks can be gated on or off independently.

5. The SRAM1 and SRAM2 clocks can be gated on or off independently.

6. SMPS mode can be used in Stop 0 mode, but no significant power gain can be expected.

7. U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event.

8. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.

9. USB_FS wakeup by resume from suspend and attach detection protocol event.

10. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5.

11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode.

Powered

Off

Powered

Off

LSE

All other peripherals are powered

off ***

I/O configuration can be floating,

pull-up or pull-down

(11)

Wakeup source

Reset pin

5 I/Os (WKUPx)

BOR, RTC, IWDG

Reset pin

5 I/Os (WKUPx)

RTC

(10)

STM32L562xx Functional overview

By default, the microcontroller is in Run mode after a system or a power reset. It is up to the user to select one of the low-power modes described below:

• Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

• Low-power run mode This mode is achieved with VCORE supplied by the low-power regulator to minimize

the regulator's operating current. The code can be executed from SRAM or from Flash, and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can be clocked by HSI16.

• Low-power sleep mode This mode is entered from the Low-power run mode. Only the CPU clock is stopped.

When wakeup is triggered by an event or an interrupt, the system reverts to the Lowpower run mode.

• Stop 0, Stop 1 and Stop 2 modes Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the VCORE domain are stopped, the PLL, the MSI RC, the HSI16 RC and the HSE crystal oscillators are disabled. The LSE or LSI is still running.

The RTC can remain active (Stop mode with RTC, Stop mode without RTC). Some peripherals with wake-up capability can enable the HSI16 RC during Stop mode

to detect their wake-up condition. Three Stop modes are available: Stop 0, Stop 1 and Stop 2 modes. In Stop 2 mode,

most of the VCORE domain is put in a lower leakage mode. Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller

wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator remains ON, allowing a very fast wakeup time but with much higher consumption.

The system clock when exiting from Stop 0, Stop 1 or Stop 2 modes can be either MSI up to 48 MHz or HSI16, depending on software configuration.

• Standby mode The Standby mode is used to achieve the lowest power consumption with BOR. The

internal regulator is switched off so that the VCORE domain is powered off. The PLL, the MSI RC, the HSI16 RC and the HSE crystal oscillators are also switched off.

The RTC can remain active (Standby mode with RTC, Standby mode without RTC). The Brownout reset (BOR) always remains active in Standby mode. The state of each I/O during Standby mode can be selected by software: I/O with

internal pull-up, internal pull-down or floating. After entering Standby mode, SRAM1 and register contents are lost except for registers

in the Backup domain and Standby circuitry. Optionally, the full SRAM2 or 4 Kbytes can be retained in Standby mode, supplied by the low-power regulator (standby with RAM2 retention mode).

DS12736 Rev 2 43/323

Functional overview STM32L562xx

The BORL (brown out detector low) can be configured in ultra-low-power mode to further reduce power consumption during standby mode.

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE).

The system clock after wakeup is MSI up to 8 MHz.

• Shutdown mode The Shutdown mode allows to achieve the lowest power consumption. The internal

regulator is switched off so that the VCORE domain is powered off. The PLL, the HSI16, the MSI, the LSI and the HSE oscillators are also switched off.

The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC). The BOR is not available in Shutdown mode. No power voltage monitoring is possible

in this mode, therefore the switch to Backup domain is not supported. SRAM1, SRAM2 and register contents are lost except for registers in the Backup

domain. The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin

event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic wakeup, timestamp, tamper).

The system clock after wakeup is MSI at 4 MHz.

44/323 DS12736 Rev 2

STM32L562xx Functional overview

Table 11. Functionalities depending on the working mode

(1)

Stop 0/1 Stop 2 Standby Shutdown

Peripheral Run Sleep

Low-

power

run

Low-

power

sleep

VBAT

Wakeup capability

CPU Y - Y - - --------

Flash memory

512 Kbyte)

(

SRAM1 (192 Kbytes)

SRAM2 (64 Kbytes) Y Y

FSMC OOOO-

OCTOSPI O O O O -

OTFDEC OOOO-

Backup registers Y Y Y Y Y

Brownout reset (BOR)

(2)

(3)

(2)

(3)

- --------

Y -Y------

Y -Y-O

(4)

----

--------

-Y-Y-Y-Y

YYYYYYYYYY- --

Programmable voltage detector

OOOOO

OOO- ----

(PVD)

Peripheral voltage monitor (PVMx;

OOOOO

OOO- ----

x=1,2,3,4)

DMA OOOO-

--------

High speed internal (HSI16)

OOOO

(5)

Oscillator HSI48 O O - - - -

High speed external (HSE)

Low speed internal (LSI)

Low speed external (LSE)

Multi speed internal (MSI)

Clock security system (CSS)

Clock security system on LSE

OOOO-

OOOOO

OOOO-

OOOOO

DS12736 Rev 2 45/323

(5)

------

--------

-O-O----

-O-O-O-O

--------

OOOOO- --

Functional overview STM32L562xx

Table 11. Functionalities depending on the working mode

(1)

(continued)

Stop 0/1 Stop 2 Standby Shutdown

Peripheral Run Sleep

Low-

power

run

Low-

power

sleep

VBAT

Wakeup capability

VDD voltage monitoring, temperature

OOOOO

OOOOO- --

monitoring

RTC / TAMP OOOOOOOOOOOOO

Number of RTC Tamper pins

USB, UCPD O

USARTx (x=1,2,3,4,5)

Low-power UART (LPUART)

88888

(8)

---O- ------

OOOOO

I2Cx (x=1,2,4) O O O O O

I2C3 OOOOO

O8O8O8O3

(6)O(6)

(6)O(6)O(6)O(6)

(7)O(7)

(7)O(7)O(7)O(7)

- ------

- ----

- ------

- ----

SPIx (x=1,2,3) O O O O -

FDCAN1 O O O O -

SDMMC1 OOOO-

SAIx (x=1,2) O O O O -

DFSDM1 OOOO-

ADCx (x=1,2) O O O O -

DAC1 O O O O O

VREFBUF O O O O O

OPAMPx (x=1,2) O O O O O

COMPx (x=1,2) OOOOO

Temperature sensor O O O O -

Timers (TIMx) O O O O -

--------

OOO- ----

--------

Low-power timer 1, 3 (LPTIM1 and

OOOOO

OOO- ----

LPTIM3)

Low-power timer 2 (LPTIM2)

Independent watchdog (IWDG)

OOOOOO- ------

OOOOO

OOOOO- --

46/323 DS12736 Rev 2

STM32L562xx Functional overview

Table 11. Functionalities depending on the working mode

(1)

(continued)

Stop 0/1 Stop 2 Standby Shutdown

Peripheral Run Sleep

Window watchdog (WWDG)

OOOO-

Low-

power

run

Low-

power

sleep

Wakeup capability

--------

VBAT

Wakeup capability

SysTick timer O O O O - --------

Touch sensing controller (TSC)

Random number generator (RNG)

AES hardware accelerator

HASH hardware accelerator

OOOO---------

(8)

OOOO-

(8)

-----------

--------

PKA O O O O - --------

CRC calculation unit

OOOO---------

GPIOs OOOOOOOO

1. Legend: Y = yes (enable). O = optional (disable by default, can be enabled by software). - = not available. Gray cells highlight the wakeup capability in each mode.

2. The Flash can be configured in Power-down mode. By default, it is not in Power-down mode.

3. The SRAM clock can be gated on or off.

4. 4 Kbytes or full SRAM2 content is preserved depending on RRS[1:0] bits configuration in PWR_CR3 register.

5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not need it anymore.

6. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event.

7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.

8. Voltage scaling ranges 0 and 1 only.

9. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.

10. The I/Os with wakeup from standby/shutdown capability are: PA0, PC13, PE6, PA2, PC5.

11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode.

(9)

pins

(10)

(11)

pins

(10)

3.9.6 Reset mode

In order to improve the consumption under reset, the I/Os state under and after reset is “analog state” (the I/O schmitt trigger is disable). In addition, the internal reset pull-up is deactivated when the reset source is internal.

DS12736 Rev 2 47/323

Functional overview STM32L562xx

3.9.7 VBAT operation

The VBAT pin allows to power the device VBAT domain from an external battery, an external supercapacitor, or from V

when there is no external battery and when an external

supercapacitor is present. The VBAT pin supplies the RTC with LSE and the backup registers. Three anti-tamper detection pins are available in VBAT mode.

The VBAT operation is automatically activated when VDD is not present. An internal VBAT battery charging circuit is embedded and can be activated when V

is present.

Note: When the microcontroller is supplied from VBAT, neither external interrupts nor RTC

alarm/events exit the microcontroller from the VBAT operation.

3.9.8 PWR TrustZone security

When the TrustZone security is activated by the TZEN option bit, the PWR is switched in TrustZone security mode.

The PWR TrustZone security allows to secure the following configuration:

• Low-power mode

• Wake-up (WKUP) pins

• Voltage detection and monitoring

• VBAT mode

Other PWR configuration bits are secure when:

• The system clock selection is secure in RCC, the voltage scaling (VOS) configuration is secure

• A GPIO is configured as secure, it's corresponding bit for Pull-up/Pull-down in standby mode is secure

• The RTC is secure, the backup domain write protection bit in PWR is secure.

3.10 Peripheral interconnect matrix

Several peripherals have direct connections between them, which allow autonomous communication between them and support the saving of CPU resources (thus power supply consumption). In addition, these hardware connections allow fast and predictable latency.

Depending on the peripherals, these interconnections can operate in Run, Sleep, Lowpower run and Sleep, Stop 0, Stop 1 and Stop 2 modes. See

Tab le 12 for more details.

48/323 DS12736 Rev 2

STM32L562xx Functional overview

Table 12. STM32L562xx peripherals interconnect matrix

Interconnect source

Interconnect

destination

Interconnect action

Run

Sleep

Low-power run

Stop 0 / Stop 1

Low-power sleep

TIMx Timers synchronization or chaining Y Y Y Y - -

ADC

TIMx

DAC1 DFSDM1

Conversion triggers Y Y Y Y - -

DMA Memory to memory transfer trigger Y Y Y Y - -

COMPx Comparator output blanking Y Y Y Y - -

TIM1, 8 TIM2, 3

Timer input channel, trigger, break from analog signals comparison

YYYY - -

COMPx

LPTIMERx

Low-power timer triggered by analog signals comparison

YYYYY

ADCx TIM1, 8 Timer triggered by analog watchdog Y Y Y Y - -

TIM16 Timer input channel from RTC events Y Y Y Y - -

RTC

All clocks sources (internal and external)

LPTIMERx

TIM2 TIM15, 16, 17

Low-power timer triggered by RTC alarms or tampers

Clock source used as input channel for RC measurement and trimming

YYYYY

YYYY - -

Stop 2

(1)

USB TIM2 Timer triggered by USB SOF Y Y - - - -

CSS CPU (hard fault) RAM (parity error) Flash memory (ECC error) COMPx

TIM1,8 TIM15,16,17

Timer break Y Y Y Y - -

PVD DFSDM1 (analog

watchdog, short circuit detection)

TIMx External trigger Y Y Y Y - -

LPTIMERx External trigger Y Y Y Y Y

GPIO

ADC DAC1

Conversion external trigger Y Y Y Y - -

DFSDM1

1. LPTIM1 and LPTIM3 only.

(1)

DS12736 Rev 2 49/323

Functional overview STM32L562xx

3.11 Reset and clock controller (RCC)

The clock controller (see Figure 7) distributes the clocks coming from the different oscillators to the core and to the peripherals. It also manages the clock gating for low-power modes and ensures the clock robustness. It features:

• Clock prescaler: to get the best trade-off between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler.

• Clock security system: clock sources can be changed safely on the fly in Run mode through a configuration register.

• Clock management: to reduce the power consumption, the clock controller can stop the clock to the core, individual peripherals or memory.

• System clock source: four different clock sources can be used to drive the master clock SYSCLK:

– 4 to 48 MHz high-speed external crystal or ceramic resonator (HSE), that can

supply a PLL. The HSE can also be configured in bypass mode for an external clock.

– 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software, that can

supply a PLL

– Multispeed internal RC oscillator (MSI), trimmable by software, able to generate

12 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is available in the system (LSE), the MSI frequency can be automatically trimmed by hardware to reach better than ±0.25% accuracy. In this mode the MSI can feed the USB device, saving the need of an external high-speed crystal (HSE). The MSI can supply a PLL.

– System PLL which can be fed by HSE, HSI16 or MSI, with a maximum frequency

at 110 MHz.

• RC48 with clock recovery system (HSI48): internal 48 MHz clock source (HSI48)can be used to drive the USB, the SDMMC or the RNG peripherals. This clock can be output on the MCO.

• UCPD kernel clock: it is derived from HSI16 clock. The HSI16 RC oscillator must be enabled prior to the UCPD kernel clock use.

• Auxiliary clock source: two ultra-low-power clock sources that can be used to drive the real-time clock:

– 32.768 kHz low-speed external crystal (LSE), supporting four drive capability

modes. The LSE can also be configured in bypass mode for an external clock.

– 32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.

The LSI clock accuracy is ±5% accuracy. The LSI clock can be divided by 128 to output a 250 Hz as source clock.

• Peripheral clock sources: several peripherals (USB, SDMMC, RNG, SAI, USARTs, I2Cs, LPTimers, ADC) have their own independent clock whatever the system clock. Three PLLs, each having three independent outputs allowing the highest flexibility, can generate independent clocks for the ADC, the USB/SDMMC/RNG and the two SAIs.

• Startup clock: after reset, the microcontroller restarts by default with an i clock (MSI). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts.

• Clock security system (CSS): this feature can be enabled by software. If a HSE clock failure occurs, the master clock is automatically switched to HSI16 and a software

nternal 4 MHz

50/323 DS12736 Rev 2

STM32L562xx Functional overview

interrupt is generated if enabled. LSE failure can also be detected and generated an interrupt.

• Clock-out capability: – MCO (microcontroller clock output): it outputs one of the internal clocks for

external use by the application

– LSCO (low-speed clock output): it outputs LSI or LSE in all low-power modes

(except VBAT).

Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 110

MHz.

DS12736 Rev 2 51/323

Functional overview STM32L562xx

MSv49302V2

SYSCLK

MCO

LSCO

PLL

SAI2_EXTCLK

48 MHz clock to USB, RNG

to ADC

to IWDG

to RTC

to PWR

HCLK

to AHB bus, core, memory and DMA

FCLK Cortex free running clock

to Cortex system timer

to APB1 peripherals

to APB2 peripherals

PCLK1

PCLK2

to SAI1

to SAI2

LSE

HSI16

SYSCLK

to USARTx

X=2..5

to LPUART1

to I2Cx

x=1,2,3,4

to LPTIMx

x=1,2

SAI1_EXTCLK

to TIMx

x=2..7

OSC32_OUT

OSC32_IN

MSI HSI16 HSE

HSE

MSI

HSI16

MSI

SYSCLK

LSE OSC

32.768 kHz

/32

AHB PRESC

/ 1,2,..512

/ 8

APB1 PRESC

/ 1,2,4,8,16

x1 or x2

HSI16

SYSCLK

LSI

LSE

HSI16

APB2 PRESC

/ 1,2,4,8,16

to TIMx

x=1,8,15,16,17

x1 or x2

USART1

LSE

HSI16

SYSCLK

/ P

/ Q

/ R

PLLSAI1

/ P

/ Q

/ R

/ M

MSI RC

100 kHz – 48 MHz

HSI RC

16 MHz

HSE OSC

4-48 MHz

Clock

detector

OSC_OUT

OSC_IN

/ 1→16

LSI RC 32 kHz

Clock

source

control

PLLSAI3CLK

PLL48M1CLK

PLLCLK

PLLSAI1CLK

PLL48M2CLK

PLLADC1CLK

PLLSAI2CLK

HSI16

PLLSAI2

/ P

/ Q

/ R

HSI16

LSI

LSE

HSE SYSCLK

PLLCLK HSI48

MSI

OCTOSPI clock

MSI

HSI16

DFSDM audio clock

SDMMC clock

/ M

RC 48 MHz

CRS clock

FDCAN

HSE

MSI HSI16 HSE

To UCPD1

HSI16

MHz

Figure 7. STM32L562xx clock tree

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STM32L562xx Functional overview

TrustZone security

When the TrustZone security is activated by the TZEN option bit, the RCC is switched in TrustZone security mode.

The RCC TrustZone security allows to secure some RCC system configuration and peripheral configuration clock from being read or modified by non-secure accesses:

• RCC system security: – HSE, HSE-CSS, HSI, MSI, LSI, LSE, LSE-CSS, HSI48 configuration and status

bits – Main PLL, PLLSAI1, PLLSAI2, AHB prescaler configuration and status bits – System clock SYSCLK and HSI48 source clock selection and status bits – MCO clock output configuration and STOPWUCK bit – Reset flag RMVF configuration bit

• RCC peripheral security: – When a peripheral is secure, the related peripheral clock, reset, clock source

selection and clock enable during low power modes control bits are secure.

• A peripheral is in secure state when: – For securable peripherals, when it's corresponding SEC security bit is set in the

TZSC (TrustZone security controller)

– For TrustZone-aware peripherals, a security feature of this peripheral is enabled

through its dedicated bits.

3.12 Clock recovery system (CRS)

The devices embed a special block which allows automatic trimming of the internal 48 MHz oscillator to guarantee its optimal accuracy over the whole device operational range. This automatic trimming is based on the external synchronization signal, which could be either derived from USB SOF signalization, from LSE oscillator, from an external signal on CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also possible to combine automatic trimming with manual trimming action.

3.13 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions.

After reset, all GPIOs are in Analog mode to reduce power consumption. The I/Os alternate function configuration can be locked if needed following a specific

sequence in order to avoid spurious writing to the I/Os registers.

GPIO TrustZone security

Each I/O pin of GPIO port can be individually configured as secure. When the selected I/O pin is configured as secure, its corresponding configuration bits for alternate function, mode selection, I/O data are secure against a non-secure access. The associated registers bit access is restricted to a secure software only. After reset, all GPIO ports are secure.

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Functional overview STM32L562xx

MSv49331V1

CORTEX

-M33

with TrustZone and FPU

DMA1 DMA2

S-bus

Fast-bus

SDMMC1

Slow-bus

BusMatrix-S

8 KB I-Cache

C-bus

MPCBB1

MPCBB2

MPCWM1

MPCWM2 MPCWM3

OctoSPI1

AHB2

peripherals

AHB1

peripherals

SRAM2

SRAM1

FLASH

512 KB

FSMC

OTFDEC

MPCBBx: Memory protection controller block based

Bus multiplexer

Legend

Master Interface

Slave Interface

MPCWMx: Memory protection controller Watermark

3.14 Multi-AHB bus matrix

The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, SDMMC1) and the slaves (Flash memory, RAM, FMC, OCTOSPI, AHB and APB peripherals). It also ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously.

Figure 8. Multi-AHB bus matrix

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STM32L562xx Functional overview

3.15 Direct memory access controller (DMA)

The device embeds 2 DMAs. Refer to Ta b le 13: DMA1 and DMA2 implementation for the features implementation.

Direct memory access (DMA) is used in order to provide a high-speed data transfer between peripherals and memory as well as from memory to memory. Data can be quickly moved by DMA without any CPU actions. This keeps the CPU resources free for other operations.

The two DMA controllers have 16 channels in total, each one dedicated to manage memory access requests from one or more peripherals. Each controller has an arbiter for handling the priority between DMA requests.

The DMA supports 8 channels for each DMA1 and DMA2, independently configurable:

• Each channel is associated either with a DMA request signal coming from a peripheral, or with a software trigger in memory-to-memory transfers. This configuration is done by software.

• Priority between the requests is programmable by software (4 levels per channel: very high, high, medium, low) or by hardware in case of equality (such as request 1 has priority over request 2).

• Transfer size of source and destination are independent (byte, half-word, word), emulating packing and unpacking. Source and destination addresses must be aligned on the data size.

• Support of transfers from/to peripherals to/from memory with circular buffer management.

• Programmable number of data to be transferred: 0 to 2

• Generation of an interrupt request per channel. Each interrupt request is caused from

any of the three DMA events: transfer complete, half transfer, or transfer error.

• TrustZone support: – Support for AHB secure and non-secure DMA transfers, independently at a first

channel level, and independently at a source and destination sub-level

– TrustZone-aware AHB slave port, protecting any secure resource (register,

• Privileged / unprivileged support: – Support for AHB privileged and unprivileged DMA transfers, independently at a

channel level

– Privileged-aware AHB slave port.

Table 13. DMA1 and DMA2 implementation

- 1.

Feature DMA1 DMA2

Number of DMA channels 8 8

TrustZone 1 (supported) 1 (supported)

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Functional overview STM32L562xx

3.16 DMA request router (DMAMUX)

When a peripheral indicates a request for DMA transfer by setting its DMA request line, the DMA request is pending until it is served and the corresponding DMA request line is reset. The DMA request router allows to route the DMA control lines between the peripherals and the DMA controllers of the product.

An embedded multi-channel DMA request generator can be considered as one of such peripherals. The routing function is ensured by a multi-channel DMA request line multiplexer. Each channel selects a unique set of DMA control lines, unconditionally or synchronously with events on synchronization inputs.

DMAMUX main features

• 16-channel programmable DMA request line multiplexer output

• 4-channel DMA request generator

• 23 trigger inputs to DMA request generator

• 23 synchronization inputs

• Per DMA request generator channel:

– DMA request trigger input selector – DMA request counter – Event overrun flag for selected DMA request trigger input

• Per DMA request line multiplexer channel output: – 90 input DMA request lines from peripherals – One DMA request line output – Synchronization input selector – DMA request counter – Event overrun flag for selected synchronization input – One event output, for DMA request chaining

• TrustZone support: – Support for AHB secure and non-secure DMA transfers, independently at a

channel level.

– TrustZone-aware AHB slave port, protecting any secure resource (register,

– Two secure and non-secure interrupt requests, resulting from any of the

respectively secure and non-secure channels. Each channel event being caused from any of the two DMAMUX input events: trigger or synchronization overrun, associated with a respectively secure and non-secure channels.

• Privileged / Unprivileged support: – Support for AHB privileged and unprivileged DMA transfers, independently, at a

channel level.

– Privileged-aware AHB slave port.

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3.17 Interrupts and events

3.17.1 Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller which is able to manage 8 priority levels, and to handle up to 109 maskable interrupt channels plus the 16 interrupt lines of the

Cortex The NVIC benefits are the following:

• Closely coupled NVIC gives low latency interrupt processing

• Interrupt entry vector table address passed directly to the core

• Allows early processing of interrupts

• Processing of late arriving higher priority interrupts

• Support for tail chaining

• Processor state automatically saved

• Interrupt entry restored on interrupt exit with no instruction overhead

• TrustZone support. The NVIC registers are banked across secure and non-secure

The NVIC hardware block provides flexible interrupt management features with minimal interrupt latency.

-M33.

states

3.17.2 Extended interrupt/event controller (EXTI)

The Extended interrupts and event controller (EXTI) manages the individual CPU and system wakeup through configurable and direct event inputs. It provides wakeup requests to the power control, and generates an interrupt request to the CPU NVIC and events to the CPU event input. For the CPU an additional Event Generation block (EVG) is needed to generate the CPU event signal.

The EXTI wakeup requests allow the system to be woken up from Stop modes. The interrupt request and event request generation can also be used in RUN modes. The

EXTI also includes the EXTI mux IOport selection. The EXTI main features are the following: The EXTI main features are the following:

• 43 input events supported

• All event inputs allow to wake up the system.

• Events which do not have an associated wakeup flag in the peripheral, have a flag in

the EXTI and generate an interrupt to the CPU from the EXTI.

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Functional overview STM32L562xx

The asynchronous event inputs are classified in 2 groups:

• Configurable events (signals from I/Os or peripherals able to generate a pulse) – Configurable events have the following features:

Selectable active trigger edge Interrupt pending status register bit independent for the rising and falling edge. Individual interrupt and event generation mask, used for conditioning the CPU wakeup, interrupt and event generation. SW trigger possibility

• Direct events (interrupt and wakeup sources from peripherals having an associated flag which requiring to be cleared in the peripheral)

– Direct events have the following features:

Fixed rising edge active trigger No interrupt pending status register bit in the EXTI. (The interrupt pending status flag is provided by the peripheral generating the event.) Individual interrupt and event generation mask, used for conditioning the CPU wakeup and event generation. No SW trigger possibility

• TrustZone secure events – The access to control and configuration bits of secure input events can be made

secure.

• EXTI IO port selection

3.18 Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator with polynomial value and size.

Among other applications, the CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a mean to verify the Flash memory integrity.

The CRC calculation unit helps to compute a signature of the software during runtime, which can be ulteriorly compared with a reference signature generated at link-time and which can be stored at a given memory location.

3.19 Flexible static memory controller (FSMC)

The flexible static memory controller (FSMC) includes two memory controllers:

• The NOR/PSRAM memory controller

• The NAND/memory controller

This memory controller is also named flexible memory controller (FMC).

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STM32L562xx Functional overview

The main features of the FSMC controller are the following:

• Interface with static-memory mapped devices including: – Static random access memory (SRAM) – NOR Flash memory/OneNAND Flash memory – PSRAM (four memory banks) – NAND Flash memory with ECC hardware to check up to 8 Kbytes of data – Ferroelectric RAM (FRAM)

• 8-,16- bit data bus width

• Independent chip select control for each memory bank

• Independent configuration for each memory bank

• Write FIFO

LCD parallel interface

The FMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost effective graphic applications using LCD modules with embedded controllers or highperformance solutions using external controllers with dedicated acceleration.

TrustZone security

When the TrustZone security is enabled, the whole FSMC banks are secure after reset. Non-secure area can be configured using the TZSC MPCWMx controller.

• The FSMC NOR/PSRAM bank: – Up to two non-secure area can be configured thought the TZSC MPCWM2

controller with a granularity of 64 Kbytes.

• The FSMC NAND bank: – Can be either configured as fully secure or fully non-secure using the TZSC

MPCWM3 controller.

The FSMC registers can be configured as secure through the TZSC controller.

3.20 Octo-SPI interface (OCTOSPI)

The OCTOSPI is a specialized communication interface targetting single, dual, quad or octal SPI memories. It can operate in any of the three following modes:

• Indirect mode: all the operations are performed using the OCTOSPI registers

• Status polling mode: the external memory status register is periodically read and an

interrupt can be generated in case of flag setting

• Memory-mapped mode: the external memory is memory mapped and is seen by the system as if it were an internal memory supporting read and write operation

The OCTOSPI supports two frame formats:

• Classical frame format with command, address, alternate byte, dummy cycles and data phase over 1, 2, 4 or 8 data pins

• HyperBus

The OCTOSPI offers the following features:

frame format

DS12736 Rev 2 59/323

Functional overview STM32L562xx

• Three functional modes: indirect, status-polling, and memory-mapped

• Read and write support in memory-mapped mode

• Supports for single, dual, quad and octal communication

• Dual-quad mode, where 8 bits can be sent/received simultaneously by accessing two

quad memories in parallel.

• SDR and DTR support

• Data strobe support

• Fully programmable opcode for both indirect and memory mapped mode

• Fully programmable frame format for both indirect and memory mapped mode

• Each of the five following phases can be configured independently (enable, length,

single/dual/quad communication) – Instruction phase – Address phase – Alternate bytes phase – Dummy cycles phase – Data phase

• HyperBus

support

• Integrated FIFO for reception and transmission

• 8, 16, and 32-bit data accesses are allowed

• DMA channel for indirect mode operations

• Timeout management

• Interrupt generation on FIFO threshold, timeout, status match, operation complete, and

access error

TrustZone security

When the TrustZone security is enabled, the whole OCTOSPI bank is secure after reset. Up to two non-secure area can be configured thought the TZSC MPCWM1 controller with a

granularity of 64 Kbytes. The OCTOSPI registers can be configured as secure through the TZSC controller.

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STM32L562xx Functional overview

3.21 Analog-to-digital converter (ADC)

The device embeds two successive approximation analog-to-digital converters with the following features:

• 12-bit native resolution, with built-in calibration

• 5.33 Msps maximum conversion rate with full resolution

– Down to 18.75 ns sampling time – Increased conversion rate for lower resolution (up to 8.88 Msps for 6-bit

resolution)

• Up to 16 external channels

• 5 internal channels: internal reference voltage, temperature sensor, VBAT/3 and DAC1

outputs

• One external reference pin is available on some package, allowing the input voltage range to be independent from the power supply

• Single-ended and differential mode inputs

• Low-power design

– Capable of low-current operation at low conversion rate (consumption decreases

linearly with speed)

– Dual clock domain architecture: ADC speed independent from CPU frequency

• Highly versatile digital interface – Single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups

of analog signals conversions can be programmed to differentiate background and high-priority real-time conversions

– Each ADC support multiple trigger inputs for synchronization with on-chip timers

and external signals – Results stored into a data register or in RAM with DMA controller support – Data pre-processing: left/right alignment and per channel offset compensation – Built-in oversampling unit for enhanced SNR – Channel-wise programmable sampling time – Analog watchdog for automatic voltage monitoring, generating interrupts and

trigger for selected timers – Hardware assistant to prepare the context of the injected channels to allow fast

context switching

3.21.1 Temperature sensor

The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature. The temperature sensor is internally connected to the ADC1_IN17 input channels which is used to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only.

To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode.

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Functional overview STM32L562xx

Table 14. Temperature sensor calibration values

Calibration value name Description Memory address

TS ADC raw data acquired at a

TS_CAL1

temperature of 30 °C (± 5 °C), V

DDA

TS ADC raw data acquired at a

TS_CAL2

temperature of 110 °C (± 5 °C), V

DDA

3.21.2 Internal voltage reference (V

The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC and the comparators. The VREFINT is internally connected to the ADC1_IN0 input channel. The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode.

Calibration value name Description Memory address

Table 15. Internal voltage reference calibration values

Raw data acquired at a

VREFINT

temperature of 30 °C (± 5 °C), V

DDA

= V

REF+

= V

REF+

REFINT

= V

REF+

0x0BFA 05A8 - 0x0BFA 05A9

= 3.0 V (± 10 mV)

0x0BFA 05CA- 0x0BFA 05CB

= 3.0 V (± 10 mV)

)

0x0BFA 05AA - 0x0BFA 05AB

= 3.0 V (± 10 mV)

3.21.3 V

This embedded hardware enables the application to measure the V the internal ADC channel ADC1_IN18. As the V and thus outside the ADC input range, the VBAT pin is internally connected to a bridge divider by 3. As a consequence, the converted digital value is one third of the V

battery voltage monitoring

BAT

battery voltage using

voltage may be higher than the VDDA,

BAT

voltage.

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STM32L562xx Functional overview

MSv40197V1

VREFBUF

Low frequency cut-off capacitor

DAC, ADC

Bandgap +

DDA

100 nF

VREF+

3.22 Digital to analog converter (DAC)

Two 12-bit buffered DAC channels can be used to convert digital signals into analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration.

This digital interface supports the following features:

• Up to two DAC output channels

• 8-bit or 12-bit output mode

• Buffer offset calibration (factory and user trimming)

• Left or right data alignment in 12-bit mode

• Synchronized update capability

• Noise-wave generation

• Triangular-wave generation

• Dual DAC channel independent or simultaneous conversions

• DMA capability for each channel

• External triggers for conversion

• Sample and hold low-power mode, with internal or external capacitor

The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels.

3.23 Voltage reference buffer (VREFBUF)

The devices embed a voltage reference buffer which can be used as voltage reference for ADC, DACs and also as voltage reference for external components through the VREF+ pin.

The internal voltage reference buffer supports two voltages:

• 2.048 V

• 2.5 V

An external voltage reference can be provided through the VREF+ pin when the internal voltage reference buffer is off.

The VREF+ pin is double-bonded with VDDA on some packages. In these packages the internal voltage reference buffer is not available.

Figure 9. Voltage reference buffer

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Functional overview STM32L562xx

3.24 Comparators (COMP)

The devices embed two rail-to-rail comparators with programmable reference voltage (internal or external), hysteresis and speed (low speed for low-power) and with selectable output polarity.

The reference voltage can be one of the following:

• External I/O

• DAC output channels

• Internal reference voltage or submultiple (1/4, 1/2, 3/4).

All comparators can wake up from Stop mode, generate interrupts and breaks for the timers and can also be combined into a window comparator.

3.25 Operational amplifier (OPAMP)

The devices embed two operational amplifiers with external or internal follower routing and PGA capability.

The operational amplifier features:

• Low input bias current

• Low offset voltage

• Low-power mode

• Rail-to-rail input

3.26 Digital filter for sigma-delta modulators (DFSDM)

The devices embed one DFSDM with four digital filters modules and eight external input serial channels (transceivers) or alternately eight internal parallel inputs support.

The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to the microcontroller and then to perform digital filtering of the received data streams (which represent analog value on Σ∆ modulators inputs).

The DFSDM can also interface the PDM (pulse density modulation) microphones and perform PDM to PCM conversion and filtering in hardware. The DFSDM features optional parallel data stream inputs from microcontrollers memory (through DMA/CPU transfers into DFSDM).

The DFSDM transceivers support several serial interface formats (to support various Σ∆ modulators) and the DFSDM digital filter modules perform digital processing according to the user’s selected filter parameters with up to 24-bit final ADC resolution.

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STM32L562xx Functional overview

The DFSDM peripheral supports:

• Up to 4 multiplexed input digital serial channels: – Configurable SPI interface to connect various ΣΔ modulators – Configurable Manchester coded 1 wire interface support – Clock output for ΣΔ modulator(s)

• Alternative inputs from up to 4 internal digital parallel channels: – Inputs with up to 16 bit resolution – Internal sources: ADCs data or memory (CPU/DMA write) data streams

• Adjustable digital signal processing: – Sincx filter: filter order/type (1..5), oversampling ratio (up to 1..1024) – Integrator: oversampling ratio (1..256)

• Up to 24-bit output data resolution: – Right bit-shifter on final data (0..31 bits)

• Signed output data format

• Automatic data offset correction (offset stored in register by user)

• Continuous or single conversion

• Start-of-conversion synchronization with:

– Software trigger – Internal timers – External events – Start-of-conversion synchronously with first DFSDM filter (DFSDM_FLT0)

• Analog watchdog feature: – Low value and high value data threshold registers – Own configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32) – Input from output data register or from one or more input digital serial channels – Continuous monitoring independently from standard conversion

• Short-circuit detector to detect saturated analog input values (bottom and top ranges): – Up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on input data stream – Mnitoring continuously each channel (4 serial channel transceiver outputs)

• Break generation on analog watchdog event or short-circuit detector event

• Extremes detector:

– Store minimum and maximum values of output data values – Refreshed by software

• DMA may be used to read the conversion data

• Interrupts: end of conversion, overrun, analog watchdog, short-circuit, channel clock

absence

• “Regular” or “injected” conversions: – “Regular” conversions can be requested at any time or even in continuous mode

without having any impact on the timing of “injected” conversions.

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Functional overview STM32L562xx

3.27 Touch sensing controller (TSC)

The touch sensing controller provides a simple solution to add capacitive sensing functionality to any application. A capacitive sensing technology is able to detect finger presence near an electrode that is protected from direct touch by a dielectric (glass, plastic or other). The capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle.

The touch sensing controller is fully supported by the STMTouch touch sensing firmware library which is free to use and allows touch sensing functionality to be implemented reliably in the end application.

The main features of the touch sensing controller are the following:

• Proven and robust surface charge transfer acquisition principle

• Supports up to 22 capacitive sensing channels

• Up to 3 capacitive sensing channels can be acquired in parallel offering a very good

response time

• Spread spectrum feature to improve system robustness in noisy environments

• Full hardware management of the charge transfer acquisition sequence

• Programmable charge transfer frequency

• Programmable sampling capacitor I/O pin

• Programmable channel I/O pin

• Programmable max count value to avoid long acquisition when a channel is faulty

• Dedicated end of acquisition and max count error flags with interrupt capability

• One sampling capacitor for up to 3 capacitive sensing channels to reduce the system

components

• Compatible with proximity, touchkey, linear and rotary touch sensor implementation

• Designed to operate with STMTouch touch sensing firmware library

Note: The number of capacitive sensing channels is dependent on the size of the packages and

subject to I/O availability.

3.28 Random number generator (RNG)

All devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit.

3.29 Advanced encryption standard hardware accelerator (AES)

The devices embed an AES hardware accelerator that can be used both to encipher and to decipher data using an AES algorithm.

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The AES peripheral supports:

• Encryption/decryption using AES Rijndael block cipher algorithm

• NIST FIPS 197 compliant implementation of AES encryption/decryption algorithm

• 128-bit and 256-bit register for storing the encryption, decryption or derivation key (4x

32-bit registers)

• Electronic codebook (ECB), cipher block chaining (CBC), Counter mode (CTR), Galois Counter Mode (GCM), Galois Message Authentication Code mode (GMAC) and Cipher Message Authentication Code mode (CMAC) supported

• Key scheduler

• Key derivation for decryption

• 128-bit data block processing

• 128-bit, 256-bit key length

• 1x32-bit INPUT buffer and 1x32-bit OUTPUT buffer

• Register access supporting 32-bit data width only

• One 128-bit Register for the initialization vector when AES is configured in CBC mode

or for the 32-bit counter initialization when CTR mode is selected, GCM mode or CMAC mode

• Automatic data flow control with support of direct memory access (DMA) using 2 channels, one for incoming data, and one for out coming data

• Suspend a message if another message with a higher priority needs to be processed.

3.30 HASH hardware accelerator (HASH)

The hash processor is a fully compliant implementation of the secure hash algorithm (SHA1, SHA-224, SHA-256), the MD5 (message-digest algorithm 5) hash algorithm and the HMAC (keyed-hash message authentication code) algorithm suitable for a variety of applications.

It computes a message digest (160 bits for the SHA-1 algorithm, 256 bits for the SHA-256 algorithm and 224 bits for the SHA-224 algorithm,128 bits for the MD5 algorithm) for messages of up to (264 - 1) bits, while the HMAC algorithms provide a way of authenticating messages by means of hash functions. The HMAC algorithms consist in calling the SHA-1, SHA-224, SHA-256 or MD5 hash function twice.

3.31 Public key accelerator PKA

The public key accelerator (PKA) is intended for the computation of cryptographic public key primitives, specifically those related to RSA, Diffie-Hellmann or ECC (elliptic curve cryptography) over GF(p) (Galois fields). To achieve high performance at a reasonable cost, these operations are executed in the Montgomery domain.

All needed computations are performed within the accelerator, so no further hardware/software elaboration is needed to process the inputs or the outputs.

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Functional overview STM32L562xx

PKA main features:

• Acceleration of RSA, DH and ECC over GF(p) operations, based on the Montgomery method for fast modular multiplications. More specifically:

– RSA modular exponentiation, RSA Chinese remainder theorem (CRT)

exponentiation – ECC scalar multiplication, point on curve check – ECDSA signature generation and verification

• Capability to handle operands up to 3136 bits for RSA/DH and 640 bits for ECC.

• Arithmetic and modular operations such as addition, subtraction, multiplication,

modular reduction, modular inversion, comparison, and Montgomery multiplication.

• Built-in Montgomery domain inward and outward transformations

• AMBA AHB slave peripheral, accessible through 32-bit word single accesses only

(otherwise, for writes, an AHB bus error is generated, and write accesses are ignored)

3.32 On-the-fly decryption engine (OTFDEC)

The embedded OTFDEC decrypts in real-time the encrypted content stored in the external Octo-SPI memories used in Memory-mapped mode.

The OTFDEC uses the AES-128 algorithm in counter mode (CTR). The OTFDEC main features are the following:

• Zero latency 128-bit decryption during STM32 AHB OCTOSPI read operations (single or multiple).

– Minimum read granularity is 8-bit, maximum is 512-bit – AES-CTR algorithm

• Up to four independent encrypted regions – Granularity of the region definition: 4096 bytes – Region configuration write locking mechanism – Option to condition data decryption on instruction fetches only.

• 128-bit data decryption specific to each protected region. – Each region has its firmware version (two bytes), its 128-bit key and a fixed 64-bit

nonce.

– Keystream based on the data system address

• Encryption keys confidentiality and integrity protection – Write only registers, with software locking mechanism

• Support for STM32 OCTOSPI pre-fetching mechanism. – AES-CTR keystream FIFO (depth=2)

• Possibility to select an enhanced encryption mode to add a proprietary layer of protection on top of AES stream cipher.

3.33 Timers and watchdogs

The devices include two advanced control timers, up to nine general-purpose timers, two basic timers, two low-power timers, two watchdog timers and a SysTick timer.

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The Tabl e 16 below compares the features of the advanced control, general-purpose and basic timers.

Table 16. Timer feature comparison

Timer type Timer

Advanced

control

General-

purpose

General-

purpose

General-

purpose

General-

purpose

Basic TIM6, TIM7 16-bit Up

TIM1, TIM8 16-bit

TIM2, TIM5 32-bit

TIM3, TIM4 16-bit

TIM15 16-bit Up

TIM16, TIM17 16-bit Up

Counter

resolution

Counter

type

Up, down,

Up/down

Up, down,

Up/down

Up, down,

Up/down

Prescaler

factor

Any integer

between 1

and 65536

Any integer

between 1

and 65536

Any integer

between 1

and 65536

Any integer

between 1

and 65536

Any integer

between 1

and 65536

Any integer

between 1

and 65536

DMA

request

generation

Yes 4 3

Yes 4 No

Yes 2 1

Yes 1 1

Yes 0 No

Capture/

compare

channels

Complementary

outputs

3.33.1 Advanced-control timer (TIM1, TIM8)

The advanced-control timers can each be seen as a three-phase PWM multiplexed on six channels. They have complementary PWM outputs with programmable inserted deadtimes. They can also be seen as complete general-purpose timers.

The four independent channels can be used for:

• Input capture

• Output compare

• PWM generation (edge or center-aligned modes) with full modulation capability (0-

100%)

• One-pulse mode output

In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled in order to turn off any power switches driven by these outputs.

Many features are shared with the general-purpose TIMx timers (described in

Section 3.33.2) using the same architecture, so the advanced-control timers can work

together with the TIMx timers via the Timer Link feature for synchronization or event chaining.

DS12736 Rev 2 69/323

Functional overview STM32L562xx

3.33.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16, TIM17)

There are up to seven synchronizable general-purpose timers embedded in the STM32L562xx devices (see Tab le Each general-purpose timer can be used to generate PWM outputs, or act as a simple time base.

• TIM2, TIM3, TIM4 and TIM5

They are full-featured general-purpose timers: – TIM2 and TIM5 have a 32-bit auto-reload up/downcounter and 32-bit prescaler – TIM3 and TIM4 have 16-bit auto-reload up/downcounter and 16-bit prescaler. These timers feature four independent channels for input capture/output compare,

PWM or one-pulse mode output. They can work together, or with the other generalpurpose timers via the Timer Link feature for synchronization or event chaining.

The counters can be frozen in debug mode. All have independent DMA request generation and support quadrature encoders.

• TIM15, 16 and 17

They are general-purpose timers with mid-range features: They have 16-bit auto-reload upcounters and 16-bit prescalers. – TIM15 has two channels and one complementary channel – TIM16 and TIM17 have one channel and one complementary channel All channels can be used for input capture/output compare, PWM or one-pulse mode

output. The timers can work together via the Timer Link feature for synchronization or event

chaining. The timers have independent DMA request generation. The counters can be frozen in debug mode.

16 for differences).

3.33.3 Basic timers (TIM6 and TIM7)

The basic timers are mainly used for DAC trigger generation. They can also be used as generic 16-bit timebases.

3.33.4 Low-power timers (LPTIM1, LPTIM2 and LPTIM3)

The devices embed two low-power timers. These timers have an independent clock and are running in Stop mode if they are clocked by LSE, LSI or an external clock. They are able to wakeup the system from Stop mode.

LPTIM1 and LPTIM3 are active in Stop 0, Stop 1 and Stop 2 modes. LPTIM2 is active in Stop 0 and Stop 1 mode.

70/323 DS12736 Rev 2

STM32L562xx Functional overview

This low-power timer supports the following features:

• 16-bit up counter with 16-bit autoreload register

• 16-bit compare register

• Configurable output: pulse, PWM

• Continuous/ one shot mode

• Selectable software/hardware input trigger

• Selectable clock source

– Internal clock sources: LSE, LSI, HSI16 or APB clock – External clock source over LPTIM input (working even with no internal clock

source running, used by pulse counter application).

• Programmable digital glitch filter

• Encoder mode (LPTIM1 only).

3.33.5 Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and an 8-bit prescaler. It is clocked from an independent 32 from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.

kHz internal RC (LSI) and as it operates independently

3.33.6 Window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

3.33.7 SysTick timer

The Cortex®-M33 with TrustZone embeds two SysTick timers. When TrustZone is activated, two SysTick timer are available:

• SysTick, Secure instance.

• SysTick, Non-secure instance.

When TrustZone is disabled, only one SysTick timer is available. This timer (secure or non-secure) is dedicated to real-time operating systems, but could

also be used as a standard down counter. It features:

• A 24-bit down counter

• Autoreload capability

• Maskable system interrupt generation when the counter reaches 0.

• Programmable clock source

DS12736 Rev 2 71/323

Functional overview STM32L562xx

3.34 Real-time clock (RTC)

The RTC supports the following features:

• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,

month, year, in BCD (binary-coded decimal) format.

• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.

• Two programmable alarms.

• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to

synchronize it with a master clock.

• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be

used to enhance the calendar precision.

• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal

inaccuracy.

• Timestamp feature which can be used to save the calendar content. This function can

be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to V

mode.

BAT

• 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable

resolution and period.

• TrustZone support:

– RTC fully securable – Alarm A, alarm B, wakeup Timer and timestamp individual secure or non-secure

configuration

The RTC is supplied through a switch that takes power either from the VDD supply when present or from the V

The RTC clock sources can be:

• A 32.768 kHz external crystal (LSE)

• An external resonator or oscillator (LSE)

• The internal low power RC oscillator (LSI, with typical frequency of 32 kHz)

• The high-speed external clock (HSE), divided by a prescaler in the RCC.

The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in all low-power modes except Shutdown mode.

All RTC events (Alarm, WakeUp Timer, Timestamp) can generate an interrupt and wakeup the device from the low-power modes.

BAT

pin.

3.35 Tamper and backup registers (TAMP)

32 32-bit backup registers are retained in all low-power modes and also in VBAT mode. They can be used to store sensitive data as their content is protected by an tamper detection circuit. 8 tamper pins and 7 internal tampers are available for anti-tamper detection.

The external tamper pins can be configured for edge detection, or level detection with or without filtering, or active tamper which increases the security level by auto checking that the tamper pins are not externally opened or shorted.

72/323 DS12736 Rev 2

STM32L562xx Functional overview

TAMP main features:

• 32 backup registers:

– The backup registers (TAMP_BKPxR) are implemented in the RTC domain that

remains powered-on by VBAT when the VDD power is switched off

• 8 external tamper detection events

– Each external event can be configured to be active or passive – External passive tampers with configurable filter and internal pull-up

• 5 internal tamper events

• Any tamper detection can generate a RTC timestamp event

• Any tamper detection can erase the backup registers

• TrustZone support:

– Tamper secure or non-secure configuration. – Backup registers configuration in 3 configurable-size areas:

1 read/write secure area 1 write secure/read non-secure area 1 read/write non-secure area

• Monotonic counter.

DS12736 Rev 2 73/323

Functional overview STM32L562xx

3.36 Inter-integrated circuit interface (I2C)

The device embeds four I2C. Refer to Ta bl e 17: I2C implementation for the features implementation.

The I2C bus interface handles communications between the microcontroller and the serial

C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.

The I2C peripheral supports:

• I2C-bus specification and user manual rev. 5 compatibility:

– Slave and master modes, multimaster capability – Standard-mode (Sm), with a bitrate up to 100 kbit/s – Fast-mode (Fm), with a bitrate up to 400 kbit/s – Fast-mode plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os – 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses – Programmable setup and hold times – Optional clock stretching

• System management bus (SMBus) specification rev 2.0 compatibility:

– Hardware PEC (packet error checking) generation and verification with ACK

control – Address resolution protocol (ARP) support – SMBus alert

• Power system management protocol (PMBus

• Independent clock: a choice of independent clock sources allowing the I2C

communication speed to be independent from the PCLK reprogramming. Refer to

Figure 7: STM32L562xx clock tree

• Wakeup from Stop mode on address match

• Programmable analog and digital noise filters

• 1-byte buffer with DMA capability

I2C features

Table 17. I2C implementation

(1)

) specification rev 1.1 compatibility

I2C1 I2C2 I2C3 I2C4

Standard-mode (up to 100 kbit/s) X X X X

Fast-mode (up to 400 kbit/s) X X X X

Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s) X X X X

Programmable analog and digital noise filters X X X X

SMBus/PMBus hardware support X X X X

Independent clock X X X X

Wakeup from Stop 0, Stop 1 mode on address match X X X X

Wakeup from Stop 2 mode on address match - - X -

1. X: supported

74/323 DS12736 Rev 2

STM32L562xx Functional overview

3.37 Universal synchronous/asynchronous receiver transmitter (USART)

The devices have three embedded universal synchronous receiver transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver transmitters (UART4, UART5).

These interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN master/slave capability. They provide hardware management of the CTS and RTS signals, and RS485 driver enable. They are able to communicate at speeds of up to 10

Mbit/s.

The USART1, USART2 and USART3 also provide a Smartcard mode (ISO 7816 compliant) and an SPI-like communication capability.

All USART have a clock domain independent from the CPU clock, allowing the USARTx (x=1,2,3,4,5) to wake up the MCU from Stop mode using baudrates up to 200 wake up events from Stop mode are programmable and can be:

• Start bit detection

• Any received data frame

• A specific programmed data frame

Kbaud. The

All USART interfaces can be served by the DMA controller.

USART modes/features

Hardware flow control for modem XXXXX X

Continuous communication using DMA XXXXX X

Multiprocessor communication XXXXX X

Synchronous mode X X X - - -

Smartcard mode X X X - - -

Single-wire half-duplex communication XXXXX X

IrDA SIR ENDEC block XXXXX -

LIN mode XXXXX -

Dual clock domain XXXXX X

Wakeup from Stop 0 / Stop 1 modes XXXXX X

Wakeup from Stop 2 mode ----- X

Receiver timeout interrupt XXXXX -

Modbus communication XXXXX -

Auto baud rate detection X (4 modes) -

Driver enable XXXXX X

Table 18. USART/UART/LPUART features

(1)

USART1 USART2 USART3 UART4 UART5 LPUART1

LPUART/USART data length 7, 8 and 9 bits

1. X = supported.

DS12736 Rev 2 75/323

Functional overview STM32L562xx

3.38 Low-power universal asynchronous receiver transmitter (LPUART)

The devices embed one low-power UART. The LPUART supports asynchronous serial communication with minimum power consumption. It supports half-duplex single-wire communication and modem operations (CTS/RTS). It allows multiprocessor communication.

The LPUART has a clock domain independent from the CPU clock, and can wakeup the system from Stop mode using baudrates up to 220 mode are programmable and can be:

• Start bit detection

• Any received data frame

• A specific programmed data frame

Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while having an extremely low energy consumption. Higher speed clock can be used to reach higher baudrates.

The LPUART interface can be served by the DMA controller.

Kbaud. The wake up events from Stop

3.39 Serial peripheral interface (SPI)

Three SPI interfaces allow communication up to slave modes, in half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives eight master mode frequencies and the frame size is configurable from 4 and hardware CRC calculation.

All SPI interfaces can be served by the DMA controller.

bits to 16 bits. The SPI interfaces support NSS pulse mode, TI mode

3.40 Serial audio interfaces (SAI)

The devices embed two SAI. Refer to Tab le 19: SAI implementation for the features implementation. The SAI bus interface handles communications between the microcontroller and the serial audio protocol.

The SAI peripheral supports:

• Two independent audio sub-blocks which can be transmitters or receivers with their

respective FIFO.

• 8-word integrated FIFOs for each audio sub-block.

• Synchronous or asynchronous mode between the audio sub-blocks.

• Master or slave configuration independent for both audio sub-blocks.

• Clock generator for each audio block to target independent audio frequency sampling

when both audio sub-blocks are configured in master mode.

• Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit.

• Peripheral with large configurability and flexibility allowing to target as example the

following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF out.

76/323 DS12736 Rev 2

STM32L562xx Functional overview

• Up to 16 slots available with configurable size and with the possibility to select which

ones are active in the audio frame.

• Number of bits by frame may be configurable.

• Frame synchronization active level configurable (offset, bit length, level).

• First active bit position in the slot is configurable.

• LSB first or MSB first for data transfer.

• Mute mode.

• Stereo/Mono audio frame capability.

• Communication clock strobing edge configurable (SCK).

• Error flags with associated interrupts if enabled respectively.

– Overrun and underrun detection. – Anticipated frame synchronization signal detection in slave mode. – Late frame synchronization signal detection in slave mode. – Codec not ready for the AC’97 mode in reception.

• Interruption sources when enabled:

–Errors. – FIFO requests.

• DMA interface with two dedicated channels to handle access to the dedicated

integrated FIFO of each SAI audio sub-block.

SAI features

Table 19. SAI implementation

(1)

SAI1 SAI2

I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 X X

Mute mode X X

Stereo/Mono audio frame capability. X X

16 slots X X

Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit X X

FIFO size X (8 Word) X (8 Word)

SPDIF X X

PDM X -

1. X: supported

3.41 Secure digital input/output and MultiMediaCards Interface (SDMMC)

The SD/SDIO, MultiMediaCard (MMC) host interface (SDMMC) provides an interface between the AHB bus and SD memory cards, SDIO cards and MMC devices.

DS12736 Rev 2 77/323

Functional overview STM32L562xx

The SDMMC features include the following:

• Full compliance with MultiMediaCard System Specification Version 4.51. Card support

for three different databus modes: 1-bit (default), 4-bit and 8-bit

• Full compatibility with previous versions of MultiMediaCards (backward compatibility)

• Full compliance with SD Memory Card Specifications Version 4.1. (SDR104

SDMMC_CK speed limited to maximum allowed IO speed, SPI mode and UHS-II mode not supported)

• Full compliance with SDIO Card Specification Version 4.0: card support for two different

databus modes: 1-bit (default) and 4-bit. (SDR104 SDMMC_CK speed limited to maximum allowed IO speed, SPI mode and UHS-II mode not supported)

• Data transfer up to 104 Mbyte/s for the 8-bit mode (depending maximum allowed IO

speed)

• Data and command output enable signals to control external bidirectional drivers.

3.42 Controller area network (FDCAN)

The controller area network (CAN) subsystem consists of one CAN modules and message RAM memory.

The CAN module (FDCAN) is compliant with ISO 11898-1 (CAN protocol specification version 2.0 part A, B) and CAN FD protocol specification version 1.0.

A 1 Kbyte message RAM memory implements filters, receive FIFOs, receive buffers, transmit event FIFOs, transmit buffers.

3.43 Universal serial bus (USB FS)

The devices embed a full-speed USB device peripheral compliant with the USB specification version 2.0. The internal USB PHY supports USB FS signaling, embedded DP pull-up and battery charging detection according to Battery Charging Specification Revision

1.2. The USB interface implements a full-speed (12 Mbit/s) function interface with added support

for USB 2.0 link power management. It has software-configurable endpoint setting with packet memory up-to 1 Kbyte and suspend/resume support.

This interface requires a precise 48 MHz clock which can be generated from the internal main PLL (the clock source must use a HSE crystal oscillator) or by the internal 48 MHz oscillator (HSI48) in automatic trimming mode. The synchronization for this oscillator can be taken from the USB data stream itself (SOF signalization) which allows crystal less operation.

3.44 USB Type-C™ / USB Power Delivery controller (UCPD)

The device embeds one controller (UCPD) compliant with USB Type-C Rev. 1.2 and USB Power Delivery Rev. 3.0 specifications.

78/323 DS12736 Rev 2

STM32L562xx Functional overview

The controller uses specific I/Os supporting the USB Type-C and USB Power Delivery requirements, featuring:

• USB Type-C pull-up (Rp, all values) and pull-down (Rd) resistors

• “Dead battery” support

• USB Power Delivery message transmission and reception

• FRS (fast role swap) support

The digital controller handles notably:

• USB Type-C level detection with debounce, generating interrupts

• FRS detection, generating an interrupt

• Byte-level interface for USB Power Delivery payload, generating interrupts (DMA

compatible)

• USB Power Delivery timing dividers (including a clock pre-scaler)

• CRC generation/checking

• 4b5b encode/decode

• Ordered sets (with a programmable ordered set mask at receive)

• Frequency recovery in receiver during preamble

The interface offers low-power operation compatible with Stop mode, maintaining the capacity to detect incoming USB Power Delivery messages and FRS signaling.

3.45 Development support

3.45.1 Serial wire JTAG debug port (SWJ-DP)

The Arm® SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

Debug is performed using two pins only instead of five required by the JTAG (JTAG pins could be re-used as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

3.45.2 Embedded Trace Macrocell™

The Arm® Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the devices through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. Real-time instruction and data flow activity be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors.

The Embedded Trace Macrocell operates with third party debugger software tools.

DS12736 Rev 2 79/323

Pinouts and pin description STM32L562xx

MSv49322V1

LQFP48

VBAT

PC13

PC14_OSC32_IN

PC15_OSC32_OUT

PH0-OSC_IN

PH1-OSC_OUT

NRST

VSSA/VREF-

VDDA/VREF+

PA0

PA1

PA2

393740

484746

222421

131415

PA3

PA4

PA7

PB2

VDD

PA5

PA6

PB10

PB0

PB1

PB11

VSS

VDD

VSS

PA13

PA12

PA11

PA10

PA9

PA8

PB15

PB14

PB13

PB12

VDD

VSS

PH3-BOOT0

PB5

PA14

PB9

PB8

PB4

PB7

PB6

PB3

PA15

MSv49311V1

LQFP48

VBAT

PC13

PC14-OSC_IN

PC15-OSC_OUT

PH0-OSC_IN

PH1-OSC_OUT

NRST

VSSA/VREF-

VDDA/VREF+

PA0

PA1

PA2

393740

484746

222421

131415

PA3

PA4

PA7

PB2

VDD

PA5

PA6

PB10

PB0

PB1

VDD12_1

VSS

VDD

VSS

PA13

PA12

PA11

PA10

PA9

PA8

PB15

PB14

PB13

PB12

VDD

VSS

PH3-BOOT0

PB5

PA14

VDD12_2

PB8

PB4

PB7

PB6

PB3

PA15

4 Pinouts and pin description

Figure 10. STM32L562xx LQFP48 pinout

1. The above figure shows the package top view.

Figure 11. STM32L562xxxxP LQFP48 external SMPS pinout

80/323 DS12736 Rev 2

1. The above figure shows the package top view.

STM32L562xx Pinouts and pin description

MSv49321V1

UFQFPN48

VBAT

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

PH0-OSC_IN

PH1-OSC_OUT

NRST

VSSA/VREF-

VDDA/VREF+

PA0

PA1

PA2

393740

484746

222421

131415

PA3

PA4

PA7

PB2

VDD

PA5

PA6

PB10

PB0

PB1

PB11

VSS

VDD

VSS

PA13

PA12

PA11

PA10

PA9

PA8

PB15

PB14

PB13

PB12

VDD

VSS

PH3-BOOT0

PB5

PA14

PB9

PB8

PB4

PB7

PB6

PB3

PA15

MSv49310V1

UFQFPN48

VBAT

PC13

PC14-OSC_IN

PC15-OSC_OUT

PH0-OSC_IN

PH1-OSC_OUT

NRST

VSSA/VREF-

VDDA/VREF+

PA0

PA1

PA2

393740

484746

222421

131415

PA3

PA4

PA7

PB2

VDD

PA5

PA6

PB10

PB0

PB1

VDD12_1

VSS

VDD

VSS

PA13

PA12

PA11

PA10

PA9

PA8

PB15

PB14

PB13

PB12

VDD

VSS

PH3-BOOT0

PB5

PA14

VDD12_2

PB8

PB4

PB7

PB6

PB3

PA15

Figure 12. STM32L562xx UFQFPN48 pinout

1. The above figure shows the package top view.

Figure 13. STM32L562xxxxP UFQFPN48 external SMPS pinout

1. The above figure shows the package top view.

DS12736 Rev 2 81/323

138

Pinouts and pin description STM32L562xx

MSv49323V1

LQFP64

VBAT

PC14-OSC32_IN

PC15-OSC32_OUT

PH0-OSC_IN

PH1-OSC_OUT

NRST

PC0

PC1

PC2

PC3

VSSA/VREF-

VDDA/VREF+

PA0

PA1

PA2

PC13

5352515049

646362

2829303132

171819

PA3

VSS

PA5

PC4

PB2

VDD

PA4

PC5

PB11

PA6

PA7

VSS

PB0

PB1

PB10

VDD

VDDUSB

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

PC6

PB15

PB14

PB13

PB12

VSS

VDD

VSS

PH3-BOOT0

PB5

PC12

PB9

PB8

PB4

PC10

PB7

PB6

PA15

PB3

PD2

PC11

PA14

MSv49316V1

LQFP64

VBAT

PC14-OSC32_IN

PC15-OSC32_OUT

PH0-OSC_IN

PH1-OSC_OUT

NRST

PC0

PC1

PC2

PC3

VSSA/VREF-

VDDA/VREF+

PA0

PA1

PA2

PC13

5352515049

646362

2829303132

171819

PA3

VSS

PA5

PB0

VDDSMPS

VDD

PA4

PB1

VSSSMPS

PA6

PA7

VSS

PB2

PB10

VLXSMPS

V15SMPS_1

VDDUSB

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

PC6

PB15

PB14

PB13

VDD

VSS

VDD

V15SMPS_2

PH3-BOOT0

PB5

PC12

VSS

PB8

PB4

PC10

PB7

PB6

PA15

PB3

PD2

PC11

PA14

Figure 14. STM32L562xx LQFP64 pinout

1. The above figure shows the package top view.

Figure 15. STM32L562xxxxQ LQFP64 SMPS step down converter pinout

82/323 DS12736 Rev 2

1. The above figure shows the package top view.

STM32L562xx Pinouts and pin description

MSv49312V2

LQFP64

VBAT

PC14-OSC32_IN

PC15-OSC32_OUT

PH0-OSC_IN

PH1-OSC_OUT

NRST

PC0

PC1

PC2

PC3

VSSA/VREF-

VDDA/VREF+

PA0

PA1

PA2

PC13

5352515049

646362

2829303132

171819

PA3

VSS

PA5

PC4

PB10

VDD

PA4

PB0

VDD12_1

PA6

PA7

VSS

PB1

PB2

PB11

VDD

VDDUSB

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

PC6

PB15

PB14

PB13

PB12

VSS

VDD

VSS

PB8

PB6

PC12

VDD12_2

PB9

PB5

PC10

PH3-BOOT0

PB7

PA15

PB4

PB3

PC11

PA14

MSv49317V1

VDD PC10 PD2 PG13 VDDIO2 PB5 PB9 V15SMPS_2

12345678

VDDUSB VSS PC12 PG12 VSS PB4 PC13 VSS

PA11 PA12 PC11 PG10 PG15

PC15-

OSC32_OUT

PA9 PA13 PA14

PC6 PC7 PA10

PB15 PB13

PB14 PB12

VDD VSS VLXSMPS

PC9

PC8

PB1

PA6

PB11

PC4

PA4

PC3

PC2

PC0

PH3-BOOT0

PA5

PA2

PB6 PB8

PA0

VREF+

PC1

VSS

PH1-

OSC_OUT

VDD

VBAT

PC14-

OSC32_IN

VDDA

VSSA/VREF-

VDD

NRST

PH0-OSC_IN

V15SMPS_1 VSSSMPS VDDSMPS PB2PB10 PA7PB0 VDD VSS

PG9 PG14 PB7

PA15 PG11 PB3

PA8 PA 3 PA1

Figure 16. STM32L562xxxxP LQFP64 external SMPS pinout

1. The above figure shows the package top view.

Figure 17. STM32L562xxxxQ WLCSP81 SMPS step down converter ballout

1. The above figure shows the package top view.

DS12736 Rev 2 83/323

138

Pinouts and pin description STM32L562xx

MSv49313V1

VDD PC10 PD2 PG13 VDDIO2 PB5 PB9 VDD12_2

12345678

VDDUSB VSS PC12 PG12 VSS PB4 PC13 VSS

PA11 PA12 PC11 PG10 PG15

PC15-

OSC32_OUT

PA9 PA13 PA14

PC6 PC7 PA10

PB15 PB13

PB14 PB12

VDD VSS PE15

PC9

PC8

PB1

PA6

PE14

PC4

PA4

PC3

PC2

PC0

PH3-BOOT0

PA5

PA2

PB6 PB8

PA0

VREF+

PC1

VSS

PH1-

OSC_OUT

VDD

VBAT

PC14-

OSC32_IN

VDDA

VSSA/VREF-

VDD

NRST

PH0-OSC_IN

VDD12_1 PB11 PB10 PB2PE13 PA7PB0 VDD VSS

PG9 PG14 PB7

PA15 PG11 PB3

PA8 PA 3 PA1

MSv49324V1

LQFP100

VSS

PH0-OSC_IN

PH1-OSC_OUT

NRST

PC0

PC1

PC2

PC3

VSSA

VREF-

VREF+

VDDA

PA0

PA1

PA2

PC15-OSC32_OUT

VDD

PE5

VBAT

PC14-OSC32_IN

PE2

PE3

PE4

PE6

PC13

89888786858483828180797877

100

37383940414243444546474849

262728

PA3

VSS

PA5

PC4

PB2

VDD

PA4

PC5

PE8

PE11

PA6

PA7

PE9

PE12

PE15

PB0

PB1

PE13

PB10

VSS

PE7

PE10

PE14

PB11

VDD

PC9

PC7

PC6

PD15

PD14

PD13

PD12

PD11

PD10

PD9

PD8

PB15

PB14

PB13

PB12

PA8

PC8

PA13

PA11

PA9

VDD

VSS

VDDUSB

PA12

PA10

VDD

VSS

PB9

PB7

PB3

PE1

PE0

PB6

PD6

PD3

PB8

PH3-BOOT0

PD5

PD2

PC12

PB5

PB4

PD1

PC11

PA15

PD7

PD4

PD0

PC10

PA14

Figure 18. STM32L562xxxxP WLCSP81 external SMPS ballout

1. The above figure shows the package top view.

Figure 19. STM32L562xx LQFP100 pinout

84/323 DS12736 Rev 2

1. The above figure shows the package top view.

STM32L562xx Pinouts and pin description

MSv49318V1

LQFP100

VSS

PH0-OSC_IN

PH1-OSC_OUT

NRST

PC0

PC1

PC2

PC3

VSSA/VREF-

VREF+

VDDA

PA0

PA1

PA2

PA3

PC15-OSC32_OUT

VDD

PE5

VBAT

PC14-OSC32_IN

PE2

PE3

PE4

PE6

PC13

89888786858483828180797877

100

37383940414243444546474849

262728

VSS

VDD

PA6

PB1

PE9

PA4

PA5

PB2

PE11

PE14

PA7

PB0

PE12

PE15

VDDSMPS

PE7

PE8

PB10

VLXSMPS

VSS

PE10

PE13

PB11

VSSSMPS

V15SMPS_1

PC9

PC7

PC6

PD15

PD14

PD13

PD12

PD11

PD10

PD9

PD8

PB15

PB14

PB13

VDD

PA8

PC8

PA13

PA11

PA9

VDD

VSS

VDDUSB

PA12

PA10

VDD

V15SMPS_2

PB9

PB7

PB3

VSS

PE0

PB6

PD6

PD3

PB8

PH3-BOOT0

PD5

PD2

PC12

PB5

PB4

PD1

PC11

PA15

PD7

PD4

PD0

PC10

PA14

Figure 20. STM32L562xxxxQ LQFP100 SMPS step down converter pinout

1. The above figure shows the package top view.

DS12736 Rev 2 85/323

138

Pinouts and pin description STM32L562xx

MSv49325V1

PB9

PG15

PE0

VDD

PB2

VDD

PB1

PB0

VSS

PC3

PA1

VSS

PE5 PE3 PE1 PB6 PG12 PD6 PD5 PD2 PC11 PA15 VDDUSB

123 56789101112

VBAT PE4 PE2 PH3-BOOT0 PB4 PG9 PD4 PD1 PC12 PC10 PA12

PC14-

OSC32_IN

PE6 PC13 PB8 PD3 PD0 PA13 PA14 PA11

PC15-

OSC32_OUT

PF0 PF3 PA9 PA10 PA8

PF2 PF1 PF4 PC7 PC9 PC8

PH0-OSC_IN PF5 PC6 PG8

PH1-

OSC_OUT

NRST PG3 PG5

VSSA/VREF- PC0

OPAMP1_VI

PD14 PD13 PD15

VREF+ PA0 PC5 PD9 PD11 PD12

VDDA PA2 PA 7 PF11 PE14 PB10 PB13 PB14 PB15

PA3 PA 6 PA4 PF12 PF15 PE11 PE15 PB11 VSS PB12 PD8

PA5

OPAMP2_VI

PC4 PF13 PG0 PE9 PE13 PG14 PG13 PG11 PD10

PB3 PG10

PB7 PB5 PD7 VDDIO2 VDD

VSS VDD

VDD VSS

PC2

PC1

PF14 PE8 PE10 PE12 VDD

PG1 PE7

VSS

PG6

PG4

VSS

PG7

PG2

MSv49319V1

PB9

V15SMPS_2

PE0

VDD

PB2

VDD

PB1

PB0

VSS

PC3

PA1

VSS

PE5 PE3 PE1 PB6 PG12 PD6 PD5 PD2 PC11 PA15 VDDUSB

123 56789101112

VBAT PE4 PE2 PH3-BOOT0 PB4 PG9 PD4 PD1 PC12 PC10 PA12

PC14-

OSC32_IN

PE6 PC13 PB8 PD3 PD0 PA13 PA14 PA 11

PC15-

OSC32_OUT

PF0 PF3 PA9 PA10 PA8

PF2 PF1 PF4 PC7 PC9 PC8

PH0-OSC_IN PF5 PC6 PG8

PH1-

OSC_OUT

NRST PG3 PG5

VSSA/VREF- PC0

OPAMP1_VI

PD14 PD13 PD15

VREF+ PA0 PC5 PD9 PD11 PD12

VDDA PA2 PA 7 PF11 PE14 PB10 PB13 PB14 PB15

PA3 PA 6 PA4 PF12 PF15 PE11 PE15 PB11 VSSSMPS PB12 PD8

PA5

OPAMP2_VI

PC4 PF13 PG0 PE9 PE13 VDDSMPS VLXSMPS V15SMPS_1 PD10

PB3 PG10

PB7 PB5 PD7 VDDIO2 VDD

VSS VDD

VDD VSS

PC2

PC1

PF14 PE8 PE10 PE12 VDD

PG1 PE7

VSS

PG6

PG4

VSS

PG7

PG2

Figure 21. STM32L562xx UFBGA132 ballout

1. The above figure shows the package top view.

Figure 22. STM32L562xxxxQ UFBGA132 SMPS step down converter ballout

86/323 DS12736 Rev 2

1. The above figure shows the package top view.

STM32L562xx Pinouts and pin description

MSv49326V1

LQFP144

23 24 25 26 27 28 29 30 31 32 33 34 35 36

13 14

PF9

PH0-OSC_IN

PH1-OSC_OUT

NRST

PC0 PC1 PC2 PC3

VSSA

VREF-

VREF+

VDDA

PA0 PA1 PA2

PF8

PF10

PF5

VDD

PF7

PF3 PF4

VSS

PF6

86 85 84 83 82 81 80 79 78 77 76 75 74 73

97 96 95

135

133

132

131

130

129

128

127

126

125

124

123

122

121

136

134

141

139

137

144

143

142

140

138

47495051525354555657585960

383940

VSS

VDD

PA6

PC5

PF11

PA4

PA5

PB0

VSS

PF14

PA7

PC4

VDD

PF15

PE7

PB1

PB2

PG0

PE8

VSS

PF12

PF13

PG1

PE9

VDD

PG3

PD15 PD14 VDD VSS PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12

PG4

PG2

VSS

PG7

PG5

PC7 PC6 VDDIO2

PG8

PG6

VDD

VSS

PB9

PB7

PB3

PE1

PE0

PB6

VDDIO2

PG13

PB8

PH3-BOOT0

VSS

PG12

PG9

PB5

PB4

PG11

PD7

VDD

PG15

PG14

PG10

PD6

120 VSS

119 PD5

118 PD4

117 PD3

116 PD2

115 PD1

114 PD0

113 PC12

112 PC11

111 PC10

110 PA15

109 PA14

108 VDD

104

107 106 105

103

PA12

VSS VDDUSB PA13

PA11

9998PC9

PC8

101 100

PA9 PA8

102 PA10

686970

PE15

PB10

VSS

PB11

646566

PE11

PE12

PE14

PE13

VDD

PE10

PA3

4 5

PF2

PF1

VBAT

PC14-OSC32_IN

PF0

PE5 PE6

PC13

PC15-OSC32_OUT

3PE4

2PE3

1PE2

Figure 23. STM32L562xx LQFP144 pinout

1. The above figure shows the package top view.

DS12736 Rev 2 87/323

138

Pinouts and pin description STM32L562xx

MSv49320V1

LQFP144

23 24 25 26 27 28 29 30 31 32 33 34 35 36

13 14

PF9

PH0-OSC_IN

PH1-OSC_OUT

NRST

PC0 PC1 PC2 PC3

VSSA/VREF-

VREF+

VDDA

PA0 PA1 PA2 PA3

PF8

PF10

PF5

VDD

PF7

PF3 PF4

VSS

PF6

86 85 84 83 82 81 80 79 78 77 76 75 74 73

97 96 95

135

133

132

131

130

129

128

127

126

125

124

123

122

121

136

134

141

139

137

144

143

142

140

138

47495051525354555657585960

383940

VDD

PA4

PA7

PB2

VDD

PA5

PA6

PF11

PF14

PG1

PB0

PB1

PF15

PE7

VSS

PF12

VSS

PE8

VDD

PE11

PF13

PG0

PE9

PE10

V15SMPS_1

PG3

PD15 PD14 VDD VSS PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 VDD

PG4

PG2

VSS

PG7

PG5

PC7 PC6 VDDIO2

PG8

PG6

VDD

V15SMPS_2

PE0

PH3-BOOT0

PB4

VSS

PE1

PB7

PG15

PG14

PB9

PB8

VDDIO2

PG13

PG9

PB6

PB5

PG12

PD7

VDD

PB3

VSS

PG10

PD6

120 VSS

119 PD5

118 PD4

117 PD3

116 PD2

115 PD1

114 PD0

113 PC12

112 PC11

111 PC10

110 PA15

109 PA14

108 VDD

104

107 106 105

103

PA12

VSS VDDUSB PA13

PA11

9998PC9

PC8

101 100

PA9 PA8

102 PA10

686970

VDDSMPS

VLXSMPS

VSS

VSSSMPS

646566

PE14

PE15

PB11

PB10

PE12

PE13

VSS

4 5

PF2

PF1

VBAT

PC14-OSC32_IN

PF0

PE5 PE6

PC13

PC15-OSC32_OUT

3PE4

2PE3

1PE2

Figure 24. STM32L562xxxxQ LQFP144 SMPS step down converter pinout

1. The above figure shows the package top view.

88/323 DS12736 Rev 2

Table 20. Legend/abbreviations used in the pinout table

Name Abbreviation Definition

Pin name Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name

S Supply pin

Pin type

I Input only pin

I/O Input / output pin

FT 5 V tolerant I/O

TT 3.6 V tolerant I/O

B Dedicated BOOT0 pin

RST Bidirectional reset pin with embedded weak pull-up resistor

STM32L562xx Pinouts and pin description

DS12736 Rev 2 89/323

I/O structure

(1)

(2)

(3)

(4)

I/O, Fm+ capable

I/O, with USB function supplied by V

I/O, with Analog switch function supplied by V

I/O supplied only by V

_c I/O, USB Type-C PD capable

_d I/O, USB Type-C PD dead battery function

Notes Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset.

Alternate

functions

Additional

functions

1. The related I/O structures in Table 21 are: FT_f, FT_fa.

2. The related I/O structures in Table 21 are: FT_u.

3. The related I/O structures in Table 21 are: FT_a, FT_fa, TT_a.

4. The related I/O structures in Table 21 are: FT_s, FT_fs.

Functions selected through GPIOx_AFR registers

Functions directly selected/enabled through peripheral registers

Option for TT or FT I/Os

DDUSB

DDA

DDIO2

90/323 DS12736 Rev 2

Table 21. STM32L562xx pin definitions

Pin Number

STM32L562xxxxP STM32L562xxxxQ STM32L562xx

Pinouts and pin description STM32L562xx

Pin name

SMPS

UFQFPN48_Ext-

LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

------1B31---1B31PE2I/OFT-

------2A22---2A22PE3I/OFT-

------3B23---3B23PE4I/OFT-

LQFP64_SMPS

WLCSP81_Ext-SMPS

WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS

UFBGA132_SMPS

LQFP48

LQFP64

UFQFPN48

LQFP100

LQFP144

UFBGA132

Pin type

(function after reset)

Notes

I/O structure

Alternate functions

TRACECK, TIM3_ETR,

SAI1_CK1,

TSC_G7_IO1,

FMC_A23,

SAI1_MCLK_A,

EVENTOUT

TRACED0, TIM3_CH1,

OCTOSPI1_DQS,

TSC_G7_IO2,

FMC_A19,

SAI1_SD_B,

EVENTOUT

TRACED1, TIM3_CH2,

SAI1_D2,

DFSDM1_DATIN3,

TSC_G7_IO3,

FMC_A20, SAI1_FS_A,

EVENTOUT

Additional

functions

------4A14---4A14PE5I/OFT-

TRACED2, TIM3_CH3,

SAI1_CK2,

DFSDM1_CKIN3,

TSC_G7_IO4,

FMC_A21,

SAI1_SCK_A,

EVENTOUT

Table 21. STM32L562xx pin definitions (continued)

Pin Number

STM32L562xxxxP STM32L562xxxxQ STM32L562xx

STM32L562xx Pinouts and pin description

DS12736 Rev 2 91/323

Additional

functions

WKUP3,

TAMP_IN3/TAMP_

OUT6

Notes

I/O structure

SMPS

UFQFPN48_Ext-

LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

WLCSP81_Ext-SMPS

LQFP64_SMPS

WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS

UFBGA132_SMPS

Pin name

LQFP48

LQFP64

UFQFPN48

LQFP100

LQFP144

UFBGA132

Pin type

(function after reset)

------5C25---5C25PE6I/OFT-

Alternate functions

TRACED3, TIM3_CH4,

SAI1_D1, FMC_A22,

SAI1_SD_A,

EVENTOUT

111B91B96B161116B16VBATS-- - -

WKUP2,

222B72B77C372227C37PC13I/OFT

(1) (2)

EVENTOUT

RTC_TS/RTC_

OUT1,

TAMP_IN1/TAMP_

OUT2

PC14-

333C93C98C183338C18

OSC3

2_IN

I/O FT

(1) (2)

EVENTOUT OSC32_IN

(PC14

)

PC15-

444C84C89D194449D19

OSC3

2_OU

I/O FT

(1) (2)

EVENTOUT OSC32_OUT

(PC15

)

-------D210----D210PF0I/O

I2C2_SDA, FMC_A0,

EVENTOUT

92/323 DS12736 Rev 2

Table 21. STM32L562xx pin definitions (continued)

Pin Number

STM32L562xxxxP STM32L562xxxxQ STM32L562xx

Pinouts and pin description STM32L562xx

Alternate functions

FT _a

I/O structure

Notes

I2C2_SCL, FMC_A1,

EVENTOUT

I2C2_SMBA, FMC_A2,

EVENTOUT

LPTIM3_IN1, FMC_A3,

EVENTOUT

LPTIM3_ETR,

FMC_A4, EVENTOUT

LPTIM3_OUT,

FMC_A5, EVENTOUT

TIM5_ETR, TIM5_CH1,

OCTOSPI1_IO3,

SAI1_SD_B,

EVENTOUT

TIM5_CH2,

OCTOSPI1_IO2,

SAI1_MCLK_B,

EVENTOUT

Pin name

SMPS

UFQFPN48_Ext-

LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

-------E211----E211PF1I/O

-------E112----E112PF2I/OFT-

-------D313----D313PF3I/O

-------E314----E314PF4I/O

-------F215----F215PF5I/O

------10F616---10F616VSSS-- - -

------11F717---11F717VDDS-- - -

--------18-----18PF6I/O

--------19-----19PF7I/O

LQFP64_SMPS

WLCSP81_Ext-SMPS

WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS

UFBGA132_SMPS

LQFP48

LQFP64

UFQFPN48

LQFP100

LQFP144

UFBGA132

Pin type

(function after reset)

Additional

functions

TAMP_IN6/TAMP_

OUT3

Table 21. STM32L562xx pin definitions (continued)

Pin Number

STM32L562xxxxP STM32L562xxxxQ STM32L562xx

STM32L562xx Pinouts and pin description

DS12736 Rev 2 93/323

Pin name

SMPS

UFQFPN48_Ext-

LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

--------20-----20PF8I/O

--------21-----21PF9I/O

--------22-----22PF10I/O

5 5 5D95D912F123 5 5 512F123

6 6 6D86D813G1246 6 613G124

LQFP64_SMPS

WLCSP81_Ext-SMPS

WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS

UFBGA132_SMPS

LQFP48

LQFP64

UFQFPN48

LQFP100

LQFP144

UFBGA132

PH0-

OSC_

(PH0)

PH1-

OSC_

OUT

(PH1)

Pin type

(function after reset)

FT _a

I/O FT - EVENTOUT OSC_IN

I/O FT - EVENTOUT OSC_OUT

I/O structure

Alternate functions

Notes

TIM5_CH3,

OCTOSPI1_IO0,

SAI1_SCK_B,

EVENTOUT

TIM5_CH4,

OCTOSPI1_IO1,

SAI1_FS_B,

TIM15_CH1,

EVENTOUT

OCTOSPI1_CLK,

DFSDM1_CKOUT,

SAI1_D3, TIM15_CH2,

EVENTOUT

Additional

functions

TAMP_IN7/TAMP_

OUT8

TAMP_IN8/TAMP_

OUT7

7 7 7E97E914G2257 7 714G225NRSTI-O

-- -

94/323 DS12736 Rev 2

Table 21. STM32L562xx pin definitions (continued)

Pin Number

STM32L562xxxxP STM32L562xxxxQ STM32L562xx

Pinouts and pin description STM32L562xx

Pin name

SMPS

UFQFPN48_Ext-

LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

- - 8E78E715H226- - 815H226PC0I/O

- - 9 F8 9 F8 16 G3 27 - - 9 16 G3 27 PC1 I/O

- - 10 F7 10 F7 17 F3 28 - - 10 17 F3 28 PC2 I/O

LQFP64_SMPS

WLCSP81_Ext-SMPS

WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS

UFBGA132_SMPS

LQFP48

LQFP64

UFQFPN48

LQFP100

LQFP144

UFBGA132

Pin type

(function after reset)

_fa

FT _a

I/O structure

Alternate functions

Notes

LPTIM1_IN1,

OCTOSPI1_IO7,

I2C3_SCL,

LPUART1_RX,

SDMMC1_D5,

SAI2_FS_A,

LPTIM2_IN1,

EVENTOUT

TRACED0,

LPTIM1_OUT,

SPI2_MOSI,

I2C3_SDA,

LPUART1_TX,

OCTOSPI1_IO4,

SAI1_SD_A,

EVENTOUT

LPTIM1_IN2,

SPI2_MISO,

DFSDM1_CKOUT,

OCTOSPI1_IO5,

EVENTOUT

Additional

functions

ADC12_IN1

ADC12_IN2

ADC12_IN3

Table 21. STM32L562xx pin definitions (continued)

Pin Number

STM32L562xxxxP STM32L562xxxxQ STM32L562xx

STM32L562xx Pinouts and pin description

DS12736 Rev 2 95/323

Alternate functions

FT _a

I/O structure

Notes

LPTIM1_ETR, LPTIM3_OUT,

SAI1_D1, SPI2_MOSI,

OCTOSPI1_IO6,

SAI1_SD_A,

LPTIM2_ETR,

EVENTOUT

Pin name

SMPS

UFQFPN48_Ext-

LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

- - 11 G7 11 G7 18 F4 29 - - 11 18 F4 29 PC3 I/O

------------19-30VSSA S - - - -

------------20-31

8 8 12 G9 12 G9 19 H1 30 8 8 12 - H1 -

- - - G8 - G8 20 J1 31 - - - 21 J1 32

- - - H9 - H9 21 K1 32 - - - 22 K1 33 VDDA S - - - -

9913-13----9913---

LQFP64_SMPS

WLCSP81_Ext-SMPS

WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS

UFBGA132_SMPS

LQFP48

LQFP64

UFQFPN48

LQFP100

LQFP144

UFBGA132

VREF

VSSA

/VREF-S-- - -

VREF

VDDA

/VREF+S-- - -

Pin type

(function after reset)

S-- - -

S - - - VREFBUF_OUT

Additional

functions

ADC12_IN4

96/323 DS12736 Rev 2

Table 21. STM32L562xx pin definitions (continued)

Pin Number

STM32L562xxxxP STM32L562xxxxQ STM32L562xx

Pinouts and pin description STM32L562xx

Pin name

SMPS

UFQFPN48_Ext-

LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

10 10 14 H8 14 H8 22 J2 33 10 10 14 23 J2 34 PA0 I/O

-------H3-----H3-

11 11 15 F6 15 F6 23 G4 34 11 11 15 24 G4 35 PA1 I/O

LQFP64_SMPS

WLCSP81_Ext-SMPS

WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS

UFBGA132_SMPS

LQFP48

LQFP64

UFQFPN48

LQFP100

LQFP144

UFBGA132

(function after reset)

OPAM P1_VINMITT- - -

Pin type

I/O structure

FT _a

Alternate functions

Notes

TIM2_CH1, TIM5_CH1,

TIM8_ETR,

USART2_CTS/USART

2_NSS, UART4_TX,

SAI1_EXTCLK,

TIM2_ETR,

EVENTOUT

TIM2_CH2, TIM5_CH2,

I2C1_SMBA,

SPI1_SCK,

USART2_RTS/USART

2_DE, UART4_RX,

OCTOSPI1_DQS,

TIM15_CH1N,

EVENTOUT

Additional

functions

OPAMP1_VINP,

ADC12_IN5,

WKUP1,

TAMP_IN2/TAMP_

OUT1

OPAMP1_VINM,

ADC12_IN6,

TAMP_IN5/TAMP_

OUT4

Table 21. STM32L562xx pin definitions (continued)

Pin Number

STM32L562xxxxP STM32L562xxxxQ STM32L562xx

STM32L562xx Pinouts and pin description

DS12736 Rev 2 97/323

Alternate functions

FT _a

TT _a

I/O structure

Notes

TIM2_CH3, TIM5_CH3,

USART2_TX,

LPUART1_TX,

OCTOSPI1_NCS,

UCPD1_FRSTX1,

SAI2_EXTCLK,

TIM15_CH1,

EVENTOUT

TIM2_CH4, TIM5_CH4,

SAI1_CK1,

USART2_RX,

LPUART1_RX,

OCTOSPI1_CLK,

SAI1_MCLK_A,

TIM15_CH2,

EVENTOUT

Pin name

SMPS

UFQFPN48_Ext-

LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

12 12 16 G6 16 G6 24 K2 35 12 12 16 25 K2 36 PA2 I/O

13 13 17 F5 17 F5 25 L1 36 13 13 17 26 L1 37 PA3 I/O

- - 18 H2 18 H2 26 G7 37 - - 18 27 G7 38 VSS S - - - -

- - 19 - 19 - 27 G6 38 - - 19 28 G6 39 VDD S - - - -

LQFP64_SMPS

WLCSP81_Ext-SMPS

WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS

UFBGA132_SMPS

LQFP48

LQFP64

UFQFPN48

LQFP100

LQFP144

UFBGA132

Pin type

(function after reset)

Additional

functions

ADC12_IN7,

WKUP4/LSCO,

COMP1_INP

OPAMP1_VOUT,

ADC12_IN8

14 14 20 H7 20 H7 28 L3 39 14 14 20 29 L3 40 PA4 I/O

TT _a

OCTOSPI1_NCS,

SPI1_NSS, SPI3_NSS,

USART2_CK,

SAI1_FS_B,

LPTIM2_OUT,

EVENTOUT

ADC12_IN9,

DAC1_OUT1

98/323 DS12736 Rev 2

Table 21. STM32L562xx pin definitions (continued)

Pin Number

STM32L562xxxxP STM32L562xxxxQ STM32L562xx

Pinouts and pin description STM32L562xx

Pin name

SMPS

UFQFPN48_Ext-

LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

15 15 21 H6 21 H6 29 M1 40 15 15 21 30 M1 41 PA5 I/O

16 16 22 G5 22 G5 30 L2 41 16 16 22 31 L2 42 PA6 I/O

-------M2-----M2-

LQFP64_SMPS

WLCSP81_Ext-SMPS

WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS

UFBGA132_SMPS

LQFP48

LQFP64

UFQFPN48

LQFP100

LQFP144

UFBGA132

(function after reset)

OPAM P2_VINMITT- - -

Pin type

I/O structure

TT _a

FT _a

Alternate functions

Notes

TIM2_CH1, TIM2_ETR,

TIM8_CH1N,

SPI1_SCK,

LPTIM2_ETR,

EVENTOUT

TIM1_BKIN,

TIM3_CH1, TIM8_BKIN, SPI1_MISO,

USART3_CTS/USART

3_NSS,

LPUART1_CTS,

OCTOSPI1_IO3,

TIM16_CH1,

EVENTOUT

Additional

functions

ADC12_IN10,

DAC1_OUT2

OPAMP2_VINP,

ADC12_IN11

Table 21. STM32L562xx pin definitions (continued)

Pin Number

STM32L562xxxxP STM32L562xxxxQ STM32L562xx

STM32L562xx Pinouts and pin description

DS12736 Rev 2 99/323

Pin name

SMPS

UFQFPN48_Ext-

LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

17 17 23 J7 23 J7 31 K3 42 17 17 23 32 K3 43 PA7 I/O

- - 24 G4 - G4 - M3 - - - 24 33 M3 44 PC4 I/O

-------J3---2534J345PC5I/O

18 18 25 J6 24 J6 32 M4 43 18 18 26 35 M4 46 PB0 I/O

LQFP64_SMPS

WLCSP81_Ext-SMPS

WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS

UFBGA132_SMPS

LQFP48

LQFP64

UFQFPN48

LQFP100

LQFP144

UFBGA132

Pin type

(function after reset)

_fa

FT _a

TT _a

I/O structure

Alternate functions

Notes

TIM1_CH1N,

TIM3_CH2,

TIM8_CH1N,

I2C3_SCL,

SPI1_MOSI,

OCTOSPI1_IO2,

TIM17_CH1,

EVENTOUT

USART3_TX,

OCTOSPI1_IO7,

EVENTOUT

SAI1_D3,

USART3_RX,

EVENTOUT

TIM1_CH2N,

TIM3_CH3,

TIM8_CH2N,

SPI1_NSS,

USART3_CK,

OCTOSPI1_IO1,

COMP1_OUT,

SAI1_EXTCLK,

EVENTOUT

Additional

functions

OPAMP2_VINM,

ADC12_IN12

COMP1_INM,

ADC12_IN13

ADC12_IN14,

WKUP5,

TAMP_IN4/TAMP_

OUT5,

COMP1_INP

OPAMP2_VOUT,

ADC12_IN15

100/323 DS12736 Rev 2

Table 21. STM32L562xx pin definitions (continued)

Pin Number

STM32L562xxxxP STM32L562xxxxQ STM32L562xx

Pinouts and pin description STM32L562xx

Alternate functions

FT _a

I/O structure

Notes

TIM1_CH3N,

TIM3_CH4,

TIM8_CH3N,

DFSDM1_DATIN0,

USART3_RTS/USART

LPUART1_RTS/LPUA

3_DE,

RT1_DE,

OCTOSPI1_IO0,

LPTIM2_IN1,

EVENTOUT

LPTIM1_OUT,

I2C3_SMBA,

DFSDM1_CKIN0, OCTOSPI1_DQS, UCPD1_FRSTX1,

EVENTOUT

OCTOSPI1_NCLK,

EVENTOUT

Pin name

SMPS

UFQFPN48_Ext-

LQFP48_Ext-SMPS

LQFP64_Ext-SMPS

19 19 26 H5 25 H5 33 L4 44 19 19 27 36 L4 47 PB1 I/O

20 20 27 J5 26 J5 34 K4 45 20 20 28 37 K4 48 PB2 I/O FT -

-------K546----K549PF11I/OFT-

-------L547----L550PF12I/OFT-FMC_A6, EVENTOUT -

---J9-J9--48-----51VSSS-- - -

LQFP64_SMPS

WLCSP81_Ext-SMPS

WLCSP81_SMPS

LQFP100_SMPS

LQFP144_SMPS

UFBGA132_SMPS

LQFP48

LQFP64

UFQFPN48

LQFP100

LQFP144

UFBGA132

Pin type

(function after reset)

Additional

functions

COMP1_INM,

ADC12_IN16

RTC_OUT2,

COMP1_INP

---J8-J8--49-----52VDDS-- - -

-------M550----M553PF13I/OFT-

I2C4_SMBA, FMC_A7,

EVENTOUT

ST MICROELECTRONICS STM32L562ZET6Q Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Table 1. Device summary

1 Introduction

2 Description

Table 2. STM32L562xx features and peripheral counts

Figure 1. STM32L562xx block diagram

3 Functional overview

3.1 Arm® Cortex®-M33 core with TrustZone® and FPU

3.2 Art Accelerator – instruction cache (ICACHE)

3.3 Memory protection unit

3.4 Embedded Flash memory

3.5 Embedded SRAM

3.6 Boot modes

Table 3. Boot modes when TrustZone is disabled (TZEN=0)

Table 4. Boot modes when TrustZone is enabled (TZEN=1)

Table 5. Boot space versus RDP protection

3.7 Global TrustZone controller (GTZC)

3.8 TrustZone security architecture

Table 6. Example of memory map security attribution vs SAU configuration regions

3.8.1 TrustZone peripheral classification

Table 7. Securable peripherals by TZSC

Table 8. TrustZone-aware peripherals

3.9 Power supply management

3.9.1 Power supply schemes

Figure 2. STM32L562xx power supply overview

Figure 3. STM32L562xxxxP power supply overview

Figure 4. STM32L562xxxxQ power supply overview

Figure 5. Power-up/down sequence

3.9.2 Power supply supervisor

3.9.3 Voltage regulator

3.9.4 SMPS step down converter

Figure 6. SMPS step down converter power supply scheme

Table 9. SMPS external components

3.9.5 Low-power modes

Table 10. STM32L562xx modes overview

Table 11. Functionalities depending on the working mode

3.9.6 Reset mode

3.9.7 VBAT operation

3.9.8 PWR TrustZone security

3.10 Peripheral interconnect matrix

Table 12. STM32L562xx peripherals interconnect matrix

3.11 Reset and clock controller (RCC)

Figure 7. STM32L562xx clock tree

3.12 Clock recovery system (CRS)

3.13 General-purpose inputs/outputs (GPIOs)

3.14 Multi-AHB bus matrix

Figure 8. Multi-AHB bus matrix

3.15 Direct memory access controller (DMA)

Table 13. DMA1 and DMA2 implementation

3.16 DMA request router (DMAMUX)

3.17 Interrupts and events

3.17.1 Nested vectored interrupt controller (NVIC)

3.17.2 Extended interrupt/event controller (EXTI)

3.18 Cyclic redundancy check calculation unit (CRC)

3.19 Flexible static memory controller (FSMC)

3.20 Octo-SPI interface (OCTOSPI)

3.21 Analog-to-digital converter (ADC)

3.21.1 Temperature sensor

Table 14. Temperature sensor calibration values

Table 15. Internal voltage reference calibration values

3.22 Digital to analog converter (DAC)

3.23 Voltage reference buffer (VREFBUF)

Figure 9. Voltage reference buffer

3.24 Comparators (COMP)

3.25 Operational amplifier (OPAMP)

3.26 Digital filter for sigma-delta modulators (DFSDM)

3.27 Touch sensing controller (TSC)

3.28 Random number generator (RNG)

3.29 Advanced encryption standard hardware accelerator (AES)

3.30 HASH hardware accelerator (HASH)

3.31 Public key accelerator PKA

3.32 On-the-fly decryption engine (OTFDEC)

3.33 Timers and watchdogs

Table 16. Timer feature comparison

3.33.1 Advanced-control timer (TIM1, TIM8)

3.33.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16, TIM17)

3.33.3 Basic timers (TIM6 and TIM7)