ST MICROELECTRONICS STM32L496RET6 Datasheet

Ultra-low-power Arm® Cortex®-M4 32-bit MCU+FPU, 100DMIPS,

UFBGA132 (7 × 7)

LQFP144 (20 × 20)

UFBGA169 (7 x 7)

WLCSP100

LQFP100 (14 x 14)

LQFP64 (10 x 10)

up to 1MB Flash, 320KB SRAM, USB OTG FS, audio, ext. SMPS

Features

 Ultra-low-power with FlexPowerControl

– 1.71 V to 3.6 V power supply – -40 °C to 85/125 °C temperature range – 320 nA in V

32x32-bit backup registers – 25 nA Shutdown mode (5 wakeup pins) – 108 nA Standby mode (5 wakeup pins) – 426 nA Standby mode with RTC – 2.57 µA Stop 2 mode, 2.86 µA Stop 2 with

RTC – 91 µA/MHz run mode (LDO Mode) – 37 μA/MHz run mode (@3.3 V SMPS

Mode) – Batch acquisition mode (BAM) – 5 µs wakeup from Stop mode – Brown out reset (BOR) in all modes except

shutdown – Interconnect matrix

 Core: Arm

Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait-state execution from Flash memory, frequency up to 80 MHz, MPU, 100 DMIPS and DSP instructions

 Performance benchmark

– 1.25 DMIPS/MHz (Drystone 2.1) – 273.55 Coremark

80 MHz)

 Energy benchmark

– 279 ULPMark™ CP score – 80.2 ULPMark™ PP score

 16 x timers: 2 x 16-bit advanced motor-control,

2 x 32-bit and 5 x 16-bit general purpose,  2 x 16-bit basic, 2 x low-power 16-bit timers (available in Stop mode), 2 x watchdogs, SysTick timer

 RTC with HW calendar, alarms and calibration

mode: supply for RTC and

BAT

32-bit Cortex®-M4 CPU with FPU,

(3.42 Coremark/MHz @

STM32L496xx

Datasheet - production data

 Up to 136 fast I/Os, most 5 V-tolerant, up to 14

I/Os with independent supply down to 1.08 V

 Dedicated Chrom-ART Accelerator™ for

enhanced graphic content creation (DMA2D)

 8- to 14-bit camera interface up to 32 MHz

(black&white) or 10 MHz (color)

 Memories

– Up to 1 MB Flash, 2 banks read-while-

write, proprietary code readout protection

– 320 KB of SRAM including 64 KB with

hardware parity check

– External memory interface for static

memories supporting SRAM, PSRAM, NOR and NAND memories

– Dual-flash Quad SPI memory interface

 Clock Sources

– 4 to 48 MHz crystal oscillator – 32 kHz crystal oscillator for RTC (LSE) – Internal 16 MHz factory-trimmed RC (±1%) – Internal low-power 32 kHz RC (±5%) – Internal multispeed 100 kHz to 48 MHz

oscillator, auto-trimmed by LSE (better than

±0.25% accuracy) – Internal 48 MHz with clock recovery – 3 PLLs for system clock, USB, audio, ADC

 LCD 8 × 40 or 4 × 44 with step-up converter  Up to 24 capacitive sensing channels: support

touchkey, linear and rotary touch sensors

 4 x digital filters for sigma delta modulator  Rich analog peripherals (independent supply)

– 3 × 12-bit ADC 5 Msps, up to 16-bit with

hardware oversampling, 200 µA/Msps

January 2020 DS11585 Rev 11 1/281

This is information on a product in full production.

www.st.com

STM32L496xx

– 2 x 12-bit DAC output channels, low-power

sample and hold – 2 x operational amplifiers with built-in PGA – 2 x ultra-low-power comparators

 20 x communication interfaces

– USB OTG 2.0 full-speed, LPM and BCD – 2 x SAIs (serial audio interface) – 4 x I2C FM+(1 Mbit/s), SMBus/PMBus – 5 x U(S)ARTs (ISO 7816, LIN, IrDA,

modem)

Table 1. Device summary

Reference Part numbers

STM32L496xx

STM32L496AG, STM32L496QG, STM32L496RG, STM32L496VG, STM32L496ZG,  STM32L496AE, STM32L496QE, STM32L496RE, STM32L496VE, STM32L496ZE

– 1 x LPUART – 3 x SPIs (4 x SPIs with the Quad SPI) – 2 x CAN (2.0B Active) and SDMMC – SWPMI single wire protocol master I/F – IRTIM (Infrared interface)

 14-channel DMA controller  True random number generator  CRC calculation unit, 96-bit unique ID  Development support: serial wire debug

(SWD), JTAG, Embedded Trace Macrocell™



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STM32L496xx Contents

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.1 Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 18

3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.6 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.7 Firewall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.8 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.9 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 22

3.10 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.10.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.10.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.10.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.10.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.10.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.10.6 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.11 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.12 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.13 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.14 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.15 Chrom-ART Accelerator™ (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.16 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.16.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 41

3.16.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 41

3.17 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.17.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.17.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 43

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Contents STM32L496xx

3.17.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.18 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.19 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.20 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.21 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.22 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.23 Liquid crystal display controller (LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.24 Digital filter for Sigma-Delta Modulators (DFSDM) . . . . . . . . . . . . . . . . . . 46

3.25 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.26 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.27 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.27.1 Advanced-control timer (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.27.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16,

TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.27.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.27.4 Low-power timer (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . 50

3.27.5 Infrared interface (IRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.27.6 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.27.7 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.27.8 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.28 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 52

3.29 Inter-integrated circuit interface (I

C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.30 Universal synchronous/asynchronous receiver transmitter (USART) . . . 54

3.31 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 55

3.32 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.33 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.34 Single wire protocol master interface (SWPMI) . . . . . . . . . . . . . . . . . . . . 57

3.35 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.36 Secure digital input/output and MultiMediaCards Interface (SDMMC) . . . 58

3.37 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 58

3.38 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.39 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 59

3.40 Dual-flash Quad SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . 60

3.41 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

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3.41.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 61

3.41.2 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 124

6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 128

6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . 128

6.3.4 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

6.3.6 Wakeup time from low-power modes and voltage scaling

transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 161

6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 166

6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

6.3.10 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

6.3.16 Extended interrupt and event controller input (EXTI) characteristics . . 185

6.3.17 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

6.3.18 Analog-to-Digital converter characteristics . . . . . . . . . . . . . . . . . . . . . 186

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Contents STM32L496xx

6.3.19 Digital-to-Analog converter characteristics . . . . . . . . . . . . . . . . . . . . . 199

6.3.20 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 204

6.3.21 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

6.3.22 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 207

6.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

6.3.24 V

6.3.25 LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

6.3.26 DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

6.3.27 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

6.3.28 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 217

6.3.29 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

6.3.30 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 247

6.3.31 SWPMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

6.3.32 SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 249

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

BAT

7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

7.1 UFBGA169 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

7.2 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

7.3 UFBGA132 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

7.4 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

7.5 WLCSP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

7.6 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

7.7 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

7.7.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

7.7.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 274

8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

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STM32L496xx List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2. STM32L496xx family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . 15

Table 3. Access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 19

Table 4. STM32L496xx modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 5. Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 6. STM32L496xx peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 7. DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 8. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 9. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 10. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 11. I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 12. STM32L496xx USART/UART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 13. SAI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 14. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 15. STM32L496xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 16. Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 17. Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 18. STM32L496xx memory map and peripheral register boundary addresses . . . . . . . . . . . 118

Table 19. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Table 20. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Table 21. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Table 22. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Table 23. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Table 24. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 128

Table 25. Embedded internal voltage reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Table 26. Current consumption in Run and Low-power run modes, code with data processing 

running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . 133

Table 27. Current consumption in Run modes, code with data processing running from Flash, 

(ART enable Cache ON Prefetch OFF) and power supplied 

(by external SMPS (VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Table 28. Current consumption in Run and Low-power run modes, code with data processing

running from Flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Table 29. Current consumption in Run modes, code with data proce

ART disable and power supplied by external SMPS (VDD12 = 1.10 V). . . . . . . . . . . . . . 136

Table 30. Current consumption in Run and Low-power run modes, code with data processing 

running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Table 31. Current consumption in Run, code with data processing running from

SRAM1 and power supplied by external SMPS (VDD12 = 1.10 V). . . . . . . . . . . . . . . . . 138

Table 32. Typical current consumption in Run and Low-power run modes, with different codes

running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . 139

Table 33. Typical current consumption in Run, with different codes running from Flash, ART 

enable (Cache ON Prefetch OFF) and power supplied 

(by external SMPS (VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Table 34. Typical current consumption in Run, with different codes running from Flash, ART 

enable (Cache ON Prefetch OFF) and power supplied 

(by external SMPS (VDD12 = 1.05 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Table 35. Typical current consumption in Run and Low-power run modes, with different codes

running from Flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

ssing running from Flash, 

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Table 36. Typical current consumption in Run modes, with different codesrunning from

Flash, ART disable and power supplied by external SMPS (VDD12 = 1.10 V) . . . . . . . . 141

Table 37. Typical current consumption in Run modes, with different codesrunning from

Flash, ART disable and power supplied by external SMPS (VDD12 = 1.05 V) . . . . . . . . 141

Table 38. Typical current consumption in Run and Low-power run modes, with different codes

running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Table 39. Typical current consumption in Run, with different codesrunning from

SRAM1 and power supplied by external SMPS (VDD12 = 1.10 V). . . . . . . . . . . . . . . . . 142

Table 40. Typical current consumption in Run, with different codesrunning from

SRAM1 and power supplied by external SMPS (VDD12 = 1.05 V). . . . . . . . . . . . . . . . . 143

Table 41. Current consumption in Sleep and Low-power sleep modes, Flash ON . . . . . . . . . . . . . 144

Table 42. Current consumption in Sleep, Flash ON and power supplied 

by external SMPS (VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Table 43. Current consumption in Low-power sleep modes, Flash in power-down . . . . . . . . . . . . . 146

Table 44. Current consumption in Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Table 45. Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Table 46. Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Table 47. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Table 48. Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 49. Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Table 50. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Table 51. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Table 52. Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Table 53. Wakeup time using USART/LPUART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Table 54. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Table 55. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Table 56. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Table 57. LSE oscillator characteristics (f

= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

LSE

Table 58. HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Table 59.

MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168

Table 60. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Table 61. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Table 62. PLL, PLLSAI1, PLLSAI2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Table 63. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Table 64. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Table 65. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Table 66. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Table 67. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Table 68. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Table 69. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Table 70. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Table 71. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Table 72. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Table 73. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Table 74. EXTI Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Table 75. Analog switches booster characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Table 76. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Table 77. Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Table 78. ADC accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Table 79. ADC accuracy - limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Table 80. ADC accuracy - limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Table 81. ADC accuracy - limited test conditions 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

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Table 82. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

Table 83. DAC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Table 84. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Table 85. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Table 86. OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Table 87. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Table 88. V Table 89. V

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

BAT

charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

BAT

Table 90. LCD controller characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Table 91. DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Table 92. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Table 93. IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Table 94. WWDG min/max timeout value at 80 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Table 95. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Table 96. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Table 97. Quad SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Table 98. QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

Table 99. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Table 100. SD / MMC dynamic characteristics, VDD=2.7 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . 226

Table 101. eMMC dynamic characteristics, VDD = 1.71 V to 1.9 V . . . . . . . . . . . . . . . . . . . . . . . . . . 227

Table 102. USB OTG DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

Table 103. USB OTG electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

Table 104. USB BCD DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

Table 105. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 233

Table 106. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 233

Table 107. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 234

Table 108. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 235

Table 109. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Table 110. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 236

Table 111. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 237

Table 112. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 238

Table 113. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

Table 114. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

Table 115. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 243

Table 116. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Table 117. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

Table 118. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 247

Table 119. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

Table 120. SWPMI electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

Table 121. SD / MMC dynamic characteristics, VDD=2.7 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . 250

Table 122. SD / MMC dynamic characteristics, VDD=1.71 V to 1.9 V

. . . . . . . . . . . . . . . . . . . . . . . . 250

Table 123. UFBGA169 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

Table 124. UFBGA169 - Recommended PCB design rules (0.5 mm pitch BGA). . . . . . . . . . . . . . . . 253

Table 125. LQFP144 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

Table 126. UFBGA132 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

Table 127. UFBGA132 - Recommended PCB design rules (0.5 mm pitch BGA). . . . . . . . . . . . . . . . 262

Table 128. LQFP100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

Table 129. WLCSP100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

Table 130. WLCSP100 - Recommended PCB design rules (0.4 mm pitch). . . . . . . . . . . . . . . . . . . . 269

Table 131. LQFP64 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

Table 132. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

Table 133. STM32L496xx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

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List of tables STM32L496xx

Table 134. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

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STM32L496xx List of figures

List of figures

Figure 1. STM32L496xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 2. Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 3. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 4. Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 5. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 6. Voltage reference buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 7. STM32L496Ax UFBGA169 pinout Figure 8. STM32L496Ax, external SMPS device, UFBGA169 pinout Figure 9. STM32L496Zx LQFP144 pinout Figure 10. STM32L496Zx, external SMPS device, LQFP144 pinout Figure 11. STM32L496Qx UFBGA132 ballout

Figure 12. STM32L496Qx, external SMPS device, UFBGA132 ballout . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 13. STM32L496Vx LQFP100 pinout Figure 14. STM32L496Vx, external SMPS device, LQFP100 pinout Figure 15. STM32L496Vx WLCSP100 pinout Figure 16. STM32L496Vx, external SMPS device, WLCSP100 pinout Figure 17. STM32L496Rx LQFP64 pinout Figure 18. STM32L496Rx, external SMPS, LQFP64 pinout

Figure 19. STM32L496xx memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 20. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Figure 21. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Figure 22. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Figure 23. Current consumption measurement scheme with and without external

SMPS power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 24. VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Figure 25. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Figure 26. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Figure 27. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Figure 28. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Figure 29. HSI16 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Figure 30. Typical current consumption versus MSI frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Figure 31. HSI48 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Figure 32. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Figure 33. I/O AC characteristics definition

Figure 34. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Figure 35. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Figure 36. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Figure 37. 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Figure 38. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

Figure 39. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

Figure 40. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

Figure 41. Quad SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

Figure 42. Quad SPI timing diagram - DDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

Figure 43. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Figure 44. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

Figure 45. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

Figure 46. SD default mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

Figure 47. USB OTG timings – definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . 229

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

(1)

. . . . . . . . . . . . . . . . . . . . . . 62

(1)

. . . . . . . . . . . . . . . . . . . . . . . . 64

(1)

. . . . . . . . . . . . . . . . . . . . . . . . 67

(1)

. . . . . . . . . . . . . . . . . . . . . . 68

DS11585 Rev 11 11/281

List of figures STM32L496xx

Figure 48. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 232

Figure 49. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 234

Figure 50. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 235

Figure 51. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 237

Figure 52. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

Figure 53. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

Figure 54. Synchronous non-multiplexed NOR/PSRAM read timings. . . . . . . . . . . . . . . . . . . . . . . . 243

Figure 55. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

Figure 56. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Figure 57. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Figure 58. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 246

Figure 59. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 247

Figure 60. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

Figure 61. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

Figure 62. SD default mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

Figure 63. UFBGA169 - Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

Figure 64. UFBGA169 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

Figure 65. UFBGA169 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

Figure 66. UFBGA169, external SMPS device, marking (package top view) . . . . . . . . . . . . . . . . . . 255

Figure 67. LQFP144 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

Figure 68. LQFP144 - Recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

Figure 69. LQFP144 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

Figure 70. LQFP144, external SMPS device, marking (package top view) . . . . . . . . . . . . . . . . . . . . 260

Figure 71. UFBGA12 - Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

Figure 72. UFBGA132 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

Figure 73. UFBGA132 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

Figure 74. UFBGA132, external SMPS device, marking (package top view) . . . . . . . . . . . . . . . . . . 263

Figure 75. LQFP100 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

Figure 76. LQFP100 -Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

Figure 77. LQFP100 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

Figure 78. LQFP100, external SMPS device, marking (package top view) . . . . . . . . . . . . . . . . . . . . 266

Figure 79. WLCSP100 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

Figure 80. WLCSP100- Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

Figure 81. WLCSP100 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

Figure 82. WLCSP100, external SMPS device, marking (package top view) . . . . . . . . . . . . . . . . . . 270

Figure 83. LQFP64 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

Figure 84. LQFP64 - Recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

Figure 85. LQFP64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

Figure 86. LQFP64, external SMPS device, marking (package top view) . . . . . . . . . . . . . . . . . . . . . 273

12/281 DS11585 Rev 11

STM32L496xx Introduction

1 Introduction

This datasheet provides the ordering information and mechanical device characteristics of

the STM32L496xx microcontrollers.

This document should be read in conjunction with the STM32L47x, STM32L48x,

STM32L49x and STM32L4Ax reference manual (RM0351). The reference manual is

available from the STMicroelectronics website www.st.com.

For information on the Arm

Reference Manual, available from the www.arm.com website.

®(a)

Cortex®-M4 core, please refer to the Cortex®-M4 Technical

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

DS11585 Rev 11 13/281

Description STM32L496xx

2 Description

The STM32L496xx devices are the ultra-low-power microcontrollers based on the high-

performance Arm

The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all

Arm

single-precision data-processing instructions and data types. It also implements a full

Cortex®-M4 32-bit RISC core operating at a frequency of up to 80 MHz.

set of DSP instructions and a memory protection unit (MPU) which enhances application

security.

The STM32L496xx devices embed high-speed memories (up to 1 Mbyte of Flash memory,

320

Kbyte of SRAM), a flexible external memory controller (FSMC) for static memories (for devices with packages of 100 pins and more), a Quad SPI flash memories interface (available on all packages) and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.

The STM32L496xx devices embed several protection mechanisms for embedded Flash memory and SRAM: readout protection, write protection, proprietary code readout protection and Firewall.

The devices offer up to three fast 12-bit ADCs (5 Msps), two comparators, two operational amplifiers, two DAC channels, an internal voltage reference buffer, a low-power RTC, two general-purpose 32-bit timer, two 16-bit PWM timers dedicated to motor control, seven general-purpose 16-bit timers, and two 16-bit low-power timers. The devices support four digital filters for external sigma delta modulators (DFSDM).

In addition, up to 24 capacitive sensing channels are available. The devices also embed an integrated LCD driver 8x40 or 4x44, with internal step-up converter.

They also feature standard and advanced communication interfaces.

 Four I2Cs  Three SPIs  Three USARTs, two UARTs and one Low-Power UART.  Two SAIs (Serial Audio Interfaces)  One SDMMC  Two CAN  One USB OTG full-speed  One SWPMI (Single Wire Protocol Master Interface)  Camera interface  DMA2D controller

The STM32L496xx operates in the -40 to +85 °C (+105 °C junction), -40 to +125 °C (+130

°C junction) temperature ranges from a 1.71 to 3.6 V VDD power supply when using

internal LDO regulator and a 1.05 to 1.32V V

DD12

supply. A comprehensive set of power-saving modes allows the design of low-power applications.

Some independent power supplies are supported: analog independent supply input for ADC, DAC, OPAMPs and comparators, 3.3

V dedicated supply input for USB and up to 14 I/Os can be supplied independently down to 1.08V. A VBAT input allows to backup the RTC and backup registers. Dedicated V

power supplies can be used to bypass the internal

DD12

LDO regulator when connected to an external SMPS.

14/281 DS11585 Rev 11

power supply when using external SMPS

STM32L496xx Description

The STM32L496xx family offers six packages from 64-pin to 169-pin packages.

Table 2. STM32L496xx family device features and peripheral counts

Peripheral STM32L496Ax STM32L496Zx STM32L496Qx STM32L496Vx STM32L496Rx

Flash memory 512KB 1MB 512KB 1MB 512KB 1MB 512KB 1MB 512KB 1MB

SRAM 320 KB

External memory controller for static

Yes Yes Yes Yes

memories

Quad SPI Yes

Advanced control

General purpose

2 (16-bit)

5 (16-bit) 2 (32-bit)

Basic 2 (16-bit)

Timers

Low power 2 (16-bit)

SysTick timer 1

Watchdog timers (independent

window)

(1)

SPI 3

Comm. interfaces

USART UART LPUART

SAI 2

3 2 1

CAN 2

USB OTG FS Yes

SDMMC Yes

SWPMI Yes

Digital filters for sigmadelta modulators

Yes (4 filters)

Number of channels 8

RTC Yes

Ta mp e r p in s 3

Camera interface Yes Yes

Chrom-ART Accelerator™

LCD COM x SEG

Yes

8x40 or 4x44

(2)

DS11585 Rev 11 15/281

Description STM32L496xx

Table 2. STM32L496xx family device features and peripheral counts (continued)

Peripheral STM32L496Ax STM32L496Zx STM32L496Qx STM32L496Vx STM32L496Rx

Random generator Yes

(3)

GPIOs Wakeup pins Nb of I/Os down to

1.08 V

136

115

110

52 5 0

4 0

Capacitive sensing Number of channels

12-bit ADCs Number of channels

24 24 24 21 21

12-bit DAC channels 2

Internal voltage reference buffer

Yes

Analog comparator 2

Operational amplifiers 2

Max. CPU frequency 80 MHz

Operating voltage (V

Operating voltage

)

DD12

Operating temperature

Packages UFBGA169 LQFP144 UFBGA132

1. For the LQFP100 and WLCSP100 packages, only FMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select.

2. Only up to 13 data bits.

3. In case external SMPS package type is used, 2 GPIO's are replaced by VDD12 pins to connect the SMPS power supplies hence reducing the number of available GPIO's by 2.

) 1.71 to 3.6 V

1.05 to 1.32 V

Ambient operating temperature: -40 to 85 °C / -40 to 125 °C

Junction temperature: -40 to 105 °C / -40 to 130 °C

LQFP100

WLCSP100

LQFP64

16/281 DS11585 Rev 11

STM32L496xx Description

MS50053V1

USB OTG

Flash up to 1 MB

Flexible static memory controller (FSMC):

SRAM, PSRAM, NOR Flash,

NAND Flash

GPIO PORT A

AHB/APB2

EXT IT. WKUP

114 AF

PA[15:0]

TIM1 / PWM

3 compl. channels (TIM1_CH[1:3]N),

4 channels (TIM1_CH[1:4]),

ETR, BKIN, BKIN2 as AF

USART1

RX, TX, CK,CTS,

RTS as AF

SPI1

MOSI, MISO,

SCK, NSS as AF

APB260 M Hz

APB1 30MHz

MOSI, MISO, SCK, NSS as AF

DAC1_OUT1

ITF

WWDG

RTC_TS

OSC32_IN

OSC32_OUT

VDDA, VSSA

VDD, VSS, NRST

smcard

IrDA

16b

SDIO / MMC

D[7:0]

CMD, CK as AF

VBAT = 1.55 to 3.6 V

SCL, SDA, SMBA as AF

JTAG & SW

ARM Cortex-M4

80 MHz

FPU

NVIC

ETM

MPU

TRACECLK

TRACED[3:0]

DMA2

ART

ACCEL/

CACHE

CLK, NE[4:1], NL, NBL[1:0], A[25:0], D[15:0], NOE, NWE, NWAIT, NCE3, INT3 as AF

RNG

DM SCL, SDA, INTN, ID, VBUS, SOF

FIFO

@ VDDA

BOR

Supply

supervision

PVD, PVM

Int

reset

XTAL 32 kHz

MAN AGT

RTC

FCLK

Standby

interface

IWDG

@VBAT

@ VDD

@VDD

AWU

Reset & clock

control

PCLKx

VDD = 1.71 to 3.6 V

VSS

Voltage

regulator

3.3 to 1.2 V

VDD

Power management

@ VDD

RTC_TAMPx

Backup register

AHB bus-matrix

TIM15

2 channels,

1 compl. channel, BKIN as

DAC1

TIM6

TIM7

TIM2

TIM3

TIM4

TIM5

USART2

USART3

I2C1/SMBUS

D-BUS

APB1 80 MHz (max)

SRAM 256 KB

SRAM 64 KB

NJTRST, JTDI,

JTCK/SWCLK

JTDO/SWD, JTDO

I-BUS

S-BUS

DMA1

PB[15:0]

PC[15:0]

PD[15:0]

PE[15:0]

PF[15:0]

PG[15:0]

PH[15:0]

GPIO PORT B

GPIO PORT C

GPIO PORT D

GPIO PORT E

GPIO PORT F

GPIO PORT G

GPIO PORT H

TIM8 / PWM

16b

TIM16

16b

TIM17

16b

3 compl. Channels (TIM1_CH[1:3]N),

4 channels (TIM1_CH[1:4]),

ETR, BKIN, BKIN2 as AF

1 channel,

1 compl. channel, BKIN as AF

1 channel,

1 compl. channel, BKIN as AF

DAC1_OUT2

16b

SCL, SDA, SMBA as AF

MOSI, MISO, SCK, NSS as AF

TX, RX as AF

RX, TX, CTS, RTS as AF

RX, TX, CK, CTS, RTS as AF

smcard

IrDA

smcard

IrDA

32b

16b

32b

4 channels, ETR as AF

AHB/APB1

OSC_IN

OSC_OUT

HCLKx

XTAL OSC

4- 48MHz

8 analog inputs common to the 3 ADCs

VREF+

USAR T 2MBps

Temperature sensor

ADC1

ADC2

ADC3

ITF

@ VDDA

8 analog inputs common to the ADC1 & 2

8 analog inputs for ADC3

SAI1

MCLK_A, SD_A, FS_A, SCK_A, EXTCLK

MCLK_B, SD_B, FS_B, SCK_B as AF

SAI2

MCLK_A, SD_A, FS_A, SCK_A, EXTCLK

MCLK_B, SD_B, FS_B, SCK_B as AF

DFSDM

SDCKIN[7:0], SDDATIN[7:0],

SDCKOUT,SDTRIG as AF

Touch sensing controller

8 Groups of 4 channels max as AF

OUT, INN, INP

LCD 8x40

LPUART1

SWPMI

LPTIM1

LPTIM2

SEGx, COMx as AF

RX, TX, CTS, RTS as AF

SWP

IN1, IN2, OUT, ETR as AF

IN1, OUT, ETR as AF

RC HSI

RC LSI

PLL 1&2&3

MSI

Quad SPI memory interface

D0[3:0], D1[3:0], CLK0, CLK1, CS

@ VDDUSB

COMP1

INP, INN, OUT

COMP2

INP, INN, OUT

@ VDDA

RTC_OUT

VDDIO, VDDUSB

FIFO

PHY

AHB1 80 MHz

CRC

OUT, INN, INP

I2C2/SMBUS

I2C3/SMBUS

OpAmp1

SP3

SP2

UART5

UART4

LCD Booster

LCD

= 2.5V to 3.6V

APB2 80MHz

AHB2 80 MHz

OpAmp2

@VDDA

Firewall

VREF Buffer

@ VDDA

@ VDD

Camera Interface

FIFO

HSYNC, VSYNC, PIXCLK, D[13:0]

CHROM-ART

DMA2D

FIFO

PI[11:0]

GPIO PORT I

TX, RX as AF

bxCAN1

SCL, SDA, SMBA as AF

I2C4/SMBUS

HSI48

bxCAN1

FIFO

CRS

CRS_SYNC

VDD12

VDD12 = 1.05 to 1.32 V

(1)

1. Only available when using external SMPS supply mode

Figure 1. STM32L496xx block diagram

Note: AF: alternate function on I/O pins.

DS11585 Rev 11 17/281

Functional overview STM32L496xx

3 Functional overview

3.1 Arm® Cortex®-M4 core with FPU

The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm® processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.

The Arm® Cortex®-M4 with FPU 32-bit RISC processor features exceptional codeefficiency, delivering the high-performance expected from an Arm usually associated with 8- and 16-bit devices.

The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution.

Its single precision FPU speeds up software development by using metalanguage development tools, while avoiding saturation.

With its embedded Arm® core, the STM32L496xx family is compatible with all Arm® tools and software.

Figure 1 shows the general block diagram of the STM32L496xx family devices.

core in the memory size

3.2 Adaptive real-time memory accelerator (ART Accelerator™)

The ART Accelerator™ is a memory accelerator which is optimized for STM32 industrystandard Arm the Arm processor to wait for the Flash memory at higher frequencies.

To release the processor near 100 DMIPS performance at 80MHz, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 64-bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 80 MHz.

Cortex®-M4 processors. It balances the inherent performance advantage of

Cortex®-M4 over Flash memory technologies, which normally requires the

3.3 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory.

The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

18/281 DS11585 Rev 11

STM32L496xx Functional overview

3.4 Embedded Flash memory

STM32L496xx devices feature up to 1 Mbyte of embedded Flash memory available for storing programs and data. The Flash memory is divided into two banks allowing readwhile-write operations. This feature allows to perform a read operation from one bank while an erase or program operation is performed to the other bank. The dual bank boot is also supported. Each bank contains 256 pages of 2

Flexible protections can be configured thanks to option bytes:  Readout protection (RDP) to protect the whole memory. Three levels are available:

– Level 0: no readout protection – Level 1: memory readout protection: the Flash memory cannot be read from or

written to if either debug features are connected, boot in RAM or bootloader is selected

– Level 2: chip readout protection: debug features (Cortex-M4 JTAG and serial

wire), boot in RAM and bootloader selection are disabled (JTAG fuse). This selection is irreversible.

Table 3. Access status versus readout protection level and execution modes

Kbyte.

Area

Main

memory

System

memory

Option

bytes

Backup

registers

SRAM2

1. Erased when RDP change from Level 1 to Level 0.

Protection

level

1 Yes Yes Yes No No No

2 Yes Yes Yes N/A N/A N/A

1 Yes No No Yes No No

2 Yes No No N/A N/A N/A

1 Yes Yes Yes Yes Yes Yes

2 Yes No No N/A N/A N/A

1YesYesN/A

2 Yes Yes N/A N/A N/A N/A

1 Yes Yes Yes

2 Yes Yes Yes N/A N/A N/A

User execution

Read Write Erase Read Write Erase

(1)

Debug, boot from RAM or boot

from system memory (loader)

No No N/A

No No No

 Write protection (WRP): the protected area is protected against erasing and

programming. Two areas per bank can be selected, with 2-Kbyte granularity.

 Proprietary code readout protection (PCROP): a part of the flash memory can be

protected against read and write from third parties. The protected area is execute-only: it can only be reached by the STM32 CPU, as an instruction code, while all other accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited. One area per bank can be selected, with 64-bit granularity. An additional option bit (PCROP_RDP) allows to select if the PCROP area is erased or not when the RDP protection is changed from Level 1 to Level 0.

(1)

DS11585 Rev 11 19/281

Functional overview STM32L496xx

The whole non-volatile memory embeds the error correction code (ECC) feature supporting:

 single error detection and correction  double error detection.  The address of the ECC fail can be read in the ECC register

3.5 Embedded SRAM

STM32L496xx devices feature 320 Kbyte of embedded SRAM. This SRAM is split into two blocks:

 256 Kbyte mapped at address 0x2000 0000 (SRAM1)  64 Kbyte located at address 0x1000 0000 with hardware parity check (SRAM2).

This memory is also mapped at address 0x2004 0000, offering a contiguous address space with the SRAM1.

This block is accessed through the ICode/DCode buses for maximum performance. These 64 Kbyte SRAM can also be retained in Standby mode.

The SRAM2 can be write-protected with 1 Kbyte granularity.

The memory can be accessed in read/write at CPU clock speed with 0 wait states.

20/281 DS11585 Rev 11

STM32L496xx Functional overview

MSv38030V3

ARM

CORTEX

-M4 with FPU

DMA1 DMA2

FMC

AHB2

peripherals

AHB1

peripherals

SRAM2

FLASH

1 MB

ACCEL

S0 S1 S2 S3 S4

M0 M1 M2 M3 M4 M5 M6

ICode

DCode

QUADSPI

DMA2D

BusMatrix-S

128KB

SRAM1

3.6 Multi-AHB bus matrix

The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs and the DMA2D) and the slaves (Flash memory, RAM, FMC, QUADSPI, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high speed peripherals work simultaneously.

Figure 2. Multi-AHB bus matrix

3.7 Firewall

The device embeds a Firewall which protects code sensitive and secure data from any access performed by a code executed outside of the protected areas.

Each illegal access generates a reset which kills immediately the detected intrusion.

DS11585 Rev 11 21/281

Functional overview STM32L496xx

The Firewall main features are the following:  Three segments can be protected and defined thanks to the Firewall registers:

– Code segment (located in Flash or SRAM1 if defined as executable protected

area) – Non-volatile data segment (located in Flash) – Volatile data segment (located in SRAM1)

 The start address and the length of each segments are configurable:

– Code segment: up to 1024 Kbyte with granularity of 256 bytes – Non-volatile data segment: up to 1024 Kbyte with granularity of 256 bytes – Volatile data segment: up to 256 Kbyte of SRAM1 with a granularity of 64 bytes

 Specific mechanism implemented to open the Firewall to get access to the protected

areas (call gate entry sequence)

 Volatile data segment can be shared or not with the non-protected code  Volatile data segment can be executed or not depending on the Firewall configuration

The Flash readout protection must be set to level 2 in order to reach the expected level of protection.

3.8 Boot modes

At startup, BOOT0 pin and nBOOT1 option bit are used to select one of three boot options:

 Boot from user Flash  Boot from system memory  Boot from embedded SRAM

BOOT0 value may come from the PH3-BOOT0 pin or from an option bit depending on the value of a user option bit to free the GPIO pad if needed.

A Flash empty check mechanism is implemented to force the boot from system flash if the first flash memory location is not programmed and if the boot selection is configured to boot from main flash.

The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART, I2C, SPI, CAN or USB OTG FS in Device mode through DFU (device firmware upgrade).

3.9 Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.

22/281 DS11585 Rev 11

STM32L496xx Functional overview

3.10 Power supply management

3.10.1 Power supply schemes

 VDD = 1.71 to 3.6 V: external power supply for I/Os (V

), the internal regulator and

DDIO1

the system analog such as reset, power management and internal clocks. It is provided externally through VDD pins.

 V

= 1.05 to 1.32 V: external power supply bypassing internal regulator when

DD12

connected to an external SMPS. It is provided externally through VDD12 pins and only available on packages with the external SMPS supply option. VDD12 does not require any external decoupling capacitance and cannot support any external load.

 V

= 1.62 V (ADCs/COMPs) / 1.8 (DAC/OPAMPs) to 3.6 V: external analog power

DDA

supply for ADCs, DAC, OPAMPs, Comparators and Voltage reference buffer. The V voltage level is independent from the V

= 3.0 to 3.6 V: external independent power supply for USB transceivers. The

DDUSB

voltage level is independent from the VDD voltage.

DDUSB

= 1.08 to 3.6 V: external power supply for 14 I/Os (PG[15:2]). The V

DDIO2

voltage level is independent from the V

= 2.5 to 3.6 V: the LCD controller can be powered either externally through VLCD

LCD

voltage.

DDIO2

DDA

pin, or internally from an internal voltage generated by the embedded step-up converter.

 V

Note: When the functions supplied by V

should preferably be shorted to V

= 1.55 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and

BAT

backup registers (through power switch) when V

DDA

, V

DDUSB

or V

is not present.

are not used, these supplies

DDIO2

Note: If these supplies are tied to ground, the I/Os supplied by these power supplies are not 5 V

tolerant (refer to

Table 19: Voltage characteristics).

Note: V

DDIOx

DDIO2

is the I/Os general purpose digital functions supply. V , with V

DDIO1

= VDD. V

supply voltage level is independent from V

DDIO2

DS11585 Rev 11 23/281

represents V

DDIOx

DDIO1

Functional overview STM32L496xx

MSv43899V1

DDA

domain

Backup domain

D/A converters

A/D converters

Standby circuitry (Wakeup logic, IWDG)

Voltage regulator

Low voltage detector

LSE crystal 32 K osc BKP registers RCC BDCR register RTC

comparators

operational amplifiers

Voltage reference buffer

I/O ring

CORE

domain

Temp. sensor

Reset block

PLL, HSI, MSI

LCD

USB transceivers

DDUSB

DDIO2

DDIO1

I/O ring

PG[15:2]

DDIO2

DDA

SSA

DDIO2

domain

CORE

BAT

Core

Digital

peripherals

Memories

DD12

Figure 3. Power supply overview

During power-up and power-down phases, the following power sequence requirements must be respected:

 When VDD is below 1 V, other power supplies (V

remain below V

 When V During the power-down phase, VDD can temporarily become lower than other supplies only

if the energy provided to the MCU remains below 1 capacitors to be discharged with different time constants during the power-down transient phase.

24/281 DS11585 Rev 11

+ 300 mV.

is above 1 V, all power supplies are independent.

DDA

, V

DDUSB

, V

DDIO2

, V

LCD

) must

mJ; this allows external decoupling

STM32L496xx Functional overview

MSv47490V1

0.3

BOR0

3.6

Operating modePower-on Power-down time

DDX

(1)

Invalid supply area V

DDX

< V

+ 300 mV

DDX

independent from V

Figure 4. Power-up/down sequence

1. V

refers to any power supply among V

DDX

3.10.2 Power supply supervisor

The device has an integrated ultra-low-power brown-out reset (BOR) active in all modes except Shutdown and ensuring proper operation after power-on and during power down. The device remains in reset mode when the monitored supply voltage V specified threshold, without the need for an external reset circuit.

The lowest BOR level is 1.71V at power on, and other higher thresholds can be selected through option bytes.The device features an embedded programmable voltage detector (PVD) that monitors the V interrupt can be generated when V higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

In addition, the device embeds a Peripheral Voltage Monitor which compares the independent supply voltages V that the peripheral is in its functional supply range.

power supply and compares it to the VPVD threshold. An

, V

DDA

drops below the VPVD threshold and/or when VDD is

, V

DDA

DDUSB

, V

DDIO2

, V

LCD

is below a

DDIO2

with a fixed threshold in order to ensure

DS11585 Rev 11 25/281

Functional overview STM32L496xx

3.10.3 Voltage regulator

Two embedded linear voltage regulators supply most of the digital circuitries: the main regulator (MR) and the low-power regulator (LPR).

 The MR is used in the Run and Sleep modes and in the Stop 0 mode.  The LPR is used in Low-Power Run, Low-Power Sleep, Stop 1 and Stop 2 modes. It is

also used to supply the 64 Kbyte SRAM2 in Standby with SRAM2 retention.

 Both regulators are in power-down in Standby and Shutdown modes: the regulator

output is in high impedance, and the kernel circuitry is powered down thus inducing zero consumption.

The ultralow-power STM32L496xx supports dynamic voltage scaling to optimize its power consumption in run mode. The voltage from the Main Regulator that supplies the logic (V

There are two power consumption ranges:

 Range 1 with the CPU running at up to 80 MHz.  Range 2 with a maximum CPU frequency of 26 MHz. All peripheral clocks are also

) can be adjusted according to the system’s maximum operating frequency.

CORE

limited to 26 MHz.

The V

can be supplied by the low-power regulator, the main regulator being switched

CORE

off. The system is then in Low-power run mode.  Low-power run mode with the CPU running at up to 2 MHz. Peripherals with

independent clock can be clocked by HSI16.

When the MR is in use, the STM32L496xx with the external SMPS option allows to force an external V

When V

DD12

supply on the VDD12 supply pins.

CORE

is forced by an external source and is higher than the output of the internal LDO, the current is taken from this external supply and the overall power efficiency is significantly improved if using an external step down DC/DC converter.

3.10.4 Low-power modes

The ultra-low-power STM32L496xx supports seven low-power modes to achieve the best compromise between low-power consumption, short startup time, available peripherals and available wakeup sources.

26/281 DS11585 Rev 11

Mode Regulator

(1)

Table 4. STM32L496xx modes overview

CPU Flash SRAM Clocks DMA & Peripherals

(2)

Wakeup source Consumption

(3)

STM32L496xx Functional overview

Wakeup time

DS11585 Rev 11 27/281

MR range 1

SMPS range 2 High 40 µA/MHz

Run

Yes ON

MR range2

SMPS range 2 Low 39 µA/MHz

LPRun LPR Yes ON

MR range 1

SMPS range 2 High 11.5 µA/MHz

Sleep

No ON

MR range2

SMPS range 2 Low 13 µA/MHz

LPSleep LPR No ON

MR Range 1

Stop 0

MR Range 2

(8)

No OFF ON

(8)

(4)

ON Any

except

(7)

except

LSE

Any

PLL

Any

PLL

LSI

All

108 µA/MHz

N/A

93 µA/MHz

All except OTG_FS, RNG

All except OTG_FS, RNG N/A 129 µA/MHz

32 µA/MHz

All

Any interrupt or

event

30 µA/MHz

All except OTG_FS, RNG

Any interrupt or

event

51 µA/MHz 6 cycles

BOR, PVD, PVM RTC,LCD, IWDG

COMPx (x=1,2)

DAC1

OPAMPx (x=1,2)

USARTx (x=1...5)

LPUART1

I2Cx (x=1...4)

(9)

(10)

LPTIMx (x=1,2)

***

All other peripherals are

Reset pin, all I/Os

BOR, PVD, PVM

RTC, LCD, IWDG

COMPx (x=1..2)

USARTx (x=1...5)

LPUART1

I2Cx (x=1...4)

(9)

(10)

LPTIMx (x=1,2)

OTG_FS SWPMI1

(11) (12)

TBD

(9)

127 µA

frozen.

(5)

N/A

(6)

to Range 1: 4 µs

to Range 2: 64 µs

(5)

6 cycles

(6)

2.7 µs in SRAM

6.2 µs in Flash

28/281 DS11585 Rev 11

Mode Regulator

(1)

CPU Flash SRAM Clocks DMA & Peripherals

Table 4. STM32L496xx modes overview (continued)

(2)

Wakeup source Consumption

(3)

Wakeup time

Functional overview STM32L496xx

BOR, PVD, PVM

Reset pin, all I/Os

BOR, PVD, PVM

RTC, LCD, IWDG

COMPx (x=1..2)

USARTx (x=1...5)

LPUART1

I2Cx (x=1...4)

(9)

(10)

LPTIMx (x=1,2)

OTG_FS SWPMI1

(11) (12)

(9)

11. 2 µA w/o RTC

11.8 µA w RT C

6.6 µs in SRAM

7.8 µs in Flash

Stop 1 LPR No Off ON

LSE

LSI

RTC, LCD, IWDG

COMPx (x=1,2)

DAC1

OPAMPx (x=1,2)

USARTx (x=1...5)

LPUART1

I2Cx (x=1...4)

(9)

(10)

LPTIMx (x=1,2)

***

All other peripherals are

frozen.

BOR, PVD, PVM

Reset pin, all I/Os

BOR, PVD, PVM

RTC, LCD, IWDG

COMPx (x=1..2)

(10)

I2C3

LPUART1

(9)

LPTIM1

2.57 µA w/o RTC

2.86 µA w/RTC

6.8 µs in SRAM

8.2 µs in Flash

Stop 2 LPR No Off ON

LSE

LSI

RTC, LCD, IWDG

COMPx (x=1..2)

(10)

I2C3

LPUART1

(9)

LPTIM1

***

All other peripherals are

frozen.

Mode Regulator

(1)

Table 4. STM32L496xx modes overview (continued)

CPU Flash SRAM Clocks DMA & Peripherals

(2)

Wakeup source Consumption

(3)

STM32L496xx Functional overview

Wakeup time

BOR, RTC, IWDG

***

All other peripherals are

powered off.

***

I/O configuration can be

Reset pin

5 I/Os (WKUPx)

BOR, RTC, IWDG

(13)

Standby

LPR

OFF

Power

ed Off

Off

SRAM

2 ON

Power

Off

LSE

LSI

floating, pull-up or pull-down

RTC

***

All other peripherals are

powered off.

I/O configuration can be

floating, pull-up or pull-

down

= 1.10 V

CORE

= 1.05 V

CORE

***

(14)

Shutdown OFF

Power

ed Off

Off

Power

Off

LSE

DS11585 Rev 11 29/281

1. LPR means Main regulator is OFF and Low-power regulator is ON.

2. All peripherals can be active or clock gated to save power consumption.

3. Typical current at V LPRun/LPSleep.

4. The Flash memory can be put in power-down and its clock can be gated off when executing from SRAM.

5. Theoretical value based on V

6. Theoretical value based on V

7. The SRAM1 and SRAM2 clocks can be gated on or off independently.

8. SMPS mode can be used in STOP0 Mode, but no significant power gain can be expected.

9. U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event.

10. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.

11. OTG_FS wakeup by resume from suspend and attach detection protocol event.

12. SWPMI1 wakeup by resume from suspend.

13. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5.

14. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode.

= 1.8 V, 25°C. Consumptions values provided running from SRAM, Flash memory Off, 80 MHz in Range 1, 26 MHz in Range 2, 2 MHz in

= 3.3 V, DC/DC Efficiency of 85%, V

Reset pin

5 I/Os (WKUPx)

RTC

(14)

0.48 µA w/o RTC

0.78 µA w/ RTC

0.11 µA w/o RTC

0.42 µA w/ RTC

0.03 µA w/o RTC

0.23 µA w/ RTC

15.3 µs

306 µs

Functional overview STM32L496xx

By default, the microcontroller is in Run mode after a system or a power Reset. It is up to the user to select one of the low-power modes described below:

 Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

 Low-power run mode

This mode is achieved with V

supplied by the low-power regulator to minimize the

CORE

regulator's operating current. The code can be executed from SRAM or from Flash, and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can be clocked by HSI16.

 Low-power sleep mode

This mode is entered from the low-power run mode. Only the CPU clock is stopped. When wakeup is triggered by an event or an interrupt, the system reverts to the lowpower run mode.

 Stop 0, Stop 1 and Stop 2 modes

Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the V

domain are stopped, the PLL, the MSI

CORE

RC, the HSI16 RC and the HSE crystal oscillators are disabled. The LSE or LSI is still running.

The RTC can remain active (Stop mode with RTC, Stop mode without RTC). Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode

to detect their wakeup condition. Three Stop modes are available: Stop 0, Stop 1 and Stop 2 modes. In Stop 2 mode,

most of the V

domain is put in a lower leakage mode.

CORE

Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator remains ON, allowing a very fast wakeup time but with much higher consumption.

The system clock when exiting from Stop 0, Stop 1 or Stop 2 modes can be either MSI up to 48 MHz or HSI16, depending on software configuration.

 Standby mode

The Standby mode is used to achieve the lowest power consumption with BOR. The internal regulator is switched off so that the V

domain is powered off. The PLL, the

CORE

MSI RC, the HSI16 RC and the HSE crystal oscillators are also switched off. The RTC can remain active (Standby mode with RTC, Standby mode without RTC). The brown-out reset (BOR) always remains active in Standby mode. The state of each I/O during standby mode can be selected by software: I/O with

internal pull-up, internal pull-down or floating. After entering Standby mode, SRAM1 and register contents are lost except for registers

in the Backup domain and Standby circuitry. Optionally, SRAM2 can be retained in Standby mode, supplied by the low-power Regulator (Standby with SRAM2 retention mode).

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE).

The system clock after wakeup is MSI up to 8 MHz.

30/281 DS11585 Rev 11

+ 251 hidden pages

ST MICROELECTRONICS STM32L496RET6 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Table 1. Device summary

1 Introduction

2 Description

Table 2. STM32L496xx family device features and peripheral counts

Figure 1. STM32L496xx block diagram

3 Functional overview

3.1 Arm® Cortex®-M4 core with FPU

3.2 Adaptive real-time memory accelerator (ART Accelerator™)

3.3 Memory protection unit

3.4 Embedded Flash memory

Table 3. Access status versus readout protection level and execution modes

3.5 Embedded SRAM

3.6 Multi-AHB bus matrix

Figure 2. Multi-AHB bus matrix

3.7 Firewall

3.8 Boot modes

3.9 Cyclic redundancy check calculation unit (CRC)

3.10 Power supply management

3.10.1 Power supply schemes

Figure 3. Power supply overview

Figure 4. Power-up/down sequence

3.10.2 Power supply supervisor

3.10.3 Voltage regulator

3.10.4 Low-power modes

Table 4. STM32L496xx modes overview