STMicroelectronics STM32L4R, STM32L4A6, STM32L4S5, STM32L4S7, STM32L4R7 Application Note

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AN4943

Application note

Using the Chrom-ART Accelerator™ to refresh an LCD-TFT

display on STM32L496xx/L4A6xx/L4Rxxx/L4Sxxx microcontrollers

Introduction

The purpose of this application note is to highlight how to refresh an LCD-TFT display via the FSMC interface using the Chrom-ART Accelerator™ on STM32L496xx/L4A6xx/L4Rxxx/L4Sxxx microcontrollers.

The STM32L496xx/L4A6xx/L4Rxxx/L4Sxxx microcontrollers implement a Chrom-Art Accelerator™ (DMA2D) that is a specialized DMA dedicated to image manipulation.

It can perform the following operations:

• Filling a part or the whole of a destination image with a specific color

• Copying a part or the whole of a source image into a part or the whole of a destination

image with a pixel format conversion

• Blending a part and/or two complete source images with a different pixel format and copying the result into a part or the whole of a destination image with a different color format.

On the STM32L496xx/L4A6xx/L4Rxxx/L4Sxxx microcontrollers, the flexible static memory controller (FSMC) is used to access the LCD-TFT display through a parallel interface.

This application note explains on:

• How to connect the LCD-TFT display to the FSMC interface

• How to configure the DMA2D for the LCD-TFT display refresh

• How to use the DMA2D byte reordering features to directly drive Intel 8080 displays.

To fully benefit from this application note, the user should be familiar with the STM32 Chrom-ART Accelerator™ (DMA2D) as described in the STM32L4x6 advanced Arm

based 32-bit MCUs reference manual (RM0351) and the STM32L4Rxxx/L4Sxxx advanced

Arm

-based 32-bit MCUs reference manual (RM0432) available from the

STMicroelectronics website www.st.com.

Type Product lines and part numbers

Microcontrollers

STM32L496AE, STM32L496AG, STM32L496QE, STM32L496QG, STM32L496RE, STM32L496RG, STM32L496VE, STM32L496VG, STM32L496ZE, STM32L496ZG

STM32L4A6AG, STM32L4A6QG, STM32L4A6RG, STM32L4A6VG, STM32L4A6ZG

STM32L4R5/S5 line, STM32L4R7/S7 line, STM32L4R9/S9 line

Table 1. Applicable products

October 2017 DocID029937 Rev 2 1/22

www.st.com

Contents AN4943

Contents

1 Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Chrom-ART Accelerator™ (DMA2D) application use case overview . . 6

3 LCD-TFT display on FSMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1 Hardware interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.2 Display Command Set (DCS) software interface . . . . . . . . . . . . . . . . . . . . 8

3.3 Controlling the D/CX signal with STM32L496xx/L4A6xx/

L4Rxxx/L4Sxxx microcontrollers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 Chrom-ART Accelerator™ (DMA2D) configuration in STM32CubeL4 11

4.1 LCD partial refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

5 New DMA2D features to support Intel 8080 displays . . . . . . . . . . . . . . 13

5.1 Intel 8080 interface color coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.2 DMA2D reordering features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.2.1 Red and blue swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.2.2 Byte swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.3 DMA2D reordering use case examples . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.3.1 24bpp/18bpp over 16-bit FSMC data bus interface . . . . . . . . . . . . . . . . 17

5.3.2 24bpp/18bpp over 8-bit FSMC data bus interface . . . . . . . . . . . . . . . . . 18

5.3.3 16bpp over 8-bit FSMC data bus interface . . . . . . . . . . . . . . . . . . . . . . 19

6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2/22 DocID029937 Rev 2

AN4943 List of tables

List of tables

Table 1. Applicable products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. FSMC signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 3. LCD-TFT signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 4. Minimum usable FSMC address bit depending on image size (16 bit RGB565 access) . . 10

Table 5. Swap operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 6. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

DocID029937 Rev 2 3/22

List of figures AN4943

List of figures

Figure 1. Display application typical use case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Display bus interface specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3. Memory map for LCD-TFT display access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 4. Automatic control of LCD-TFT display data/command by FSMC interface . . . . . . . . . . . . 10

Figure 5. 24bpp over 16-bit interface color coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 6. 16bpp over 8-bit interface color coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 7. 24bpp over 8-bit interface color coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 8. DMA2D operations to support 24bpp over 16-bit interface. . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 9. DMA2D operations to support 24bpp over 8-bit interface. . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 10. DMA2D operations to support 16bpp over 8-bit interface. . . . . . . . . . . . . . . . . . . . . . . . . . 19

4/22 DocID029937 Rev 2

AN4943 Reference documents

1 Reference documents

The following documents are available on www.st.com.

• STM32L4x6 advanced Arm®-based 32-bit MCUs reference manual (RM0351)

• STM32L4Rxxx/L4Sxxx advanced Arm

(RM0432)

• Discovery kit with STM32L496AG MCU user manual (UM2160)

• Embedded software for the STM32L4 Series (STM32CubeL4)

This application note applies to Arm®-based devices.

-based 32-bit MCUs reference manual

DocID029937 Rev 2 5/22

Chrom-ART Accelerator™ (DMA2D) application use case overview AN4943

MSv44235V2

Frame buffer in

internal SRAM

STM32L496xx/L4A6xx/L4Rxxx/L4Sxxx

SRAM

DMA2D

FSMC

LCD-TFT

display

Quad-SPI

Flash

Quad-SPI

interface

Graphical primitives in external Quad-SPI Flash memory

Step 1

Step 2

2 Chrom-ART Accelerator™ (DMA2D) application use

case overview

A typical application displaying an image into an LCD-TFT display is divided in 2 steps.

• Step1: creation of the frame buffer content

– The frame buffer is built by composing graphical primitives like icons, pictures and

fonts

– This operation is done by the CPU running a graphical library software

– It can be accelerated by a dedicated hardware used with the CPU through the

graphical library (Chrom-ART Accelerator™ (DMA2D))

– The more often the frame buffer is updated, the more fluid are the animations

• Step2: display of the frame buffer onto the LCD-TFT display

– The frame buffer is transferred to the display through a dedicated hardware

interface

– The transfer can be done using the CPU, the system DMA or using the Chrom-

ART Accelerator™ (DMA2D)

In a typical display application example using the STM32L496xx/L4A6xx/L4Rxxx/L4Sxxx microcontrollers, the Flexible Static Memory Controller (FSMC) is used as the hardware interface to the LCD-TFT display, the graphical primitives like pictures, icons or fonts are stored in the external Quad-SPI Flash memory and the frame buffer is stored in the internal SRAM. The transfer of the frame buffer to the LCD-TFT display can also be managed by the Chrom-ART Accelerator™ (DMA2D), hence not using the CPU or the DMA resources.

This is showed in Figure 1: Display application typical use case.

Figure 1. Display application typical use case

6/22 DocID029937 Rev 2

AN4943 LCD-TFT display on FSMC

The Chrom-ART Accelerator™ (DMA2D) can update the whole image on the display (full refresh) or only a part of it (partial refresh).

The configuration of the Chrom-ART Accelerator™ (DMA2D) (full or partial refresh) is done by programming specific registers through the high level HAL library function as shown in

Section 4: Chrom-ART Accelerator™ (DMA2D) configuration in STM32CubeL4.

3 LCD-TFT display on FSMC

3.1 Hardware interface description

The below signals are used to connect the Flexible Static Memory interface (FSMC) to the LCD-TFT display:

Signal name FSMC I/O Function

A[25:0] O Address bus

D[15:0] I/O Bidirectional data bus

NE[x] O Chip select, x=1..4

Table 2. FSMC signals

NOE O Output enable

NWE O Write enable

Signal name

D/CX I Data/command control signal

D[15:0] I/O Bidirectional information signals bus

CSX I Chip select control signal

RDX I Read control signal

WRX I Write control signal

RESX I Reset

1. The signal names are provided according the Type B Display Bus Interface (DBI) as described in the MIPI Alliance standard for display bus interface.

(1)

TE O Tearing effect

Table 3. LCD-TFT signals

LCD-TFT I/O Function

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