ST MICROELECTRONICS STM32L476RCT6 Datasheet

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STM32L476xx

UFBGA144 (10 × 10)

LQFP144 (20 × 20)

LQFP100 (14 × 14)

LQFP64 (10 × 10)

UFBGA132 (7 × 7)

WLCSP72 WLCSP81

Ultra-low-power Arm® Cortex®-M4 32-bit MCU+FPU, 100DMIPS,

up to 1MB Flash, 128 KB SRAM, USB OTG FS, LCD, ext. SMPS

Datasheet - production data

Features

• Ultra-low-power with FlexPowerControl – 1.71 V to 3.6 V power supply – -40 °C to 85/105/125 °C temperature range – 300 nA in V

32x32-bit backup registers – 30 nA Shutdown mode (5 wakeup pins) – 120 nA Standby mode (5 wakeup pins) – 420 nA Standby mode with RTC – 1.1 µA Stop 2 mode, 1.4 µA with RTC – 100 µA/MHz run mode (LDO Mode) –39 A/MHz run mode (@3.3 V SMPS

Mode) – Batch acquisition mode (BAM) – 4 µs wakeup from Stop mode – Brown out reset (BOR) – Interconnect matrix

• Core: Arm

Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait-state execution from Flash memory, frequency up to 80 MHz, MPU, 100DMIPS and DSP instructions

• Performance benchmark – 1.25 DMIPS/MHz (Drystone 2.1) – 273.55 CoreMark

80 MHz)

• Energy benchmark – 294 ULPMark™ CP score – 106 ULPMark™ PP score

• Clock Sources – 4 to 48 MHz crystal oscillator – 32 kHz crystal oscillator for RTC (LSE) – Internal 16 MHz factory-trimmed RC (±1%) – Internal low-power 32 kHz RC (±5%) – Internal multispeed 100 kHz to 48 MHz

oscillator, auto-trimmed by LSE (better than ±0.25 % accuracy)

– 3 PLLs for system clock, USB, audio, ADC

mode: supply for RTC and

BAT

32-bit Cortex®-M4 CPU with FPU,

(3.42 CoreMark/MHz @

• Up to 114 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V

• RTC with HW calendar, alarms and calibration

• LCD 8× 40 or 4× 44 with step-up converter

• Up to 24 capacitive sensing channels: support

touchkey, linear and rotary touch sensors

• 16x timers: 2x 16-bit advanced motor-control, 2x 32-bit and 5x 16-bit general purpose, 2x 16bit basic, 2x low-power 16-bit timers (available in Stop mode), 2x watchdogs, SysTick timer

• Memories – Up to 1 MB Flash, 2 banks read-while-

write, proprietary code readout protection

– Up to 128 KB of SRAM including 32 KB

with hardware parity check

– External memory interface for static

memories supporting SRAM, PSRAM, NOR and NAND memories

– Quad SPI memory interface

• 4x digital filters for sigma delta modulator

• Rich analog peripherals (independent supply)

– 3x 12-bit ADC 5 Msps, up to 16-bit with

hardware oversampling, 200 µA/Msps

– 2x 12-bit DAC output channels, low-power

sample and hold – 2x operational amplifiers with built-in PGA – 2x ultra-low-power comparators

• 20x communication interfaces – USB OTG 2.0 full-speed, LPM and BCD – 2x SAIs (serial audio interface) –3x I2C FM+(1 Mbit/s), SMBus/PMBus – 5x USARTs (ISO 7816, LIN, IrDA, modem) – 1x LPUART (Stop 2 wake-up)

June 2019 DS10198 Rev 8 1/270

This is information on a product in full production.

www.st.com

STM32L476xx

– 3x SPIs (and 1x Quad SPI) – CAN (2.0B Active) and SDMMC interface – SWPMI single wire protocol master I/F – IRTIM (Infrared interface)

• 14-channel DMA controller

Table 1. Device summary

Reference Part numbers

STM32L476RG, STM32L476JG, STM32L476MG, STM32L476ME, STM32L476VG,

STM32L476xx

STM32L476QG, STM32L476ZG, STM32L476RE, STM32L476JE, STM32L476VE, STM32L476QE, STM32L476ZE, STM32L476RC, STM32L476VC

• True random number generator

• CRC calculation unit, 96-bit unique ID

• Development support: serial wire debug

(SWD), JTAG, Embedded Trace Macrocell™

• All packages are ECOPACK2

compliant

2/270 DS10198 Rev 8

STM32L476xx Contents

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.1 Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 18

3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.6 Firewall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.7 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.8 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 21

3.9 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.9.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.9.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.9.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.9.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.9.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.9.6 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.10 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.11 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.12 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.13 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.14 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.14.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 40

3.14.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 40

3.15 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.15.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.15.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.15.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.16 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

DS10198 Rev 8 3/270

Contents STM32L476xx

3.17 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.18 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.19 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.20 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.21 Liquid crystal display controller (LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.22 Digital filter for Sigma-Delta Modulators (DFSDM) . . . . . . . . . . . . . . . . . . 45

3.23 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.24 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.24.1 Advanced-control timer (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.24.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16,

TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.24.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.24.4 Low-power timer (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . 49

3.24.5 Infrared interface (IRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.24.6 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.24.7 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.24.8 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.25 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 51

3.26 Inter-integrated circuit interface (I

C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.27 Universal synchronous/asynchronous receiver transmitter (USART) . . . 53

3.28 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 54

3.29 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.30 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.31 Single wire protocol master interface (SWPMI) . . . . . . . . . . . . . . . . . . . . 56

3.32 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.33 Secure digital input/output and MultiMediaCards Interface (SDMMC) . . . 57

3.34 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 57

3.35 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 58

3.36 Quad SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.37 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

3.37.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 60

3.37.2 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

4/270 DS10198 Rev 8

STM32L476xx Contents

5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 115

6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118

6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 119

6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . 120

6.3.4 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

6.3.6 Wakeup time from low-power modes and voltage scaling

transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 153

6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 158

6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

6.3.10 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

6.3.16 Extended interrupt and event controller input (EXTI) characteristics . . 176

6.3.17 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

6.3.18 Analog-to-Digital converter characteristics . . . . . . . . . . . . . . . . . . . . . 177

6.3.19 Digital-to-Analog converter characteristics . . . . . . . . . . . . . . . . . . . . . 190

6.3.20 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 195

6.3.21 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

6.3.22 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 198

6.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

DS10198 Rev 8 5/270

Contents STM32L476xx

6.3.24 V

6.3.25 LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

6.3.26 DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

6.3.27 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

6.3.28 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 208

6.3.29 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

6.3.30 SWPMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

BAT

7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

7.1 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

7.2 UFBGA144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

7.3 UFBGA132 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

7.4 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

7.5 WLCSP81 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

7.6 WLCSP72 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

7.7 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

7.8 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

7.8.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

7.8.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 261

8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

6/270 DS10198 Rev 8

STM32L476xx List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2. STM32L476xx family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . 15

Table 3. Access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 19

Table 4. STM32L476xx modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 5. Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 6. STM32L476xx peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 7. DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 8. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 9. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 10. DFSDM1 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 11. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 12. I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 13. STM32L476xx USART/UART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 14. SAI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 15. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 16. STM32L476xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 17. Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 18. Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 19. STM32L476xx memory map and peripheral register boundary addresses . . . . . . . . . . . 108

Table 20. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Table 21. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Table 22. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 23. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Table 24. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Table 25. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 120

Table 26. Embedded internal voltage reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 27. Current consumption in Run and Low-power run modes, code with data processing

running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . 125

Table 28. Current consumption in Run modes, code with data processing running from Flash,

ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS

(VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Table 29. Current consumption in Run and Low-power run modes, code with data processing

running from Flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Table 30. Current consumption in Run modes, code with data processing running from Flash,

ART disable and power supplied by external SMPS (VDD12 = 1.10 V). . . . . . . . . . . . . . 128

Table 31. Current consumption in Run and Low-power run modes, code with data processing

running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 32. Current consumption in Run, code with data processing running from

SRAM1 and power supplied by external SMPS (VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . 130

Table 33. Typical current consumption in Run and Low-power run modes, with different codes

running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . 131

Table 34. Typical current consumption in Run, with different codes running from Flash,

ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS

(VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Table 35. Typical current consumption in Run, with different codes running from Flash,

ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS

(VDD12 = 1.05 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Table 36. Typical current consumption in Run and Low-power run modes, with different codes

DS10198 Rev 8 7/270

List of tables STM32L476xx

running from Flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Table 37. Typical current consumption in Run modes, with different codes running from

Flash, ART disable and power supplied by external SMPS (VDD12 = 1.10 V) . . . . . . . . 133

Table 38. Typical current consumption in Run modes, with different codes running

from Flash, ART disable and power supplied by external SMPS (VDD12 = 1.05 V) . . . . 133

Table 39. Typical current consumption in Run and Low-power run modes, with different codes

running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Table 40. Typical current consumption in Run mode, with different codes running from

SRAM1 and power supplied by external SMPS (VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . 134

Table 41. Typical current consumption in Run mode, with different codes running from

SRAM1 and power supplied by external SMPS (VDD12 = 1.05 V) . . . . . . . . . . . . . . . . . 135

Table 42. Current consumption in Sleep and Low-power sleep modes, Flash ON . . . . . . . . . . . . . 136

Table 43. Current consumption in Sleep, Flash ON and power supplied by external SMPS

(VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Table 44. Current consumption in Low-power sleep modes, Flash in power-down . . . . . . . . . . . . . 137

Table 45. Current consumption in Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Table 46. Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Table 47. Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Table 48. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Table 49. Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Table 50. Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Table 51. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Table 52. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Table 53. Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 54. Wakeup time using USART/LPUART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 55. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 56. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Table 57. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Table 58. LSE oscillator characteristics (f

= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

LSE

Table 59. HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Table 60.

MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Table 61. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Table 62. PLL, PLLSAI1, PLLSAI2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Table 63. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Table 64. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Table 65. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Table 66. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Table 67. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Table 68. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Table 69. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Table 70. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Table 71. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Table 72. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Table 73. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Table 74. EXTI input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Table 75. Analog switches booster characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Table 76. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Table 77. Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Table 78. ADC accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Table 79. ADC accuracy - limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Table 80. ADC accuracy - limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Table 81. ADC accuracy - limited test conditions 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

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STM32L476xx List of tables

Table 82. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Table 83. DAC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Table 84. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Table 85. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Table 86. OPAMP characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Table 87. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Table 88. V Table 89. V

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

BAT

charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

BAT

Table 90. LCD controller characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Table 91. DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Table 92. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Table 93. IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Table 94. WWDG min/max timeout value at 80 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Table 95. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

Table 96. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Table 97. Quad SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Table 98. QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Table 99. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Table 100. SD / MMC dynamic characteristics, VDD=2.7 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . 216

Table 101. eMMC dynamic characteristics, VDD = 1.71 V to 1.9 V . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Table 102. USB OTG DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Table 103. USB OTG electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

Table 104. USB BCD DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

Table 105. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 223

Table 106. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 223

Table 107. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 224

Table 108. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 225

Table 109. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 226

Table 110. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 226

Table 111. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 228

Table 112. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 228

Table 113. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

Table 114. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

Table 115. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 233

Table 116. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Table 117. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

Table 118. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 237

Table 119. SWPMI electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

Table 120. LQFP - 144-pin, 20 x 20 mm low-profile quad flat package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

Table 121. UFBGA - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball

grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

Table 122. UFBGA144 recommended PCB design rules (0.80 mm pitch BGA) . . . . . . . . . . . . . . . . 244

Table 123. UFBGA - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Table 124. UFBGA132 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 247

Table 125. LQFP - 100 pins, 14 x 14 mm low-profile quad flat package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

Table 126. WLCSP- 81-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

Table 127. WLCSP81 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . 253

Table 128. WLCSP - 72-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip

DS10198 Rev 8 9/270

List of tables STM32L476xx

scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Table 129. WLCSP72 recommended PCB design rules (0.4 mm pitch BGA) . . . . . . . . . . . . . . . . . . 256

Table 130. LQFP - 64 pins, 10 x 10 mm low-profile quad flat

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

Table 131. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

Table 132. STM32L476xx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

Table 133. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

10/270 DS10198 Rev 8

STM32L476xx List of figures

List of figures

Figure 1. STM32L476xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 2. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 3. Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 4. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 5. Voltage reference buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 6. STM32L476Zx LQFP144 pinout Figure 7. STM32L476Zx, external SMPS device, LQFP144 pinout Figure 8. STM32L476Zx UFBGA144 ballout Figure 9. STM32L476Qx UFBGA132 ballout

Figure 10. STM32L476Qx, external SMPS device, UFBGA132 ballout . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 11. STM32L476Vx LQFP100 pinout Figure 12. STM32L476Mx WLCSP81 ballout Figure 13. STM32L476Jx WLCSP72 ballout Figure 14. STM32L476Jx, external SMPS device, WLCSP72 ballout Figure 15. STM32L476Rx LQFP64 pinout Figure 16. STM32L476Rx, external SMPS device, LQFP64 pinout

Figure 17. STM32L476xx memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 18. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 19. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 20. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 21. Current consumption measurement scheme with and without external

SMPS power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 22. VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Figure 23. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Figure 24. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Figure 25. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Figure 26. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Figure 27. HSI16 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Figure 28. Typical current consumption versus MSI frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Figure 29. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Figure 30. I/O AC characteristics definition

Figure 31. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Figure 32. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Figure 33. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Figure 34. 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Figure 35. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Figure 36. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Figure 37. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Figure 38. Quad SPI timing diagram - SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Figure 39. Quad SPI timing diagram - DDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Figure 40. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

Figure 41. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Figure 42. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Figure 43. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Figure 44. USB OTG timings – definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . 219

Figure 45. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 222

Figure 46. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 224

Figure 47. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 225

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

(1)

. . . . . . . . . . . . . . . . . . . . . . . . 62

(1)

. . . . . . . . . . . . . . . . . . . . . . . 66

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . 67

DS10198 Rev 8 11/270

List of figures STM32L476xx

Figure 48. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 227

Figure 49. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

Figure 50. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

Figure 51. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 233

Figure 52. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

Figure 53. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Figure 54. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Figure 55. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 236

Figure 56. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 237

Figure 57. LQFP - 144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . 239

Figure 58. LQFP - 144-pin,20 x 20 mm low-profile quad flat package

recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

Figure 59. LQFP144 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

Figure 60. UFBGA - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball

grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

Figure 61. UFBGA - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball

grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

Figure 62. UFBGA144 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Figure 63. UFBGA - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Figure 64. UFBGA - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array

package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

Figure 65. UFBGA132 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

Figure 66. LQFP - 100 pins, 14 x 14 mm low-profile quad flat package outline. . . . . . . . . . . . . . . . . 249

Figure 67. LQFP - 100 pins, 14 x 14 mm low-profile quad flat

recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

Figure 68. LQFP100 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

Figure 69. WLCSP - 81-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level

chip scale package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

Figure 70. WLCSP81- 81-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale

package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

Figure 71. WLCSP81 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

Figure 72. WLCSP - 72-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip

scale package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Figure 73. WLCSP72 - 72-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level

chip scale package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

Figure 74. WLCSP72 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

Figure 75. LQFP - 64 pins, 10 x 10 mm low-profile quad flat package outline. . . . . . . . . . . . . . . . . . 258

Figure 76. LQFP - 64 pins, 10 x 10 mm low-profile quad flat package

recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

Figure 77. LQFP64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

Figure 78. LQFP64 P

max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

12/270 DS10198 Rev 8

STM32L476xx Introduction

1 Introduction

This datasheet provides the ordering information and mechanical device characteristics of

the STM32L476xx microcontrollers.

This document should be read in conjunction with the STM32L4x6 reference manual

(RM0351). The reference manual is available from the STMicroelectronics website

www.st.com.

For information on the Arm

Reference Manual, available from the www.arm.com website.

®(a)

Cortex®-M4 core, please refer to the Cortex®-M4 Technical

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

DS10198 Rev 8 13/270

Description STM32L476xx

2 Description

The STM32L476xx devices are the ultra-low-power microcontrollers based on the high-

performance Arm

The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all

Arm

single-precision data-processing instructions and data types. It also implements a full

Cortex®-M4 32-bit RISC core operating at a frequency of up to 80 MHz.

set of DSP instructions and a memory protection unit (MPU) which enhances application

security.

The STM32L476xx devices embed high-speed memories (Flash memory up to 1 Mbyte, up

to 128

Kbyte of SRAM), a flexible external memory controller (FSMC) for static memories (for devices with packages of 100 pins and more), a Quad SPI flash memories interface (available on all packages) and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.

The STM32L476xx devices embed several protection mechanisms for embedded Flash memory and SRAM: readout protection, write protection, proprietary code readout protection and Firewall.

The devices offer up to three fast 12-bit ADCs (5 Msps), two comparators, two operational amplifiers, two DAC channels, an internal voltage reference buffer, a low-power RTC, two general-purpose 32-bit timer, two 16-bit PWM timers dedicated to motor control, seven general-purpose 16-bit timers, and two 16-bit low-power timers. The devices support four digital filters for external sigma delta modulators (DFSDM).

In addition, up to 24 capacitive sensing channels are available. The devices also embed an integrated LCD driver 8x40 or 4x44, with internal step-up converter.

They also feature standard and advanced communication interfaces.

• Three I2Cs

• Three SPIs

• Three USARTs, two UARTs and one Low-Power UART.

• Two SAIs (Serial Audio Interfaces)

• One SDMMC

• One CAN

• One USB OTG full-speed

• One SWPMI (Single Wire Protocol Master Interface)

The STM32L476xx operates in the -40 to +85 °C (+105 °C junction), -40 to +105 °C (+125

°C junction) and -40 to +125 °C (+130 °C junction) temperature ranges from a 1.71 to

3.6

V VDD power supply when using internal LDO regulator and a 1.05 to 1.32V V power supply when using external SMPS supply. A comprehensive set of power-saving modes allows the design of low-power applications.

Some independent power supplies are supported: analog independent supply input for ADC, DAC, OPAMPs and comparators, 3.3

V dedicated supply input for USB and up to 14 I/Os can be supplied independently down to 1.08V. A VBAT input allows to backup the RTC and backup registers. Dedicated V

power supplies can be used to bypass the internal

DD12

LDO regulator when connected to an external SMPS.

The STM32L476xx family offers six packages from 64-pin to 144-pin packages.

14/270 DS10198 Rev 8

DD12

STM32L476xx Description

Table 2. STM32L476xx family device features and peripheral counts

Peripheral

Flash memory

STM32

L476Zx

512K

1MB

STM32

L476Qx

512K

1MB

STM32

L476Vx

256KB512K

1MB

512K

SRAM 128KB

External memory controller for static

Yes Yes Yes

(1)

memories

Quad SPI Yes

Advanced control

General purpose

2 (16-bit)

5 (16-bit) 2 (32-bit)

Basic 2 (16-bit)

Timers

Low -power 2 (16-bit)

SysTick timer

Watchdog timers (indepen-

2 dent, window)

SPI 3

Comm. interfaces

USART UART LPUART

SAI 2

CAN 1

USB OTG FS

Yes

SDMMC Yes

SWPMI Yes

STM32

L476Mx

1MB

STM32

L476Jx

512K

1MB

256KB512K

No No No

STM32

L476Rx

1MB

Digital filters for sigmadelta modulators

Yes (4 filters)

Number of channels 8

RTC Yes

Tamper pins 3 2 2 2

LCD COM x SEG

Yes

8x40 or

4x44

Yes

8x40 or

4x44

Yes

8x40 or 4x44

Yes

8x30 or

4x32

Yes

8x28 or

4x32

Yes

8x28 or 4x32

DS10198 Rev 8 15/270

Description STM32L476xx

Table 2. STM32L476xx family device features and peripheral counts (continued)

Peripheral

STM32

L476Zx

STM32

L476Qx

STM32

L476Vx

STM32

L476Mx

STM32

L476Jx

STM32

L476Rx

Random generator Yes

(2)

GPIOs Wakeup pins Nb of I/Os down to

114

109

65 5 0

4 6

51 4 6

4 0

1.08 V

Capacitive sensing Number of channels

12-bit ADCs Number of channels

24 24 21 12 12 12

12-bit DAC channels 2

Internal voltage reference buffer

Yes No

Analog comparator 2

Operational amplifiers 2

Max. CPU frequency 80 MHz

Operating voltage (V

)

DD12

Operating temperature

Packages

1. For the LQFP100 package, only FMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select.

2. In case external SMPS package type is used, 2 GPIO's are replaced by VDD12 pins to connect the SMPS power supplies hence reducing the number of available GPIO's by 2.

) 1.71 to 3.6 V

1.05 to 1.32 V

Ambient operating temperature: -40 to 85 °C / -40 to 105 °C / -40 to 125 °C

Junction temperature: -40 to 105 °C / -40 to 125 °C / -40 to 130 °C

LQFP144

UFBGA144

UFBGA

132

LQFP100 WLCSP81 WLCSP72 LQFP64

16/270 DS10198 Rev 8

STM32L476xx Description

MS31263V8

USB OTG

Flash up to 1 MB

Flexible static memory controller (FSMC):

SRAM, PSRAM, NOR Flash,

NAND Flash

GPIO PORT A

AHB/APB2

EXT IT. WKUP

114 AF

PA[15:0]

TIM1 / PWM

3 compl. channels (TIM1_CH[1:3]N),

4 channels (TIM1_CH[1:4]),

ETR, BKIN, BKIN2 as AF

USART1

RX, TX, CK,CTS,

RTS as AF

SPI1

MOSI, MISO,

SCK, NSS as AF

APB260 M Hz

APB1 30MHz

MOSI, MISO, SCK, NSS as AF

DAC1_OUT1

ITF

WWDG

RTC_TS

OSC32_IN

OSC32_OUT

smcard

IrDA

16b

SDIO / MMC

D[7:0]

CMD, CK as AF

VBAT = 1.55 to 3.6 V

SCL, SDA, SMBA as AF

JTAG & SW

ARM Cortex-M4

80 MHz

FPU

NVIC

ETM

MPU

DMA2

ART

ACCEL/

CACHE

CLK, NE[4:1], NL, NBL[1:0], A[25:0], D[15:0], NOE, NWE, NWAIT, NCE3, INT3 as AF

RNG

FIFO

@ VDDA

BOR

Supply

supervision

PVD, PVM

Int

reset

XTAL 32 kHz

MAN AGT

RTC

FCLK

Standby

interface

IWDG

@VBAT

@ VDD

@VDD

AWU

Reset & clock

control

PCLKx

Voltage regulator

3.3 to 1.2 V

VDD

Power management

@ VDD

RTC_TAMPx

Backup register

AHB bus-matrix

TIM15

2 channels,

1 compl. channel, BKIN as AF

TIM6

TIM7

TIM2

TIM3

TIM4

TIM5

USART2

USART3

I2C1/SMBUS

D-BUS

FIFO

APB1 80 MHz (max)

SRAM 96 KB

SRAM 32 KB

I-BUS

S-BUS

DMA1

PB[15:0]

PC[15:0]

PD[15:0]

PE[15:0]

PF[15:0]

PG[15:0]

PH[1:0]

GPIO PORT B

GPIO PORT C

GPIO PORT D

GPIO PORT E

GPIO PORT F

GPIO PORT G

GPIO PORT H

TIM8 / PWM

16b

TIM16

16b

TIM17

16b

3 compl. channels (TIM1_CH[1:3]N),

4 channels (TIM1_CH[1:4]),

ETR, BKIN, BKIN2 as AF

1 channel,

1 compl. channel, BKIN as AF

1 channel,

1 compl. channel, BKIN as AF

DAC1_OUT2

16b

SCL, SDA, SMBA as AF

MOSI, MISO, SCK, NSS as AF

TX, RX as AF

RX, TX, CTS, RTS as AF

RX, TX, CK, CTS, RTS as AF

smcard

IrDA

smcard

IrDA

32b

16b

32b

4 channels, ETR as AF

AHB/APB1

OSC_IN

OSC_OUT

HCLKx

XTAL OSC

4- 16MHz

8 analog inputs common

to the 3 ADCs

VREF+

USAR T 2M Bps

Temperature sensor

ADC1

ADC2

ADC3

ITF

@ VDDA

8 analog inputs common

to the ADC1 & 2

8 analog inputs for ADC3

SAI1

MCLK_A, SD_A, FS_A, SCK_A, EXTCLK

MCLK_B, SD_B, FS_B, SCK_B as AF

SAI2

MCLK_A, SD_A, FS_A, SCK_A, EXTCLK

MCLK_B, SD_B, FS_B, SCK_B as AF

DFSDM

SDCKIN[7:0], SDDATIN[7:0],

SDCKOUT,SDTRIG as AF

Touch sensing controller

8 Groups of

3 channels max as AF

VOUT, VINM, VINP

LCD 8x40

LPUART1

SWPMI1

LPTIM1

LPTIM2

SEGx, COMx as AF

RX, TX, CTS, RTS as AF

IO RX, TX, SUSPEND as AF

IN1, IN2, OUT, ETR as AF

IN1, OUT, ETR as AF

RC HSI

RC LSI

PLL 1&2&3

MSI

Quad SPI memory interface

BK1_IO[3:0] CLK NCS

@ VDDUSB

COMP1

INP, INM, OUT

COMP2

INP, INM, OUT

@ VDDA

RTC_OUT

FIFO

PHY

AHB1 80 MHz

CRC

I2C2/SMBUS

I2C3/SMBUS

bxCAN1

OpAmp1

SP3

SP2

UART5

UART4

LCD Booster

LCD

= 2.5V to 3.6V

APB2 80MHz

AHB2 80 MHz

OpAmp2

@VDDA

Firewall

VREF Buffer

@ VDDA

@ VDD

DP DM

SCL, SDA, INTN, ID, VBUS, SOF

VDD = 1.71 to 3.6 V

VSS

VDDA, VSSA

VDD, VSS, NRST

VDDIO2, VDDUSB

VOUT, VINM, VINP

TRACECLK

TRACED[3:0]

NJTRST, JTDI,

JTCK/SWCLK

JTDO/SWD, JTDO

VDD12 = 1.05 to 1.32 V

(1)

VDD12

1. Only available when using external SMPS supply mode.

DAC1

Figure 1. STM32L476xx block diagram

Note: AF: alternate function on I/O pins.

DS10198 Rev 8 17/270

Functional overview STM32L476xx

3 Functional overview

3.1 Arm® Cortex®-M4 core with FPU

The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm® processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.

The Arm® Cortex®-M4 with FPU 32-bit RISC processor features exceptional codeefficiency, delivering the high-performance expected from an Arm usually associated with 8- and 16-bit devices.

The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution.

Its single precision FPU speeds up software development by using metalanguage development tools, while avoiding saturation.

With its embedded Arm® core, the STM32L476xx family is compatible with all Arm® tools and software.

Figure 1 shows the general block diagram of the STM32L476xx family devices.

core in the memory size

3.2 Adaptive real-time memory accelerator (ART Accelerator™)

The ART Accelerator™ is a memory accelerator which is optimized for STM32 industrystandard Arm the Arm processor to wait for the Flash memory at higher frequencies.

To release the processor near 100 DMIPS performance at 80MHz, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 64-bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 80 MHz.

Cortex®-M4 processors. It balances the inherent performance advantage of

Cortex®-M4 over Flash memory technologies, which normally requires the

3.3 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory.

The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

18/270 DS10198 Rev 8

STM32L476xx Functional overview

3.4 Embedded Flash memory

STM32L476xx devices feature up to 1 Mbyte of embedded Flash memory available for storing programs and data. The Flash memory is divided into two banks allowing readwhile-write operations. This feature allows to perform a read operation from one bank while an erase or program operation is performed to the other bank. The dual bank boot is also supported. Each bank contains 256 pages of 2

Flexible protections can be configured thanks to option bytes:

• Readout protection (RDP) to protect the whole memory. Three levels are available:

– Level 0: no readout protection

– Level 1: memory readout protection: the Flash memory cannot be read from or

written to if either debug features are connected, boot in RAM or bootloader is selected

– Level 2: chip readout protection: debug features (Cortex-M4 JTAG and serial

wire), boot in RAM and bootloader selection are disabled (JTAG fuse). This selection is irreversible.

Table 3. Access status versus readout protection level and execution modes

Kbyte.

Area

Main

memory

System

memory

Option

bytes

Backup

registers

SRAM2

1. Erased when RDP change from Level 1 to Level 0.

Protection

level

1 Yes Yes Yes No No No

2 Yes Yes Yes N/A N/A N/A

1 Yes No No Yes No No

2 Yes No No N/A N/A N/A

1 Yes Yes Yes Yes Yes Yes

2 Yes No No N/A N/A N/A

1YesYesN/A

2 Yes Yes N/A N/A N/A N/A

1 Yes Yes Yes

2 Yes Yes Yes N/A N/A N/A

User execution

Read Write Erase Read Write Erase

(1)

Debug, boot from RAM or boot

from system memory (loader)

No No N/A

No No No

• Write protection (WRP): the protected area is protected against erasing and programming. Two areas per bank can be selected, with 2-Kbyte granularity.

• Proprietary code readout protection (PCROP): a part of the flash memory can be protected against read and write from third parties. The protected area is execute-only: it can only be reached by the STM32 CPU, as an instruction code, while all other accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited. One area per bank can be selected, with 64-bit granularity. An additional option bit (PCROP_RDP) allows to select if the PCROP area is erased or not when the RDP protection is changed from Level 1 to Level 0.

(1)

DS10198 Rev 8 19/270

Functional overview STM32L476xx

The whole non-volatile memory embeds the error correction code (ECC) feature supporting:

• single error detection and correction

• double error detection.

• The address of the ECC fail can be read in the ECC register

3.5 Embedded SRAM

STM32L476xx devices feature up to 128 Kbyte of embedded SRAM. This SRAM is split into two blocks:

• 96 Kbyte mapped at address 0x2000 0000 (SRAM1)

• 32 Kbyte located at address 0x1000 0000 with hardware parity check (SRAM2).

This block is accessed through the ICode/DCode buses for maximum performance. These 32 Kbyte SRAM can also be retained in Standby mode.

The SRAM2 can be write-protected with 1 Kbyte granularity.

The memory can be accessed in read/write at CPU clock speed with 0 wait states.

3.6 Firewall

The device embeds a Firewall which protects code sensitive and secure data from any access performed by a code executed outside of the protected areas.

Each illegal access generates a reset which kills immediately the detected intrusion.

The Firewall main features are the following:

• Three segments can be protected and defined thanks to the Firewall registers: – Code segment (located in Flash or SRAM1 if defined as executable protected

area) – Non-volatile data segment (located in Flash) – Volatile data segment (located in SRAM1)

• The start address and the length of each segments are configurable: – Code segment: up to 1024 Kbyte with granularity of 256 bytes – Non-volatile data segment: up to 1024 Kbyte with granularity of 256 bytes – Volatile data segment: up to 96 Kbyte with a granularity of 64 bytes

• Specific mechanism implemented to open the Firewall to get access to the protected areas (call gate entry sequence)

• Volatile data segment can be shared or not with the non-protected code

• Volatile data segment can be executed or not depending on the Firewall configuration

The Flash readout protection must be set to level 2 in order to reach the expected level of protection.

20/270 DS10198 Rev 8

STM32L476xx Functional overview

3.7 Boot modes

At startup, BOOT0 pin and BOOT1 option bit are used to select one of three boot options:

• Boot from user Flash

• Boot from system memory

• Boot from embedded SRAM

The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART, I2C, SPI, CAN or USB OTG FS in Device mode through DFU (device firmware upgrade).

3.8 Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.

3.9 Power supply management

3.9.1 Power supply schemes

• VDD = 1.71 to 3.6 V: external power supply for I/Os (V the system analog such as reset, power management and internal clocks. It is provided externally through VDD pins.

• V

Note: When the functions supplied by V

should preferably be shorted to V

= 1.05 to 1.32 V: external power supply bypassing internal regulator when

DD12

connected to an external SMPS. It is provided externally through VDD12 pins and only available on packages with the external SMPS supply option. VDD12 does not require any external decoupling capacitance and cannot support any external load.

= 1.62 V (ADCs/COMPs) / 1.8 (DAC/OPAMPs) to 3.6 V: external analog power

DDA

supply for ADCs, DAC, OPAMPs, Comparators and Voltage reference buffer. The V voltage level is independent from the V

= 3.0 to 3.6 V: external independent power supply for USB transceivers. The

DDUSB

voltage level is independent from the VDD voltage.

DDUSB

= 1.08 to 3.6 V: external power supply for 14 I/Os (PG[15:2]). The V

DDIO2

voltage level is independent from the V

= 2.5 to 3.6 V: the LCD controller can be powered either externally through VLCD

LCD

pin, or internally from an internal voltage generated by the embedded step-up converter.

= 1.55 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and

BAT

backup registers (through power switch) when V

, V

DDA

DDUSB

voltage.

or V

DDIO2

), the internal regulator and

DDIO1

is not present.

are not used, these supplies

DDIO2

DDA

DS10198 Rev 8 21/270

Functional overview STM32L476xx

MSv45700V1

Low voltage detector

DDA

domain

BAT

3 x A/D converters 2 x comparators 2 x D/A converters 2 x operational amplifiers Voltage reference buffer

domain

I/O ring

SSA

Reset block Temp. sensor 3 x PLL, HSI, MSI

Standby circuitry (Wakeup logic, IWDG)

Voltage regulator

DDIO1

LSE crystal 32 K osc BKP registers RCC BDCR register RTC

Backup domain

Core SRAM1 SRAM2 Digital peripherals

CORE

domain

CORE

LCD

USB transceivers

DDUSB

DDIO2

domain

I/O ring

DDIO2

PG[15:2]

Flash memory

DD12

Note: If these supplies are tied to ground, the I/Os supplied by these power supplies are not 5 V

tolerant (refer to

Tabl e 20: Voltage characteristics).

Note: V

DDIOx

DDIO2

is the I/Os general purpose digital functions supply. V , with V

DDIO1

= VDD. V

supply voltage level is independent from V

DDIO2

Figure 2. Power supply overview

represents V

DDIOx

DDIO1

During power-up and power-down phases, the following power sequence requirements must be respected:

• When VDD is below 1 V, other power supplies (V

• When V

During the power-down phase, VDD can temporarily become lower than other supplies only if the energy provided to the MCU remains below 1 capacitors to be discharged with different time constants during the power-down transient phase.

remain below V

, V

+ 300 mV.

is above 1 V, all power supplies are independent.

DDA

mJ; this allows external decoupling

DDUSB

, V

DDIO2

, V

LCD

) must

22/270 DS10198 Rev 8

STM32L476xx Functional overview

MSv47490V1

0.3

BOR0

3.6

Operating modePower-on Power-down time

DDX

(1)

Invalid supply area V

DDX

< V

+ 300 mV

DDX

independent from V

Figure 3. Power-up/down sequence

1. V

refers to any power supply among V

DDX

3.9.2 Power supply supervisor

The device has an integrated ultra-low-power brown-out reset (BOR) active in all modes except Shutdown and ensuring proper operation after power-on and during power down. The device remains in reset mode when the monitored supply voltage V specified threshold, without the need for an external reset circuit.

The lowest BOR level is 1.71V at power on, and other higher thresholds can be selected through option bytes.The device features an embedded programmable voltage detector (PVD) that monitors the V interrupt can be generated when V higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

In addition, the device embeds a Peripheral Voltage Monitor which compares the independent supply voltages V that the peripheral is in its functional supply range.

power supply and compares it to the VPVD threshold. An

DDA

, V

DDA

drops below the VPVD threshold and/or when VDD is

, V

DDUSB

, V

LCD

is below a

DDIO2

with a fixed threshold in order to ensure

DDIO2

DS10198 Rev 8 23/270

Functional overview STM32L476xx

3.9.3 Voltage regulator

Two embedded linear voltage regulators supply most of the digital circuitries: the main regulator (MR) and the low-power regulator (LPR).

• The MR is used in the Run and Sleep modes and in the Stop 0 mode.

• The LPR is used in Low-Power Run, Low-Power Sleep, Stop 1 and Stop 2 modes. It is

also used to supply the 32 Kbyte SRAM2 in Standby with SRAM2 retention.

• Both regulators are in power-down in Standby and Shutdown modes: the regulator output is in high impedance, and the kernel circuitry is powered down thus inducing zero consumption.

The ultralow-power STM32L476xx supports dynamic voltage scaling to optimize its power consumption in run mode. The voltage from the Main Regulator that supplies the logic (V

There are two power consumption ranges:

• Range 1 with the CPU running at up to 80 MHz.

• Range 2 with a maximum CPU frequency of 26 MHz. All peripheral clocks are also

) can be adjusted according to the system’s maximum operating frequency.

CORE

limited to 26 MHz.

The V

can be supplied by the low-power regulator, the main regulator being switched

CORE

off. The system is then in Low-power run mode.

• Low-power run mode with the CPU running at up to 2 MHz. Peripherals with independent clock can be clocked by HSI16.

When the MR is in use, the STM32L476xx with the external SMPS option allows to force an external V

When V

DD12

supply on the VDD12 supply pins.

CORE

is forced by an external source and is higher than the output of the internal LDO, the current is taken from this external supply and the overall power efficiency is significantly improved if using an external step down DC/DC converter.

3.9.4 Low-power modes

The ultra-low-power STM32L476xx supports seven low-power modes to achieve the best compromise between low-power consumption, short startup time, available peripherals and available wakeup sources.

24/270 DS10198 Rev 8

STM32L476xx Functional overview

Table 4. STM32L476xx modes overview

DS10198 Rev 8 25/270

Mode

Regulator

(1)

CPU Flash SRAM Clocks DMA & Peripherals

range 1

SMPS

range 2

High

Run

Yes ON

range2

SMPS

range 2

Low

LPRun LPR Yes ON

MR range

SMPS

range 2

High

Sleep

No ON

range2

SMPS

range 2

Low

LPSleep LPR No ON

(4)

ON Any

(7)

except

Any

PLL

Any

PLL

(2)

Wakeup source Consumption

112 µA/MHz

All

40 µA/MHz

N/A

100 µA/MHz

All except OTG_FS, RNG

39 µA/MHz

All except OTG_FS, RNG N/A 136 µA/MHz

37 µA/MHz

All

13 µA/MHz

Any interrupt or

event

35 µA/MHz

All except OTG_FS, RNG

15 µA/MHz

All except OTG_FS, RNG

Any interrupt or

event

40 µA/MHz 6 cycles

(3)

(5)

(6)

to Range 1: 4 µs

to Range 2: 64 µs

(5)

(6)

Wakeup time

N/A

6 cycles

26/270 DS10198 Rev 8

Table 4. STM32L476xx modes overview (continued)

Functional overview STM32L476xx

Mode

Stop 0

Regulator

(1)

Range 1

Range 2

CPU Flash SRAM Clocks DMA & Peripherals

(8)

No Off ON

(8)

Stop 1 LPR No Off ON

LSE

LSI

LSE

LSI

(2)

BOR, PVD, PVM

RTC, LCD, IWDG

COMPx (x=1,2)

DAC1

OPAMPx (x=1,2)

USARTx (x=1...5)

LPUART1

I2Cx (x=1...3)

(9)

(10)

LPTIMx (x=1,2)

***

All other peripherals are

frozen.

BOR, PVD, PVM

RTC, LCD, IWDG

COMPx (x=1,2)

DAC1

OPAMPx (x=1,2)

USARTx (x=1...5)

LPUART1

I2Cx (x=1...3)

(9)

(10)

LPTIMx (x=1,2)

***

All other peripherals are

frozen.

Wakeup source Consumption

Reset pin, all I/Os

BOR, PVD, PVM

RTC, LCD, IWDG

COMPx (x=1..2)

USARTx (x=1...5)

LPUART1

I2Cx (x=1...3)

(9)

108 µA

(10)

LPTIMx (x=1,2)

OTG_FS SWPMI1

(11)

(12)

Reset pin, all I/Os

BOR, PVD, PVM

RTC, LCD, IWDG

COMPx (x=1..2)

(9)

USARTx (x=1...5)

LPUART1

I2Cx (x=1...3)

(9)

(10)

6.6 µA w/o RTC

6.9 µA w RTC

LPTIMx (x=1,2)

OTG_FS SWPMI1

(11)

(12)

(3)

0.7 µs in SRAM

4.5 µs in Flash

Wakeup time

4 µs in SRAM

6 µs in Flash

Table 4. STM32L476xx modes overview (continued)

STM32L476xx Functional overview

DS10198 Rev 8 27/270

Mode

Regulator

(1)

CPU Flash SRAM Clocks DMA & Peripherals

Stop 2 LPR No Off ON

LPR

Standby

OFF

Shutdown OFF

Powered

Off

Powered

Off

Powered

SRAM2

Off

LSE

LSI

LSE

LSI

LSE

(2)

BOR, PVD, PVM

RTC, LCD, IWDG

COMPx (x=1..2)

(10)

I2C3

LPUART1

(9)

LPTIM1

***

All other peripherals are

frozen.

BOR, RTC, IWDG

***

All other peripherals are

powered off.

***

I/O configuration can be

floating, pull-up or pull-down

RTC

***

All other peripherals are

powered off.

***

I/O configuration can be

floating, pull-up or pull-

down

(14)

Wakeup source Consumption

Reset pin, all I/Os

BOR, PVD, PVM

RTC, LCD, IWDG

COMPx (x=1..2)

(10)

I2C3

LPUART1

(9)

1.1 µA w/o RTC

1.4 µA w/RTC

LPTIM1

0.35 µA w/o RTC

0.65 µA w/ RTC

Reset pin

5 I/Os (WKUPx)

BOR, RTC, IWDG

(13)

0.12 µA w/o RTC

0.42 µA w/ RTC

Reset pin

5 I/Os (WKUPx)

RTC

0.03 µA w/o RTC

(13)

0.33 µA w/ RTC

(3)

Wakeup time

5 µs in SRAM

7 µs in Flash

14 µs

256 µs

1. LPR means Main regulator is OFF and Low-power regulator is ON.

2. All peripherals can be active or clock gated to save power consumption.

3. Typical current at V LPRun/LPSleep.

4. The Flash memory can be put in power-down and its clock can be gated off when executing from SRAM.

5. Theoretical value based on V

6. Theoretical value based on V

7. The SRAM1 and SRAM2 clocks can be gated on or off independently.

= 1.8 V, 25°C. Consumptions values provided running from SRAM, Flash memory Off, 80 MHz in Range 1, 26 MHz in Range 2, 2 MHz in

= 3.3 V, DC/DC Efficiency of 85%, V

CORE

= 1.10 V

= 1.05 V

28/270 DS10198 Rev 8

8. SMPS mode can be used in STOP0 Mode, but no significant power gain can be expected.

9. U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event.

10. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.

11. OTG_FS wakeup by resume from suspend and attach detection protocol event.

12. SWPMI1 wakeup by resume from suspend.

13. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5.

14. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode.

Functional overview STM32L476xx

STM32L476xx Functional overview

By default, the microcontroller is in Run mode after a system or a power Reset. It is up to the user to select one of the low-power modes described below:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

• Low-power run mode

This mode is achieved with V

supplied by the low-power regulator to minimize the

CORE

regulator's operating current. The code can be executed from SRAM or from Flash, and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can be clocked by HSI16.

• Low-power sleep mode

This mode is entered from the low-power run mode. Only the CPU clock is stopped. When wakeup is triggered by an event or an interrupt, the system reverts to the lowpower run mode.

• Stop 0, Stop 1 and Stop 2 modes

Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the V

domain are stopped, the PLL, the MSI

CORE

RC, the HSI16 RC and the HSE crystal oscillators are disabled. The LSE or LSI is still running.

The RTC can remain active (Stop mode with RTC, Stop mode without RTC).

Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode to detect their wakeup condition.

Three Stop modes are available: Stop 0, Stop 1 and Stop 2 modes. In Stop 2 mode, most of the V

domain is put in a lower leakage mode.

CORE

Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator remains ON, allowing a very fast wakeup time but with much higher consumption.

The system clock when exiting from Stop 0, Stop 1 or Stop 2 modes can be either MSI up to 48 MHz or HSI16, depending on software configuration.

• Standby mode

The Standby mode is used to achieve the lowest power consumption with BOR. The internal regulator is switched off so that the V

domain is powered off. The PLL, the

CORE

MSI RC, the HSI16 RC and the HSE crystal oscillators are also switched off.

The RTC can remain active (Standby mode with RTC, Standby mode without RTC).

The brown-out reset (BOR) always remains active in Standby mode.

The state of each I/O during standby mode can be selected by software: I/O with internal pull-up, internal pull-down or floating.

After entering Standby mode, SRAM1 and register contents are lost except for registers in the Backup domain and Standby circuitry. Optionally, SRAM2 can be retained in Standby mode, supplied by the low-power Regulator (Standby with SRAM2 retention mode).

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE).

The system clock after wakeup is MSI up to 8 MHz.

DS10198 Rev 8 29/270

Functional overview STM32L476xx

• Shutdown mode

The Shutdown mode allows to achieve the lowest power consumption. The internal regulator is switched off so that the V

domain is powered off. The PLL, the HSI16,

CORE

the MSI, the LSI and the HSE oscillators are also switched off.

The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).

The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode, therefore the switch to Backup domain is not supported.

SRAM1, SRAM2 and register contents are lost except for registers in the Backup domain.

The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic wakeup, timestamp, tamper).

The system clock after wakeup is MSI at 4 MHz.

30/270 DS10198 Rev 8

+ 240 hidden pages

ST MICROELECTRONICS STM32L476RCT6 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Table 1. Device summary

1 Introduction

2 Description

Table 2. STM32L476xx family device features and peripheral counts

Figure 1. STM32L476xx block diagram

3 Functional overview

3.1 Arm® Cortex®-M4 core with FPU

3.2 Adaptive real-time memory accelerator (ART Accelerator™)

3.3 Memory protection unit

3.4 Embedded Flash memory

Table 3. Access status versus readout protection level and execution modes

3.5 Embedded SRAM

3.6 Firewall

3.7 Boot modes

3.8 Cyclic redundancy check calculation unit (CRC)

3.9 Power supply management

3.9.1 Power supply schemes

Figure 2. Power supply overview

Figure 3. Power-up/down sequence

3.9.2 Power supply supervisor

3.9.3 Voltage regulator

3.9.4 Low-power modes

Table 4. STM32L476xx modes overview