ST MICROELECTRONICS STM32L476RCT6 Datasheet

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STM32L476xx

UFBGA144 (10 × 10)

LQFP144 (20 × 20)

LQFP100 (14 × 14)

LQFP64 (10 × 10)

UFBGA132 (7 × 7)

WLCSP72 WLCSP81

Ultra-low-power Arm® Cortex®-M4 32-bit MCU+FPU, 100DMIPS,

up to 1MB Flash, 128 KB SRAM, USB OTG FS, LCD, ext. SMPS

Datasheet - production data

Features

• Ultra-low-power with FlexPowerControl – 1.71 V to 3.6 V power supply – -40 °C to 85/105/125 °C temperature range – 300 nA in V

32x32-bit backup registers – 30 nA Shutdown mode (5 wakeup pins) – 120 nA Standby mode (5 wakeup pins) – 420 nA Standby mode with RTC – 1.1 µA Stop 2 mode, 1.4 µA with RTC – 100 µA/MHz run mode (LDO Mode) –39 A/MHz run mode (@3.3 V SMPS

Mode) – Batch acquisition mode (BAM) – 4 µs wakeup from Stop mode – Brown out reset (BOR) – Interconnect matrix

• Core: Arm

Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait-state execution from Flash memory, frequency up to 80 MHz, MPU, 100DMIPS and DSP instructions

• Performance benchmark – 1.25 DMIPS/MHz (Drystone 2.1) – 273.55 CoreMark

80 MHz)

• Energy benchmark – 294 ULPMark™ CP score – 106 ULPMark™ PP score

• Clock Sources – 4 to 48 MHz crystal oscillator – 32 kHz crystal oscillator for RTC (LSE) – Internal 16 MHz factory-trimmed RC (±1%) – Internal low-power 32 kHz RC (±5%) – Internal multispeed 100 kHz to 48 MHz

oscillator, auto-trimmed by LSE (better than ±0.25 % accuracy)

– 3 PLLs for system clock, USB, audio, ADC

mode: supply for RTC and

BAT

32-bit Cortex®-M4 CPU with FPU,

(3.42 CoreMark/MHz @

• Up to 114 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V

• RTC with HW calendar, alarms and calibration

• LCD 8× 40 or 4× 44 with step-up converter

• Up to 24 capacitive sensing channels: support

touchkey, linear and rotary touch sensors

• 16x timers: 2x 16-bit advanced motor-control, 2x 32-bit and 5x 16-bit general purpose, 2x 16bit basic, 2x low-power 16-bit timers (available in Stop mode), 2x watchdogs, SysTick timer

• Memories – Up to 1 MB Flash, 2 banks read-while-

write, proprietary code readout protection

– Up to 128 KB of SRAM including 32 KB

with hardware parity check

– External memory interface for static

memories supporting SRAM, PSRAM, NOR and NAND memories

– Quad SPI memory interface

• 4x digital filters for sigma delta modulator

• Rich analog peripherals (independent supply)

– 3x 12-bit ADC 5 Msps, up to 16-bit with

hardware oversampling, 200 µA/Msps

– 2x 12-bit DAC output channels, low-power

sample and hold – 2x operational amplifiers with built-in PGA – 2x ultra-low-power comparators

• 20x communication interfaces – USB OTG 2.0 full-speed, LPM and BCD – 2x SAIs (serial audio interface) –3x I2C FM+(1 Mbit/s), SMBus/PMBus – 5x USARTs (ISO 7816, LIN, IrDA, modem) – 1x LPUART (Stop 2 wake-up)

June 2019 DS10198 Rev 8 1/270

This is information on a product in full production.

www.st.com

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STM32L476xx

– 3x SPIs (and 1x Quad SPI) – CAN (2.0B Active) and SDMMC interface – SWPMI single wire protocol master I/F – IRTIM (Infrared interface)

• 14-channel DMA controller

Table 1. Device summary

Reference Part numbers

STM32L476RG, STM32L476JG, STM32L476MG, STM32L476ME, STM32L476VG,

STM32L476xx

STM32L476QG, STM32L476ZG, STM32L476RE, STM32L476JE, STM32L476VE, STM32L476QE, STM32L476ZE, STM32L476RC, STM32L476VC

• True random number generator

• CRC calculation unit, 96-bit unique ID

• Development support: serial wire debug

(SWD), JTAG, Embedded Trace Macrocell™

• All packages are ECOPACK2

compliant

2/270 DS10198 Rev 8

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STM32L476xx Contents

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.1 Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 18

3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.6 Firewall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.7 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.8 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 21

3.9 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.9.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.9.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.9.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.9.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.9.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.9.6 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.10 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.11 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.12 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.13 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.14 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.14.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 40

3.14.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 40

3.15 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.15.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.15.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.15.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.16 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

DS10198 Rev 8 3/270

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Contents STM32L476xx

3.17 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.18 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.19 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.20 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.21 Liquid crystal display controller (LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.22 Digital filter for Sigma-Delta Modulators (DFSDM) . . . . . . . . . . . . . . . . . . 45

3.23 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.24 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.24.1 Advanced-control timer (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.24.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16,

TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.24.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.24.4 Low-power timer (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . 49

3.24.5 Infrared interface (IRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.24.6 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.24.7 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.24.8 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.25 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 51

3.26 Inter-integrated circuit interface (I

C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.27 Universal synchronous/asynchronous receiver transmitter (USART) . . . 53

3.28 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 54

3.29 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.30 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.31 Single wire protocol master interface (SWPMI) . . . . . . . . . . . . . . . . . . . . 56

3.32 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.33 Secure digital input/output and MultiMediaCards Interface (SDMMC) . . . 57

3.34 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 57

3.35 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 58

3.36 Quad SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.37 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

3.37.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 60

3.37.2 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

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STM32L476xx Contents

5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 115

6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118

6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 119

6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . 120

6.3.4 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

6.3.6 Wakeup time from low-power modes and voltage scaling

transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 153

6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 158

6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

6.3.10 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

6.3.16 Extended interrupt and event controller input (EXTI) characteristics . . 176

6.3.17 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

6.3.18 Analog-to-Digital converter characteristics . . . . . . . . . . . . . . . . . . . . . 177

6.3.19 Digital-to-Analog converter characteristics . . . . . . . . . . . . . . . . . . . . . 190

6.3.20 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 195

6.3.21 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

6.3.22 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 198

6.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

DS10198 Rev 8 5/270

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Contents STM32L476xx

6.3.24 V

6.3.25 LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

6.3.26 DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

6.3.27 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

6.3.28 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 208

6.3.29 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

6.3.30 SWPMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

BAT

7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

7.1 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

7.2 UFBGA144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

7.3 UFBGA132 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

7.4 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

7.5 WLCSP81 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

7.6 WLCSP72 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

7.7 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

7.8 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

7.8.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

7.8.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 261

8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

6/270 DS10198 Rev 8

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STM32L476xx List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2. STM32L476xx family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . 15

Table 3. Access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 19

Table 4. STM32L476xx modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 5. Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 6. STM32L476xx peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 7. DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 8. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 9. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 10. DFSDM1 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 11. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 12. I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 13. STM32L476xx USART/UART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 14. SAI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 15. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 16. STM32L476xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 17. Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 18. Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 19. STM32L476xx memory map and peripheral register boundary addresses . . . . . . . . . . . 108

Table 20. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Table 21. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Table 22. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 23. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Table 24. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Table 25. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 120

Table 26. Embedded internal voltage reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 27. Current consumption in Run and Low-power run modes, code with data processing

running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . 125

Table 28. Current consumption in Run modes, code with data processing running from Flash,

ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS

(VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Table 29. Current consumption in Run and Low-power run modes, code with data processing

running from Flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Table 30. Current consumption in Run modes, code with data processing running from Flash,

ART disable and power supplied by external SMPS (VDD12 = 1.10 V). . . . . . . . . . . . . . 128

Table 31. Current consumption in Run and Low-power run modes, code with data processing

running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 32. Current consumption in Run, code with data processing running from

SRAM1 and power supplied by external SMPS (VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . 130

Table 33. Typical current consumption in Run and Low-power run modes, with different codes

running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . 131

Table 34. Typical current consumption in Run, with different codes running from Flash,

ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS

(VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Table 35. Typical current consumption in Run, with different codes running from Flash,

ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS

(VDD12 = 1.05 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Table 36. Typical current consumption in Run and Low-power run modes, with different codes

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List of tables STM32L476xx

running from Flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Table 37. Typical current consumption in Run modes, with different codes running from

Flash, ART disable and power supplied by external SMPS (VDD12 = 1.10 V) . . . . . . . . 133

Table 38. Typical current consumption in Run modes, with different codes running

from Flash, ART disable and power supplied by external SMPS (VDD12 = 1.05 V) . . . . 133

Table 39. Typical current consumption in Run and Low-power run modes, with different codes

running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Table 40. Typical current consumption in Run mode, with different codes running from

SRAM1 and power supplied by external SMPS (VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . 134

Table 41. Typical current consumption in Run mode, with different codes running from

SRAM1 and power supplied by external SMPS (VDD12 = 1.05 V) . . . . . . . . . . . . . . . . . 135

Table 42. Current consumption in Sleep and Low-power sleep modes, Flash ON . . . . . . . . . . . . . 136

Table 43. Current consumption in Sleep, Flash ON and power supplied by external SMPS

(VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Table 44. Current consumption in Low-power sleep modes, Flash in power-down . . . . . . . . . . . . . 137

Table 45. Current consumption in Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Table 46. Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Table 47. Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Table 48. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Table 49. Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Table 50. Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Table 51. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Table 52. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Table 53. Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 54. Wakeup time using USART/LPUART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 55. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 56. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Table 57. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Table 58. LSE oscillator characteristics (f

= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

LSE

Table 59. HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Table 60.

MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Table 61. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Table 62. PLL, PLLSAI1, PLLSAI2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Table 63. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Table 64. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Table 65. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Table 66. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Table 67. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Table 68. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Table 69. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Table 70. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Table 71. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Table 72. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Table 73. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Table 74. EXTI input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Table 75. Analog switches booster characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Table 76. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Table 77. Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Table 78. ADC accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Table 79. ADC accuracy - limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Table 80. ADC accuracy - limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Table 81. ADC accuracy - limited test conditions 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

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Table 82. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Table 83. DAC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Table 84. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Table 85. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Table 86. OPAMP characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Table 87. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Table 88. V Table 89. V

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

BAT

charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

BAT

Table 90. LCD controller characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Table 91. DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Table 92. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Table 93. IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Table 94. WWDG min/max timeout value at 80 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Table 95. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

Table 96. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Table 97. Quad SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Table 98. QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Table 99. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Table 100. SD / MMC dynamic characteristics, VDD=2.7 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . 216

Table 101. eMMC dynamic characteristics, VDD = 1.71 V to 1.9 V . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Table 102. USB OTG DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Table 103. USB OTG electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

Table 104. USB BCD DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

Table 105. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 223

Table 106. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 223

Table 107. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 224

Table 108. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 225

Table 109. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 226

Table 110. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 226

Table 111. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 228

Table 112. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 228

Table 113. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

Table 114. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

Table 115. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 233

Table 116. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Table 117. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

Table 118. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 237

Table 119. SWPMI electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

Table 120. LQFP - 144-pin, 20 x 20 mm low-profile quad flat package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

Table 121. UFBGA - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball

grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

Table 122. UFBGA144 recommended PCB design rules (0.80 mm pitch BGA) . . . . . . . . . . . . . . . . 244

Table 123. UFBGA - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Table 124. UFBGA132 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 247

Table 125. LQFP - 100 pins, 14 x 14 mm low-profile quad flat package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

Table 126. WLCSP- 81-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

Table 127. WLCSP81 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . 253

Table 128. WLCSP - 72-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip

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List of tables STM32L476xx

scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Table 129. WLCSP72 recommended PCB design rules (0.4 mm pitch BGA) . . . . . . . . . . . . . . . . . . 256

Table 130. LQFP - 64 pins, 10 x 10 mm low-profile quad flat

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

Table 131. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

Table 132. STM32L476xx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

Table 133. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

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STM32L476xx List of figures

List of figures

Figure 1. STM32L476xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 2. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 3. Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 4. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 5. Voltage reference buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 6. STM32L476Zx LQFP144 pinout Figure 7. STM32L476Zx, external SMPS device, LQFP144 pinout Figure 8. STM32L476Zx UFBGA144 ballout Figure 9. STM32L476Qx UFBGA132 ballout

Figure 10. STM32L476Qx, external SMPS device, UFBGA132 ballout . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 11. STM32L476Vx LQFP100 pinout Figure 12. STM32L476Mx WLCSP81 ballout Figure 13. STM32L476Jx WLCSP72 ballout Figure 14. STM32L476Jx, external SMPS device, WLCSP72 ballout Figure 15. STM32L476Rx LQFP64 pinout Figure 16. STM32L476Rx, external SMPS device, LQFP64 pinout

Figure 17. STM32L476xx memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 18. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 19. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 20. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 21. Current consumption measurement scheme with and without external

SMPS power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 22. VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Figure 23. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Figure 24. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Figure 25. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Figure 26. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Figure 27. HSI16 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Figure 28. Typical current consumption versus MSI frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Figure 29. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Figure 30. I/O AC characteristics definition

Figure 31. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Figure 32. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Figure 33. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Figure 34. 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Figure 35. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Figure 36. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Figure 37. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Figure 38. Quad SPI timing diagram - SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Figure 39. Quad SPI timing diagram - DDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Figure 40. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

Figure 41. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Figure 42. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Figure 43. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Figure 44. USB OTG timings – definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . 219

Figure 45. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 222

Figure 46. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 224

Figure 47. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 225

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

(1)

. . . . . . . . . . . . . . . . . . . . . . . . 62

(1)

. . . . . . . . . . . . . . . . . . . . . . . 66

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . 67

DS10198 Rev 8 11/270

Page 12

List of figures STM32L476xx

Figure 48. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 227

Figure 49. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

Figure 50. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

Figure 51. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 233

Figure 52. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

Figure 53. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Figure 54. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Figure 55. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 236

Figure 56. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 237

Figure 57. LQFP - 144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . 239

Figure 58. LQFP - 144-pin,20 x 20 mm low-profile quad flat package

recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

Figure 59. LQFP144 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

Figure 60. UFBGA - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball

grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

Figure 61. UFBGA - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball

grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

Figure 62. UFBGA144 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Figure 63. UFBGA - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Figure 64. UFBGA - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array

package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

Figure 65. UFBGA132 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

Figure 66. LQFP - 100 pins, 14 x 14 mm low-profile quad flat package outline. . . . . . . . . . . . . . . . . 249

Figure 67. LQFP - 100 pins, 14 x 14 mm low-profile quad flat

recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

Figure 68. LQFP100 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

Figure 69. WLCSP - 81-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level

chip scale package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

Figure 70. WLCSP81- 81-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale

package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

Figure 71. WLCSP81 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

Figure 72. WLCSP - 72-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip

scale package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Figure 73. WLCSP72 - 72-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level

chip scale package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

Figure 74. WLCSP72 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

Figure 75. LQFP - 64 pins, 10 x 10 mm low-profile quad flat package outline. . . . . . . . . . . . . . . . . . 258

Figure 76. LQFP - 64 pins, 10 x 10 mm low-profile quad flat package

recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

Figure 77. LQFP64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

Figure 78. LQFP64 P

max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

12/270 DS10198 Rev 8

Page 13

STM32L476xx Introduction

1 Introduction

This datasheet provides the ordering information and mechanical device characteristics of

the STM32L476xx microcontrollers.

This document should be read in conjunction with the STM32L4x6 reference manual

(RM0351). The reference manual is available from the STMicroelectronics website

www.st.com.

For information on the Arm

Reference Manual, available from the www.arm.com website.

®(a)

Cortex®-M4 core, please refer to the Cortex®-M4 Technical

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

DS10198 Rev 8 13/270

Page 14

Description STM32L476xx

2 Description

The STM32L476xx devices are the ultra-low-power microcontrollers based on the high-

performance Arm

The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all

Arm

single-precision data-processing instructions and data types. It also implements a full

Cortex®-M4 32-bit RISC core operating at a frequency of up to 80 MHz.

set of DSP instructions and a memory protection unit (MPU) which enhances application

security.

The STM32L476xx devices embed high-speed memories (Flash memory up to 1 Mbyte, up

to 128

Kbyte of SRAM), a flexible external memory controller (FSMC) for static memories (for devices with packages of 100 pins and more), a Quad SPI flash memories interface (available on all packages) and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.

The STM32L476xx devices embed several protection mechanisms for embedded Flash memory and SRAM: readout protection, write protection, proprietary code readout protection and Firewall.

The devices offer up to three fast 12-bit ADCs (5 Msps), two comparators, two operational amplifiers, two DAC channels, an internal voltage reference buffer, a low-power RTC, two general-purpose 32-bit timer, two 16-bit PWM timers dedicated to motor control, seven general-purpose 16-bit timers, and two 16-bit low-power timers. The devices support four digital filters for external sigma delta modulators (DFSDM).

In addition, up to 24 capacitive sensing channels are available. The devices also embed an integrated LCD driver 8x40 or 4x44, with internal step-up converter.

They also feature standard and advanced communication interfaces.

• Three I2Cs

• Three SPIs

• Three USARTs, two UARTs and one Low-Power UART.

• Two SAIs (Serial Audio Interfaces)

• One SDMMC

• One CAN

• One USB OTG full-speed

• One SWPMI (Single Wire Protocol Master Interface)

The STM32L476xx operates in the -40 to +85 °C (+105 °C junction), -40 to +105 °C (+125

°C junction) and -40 to +125 °C (+130 °C junction) temperature ranges from a 1.71 to

3.6

V VDD power supply when using internal LDO regulator and a 1.05 to 1.32V V power supply when using external SMPS supply. A comprehensive set of power-saving modes allows the design of low-power applications.

Some independent power supplies are supported: analog independent supply input for ADC, DAC, OPAMPs and comparators, 3.3

V dedicated supply input for USB and up to 14 I/Os can be supplied independently down to 1.08V. A VBAT input allows to backup the RTC and backup registers. Dedicated V

power supplies can be used to bypass the internal

DD12

LDO regulator when connected to an external SMPS.

The STM32L476xx family offers six packages from 64-pin to 144-pin packages.

14/270 DS10198 Rev 8

DD12

Page 15

STM32L476xx Description

Table 2. STM32L476xx family device features and peripheral counts

Peripheral

Flash memory

STM32

L476Zx

512K

1MB

STM32

L476Qx

512K

1MB

STM32

L476Vx

256KB512K

1MB

512K

SRAM 128KB

External memory controller for static

Yes Yes Yes

(1)

memories

Quad SPI Yes

Advanced control

General purpose

2 (16-bit)

5 (16-bit) 2 (32-bit)

Basic 2 (16-bit)

Timers

Low -power 2 (16-bit)

SysTick timer

Watchdog timers (indepen-

2 dent, window)

SPI 3

Comm. interfaces

USART UART LPUART

SAI 2

CAN 1

USB OTG FS

Yes

SDMMC Yes

SWPMI Yes

STM32

L476Mx

1MB

STM32

L476Jx

512K

1MB

256KB512K

No No No

STM32

L476Rx

1MB

Digital filters for sigmadelta modulators

Yes (4 filters)

Number of channels 8

RTC Yes

Tamper pins 3 2 2 2

LCD COM x SEG

Yes

8x40 or

4x44

Yes

8x40 or

4x44

Yes

8x40 or 4x44

Yes

8x30 or

4x32

Yes

8x28 or

4x32

Yes

8x28 or 4x32

DS10198 Rev 8 15/270

Page 16

Description STM32L476xx

Table 2. STM32L476xx family device features and peripheral counts (continued)

Peripheral

STM32

L476Zx

STM32

L476Qx

STM32

L476Vx

STM32

L476Mx

STM32

L476Jx

STM32

L476Rx

Random generator Yes

(2)

GPIOs Wakeup pins Nb of I/Os down to

114

109

65 5 0

4 6

51 4 6

4 0

1.08 V

Capacitive sensing Number of channels

12-bit ADCs Number of channels

24 24 21 12 12 12

12-bit DAC channels 2

Internal voltage reference buffer

Yes No

Analog comparator 2

Operational amplifiers 2

Max. CPU frequency 80 MHz

Operating voltage (V

)

DD12

Operating temperature

Packages

1. For the LQFP100 package, only FMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select.

2. In case external SMPS package type is used, 2 GPIO's are replaced by VDD12 pins to connect the SMPS power supplies hence reducing the number of available GPIO's by 2.

) 1.71 to 3.6 V

1.05 to 1.32 V

Ambient operating temperature: -40 to 85 °C / -40 to 105 °C / -40 to 125 °C

Junction temperature: -40 to 105 °C / -40 to 125 °C / -40 to 130 °C

LQFP144

UFBGA144

UFBGA

132

LQFP100 WLCSP81 WLCSP72 LQFP64

16/270 DS10198 Rev 8

Page 17

STM32L476xx Description

MS31263V8

USB OTG

Flash up to 1 MB

Flexible static memory controller (FSMC):

SRAM, PSRAM, NOR Flash,

NAND Flash

GPIO PORT A

AHB/APB2

EXT IT. WKUP

114 AF

PA[15:0]

TIM1 / PWM

3 compl. channels (TIM1_CH[1:3]N),

4 channels (TIM1_CH[1:4]),

ETR, BKIN, BKIN2 as AF

USART1

RX, TX, CK,CTS,

RTS as AF

SPI1

MOSI, MISO,

SCK, NSS as AF

APB260 M Hz

APB1 30MHz

MOSI, MISO, SCK, NSS as AF

DAC1_OUT1

ITF

WWDG

RTC_TS

OSC32_IN

OSC32_OUT

smcard

IrDA

16b

SDIO / MMC

D[7:0]

CMD, CK as AF

VBAT = 1.55 to 3.6 V

SCL, SDA, SMBA as AF

JTAG & SW

ARM Cortex-M4

80 MHz

FPU

NVIC

ETM

MPU

DMA2

ART

ACCEL/

CACHE

CLK, NE[4:1], NL, NBL[1:0], A[25:0], D[15:0], NOE, NWE, NWAIT, NCE3, INT3 as AF

RNG

FIFO

@ VDDA

BOR

Supply

supervision

PVD, PVM

Int

reset

XTAL 32 kHz

MAN AGT

RTC

FCLK

Standby

interface

IWDG

@VBAT

@ VDD

@VDD

AWU

Reset & clock

control

PCLKx

Voltage regulator

3.3 to 1.2 V

VDD

Power management

@ VDD

RTC_TAMPx

Backup register

AHB bus-matrix

TIM15

2 channels,

1 compl. channel, BKIN as AF

TIM6

TIM7

TIM2

TIM3

TIM4

TIM5

USART2

USART3

I2C1/SMBUS

D-BUS

FIFO

APB1 80 MHz (max)

SRAM 96 KB

SRAM 32 KB

I-BUS

S-BUS

DMA1

PB[15:0]

PC[15:0]

PD[15:0]

PE[15:0]

PF[15:0]

PG[15:0]

PH[1:0]

GPIO PORT B

GPIO PORT C

GPIO PORT D

GPIO PORT E

GPIO PORT F

GPIO PORT G

GPIO PORT H

TIM8 / PWM

16b

TIM16

16b

TIM17

16b

3 compl. channels (TIM1_CH[1:3]N),

4 channels (TIM1_CH[1:4]),

ETR, BKIN, BKIN2 as AF

1 channel,

1 compl. channel, BKIN as AF

1 channel,

1 compl. channel, BKIN as AF

DAC1_OUT2

16b

SCL, SDA, SMBA as AF

MOSI, MISO, SCK, NSS as AF

TX, RX as AF

RX, TX, CTS, RTS as AF

RX, TX, CK, CTS, RTS as AF

smcard

IrDA

smcard

IrDA

32b

16b

32b

4 channels, ETR as AF

AHB/APB1

OSC_IN

OSC_OUT

HCLKx

XTAL OSC

4- 16MHz

8 analog inputs common

to the 3 ADCs

VREF+

USAR T 2M Bps

Temperature sensor

ADC1

ADC2

ADC3

ITF

@ VDDA

8 analog inputs common

to the ADC1 & 2

8 analog inputs for ADC3

SAI1

MCLK_A, SD_A, FS_A, SCK_A, EXTCLK

MCLK_B, SD_B, FS_B, SCK_B as AF

SAI2

MCLK_A, SD_A, FS_A, SCK_A, EXTCLK

MCLK_B, SD_B, FS_B, SCK_B as AF

DFSDM

SDCKIN[7:0], SDDATIN[7:0],

SDCKOUT,SDTRIG as AF

Touch sensing controller

8 Groups of

3 channels max as AF

VOUT, VINM, VINP

LCD 8x40

LPUART1

SWPMI1

LPTIM1

LPTIM2

SEGx, COMx as AF

RX, TX, CTS, RTS as AF

IO RX, TX, SUSPEND as AF

IN1, IN2, OUT, ETR as AF

IN1, OUT, ETR as AF

RC HSI

RC LSI

PLL 1&2&3

MSI

Quad SPI memory interface

BK1_IO[3:0] CLK NCS

@ VDDUSB

COMP1

INP, INM, OUT

COMP2

INP, INM, OUT

@ VDDA

RTC_OUT

FIFO

PHY

AHB1 80 MHz

CRC

I2C2/SMBUS

I2C3/SMBUS

bxCAN1

OpAmp1

SP3

SP2

UART5

UART4

LCD Booster

LCD

= 2.5V to 3.6V

APB2 80MHz

AHB2 80 MHz

OpAmp2

@VDDA

Firewall

VREF Buffer

@ VDDA

@ VDD

DP DM

SCL, SDA, INTN, ID, VBUS, SOF

VDD = 1.71 to 3.6 V

VSS

VDDA, VSSA

VDD, VSS, NRST

VDDIO2, VDDUSB

VOUT, VINM, VINP

TRACECLK

TRACED[3:0]

NJTRST, JTDI,

JTCK/SWCLK

JTDO/SWD, JTDO

VDD12 = 1.05 to 1.32 V

(1)

VDD12

1. Only available when using external SMPS supply mode.

DAC1

Figure 1. STM32L476xx block diagram

Note: AF: alternate function on I/O pins.

DS10198 Rev 8 17/270

Page 18

Functional overview STM32L476xx

3 Functional overview

3.1 Arm® Cortex®-M4 core with FPU

The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm® processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.

The Arm® Cortex®-M4 with FPU 32-bit RISC processor features exceptional codeefficiency, delivering the high-performance expected from an Arm usually associated with 8- and 16-bit devices.

The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution.

Its single precision FPU speeds up software development by using metalanguage development tools, while avoiding saturation.

With its embedded Arm® core, the STM32L476xx family is compatible with all Arm® tools and software.

Figure 1 shows the general block diagram of the STM32L476xx family devices.

core in the memory size

3.2 Adaptive real-time memory accelerator (ART Accelerator™)

The ART Accelerator™ is a memory accelerator which is optimized for STM32 industrystandard Arm the Arm processor to wait for the Flash memory at higher frequencies.

To release the processor near 100 DMIPS performance at 80MHz, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 64-bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 80 MHz.

Cortex®-M4 processors. It balances the inherent performance advantage of

Cortex®-M4 over Flash memory technologies, which normally requires the

3.3 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory.

The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

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STM32L476xx Functional overview

3.4 Embedded Flash memory

STM32L476xx devices feature up to 1 Mbyte of embedded Flash memory available for storing programs and data. The Flash memory is divided into two banks allowing readwhile-write operations. This feature allows to perform a read operation from one bank while an erase or program operation is performed to the other bank. The dual bank boot is also supported. Each bank contains 256 pages of 2

Flexible protections can be configured thanks to option bytes:

• Readout protection (RDP) to protect the whole memory. Three levels are available:

– Level 0: no readout protection

– Level 1: memory readout protection: the Flash memory cannot be read from or

written to if either debug features are connected, boot in RAM or bootloader is selected

– Level 2: chip readout protection: debug features (Cortex-M4 JTAG and serial

wire), boot in RAM and bootloader selection are disabled (JTAG fuse). This selection is irreversible.

Table 3. Access status versus readout protection level and execution modes

Kbyte.

Area

Main

memory

System

memory

Option

bytes

Backup

registers

SRAM2

1. Erased when RDP change from Level 1 to Level 0.

Protection

level

1 Yes Yes Yes No No No

2 Yes Yes Yes N/A N/A N/A

1 Yes No No Yes No No

2 Yes No No N/A N/A N/A

1 Yes Yes Yes Yes Yes Yes

2 Yes No No N/A N/A N/A

1YesYesN/A

2 Yes Yes N/A N/A N/A N/A

1 Yes Yes Yes

2 Yes Yes Yes N/A N/A N/A

User execution

Read Write Erase Read Write Erase

(1)

Debug, boot from RAM or boot

from system memory (loader)

No No N/A

No No No

• Write protection (WRP): the protected area is protected against erasing and programming. Two areas per bank can be selected, with 2-Kbyte granularity.

• Proprietary code readout protection (PCROP): a part of the flash memory can be protected against read and write from third parties. The protected area is execute-only: it can only be reached by the STM32 CPU, as an instruction code, while all other accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited. One area per bank can be selected, with 64-bit granularity. An additional option bit (PCROP_RDP) allows to select if the PCROP area is erased or not when the RDP protection is changed from Level 1 to Level 0.

(1)

DS10198 Rev 8 19/270

Page 20

Functional overview STM32L476xx

The whole non-volatile memory embeds the error correction code (ECC) feature supporting:

• single error detection and correction

• double error detection.

• The address of the ECC fail can be read in the ECC register

3.5 Embedded SRAM

STM32L476xx devices feature up to 128 Kbyte of embedded SRAM. This SRAM is split into two blocks:

• 96 Kbyte mapped at address 0x2000 0000 (SRAM1)

• 32 Kbyte located at address 0x1000 0000 with hardware parity check (SRAM2).

This block is accessed through the ICode/DCode buses for maximum performance. These 32 Kbyte SRAM can also be retained in Standby mode.

The SRAM2 can be write-protected with 1 Kbyte granularity.

The memory can be accessed in read/write at CPU clock speed with 0 wait states.

3.6 Firewall

The device embeds a Firewall which protects code sensitive and secure data from any access performed by a code executed outside of the protected areas.

Each illegal access generates a reset which kills immediately the detected intrusion.

The Firewall main features are the following:

• Three segments can be protected and defined thanks to the Firewall registers: – Code segment (located in Flash or SRAM1 if defined as executable protected

area) – Non-volatile data segment (located in Flash) – Volatile data segment (located in SRAM1)

• The start address and the length of each segments are configurable: – Code segment: up to 1024 Kbyte with granularity of 256 bytes – Non-volatile data segment: up to 1024 Kbyte with granularity of 256 bytes – Volatile data segment: up to 96 Kbyte with a granularity of 64 bytes

• Specific mechanism implemented to open the Firewall to get access to the protected areas (call gate entry sequence)

• Volatile data segment can be shared or not with the non-protected code

• Volatile data segment can be executed or not depending on the Firewall configuration

The Flash readout protection must be set to level 2 in order to reach the expected level of protection.

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STM32L476xx Functional overview

3.7 Boot modes

At startup, BOOT0 pin and BOOT1 option bit are used to select one of three boot options:

• Boot from user Flash

• Boot from system memory

• Boot from embedded SRAM

The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART, I2C, SPI, CAN or USB OTG FS in Device mode through DFU (device firmware upgrade).

3.8 Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.

3.9 Power supply management

3.9.1 Power supply schemes

• VDD = 1.71 to 3.6 V: external power supply for I/Os (V the system analog such as reset, power management and internal clocks. It is provided externally through VDD pins.

• V

Note: When the functions supplied by V

should preferably be shorted to V

= 1.05 to 1.32 V: external power supply bypassing internal regulator when

DD12

connected to an external SMPS. It is provided externally through VDD12 pins and only available on packages with the external SMPS supply option. VDD12 does not require any external decoupling capacitance and cannot support any external load.

= 1.62 V (ADCs/COMPs) / 1.8 (DAC/OPAMPs) to 3.6 V: external analog power

DDA

supply for ADCs, DAC, OPAMPs, Comparators and Voltage reference buffer. The V voltage level is independent from the V

= 3.0 to 3.6 V: external independent power supply for USB transceivers. The

DDUSB

voltage level is independent from the VDD voltage.

DDUSB

= 1.08 to 3.6 V: external power supply for 14 I/Os (PG[15:2]). The V

DDIO2

voltage level is independent from the V

= 2.5 to 3.6 V: the LCD controller can be powered either externally through VLCD

LCD

pin, or internally from an internal voltage generated by the embedded step-up converter.

= 1.55 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and

BAT

backup registers (through power switch) when V

, V

DDA

DDUSB

voltage.

or V

DDIO2

), the internal regulator and

DDIO1

is not present.

are not used, these supplies

DDIO2

DDA

DS10198 Rev 8 21/270

Page 22

Functional overview STM32L476xx

MSv45700V1

Low voltage detector

DDA

domain

BAT

3 x A/D converters 2 x comparators 2 x D/A converters 2 x operational amplifiers Voltage reference buffer

domain

I/O ring

SSA

Reset block Temp. sensor 3 x PLL, HSI, MSI

Standby circuitry (Wakeup logic, IWDG)

Voltage regulator

DDIO1

LSE crystal 32 K osc BKP registers RCC BDCR register RTC

Backup domain

Core SRAM1 SRAM2 Digital peripherals

CORE

domain

CORE

LCD

USB transceivers

DDUSB

DDIO2

domain

I/O ring

DDIO2

PG[15:2]

Flash memory

DD12

Note: If these supplies are tied to ground, the I/Os supplied by these power supplies are not 5 V

tolerant (refer to

Tabl e 20: Voltage characteristics).

Note: V

DDIOx

DDIO2

is the I/Os general purpose digital functions supply. V , with V

DDIO1

= VDD. V

supply voltage level is independent from V

DDIO2

Figure 2. Power supply overview

represents V

DDIOx

DDIO1

During power-up and power-down phases, the following power sequence requirements must be respected:

• When VDD is below 1 V, other power supplies (V

• When V

During the power-down phase, VDD can temporarily become lower than other supplies only if the energy provided to the MCU remains below 1 capacitors to be discharged with different time constants during the power-down transient phase.

remain below V

, V

+ 300 mV.

is above 1 V, all power supplies are independent.

DDA

mJ; this allows external decoupling

DDUSB

, V

DDIO2

, V

LCD

) must

22/270 DS10198 Rev 8

Page 23

STM32L476xx Functional overview

MSv47490V1

0.3

BOR0

3.6

Operating modePower-on Power-down time

DDX

(1)

Invalid supply area V

DDX

< V

+ 300 mV

DDX

independent from V

Figure 3. Power-up/down sequence

1. V

refers to any power supply among V

DDX

3.9.2 Power supply supervisor

The device has an integrated ultra-low-power brown-out reset (BOR) active in all modes except Shutdown and ensuring proper operation after power-on and during power down. The device remains in reset mode when the monitored supply voltage V specified threshold, without the need for an external reset circuit.

The lowest BOR level is 1.71V at power on, and other higher thresholds can be selected through option bytes.The device features an embedded programmable voltage detector (PVD) that monitors the V interrupt can be generated when V higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

In addition, the device embeds a Peripheral Voltage Monitor which compares the independent supply voltages V that the peripheral is in its functional supply range.

power supply and compares it to the VPVD threshold. An

DDA

, V

DDA

drops below the VPVD threshold and/or when VDD is

, V

DDUSB

, V

LCD

is below a

DDIO2

with a fixed threshold in order to ensure

DDIO2

DS10198 Rev 8 23/270

Page 24

Functional overview STM32L476xx

3.9.3 Voltage regulator

Two embedded linear voltage regulators supply most of the digital circuitries: the main regulator (MR) and the low-power regulator (LPR).

• The MR is used in the Run and Sleep modes and in the Stop 0 mode.

• The LPR is used in Low-Power Run, Low-Power Sleep, Stop 1 and Stop 2 modes. It is

also used to supply the 32 Kbyte SRAM2 in Standby with SRAM2 retention.

• Both regulators are in power-down in Standby and Shutdown modes: the regulator output is in high impedance, and the kernel circuitry is powered down thus inducing zero consumption.

The ultralow-power STM32L476xx supports dynamic voltage scaling to optimize its power consumption in run mode. The voltage from the Main Regulator that supplies the logic (V

There are two power consumption ranges:

• Range 1 with the CPU running at up to 80 MHz.

• Range 2 with a maximum CPU frequency of 26 MHz. All peripheral clocks are also

) can be adjusted according to the system’s maximum operating frequency.

CORE

limited to 26 MHz.

The V

can be supplied by the low-power regulator, the main regulator being switched

CORE

off. The system is then in Low-power run mode.

• Low-power run mode with the CPU running at up to 2 MHz. Peripherals with independent clock can be clocked by HSI16.

When the MR is in use, the STM32L476xx with the external SMPS option allows to force an external V

When V

DD12

supply on the VDD12 supply pins.

CORE

is forced by an external source and is higher than the output of the internal LDO, the current is taken from this external supply and the overall power efficiency is significantly improved if using an external step down DC/DC converter.

3.9.4 Low-power modes

The ultra-low-power STM32L476xx supports seven low-power modes to achieve the best compromise between low-power consumption, short startup time, available peripherals and available wakeup sources.

24/270 DS10198 Rev 8

Page 25

STM32L476xx Functional overview

Table 4. STM32L476xx modes overview

DS10198 Rev 8 25/270

Mode

Regulator

(1)

CPU Flash SRAM Clocks DMA & Peripherals

range 1

SMPS

range 2

High

Run

Yes ON

range2

SMPS

range 2

Low

LPRun LPR Yes ON

MR range

SMPS

range 2

High

Sleep

No ON

range2

SMPS

range 2

Low

LPSleep LPR No ON

(4)

ON Any

(7)

except

Any

PLL

Any

PLL

(2)

Wakeup source Consumption

112 µA/MHz

All

40 µA/MHz

N/A

100 µA/MHz

All except OTG_FS, RNG

39 µA/MHz

All except OTG_FS, RNG N/A 136 µA/MHz

37 µA/MHz

All

13 µA/MHz

Any interrupt or

event

35 µA/MHz

All except OTG_FS, RNG

15 µA/MHz

All except OTG_FS, RNG

Any interrupt or

event

40 µA/MHz 6 cycles

(3)

(5)

(6)

to Range 1: 4 µs

to Range 2: 64 µs

(5)

(6)

Wakeup time

N/A

6 cycles

Page 26

26/270 DS10198 Rev 8

Table 4. STM32L476xx modes overview (continued)

Functional overview STM32L476xx

Mode

Stop 0

Regulator

(1)

Range 1

Range 2

CPU Flash SRAM Clocks DMA & Peripherals

(8)

No Off ON

(8)

Stop 1 LPR No Off ON

LSE

LSI

LSE

LSI

(2)

BOR, PVD, PVM

RTC, LCD, IWDG

COMPx (x=1,2)

DAC1

OPAMPx (x=1,2)

USARTx (x=1...5)

LPUART1

I2Cx (x=1...3)

(9)

(10)

LPTIMx (x=1,2)

***

All other peripherals are

frozen.

BOR, PVD, PVM

RTC, LCD, IWDG

COMPx (x=1,2)

DAC1

OPAMPx (x=1,2)

USARTx (x=1...5)

LPUART1

I2Cx (x=1...3)

(9)

(10)

LPTIMx (x=1,2)

***

All other peripherals are

frozen.

Wakeup source Consumption

Reset pin, all I/Os

BOR, PVD, PVM

RTC, LCD, IWDG

COMPx (x=1..2)

USARTx (x=1...5)

LPUART1

I2Cx (x=1...3)

(9)

108 µA

(10)

LPTIMx (x=1,2)

OTG_FS SWPMI1

(11)

(12)

Reset pin, all I/Os

BOR, PVD, PVM

RTC, LCD, IWDG

COMPx (x=1..2)

(9)

USARTx (x=1...5)

LPUART1

I2Cx (x=1...3)

(9)

(10)

6.6 µA w/o RTC

6.9 µA w RTC

LPTIMx (x=1,2)

OTG_FS SWPMI1

(11)

(12)

(3)

0.7 µs in SRAM

4.5 µs in Flash

Wakeup time

4 µs in SRAM

6 µs in Flash

Page 27

Table 4. STM32L476xx modes overview (continued)

STM32L476xx Functional overview

DS10198 Rev 8 27/270

Mode

Regulator

(1)

CPU Flash SRAM Clocks DMA & Peripherals

Stop 2 LPR No Off ON

LPR

Standby

OFF

Shutdown OFF

Powered

Off

Powered

Off

Powered

SRAM2

Off

LSE

LSI

LSE

LSI

LSE

(2)

BOR, PVD, PVM

RTC, LCD, IWDG

COMPx (x=1..2)

(10)

I2C3

LPUART1

(9)

LPTIM1

***

All other peripherals are

frozen.

BOR, RTC, IWDG

***

All other peripherals are

powered off.

***

I/O configuration can be

floating, pull-up or pull-down

RTC

***

All other peripherals are

powered off.

***

I/O configuration can be

floating, pull-up or pull-

down

(14)

Wakeup source Consumption

Reset pin, all I/Os

BOR, PVD, PVM

RTC, LCD, IWDG

COMPx (x=1..2)

(10)

I2C3

LPUART1

(9)

1.1 µA w/o RTC

1.4 µA w/RTC

LPTIM1

0.35 µA w/o RTC

0.65 µA w/ RTC

Reset pin

5 I/Os (WKUPx)

BOR, RTC, IWDG

(13)

0.12 µA w/o RTC

0.42 µA w/ RTC

Reset pin

5 I/Os (WKUPx)

RTC

0.03 µA w/o RTC

(13)

0.33 µA w/ RTC

(3)

Wakeup time

5 µs in SRAM

7 µs in Flash

14 µs

256 µs

1. LPR means Main regulator is OFF and Low-power regulator is ON.

2. All peripherals can be active or clock gated to save power consumption.

3. Typical current at V LPRun/LPSleep.

4. The Flash memory can be put in power-down and its clock can be gated off when executing from SRAM.

5. Theoretical value based on V

6. Theoretical value based on V

7. The SRAM1 and SRAM2 clocks can be gated on or off independently.

= 1.8 V, 25°C. Consumptions values provided running from SRAM, Flash memory Off, 80 MHz in Range 1, 26 MHz in Range 2, 2 MHz in

= 3.3 V, DC/DC Efficiency of 85%, V

CORE

= 1.10 V

= 1.05 V

Page 28

28/270 DS10198 Rev 8

8. SMPS mode can be used in STOP0 Mode, but no significant power gain can be expected.

9. U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event.

10. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.

11. OTG_FS wakeup by resume from suspend and attach detection protocol event.

12. SWPMI1 wakeup by resume from suspend.

13. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5.

14. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode.

Functional overview STM32L476xx

Page 29

STM32L476xx Functional overview

By default, the microcontroller is in Run mode after a system or a power Reset. It is up to the user to select one of the low-power modes described below:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

• Low-power run mode

This mode is achieved with V

supplied by the low-power regulator to minimize the

CORE

regulator's operating current. The code can be executed from SRAM or from Flash, and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can be clocked by HSI16.

• Low-power sleep mode

This mode is entered from the low-power run mode. Only the CPU clock is stopped. When wakeup is triggered by an event or an interrupt, the system reverts to the lowpower run mode.

• Stop 0, Stop 1 and Stop 2 modes

Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the V

domain are stopped, the PLL, the MSI

CORE

RC, the HSI16 RC and the HSE crystal oscillators are disabled. The LSE or LSI is still running.

The RTC can remain active (Stop mode with RTC, Stop mode without RTC).

Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode to detect their wakeup condition.

Three Stop modes are available: Stop 0, Stop 1 and Stop 2 modes. In Stop 2 mode, most of the V

domain is put in a lower leakage mode.

CORE

Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator remains ON, allowing a very fast wakeup time but with much higher consumption.

The system clock when exiting from Stop 0, Stop 1 or Stop 2 modes can be either MSI up to 48 MHz or HSI16, depending on software configuration.

• Standby mode

The Standby mode is used to achieve the lowest power consumption with BOR. The internal regulator is switched off so that the V

domain is powered off. The PLL, the

CORE

MSI RC, the HSI16 RC and the HSE crystal oscillators are also switched off.

The RTC can remain active (Standby mode with RTC, Standby mode without RTC).

The brown-out reset (BOR) always remains active in Standby mode.

The state of each I/O during standby mode can be selected by software: I/O with internal pull-up, internal pull-down or floating.

After entering Standby mode, SRAM1 and register contents are lost except for registers in the Backup domain and Standby circuitry. Optionally, SRAM2 can be retained in Standby mode, supplied by the low-power Regulator (Standby with SRAM2 retention mode).

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE).

The system clock after wakeup is MSI up to 8 MHz.

DS10198 Rev 8 29/270

Page 30

Functional overview STM32L476xx

• Shutdown mode

The Shutdown mode allows to achieve the lowest power consumption. The internal regulator is switched off so that the V

domain is powered off. The PLL, the HSI16,

CORE

the MSI, the LSI and the HSE oscillators are also switched off.

The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).

The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode, therefore the switch to Backup domain is not supported.

SRAM1, SRAM2 and register contents are lost except for registers in the Backup domain.

The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic wakeup, timestamp, tamper).

The system clock after wakeup is MSI at 4 MHz.

30/270 DS10198 Rev 8

Page 31

STM32L476xx Functional overview

Table 5. Functionalities depending on the working mode

(1)

Stop 0/1 Stop 2 Standby Shutdown

Peripheral Run Sleep

Low-

power

run

Low-

power

sleep

VBAT

Wakeup capability

CPU Y - Y - - --------

Flash memory (up to 1 MB)

SRAM1 (up to 96 KB)

SRAM2 (32 KB) Y Y

FSMC OOOO-

Quad SPI O O O O -

Backup Registers Y Y Y Y Y

Brown-out reset (BOR)

(2)

(3)

(2)

(3)

- --------

Y -Y------

Y -Y-O

YYYYY

(4)

----

--------

-Y-Y-Y-Y

YYYYY- --

Programmable Voltage Detector

OOOOOOOO- ----

(PVD)

Peripheral Voltage Monitor (PVMx;

OOOOO

OOO- ----

x=1,2,3,4)

DMA OOOO-

High Speed Internal (HSI16)

High Speed External (HSE)

OOOO

OOOO-

--------

(5)

------

--------

Low Speed Internal (LSI)

Low Speed External (LSE)

Multi-Speed Internal (MSI)

Clock Security System (CSS)

Clock Security System on LSE

OOOOO

OOOO-

OOOOO

-O-O----

-O-O-O-O

--------

OOOOO- --

RTC / Auto wakeup O O O O O OOOOOOOO

Number of RTC Tamper pins

33333

O3O3O3O3

DS10198 Rev 8 31/270

Page 32

Functional overview STM32L476xx

Table 5. Functionalities depending on the working mode

(1)

(continued)

Stop 0/1 Stop 2 Standby Shutdown

Peripheral Run Sleep

Low-

power

run

Low-

power

sleep

VBAT

Wakeup capability

LCD OOOOOOOO- ----

USB OTG FS O

USARTx (x=1,2,3,4,5)

Low-power UART (LPUART)

(8)

OOOOO

I2Cx (x=1,2) O O O O O

I2C3 OOOOO

SPIx (x=1,2,3) O O O O -

CAN OOOO-

SDMMC1 O O O O -

(8)

---O- ------

(6)O(6)

(6)O(6)O(6)O(6)

(7)O(7)

(7)O(7)O(7)O(7)

- ------

- ----

- ------

- ----

--------

SWPMI1 OOOO-

SAIx (x=1,2) O O O O -

DFSDM1 OOOO-

ADCx (x=1,2,3) O O O O -

DAC1 O O O O O

VREFBUF O O O O O

OPAMPx (x=1,2) O O O O O

COMPx (x=1,2) O O O O O

Temperature sensor O O O O -

Timers (TIMx) O O O O -

Low-power timer 1 (LPTIM1)

Low-power timer 2 (LPTIM2)

Independent watchdog (IWDG)

Window watchdog (WWDG)

OOOOOOOO- ----

OOOOO

OOOO-

O- ------

--------

OOO- ----

--------

O- ------

OOOOO- --

--------

SysTick timer O O O O - --------

Touch sensing controller (TSC)

OOOO---------

32/270 DS10198 Rev 8

Page 33

STM32L476xx Functional overview

Table 5. Functionalities depending on the working mode

(1)

(continued)

Stop 0/1 Stop 2 Standby Shutdown

Peripheral Run Sleep

Random number generator (RNG)

(8)

Low-

power

run

(8)

Low-

power

sleep

Wakeup capability

VBAT

Wakeup capability

-----------

CRC calculation unit O O O O - --------

GPIOs OOOOO

1. Legend: Y = Yes (Enable). O = Optional (Disable by default. Can be enabled by software). - = Not available.

2. The Flash can be configured in power-down mode. By default, it is not in power-down mode.

3. The SRAM clock can be gated on or off.

4. SRAM2 content is preserved when the bit RRS is set in PWR_CR3 register.

5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not need it anymore.

6. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event.

7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.

8. Voltage scaling Range 1 only.

9. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.

10. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5.

11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode.

OOO

(9)

pins

(10)

(11)

pins

(10)

3.9.5 Reset mode

In order to improve the consumption under reset, the I/Os state under and after reset is “analog state” (the I/O schmitt trigger is disable). In addition, the internal reset pull-up is deactivated when the reset source is internal.

3.9.6 VBAT operation

The VBAT pin allows to power the device VBAT domain from an external battery, an external supercapacitor, or from V present. The VBAT pin supplies the RTC with LSE and the backup registers. Three antitamper detection pins are available in VBAT mode.

VBAT operation is automatically activated when VDD is not present.

An internal VBAT battery charging circuit is embedded and can be activated when VDD is present.

Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events

do not exit it from VBAT operation.

when no external battery and an external supercapacitor are

DS10198 Rev 8 33/270

Page 34

Functional overview STM32L476xx

3.10 Interconnect matrix

Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections allow fast and predictable latency.

Depending on peripherals, these interconnections can operate in Run, Sleep, low-power run and sleep, Stop 0, Stop 1 and Stop 2 modes.

Table 6. STM32L476xx peripherals interconnect matrix

Interconnect source

TIMx

TIM16/TIM17 IRTIM Infrared interface output generation Y Y Y Y - -

COMPx

ADCx TIM1, 8 Timer triggered by analog watchdog Y Y Y Y - -

RTC

Interconnect

destination

TIMx Timers synchronization or chaining Y Y Y Y - -

ADCx DAC1 DFSDM1

DMA Memory to memory transfer trigger Y Y Y Y - -

COMPx Comparator output blanking Y Y Y Y - -

TIM1, 8 TIM2, 3

LPTIMERx

TIM16 Timer input channel from RTC events Y Y Y Y - -

LPTIMERx

Conversion triggers Y Y Y Y - -

Timer input channel, trigger, break from analog signals comparison

Low-power timer triggered by analog signals comparison

Low-power timer triggered by RTC alarms or tampers

Interconnect action

Run

Sleep

Low-power sleep

Stop 0 / Stop 1

Low-power run

YYYY - -

YYYYY

Stop 2

(1)

All clocks sources (internal and external)

USB TIM2 Timer triggered by USB SOF Y Y - - - -

CSS CPU (hard fault) RAM (parity error) Flash memory (ECC error) COMPx PVD DFSDM1 (analog

watchdog, short circuit detection)

34/270 DS10198 Rev 8

TIM2 TIM15, 16, 17

TIM1,8 TIM15,16,17

Clock source used as input channel for RC measurement and trimming

Timer break Y Y Y Y - -

YYYY - -

Page 35

STM32L476xx Functional overview

Table 6. STM32L476xx peripherals interconnect matrix (continued)

Interconnect source

GPIO

1. LPTIM1 only.

Interconnect

destination

Interconnect action

Run

Sleep

Low-power run

Stop 0 / Stop 1

Low-power sleep

TIMx External trigger Y Y Y Y - -

LPTIMERx External trigger Y Y Y Y Y

ADCx DAC1

Conversion external trigger Y Y Y Y - -

DFSDM1

Stop 2

(1)

DS10198 Rev 8 35/270

Page 36

Functional overview STM32L476xx

3.11 Clocks and startup

The clock controller (see Figure 4) distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. It features:

• Clock prescaler: to get the best trade-off between speed and current consumption,

the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler

• Safe clock switching: clock sources can be changed safely on the fly in run mode

through a configuration register.

• Clock management: to reduce power consumption, the clock controller can stop the

clock to the core, individual peripherals or memory.

• System clock source: four different clock sources can be used to drive the master

clock SYSCLK:

– 4-48 MHz high-speed external crystal or ceramic resonator (HSE), that can supply

a PLL. The HSE can also be configured in bypass mode for an external clock.

– 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software, that can

supply a PLL

– Multispeed internal RC oscillator (MSI), trimmable by software, able to generate

12 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is available in the system (LSE), the MSI frequency can be automatically trimmed by hardware to reach better than ±0.25% accuracy. In this mode the MSI can feed the USB device, saving the need of an external high-speed crystal (HSE). The MSI can supply a PLL.

– System PLL which can be fed by HSE, HSI16 or MSI, with a maximum frequency

at 80 MHz.

• Auxiliary clock source: two ultralow-power clock sources that can be used to drive

the LCD controller and the real-time clock:

– 32.768 kHz low-speed external crystal (LSE), supporting four drive capability

modes. The LSE can also be configured in bypass mode for an external clock.

– 32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.

The LSI clock accuracy is ±5% accuracy.

• Peripheral clock sources: Several peripherals (USB, SDMMC, RNG, SAI, USARTs,

I2Cs, LPTimers, ADC, SWPMI) have their own independent clock whatever the system clock. Three PLLs, each having three independent outputs allowing the highest flexibility, can generate independent clocks for the ADC, the USB/SDMMC/RNG and the two SAIs.

• Startup clock: after reset, the microcontroller restarts by default with an internal 4 MHz

clock (MSI). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts.

• Clock security system (CSS): this feature can be enabled by software. If a HSE clock

failure occurs, the master clock is automatically switched to HSI16 and a software

36/270 DS10198 Rev 8

Page 37

STM32L476xx Functional overview

interrupt is generated if enabled. LSE failure can also be detected and generated an interrupt.

• Clock-out capability:

– MCO: microcontroller clock output: it outputs one of the internal clocks for

external use by the application. Low frequency clocks (LSI, LSE) are available down to Stop 1 low power state.

– LSCO: low speed clock output: it outputs LSI or LSE in all low-power modes

down to Standby mode. LSE can also be output on LSCO in Shutdown mode. LSCO is not available in VBAT mode.

Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 80 MHz.

DS10198 Rev 8 37/270

Page 38

Functional overview STM32L476xx

PLLCLK

MS32440V3

SYSCLK

MCO

LSCO

SAI2_EXTCLK

48 MHz clock to USB, RNG, SDMMC

to ADC

to IWDG

to RTC and LCD

to PWR

HCLK

to AHB bus, core, memory and DMA

FCLK Cortex free running clock

to Cortex system timer

to APB1 peripherals

to APB2 peripherals

PCLK1

PCLK2

to SAI1

to SAI2

LSE

HSI16

SYSCLK

to USARTx

x=2..5

to LPUART1

to I2Cx

x=1,2,3

to LPTIMx

x=1,2

SAI1_EXTCLK

to SWPMI

to TIMx

x=2..7

OSC32_OUT

OSC32_IN

MSI

HSI16

HSE

HSI16

LSI

LSE

HSE

SYSCLK

HSE

MSI

HSI16

MSI

SYSCLK

LSE OSC

32.768 kHz

/32

AHB

PRESC

/ 1,2,..512

/ 8

APB1

PRESC

/ 1,2,4,8,16

x1 or x2

HSI16

SYSCLK

LSI

LSE

HSI16

APB2

PRESC

/ 1,2,4,8,16

to TIMx

x=1,8,15,16,17

x1 or x2

USART1

LSE

HSI16

SYSCLK

/ M

MSI RC

100 kHz – 48 MHz

HSI RC 16 MHz

HSE OSC 4-48 MHz

Clock

detector

OSC_OUT

OSC_IN

/ 1→16

LSI RC 32 kHz

Clock source control

PLLSAI3CLK

PLL48M1CLK

PLLCLK

PLLSAI1CLK

PLL48M2CLK

PLLADC1CLK

PLLSAI2CLK

PLLADC2CLK

MSI

PLLSAI1

VCO

/ P

/ R

/ Q

PLLSAI2

VCO

/ P

/ R

/ Q

PLL

VCO

/ P

/ R

/ Q

Figure 4. Clock tree

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STM32L476xx Functional overview

3.12 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be achieved thanks to their mapping on the AHB2 bus.

The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.

3.13 Direct memory access controller (DMA)

The device embeds 2 DMAs. Refer to Tab le 7: DMA implementation for the features implementation.

Direct memory access (DMA) is used in order to provide high-speed data transfer between peripherals and memory as well as memory to memory. Data can be quickly moved by DMA without any CPU actions. This keeps CPU resources free for other operations.

The two DMA controllers have 14 channels in total, each dedicated to managing memory access requests from one or more peripherals. Each has an arbiter for handling the priority between DMA requests.

The DMA supports:

• 14 independently configurable channels (requests)

• Each channel is connected to dedicated hardware DMA requests, software trigger is

also supported on each channel. This configuration is done by software.

• Priorities between requests from channels of one DMA are software programmable (4 levels consisting of very high, high, medium, low) or hardware in case of equality (request 1 has priority over request 2, etc.)

• Independent source and destination transfer size (byte, half word, word), emulating packing and unpacking. Source/destination addresses must be aligned on the data size.

• Support for circular buffer management

• 3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error)

logically ORed together in a single interrupt request for each channel

• Memory-to-memory transfer

• Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral

transfers

• Access to Flash, SRAM, APB and AHB peripherals as source and destination

• Programmable number of data to be transferred: up to 65536.

DMA features DMA1 DMA2

Table 7. DMA implementation

Number of regular channels 7 7

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3.14 Interrupts and events

3.14.1 Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 81 maskable interrupt channels plus the 16 interrupt lines of the Cortex M4.

The NVIC benefits are the following:

• Closely coupled NVIC gives low latency interrupt processing

• Interrupt entry vector table address passed directly to the core

• Allows early processing of interrupts

• Processing of late arriving higher priority interrupts

• Support for tail chaining

• Processor state automatically saved on interrupt entry, and restored on interrupt exit,

with no instruction overhead

The NVIC hardware block provides flexible interrupt management features with minimal interrupt latency.

3.14.2 Extended interrupt/event controller (EXTI)

The extended interrupt/event controller consists of 40 edge detector lines used to generate interrupt/event requests and wake-up the system from Stop mode. Each external line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The internal lines are connected to peripherals with wakeup from Stop mode capability. The EXTI can detect an external line with a pulse width shorter than the internal clock period. Up to 114 GPIOs can be connected to the 16 external interrupt lines.

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STM32L476xx Functional overview

3.15 Analog to digital converter (ADC)

The device embeds 3 successive approximation analog-to-digital converters with the following features:

• 12-bit native resolution, with built-in calibration

• 5.33 Msps maximum conversion rate with full resolution

– Down to 18.75 ns sampling time

– Increased conversion rate for lower resolution (up to 8.88 Msps for 6-bit

resolution)

• Up to 24 external channels, some of them shared between ADC1 and ADC2, or ADC1, ADC2 and ADC3.

• 5 internal channels: internal reference voltage, temperature sensor, VBAT/3, DAC1_OUT1 and DAC1_OUT2.

• One external reference pin is available on some package, allowing the input voltage range to be independent from the power supply

• Single-ended and differential mode inputs

• Low-power design

– Capable of low-current operation at low conversion rate (consumption decreases

linearly with speed)

– Dual clock domain architecture: ADC speed independent from CPU frequency

• Highly versatile digital interface

– Single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups

of analog signals conversions can be programmed to differentiate background and high-priority real-time conversions

– Handles two ADC converters for dual mode operation (simultaneous or

interleaved sampling modes)

– Each ADC support multiple trigger inputs for synchronization with on-chip timers

and external signals

– Results stored into 3 data register or in RAM with DMA controller support

– Data pre-processing: left/right alignment and per channel offset compensation

– Built-in oversampling unit for enhanced SNR

– Channel-wise programmable sampling time

– Three analog watchdog for automatic voltage monitoring, generating interrupts

and trigger for selected timers

– Hardware assistant to prepare the context of the injected channels to allow fast

context switching

3.15.1 Temperature sensor

The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature.

The temperature sensor is internally connected to the ADC1_IN17 and ADC3_IN17 input channels which is used to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only.

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Functional overview STM32L476xx

To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode.

Calibration value name Description Memory address

TS_CAL1

TS_CAL2

Table 8. Temperature sensor calibration values

TS ADC raw data acquired at a temperature of 30 °C (± 5 °C), V

= V

DDA

TS ADC raw data acquired at a temperature of 110 °C (± 5 °C), V

= V

DDA

= 3.0 V (± 10 mV)

REF+

= 3.0 V (± 10 mV)

REF+

0x1FFF 75A8 - 0x1FFF 75A9

0x1FFF 75CA - 0x1FFF 75CB

3.15.2 Internal voltage reference (V

The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC and Comparators. VREFINT is internally connected to the ADC1_IN0 input channel. The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode.

3.15.3 V

This embedded hardware feature allows the application to measure the V using the internal ADC channel ADC1_IN18 or ADC3_IN18. As the V higher than V connected to a bridge divider by 3. As a consequence, the converted digital value is one third the V

Calibration value name Description Memory address

battery voltage monitoring

BAT

Table 9. Internal voltage reference calibration values

Raw data acquired at a

VREFINT

, and thus outside the ADC input range, the VBAT pin is internally

DDA

temperature of 30 °C (± 5 °C), V

DDA

voltage.

REFINT

= V

REF+

)

= 3.0 V (± 10 mV)

0x1FFF 75AA - 0x1FFF 75AB

battery voltage

BAT

voltage may be

BAT

3.16 Digital to analog converter (DAC)

Two 12-bit buffered DAC channels can be used to convert digital signals into analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration.

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STM32L476xx Functional overview

MSv40197V1

VREFBUF

Low frequency cut-off capacitor

DAC, ADC

Bandgap +

DDA

100 nF

VREF+

This digital interface supports the following features:

• Up to two DAC output channels

• 8-bit or 12-bit output mode

• Buffer offset calibration (factory and user trimming)

• Left or right data alignment in 12-bit mode

• Synchronized update capability

• Noise-wave generation

• Triangular-wave generation

• Dual DAC channel independent or simultaneous conversions

• DMA capability for each channel

• External triggers for conversion

• Sample and hold low-power mode, with internal or external capacitor

The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels.

3.17 Voltage reference buffer (VREFBUF)

The STM32L476xx devices embed an voltage reference buffer which can be used as voltage reference for ADCs, DAC and also as voltage reference for external components through the VREF+ pin.

The internal voltage reference buffer supports two voltages:

• 2.048 V

• 2.5 V

An external voltage reference can be provided through the VREF+ pin when the internal voltage reference buffer is off.

The VREF+ pin is double-bonded with VDDA on some packages. In these packages the internal voltage reference buffer is not available.

Figure 5. Voltage reference buffer

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Functional overview STM32L476xx

3.18 Comparators (COMP)

The STM32L476xx devices embed two rail-to-rail comparators with programmable reference voltage (internal or external), hysteresis and speed (low speed for low-power) and with selectable output polarity.

The reference voltage can be one of the following:

• External I/O

• DAC output channels

• Internal reference voltage or submultiple (1/4, 1/2, 3/4).

All comparators can wake up from Stop mode, generate interrupts and breaks for the timers and can be also combined into a window comparator.

3.19 Operational amplifier (OPAMP)

The STM32L476xx embeds two operational amplifiers with external or internal follower routing and PGA capability.

The operational amplifier features:

• Low input bias current

• Low offset voltage

• Low-power mode

• Rail-to-rail input

3.20 Touch sensing controller (TSC)

The touch sensing controller provides a simple solution for adding capacitive sensing functionality to any application. Capacitive sensing technology is able to detect finger presence near an electrode which is protected from direct touch by a dielectric (glass, plastic, ...). The capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle.

The touch sensing controller is fully supported by the STMTouch touch sensing firmware library which is free to use and allows touch sensing functionality to be implemented reliably in the end application.

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STM32L476xx Functional overview

The main features of the touch sensing controller are the following:

• Proven and robust surface charge transfer acquisition principle

• Supports up to 24 capacitive sensing channels

• Up to 3 capacitive sensing channels can be acquired in parallel offering a very good

response time

• Spread spectrum feature to improve system robustness in noisy environments

• Full hardware management of the charge transfer acquisition sequence

• Programmable charge transfer frequency

• Programmable sampling capacitor I/O pin

• Programmable channel I/O pin

• Programmable max count value to avoid long acquisition when a channel is faulty

• Dedicated end of acquisition and max count error flags with interrupt capability

• One sampling capacitor for up to 3 capacitive sensing channels to reduce the system

components

• Compatible with proximity, touchkey, linear and rotary touch sensor implementation

• Designed to operate with STMTouch touch sensing firmware library

Note: The number of capacitive sensing channels is dependent on the size of the packages and

subject to I/O availability.

3.21 Liquid crystal display controller (LCD)

The LCD drives up to 8 common terminals and 44 segment terminals to drive up to 320 pixels.

• Internal step-up converter to guarantee functionality and contrast control irrespective of V

. This converter can be deactivated, in which case the VLCD pin is used to provide

the voltage to the LCD

• Supports static, 1/2, 1/3, 1/4 and 1/8 duty

• Supports static, 1/2, 1/3 and 1/4 bias

• Phase inversion to reduce power consumption and EMI

• Integrated voltage output buffers for higher LCD driving capability

• Up to 8 pixels can be programmed to blink

• Unneeded segments and common pins can be used as general I/O pins

• LCD RAM can be updated at any time owing to a double-buffer

• The LCD controller can operate in Stop mode

3.22 Digital filter for Sigma-Delta Modulators (DFSDM)

The device embeds one DFSDM with 4 digital filters modules and 8 external input serial channels (transceivers) or alternately 8 internal parallel inputs support.

The DFSDM peripheral is dedicated to interface the external  modulators to microcontroller and then to perform digital filtering of the received data streams (which represent analog value on  modulators inputs). DFSDM can also interface PDM (Pulse Density Modulation) microphones and perform PDM to PCM conversion and filtering in

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Functional overview STM32L476xx

hardware. DFSDM features optional parallel data stream inputs from microcontrollers memory (through DMA/CPU transfers into DFSDM).

DFSDM transceivers support several serial interface formats (to support various  modulators). DFSDM digital filter modules perform digital processing according user selected filter parameters with up to 24-bit final ADC resolution.

The DFSDM peripheral supports:

• 8 multiplexed input digital serial channels:

– configurable SPI interface to connect various SD modulator(s)

– configurable Manchester coded 1 wire interface support

– PDM (Pulse Density Modulation) microphone input support

– maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)

– clock output for SD modulator(s): 0..20 MHz

• alternative inputs from 8 internal digital parallel channels (up to 16 bit input resolution):

– internal sources: device memory data streams (DMA)

• 4 digital filter modules with adjustable digital signal processing:

–Sinc

filter: filter order/type (1..5), oversampling ratio (up to 1..1024)

– integrator: oversampling ratio (1..256)

• up to 24-bit output data resolution, signed output data format

• automatic data offset correction (offset stored in register by user)

• continuous or single conversion

• start-of-conversion triggered by:

– software trigger

– internal timers

– external events

– start-of-conversion synchronously with first digital filter module (DFSDM1_FLT0)

• analog watchdog feature:

– low value and high value data threshold registers

– dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32)

– input from final output data or from selected input digital serial channels

– continuous monitoring independently from standard conversion

• short circuit detector to detect saturated analog input values (bottom and top range):

– up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on serial data stream

– monitoring continuously each input serial channel

• break signal generation on analog watchdog event or on short circuit detector event

• extremes detector:

– storage of minimum and maximum values of final conversion data

– refreshed by software

• DMA capability to read the final conversion data

• interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial

channel clock absence

• “regular” or “injected” conversions:

– “regular” conversions can be requested at any time or even in continuous mode

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STM32L476xx Functional overview

without having any impact on the timing of “injected” conversions

– “injected” conversions for precise timing and with high conversion priority

DFSDM features DFSDM1

Number of channels 8

Number of filters 4

Input from internal ADC -

Supported trigger sources 10

Pulses skipper -

ID registers support -

Table 10. DFSDM1 implementation

3.23 Random number generator (RNG)

All devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit.

3.24 Timers and watchdogs

The STM32L476xx includes two advanced control timers, up to nine general-purpose timers, two basic timers, two low-power timers, two watchdog timers and a SysTick timer. The table below compares the features of the advanced control, general purpose and basic timers.

Timer type Timer

Advanced

control

General-

purpose

General-

purpose

General-

purpose

TIM1, TIM8 16-bit

TIM2, TIM5 32-bit

TIM3, TIM4 16-bit

TIM15 16-bit Up

Table 11. Timer feature comparison

Counter

resolution

Counter

type

Up, down,

Up/down

Up, down,

Up/down

Up, down,

Up/down

Prescaler

factor

Any integer

between 1 and 65536

Any integer

between 1 and 65536

Any integer

between 1 and 65536

Any integer

between 1 and 65536

DMA

request

generation

Yes 4 3

Yes 4 No

Yes 2 1

Capture/ compare

channels

Complementary

outputs

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Functional overview STM32L476xx

Table 11. Timer feature comparison (continued)

Timer type Timer

General-

purpose

Basic TIM6, TIM7 16-bit Up

TIM16, TIM17 16-bit Up

Counter

resolution

Counter

type

Prescaler

factor

Any integer

between 1 and 65536

Any integer

between 1 and 65536

3.24.1 Advanced-control timer (TIM1, TIM8)

The advanced-control timer can each be seen as a three-phase PWM multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted deadtimes. They can also be seen as complete general-purpose timers. The 4 independent channels can be used for:

• Input capture

• Output compare

• PWM generation (edge or center-aligned modes) with full modulation capability (0-

100%)

• One-pulse mode output

In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled to turn off any power switches driven by these outputs.

DMA

request

generation

Yes 1 1

Yes 0 No

Capture/ compare

channels

Complementary

outputs

Many features are shared with those of the general-purpose TIMx timers (described in

Section 3.24.2) using the same architecture, so the advanced-control timers can work

together with the TIMx timers via the Timer Link feature for synchronization or event chaining.

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3.24.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16, TIM17)

There are up to seven synchronizable general-purpose timers embedded in the STM32L476xx (see generate PWM outputs, or act as a simple time base.

• TIM2, TIM3, TIM4 and TIM5

They are full-featured general-purpose timers:

– TIM2 and TIM5 have a 32-bit auto-reload up/downcounter and 32-bit prescaler

– TIM3 and TIM4 have 16-bit auto-reload up/downcounter and 16-bit prescaler.

These timers feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. They can work together, or with the other general-purpose timers via the Timer Link feature for synchronization or event chaining.

The counters can be frozen in debug mode.

All have independent DMA request generation and support quadrature encoders.

• TIM15, 16 and 17

They are general-purpose timers with mid-range features:

They have 16-bit auto-reload upcounters and 16-bit prescalers.

– TIM15 has 2 channels and 1 complementary channel

– TIM16 and TIM17 have 1 channel and 1 complementary channel

All channels can be used for input capture/output compare, PWM or one-pulse mode output.

The timers can work together via the Timer Link feature for synchronization or event chaining. The timers have independent DMA request generation.

The counters can be frozen in debug mode.

Tabl e 11 for differences). Each general-purpose timer can be used to

3.24.3 Basic timers (TIM6 and TIM7)

The basic timers are mainly used for DAC trigger generation. They can also be used as generic 16-bit timebases.

3.24.4 Low-power timer (LPTIM1 and LPTIM2)

The devices embed two low-power timers. These timers have an independent clock and are running in Stop mode if they are clocked by LSE, LSI or an external clock. They are able to wakeup the system from Stop mode.

LPTIM1 is active in Stop 0, Stop 1 and Stop 2 modes.

LPTIM2 is active in Stop 0 and Stop 1 mode.

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Functional overview STM32L476xx

This low-power timer supports the following features:

• 16-bit up counter with 16-bit autoreload register

• 16-bit compare register

• Configurable output: pulse, PWM

• Continuous/ one shot mode

• Selectable software/hardware input trigger

• Selectable clock source

– Internal clock sources: LSE, LSI, HSI16 or APB clock

– External clock source over LPTIM input (working even with no internal clock

source running, used by pulse counter application).

• Programmable digital glitch filter

• Encoder mode (LPTIM1 only)

3.24.5 Infrared interface (IRTIM)

The STM32L476xx includes one infrared interface (IRTIM). It can be used with an infrared LED to perform remote control functions. It uses TIM16 and TIM17 output channels to generate output signal waveforms on IR_OUT pin.

3.24.6 Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.

kHz internal RC (LSI) and as it operates independently

3.24.7 System window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

3.24.8 SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features:

• A 24-bit down counter

• Autoreload capability

• Maskable system interrupt generation when the counter reaches 0.

• Programmable clock source

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3.25 Real-time clock (RTC) and backup registers

The RTC is an independent BCD timer/counter. It supports the following features:

• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,

month, year, in BCD (binary-coded decimal) format.

• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.

• Two programmable alarms.

• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to

synchronize it with a master clock.

• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be

used to enhance the calendar precision.

• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal

inaccuracy.

• Three anti-tamper detection pins with programmable filter.

• Timestamp feature which can be used to save the calendar content. This function can

be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to VBAT mode.

• 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable

resolution and period.

The RTC and the 32 backup registers are supplied through a switch that takes power either from the V

supply when present or from the VBAT pin.

The backup registers are 32-bit registers used to store 128 bytes of user application data when V

power is not present. They are not reset by a system or power reset, or when the

device wakes up from Standby or Shutdown mode.

The RTC clock sources can be:

• A 32.768 kHz external crystal (LSE)

• An external resonator or oscillator (LSE)

• The internal low power RC oscillator (LSI, with typical frequency of 32 kHz)

• The high-speed external clock (HSE) divided by 32.

The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in all low-power modes except Shutdown mode.

All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt and wakeup the device from the low-power modes.

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3.26 Inter-integrated circuit interface (I2C)

The device embeds three I2C. Refer to Table 12: I2C implementation for the features implementation.

The I2C bus interface handles communications between the microcontroller and the serial

C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.

The I2C peripheral supports:

• I2C-bus specification and user manual rev. 5 compatibility:

– Slave and master modes, multimaster capability

– Standard-mode (Sm), with a bitrate up to 100 kbit/s

– Fast-mode (Fm), with a bitrate up to 400 kbit/s

– Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os

– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses

– Programmable setup and hold times

– Optional clock stretching

• System Management Bus (SMBus) specification rev 2.0 compatibility:

– Hardware PEC (Packet Error Checking) generation and verification with ACK

control

– Address resolution protocol (ARP) support

– SMBus alert

• Power System Management Protocol (PMBus

• Independent clock: a choice of independent clock sources allowing the I2C

communication speed to be independent from the PCLK reprogramming. Refer to

Figure 4: Clock tree.

• Wakeup from Stop mode on address match

• Programmable analog and digital noise filters

• 1-byte buffer with DMA capability

I2C features

Table 12. I2C implementation

(1)

) specification rev 1.1 compatibility

I2C1 I2C2 I2C3

Standard-mode (up to 100 kbit/s) X X X

Fast-mode (up to 400 kbit/s) X X X

Fast-mode Plus with 20mA output drive I/Os (up to 1 Mbit/s) X X X

Programmable analog and digital noise filters X X X

SMBus/PMBus hardware support X X X

Independent clock X X X

Wakeup from Stop 0 / Stop 1 mode on address match X X X

Wakeup from Stop 2 mode on address match - - X

1. X: supported

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3.27 Universal synchronous/asynchronous receiver transmitter (USART)

The STM32L476xx devices have three embedded universal synchronous receiver transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver transmitters (UART4, UART5).

These interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. They provide hardware management of the CTS and RTS signals, and RS485 Driver Enable. They are able to communicate at speeds of up to 10Mbit/s.

USART1, USART2 and USART3 also provide Smart Card mode (ISO 7816 compliant) and SPI-like communication capability.

All USART have a clock domain independent from the CPU clock, allowing the USARTx (x=1,2,3,4,5) to wake up the MCU from Stop mode using baudrates up to 204 wake up events from Stop mode are programmable and can be:

• Start bit detection

• Any received data frame

• A specific programmed data frame

Kbaud. The

All USART interfaces can be served by the DMA controller.

USART modes/features

Hardware flow control for modem XXXXX X

Continuous communication using DMA XXXXX X

Multiprocessor communication XXXXX X

Synchronous mode X X X - - -

Smartcard mode X X X - - -

Single-wire half-duplex communication XXXXX X

IrDA SIR ENDEC block XXXXX -

LIN mode XXXXX -

Dual clock domain XXXXX X

Wakeup from Stop 0 / Stop 1 modes XXXXX X

Wakeup from Stop 2 mode ----- X

Receiver timeout interrupt XXXXX -

Modbus communication XXXXX -

Auto baud rate detection X (4 modes) -

Driver Enable XXXXX X

Table 13. STM32L476xx USART/UART/LPUART features

(1)

USART1 USART2 USART3 UART4 UART5 LPUART1

LPUART/USART data length 7, 8 and 9 bits

1. X = supported.

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3.28 Low-power universal asynchronous receiver transmitter (LPUART)

The device embeds one Low-Power UART. The LPUART supports asynchronous serial communication with minimum power consumption. It supports half duplex single wire communication and modem operations (CTS/RTS). It allows multiprocessor communication.

The LPUART has a clock domain independent from the CPU clock, and can wakeup the system from Stop mode using baudrates up to 220 mode are programmable and can be:

• Start bit detection

• Any received data frame

• A specific programmed data frame

Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while having an extremely low energy consumption. Higher speed clock can be used to reach higher baudrates.

LPUART interface can be served by the DMA controller.

Kbaud. The wake up events from Stop

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STM32L476xx Functional overview

3.29 Serial peripheral interface (SPI)

Three SPI interfaces allow communication up to 40 Mbits/s in master and up to 24 Mbits/s slave modes, in half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI interfaces support NSS pulse mode, TI mode and Hardware CRC calculation.

All SPI interfaces can be served by the DMA controller.

3.30 Serial audio interfaces (SAI)

The device embeds 2 SAI. Refer to Tab le 14: SAI implementation for the features implementation. The SAI bus interface handles communications between the microcontroller and the serial audio protocol.

The SAI peripheral supports:

• Two independent audio sub-blocks which can be transmitters or receivers with their

respective FIFO.

• 8-word integrated FIFOs for each audio sub-block.

• Synchronous or asynchronous mode between the audio sub-blocks.

• Master or slave configuration independent for both audio sub-blocks.

• Clock generator for each audio block to target independent audio frequency sampling

when both audio sub-blocks are configured in master mode.

• Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit.

• Peripheral with large configurability and flexibility allowing to target as example the

following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF out.

• Up to 16 slots available with configurable size and with the possibility to select which

ones are active in the audio frame.

• Number of bits by frame may be configurable.

• Frame synchronization active level configurable (offset, bit length, level).

• First active bit position in the slot is configurable.

• LSB first or MSB first for data transfer.

• Mute mode.

• Stereo/Mono audio frame capability.

• Communication clock strobing edge configurable (SCK).

• Error flags with associated interrupts if enabled respectively.

– Overrun and underrun detection.

– Anticipated frame synchronization signal detection in slave mode.

– Late frame synchronization signal detection in slave mode.

– Codec not ready for the AC’97 mode in reception.

• Interruption sources when enabled:

–Errors.

– FIFO requests.

• DMA interface with 2 dedicated channels to handle access to the dedicated integrated

FIFO of each SAI audio sub-block.

DS10198 Rev 8 55/270

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Functional overview STM32L476xx

SAI features

I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 X X

Mute mode X X

Stereo/Mono audio frame capability. X X

16 slots X X

Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit X X

FIFO Size X (8 Word) X (8 Word)

SPDIF X X

1. X: supported

Table 14. SAI implementation

(1)

SAI1 SAI2

3.31 Single wire protocol master interface (SWPMI)

The Single wire protocol master interface (SWPMI) is the master interface corresponding to the Contactless Frontend (CLF) defined in the ETSI TS 102 613 technical specification. The main features are:

• full-duplex communication mode

• automatic SWP bus state management (active, suspend, resume)

• configurable bitrate up to 2 Mbit/s

• automatic SOF, EOF and CRC handling

SWPMI can be served by the DMA controller.

3.32 Controller area network (CAN)

The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and 14 scalable filter banks.

56/270 DS10198 Rev 8

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STM32L476xx Functional overview

The CAN peripheral supports:

• Supports CAN protocol version 2.0 A, B Active

• Bit rates up to 1 Mbit/s

• Transmission

– Three transmit mailboxes

– Configurable transmit priority

• Reception

– Two receive FIFOs with three stages

– 14 Scalable filter banks

– Identifier list feature

– Configurable FIFO overrun

• Time-triggered communication option

– Disable automatic retransmission mode

– 16-bit free running timer

– Time Stamp sent in last two data bytes

• Management

– Maskable interrupts

– Software-efficient mailbox mapping at a unique address space

3.33 Secure digital input/output and MultiMediaCards Interface (SDMMC)

The card host interface (SDMMC) provides an interface between the APB peripheral bus and MultiMediaCards (MMCs), SD memory cards and SDIO cards.

The SDMMC features include the following:

• Full compliance with MultiMediaCard System Specification Version 4.2. Card support

for three different databus modes: 1-bit (default), 4-bit and 8-bit

• Full compatibility with previous versions of MultiMediaCards (forward compatibility)

• Full compliance with SD Memory Card Specifications Version 2.0

• Full compliance with SD I/O Card Specification Version 2.0: card support for two

different databus modes: 1-bit (default) and 4-bit

• Data transfer up to 48 MHz for the 8 bit mode

• Data write and read with DMA capability

3.34 Universal serial bus on-the-go full-speed (OTG_FS)

The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 2.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that can be provided by the internal multispeed oscillator (MSI) automatically trimmed by 32.768 kHz external oscillator (LSE).This allows to use the USB device without external high speed crystal (HSE).

DS10198 Rev 8 57/270

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Functional overview STM32L476xx

The major features are:

• Combined Rx and Tx FIFO size of 1.25 KB with dynamic FIFO sizing

• Supports the session request protocol (SRP) and host negotiation protocol (HNP)

• 1 bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints

• 12 host channels with periodic OUT support

• HNP/SNP/IP inside (no need for any external resistor)

• USB 2.0 LPM (Link Power Management) support

• Battery Charging Specification Revision 1.2 support

• Internal FS OTG PHY support

For OTG/Host modes, a power switch is needed in case bus-powered devices are connected.

3.35 Flexible static memory controller (FSMC)

The Flexible static memory controller (FSMC) includes two memory controllers:

• The NOR/PSRAM memory controller

• The NAND/memory controller

This memory controller is also named Flexible memory controller (FMC).

The main features of the FMC controller are the following:

• Interface with static-memory mapped devices including:

– Static random access memory (SRAM)

– NOR Flash memory/OneNAND Flash memory

– PSRAM (4 memory banks)

– NAND Flash memory with ECC hardware to check up to 8 Kbyte of data

• 8-,16- bit data bus width

• Independent Chip Select control for each memory bank

• Independent configuration for each memory bank

• Write FIFO

• The Maximum FMC_CLK frequency for synchronous accesses is HCLK/2.

LCD parallel interface

The FMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost effective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration.

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STM32L476xx Functional overview

3.36 Quad SPI memory interface (QUADSPI)

The Quad SPI is a specialized communication interface targeting single, dual or quad SPI flash memories. It can operate in any of the three following modes:

• Indirect mode: all the operations are performed using the QUADSPI registers

• Status polling mode: the external flash status register is periodically read and an

interrupt can be generated in case of flag setting

• Memory-mapped mode: the external Flash is memory mapped and is seen by the

system as if it were an internal memory

The Quad SPI interface supports:

• Three functional modes: indirect, status-polling, and memory-mapped

• SDR and DDR support

• Fully programmable opcode for both indirect and memory mapped mode

• Fully programmable frame format for both indirect and memory mapped mode

• Each of the 5 following phases can be configured independently (enable, length,

single/dual/quad communication)

– Instruction phase

– Address phase

– Alternate bytes phase

– Dummy cycles phase

– Data phase

• Integrated FIFO for reception and transmission

• 8, 16, and 32-bit data accesses are allowed

• DMA channel for indirect mode operations

• Programmable masking for external flash flag management

• Timeout management

• Interrupt generation on FIFO threshold, timeout, status match, operation complete, and

access error

DS10198 Rev 8 59/270

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Functional overview STM32L476xx

3.37 Development support

3.37.1 Serial wire JTAG debug port (SWJ-DP)

The Arm® SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

3.37.2 Embedded Trace Macrocell™

The Arm® Embedded Trace Macrocell™ provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32L476xx through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. Real-time instruction and data flow activity be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors.

The Embedded Trace Macrocell™ operates with third party debugger software tools.

60/270 DS10198 Rev 8

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STM32L476xx Pinouts and pin description

MS31270V5

LQFP144

23 24 25 26 27 28 29 30 31 32 33 34 35 36

13 14

PF9

PH0-OSC_IN (PH0)

PH1-OSC_OUT (PH1)

NRST

PC0 PC1 PC2 PC3

VSSA

VREF-

VREF+

VDDA

PA0 PA1 PA2

PF8

PF10

PF5

VDD

PF7

PF3 PF4

VSS

PF6

86 85 84 83 82 81 80 79 78 77 76 75 74 73

97 96 95

135

133

132

131

130

129

128

127

126

125

124

123

122

121

136

134

141

139

137

144

143

142

140

138

47495051525354555657585960

383940

VSS

VDD

PA6

PC5

PF11

PA4

PA5

PB0

VSS

PF14

PA7

PC4

VDD

PF15

PE7

PB1

PB2

PG0

PE8

VSS

PF12

PF13

PG1

PE9

VDD

PG3

PD15 PD14 VDD VSS PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12

PG4

PG2

VSS

PG7

PG5

PC7 PC6 VDDIO2

PG8

PG6

VDD

VSS

PB9

PB7

PB3 (JTDO-TRACESWO)

PE1

PE0

PB6

VDDIO2

PG13

PB8

BOOT0

VSS

PG12

PG9

PB5

PB4 (NJTRST)

PG11

PD7

VDD

PG15

PG14

PG10

PD6

120 VSS

119 PD5

118 PD4

117 PD3

116 PD2

115 PD1

114 PD0

113 PC12

112 PC11

111 PC10

110 PA15 (JTDI)

109 PA14 (JTCK-SWCLK)

108 VDD

104

107 106 105

103

PA12

VSS VDDUSB PA13 (JTMS-SWDIO)

PA11

9998PC9

PC8

101 100

PA9 PA8

102 PA10

686970

PE15

PB10

VSS

PB11

646566

PE11

PE12

PE14

PE13

VDD

PE10

PA3

4 5

PF2

PF1

VBAT

PC14-OSC32_IN (PC14)

PF0

PE5 PE6

PC13

PC15-OSC32_OUT (PC15)

3PE4

2PE3

1PE2

4 Pinouts and pin description

Figure 6. STM32L476Zx LQFP144 pinout

(1)

1. The above figure shows the package top view.

DS10198 Rev 8 61/270

111

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Pinouts and pin description STM32L476xx

MSv43895V2

LQFP144

23 24 25 26 27 28 29 30 31 32 33 34 35 36

13 14

PF9

PH0-OSC_IN (PH0)

PH1-OSC_OUT (PH1)

NRST

PC0 PC1 PC2 PC3

VSSA

VREF-

VREF+

VDDA

PA0 PA1 PA2

PF8

PF10

PF5

VDD

PF7

PF3 PF4

VSS

PF6

86 85 84 83 82 81 80 79 78 77 76 75 74 73

97 96 95

135

133

132

131

130

129

128

127

126

125

124

123

122

121

136

134

141

139

137

144

143

142

140

138

47495051525354555657585960

383940

VSS

VDD

PA6

PC5

PF11

PA4

PA5

PB0

VSS

PF14

PA7

PC4

VDD

PF15

PE7

PB1

PB2

PG0

PE8

VSS

PF12

PF13

PG1

PE9

VDD

PG3

PD15 PD14 VDD VSS PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12

PG4

PG2

VSS

PG7

PG5

PC7 PC6 VDDIO2

PG8

PG6

VDD

VSS

PE0

BOOT0

PB4 (NJTRST)

VDD12

PE1

PB7

VDDIO2

PG13

PB9

PB8

VSS

PG12

PG9

PB6

PB5

PG11

PD7

VDD

PB3 (JTDO-TRACESWO)

PG14

PG10

PD6

120 VSS

119 PD5

118 PD4

117 PD3

116 PD2

115 PD1

114 PD0

113 PC12

112 PC11

111 PC10

110 PA15 (JTDI)

109 PA14 (JTCK-SWCLK)

108 VDD

104

107 106 105

103

PA12

VSS VDDUSB PA13 (JTMS-SWDIO)

PA11

9998PC9

PC8

101 100

PA9 PA8

102 PA10

686970

PE15

PB10

VSS

VDD12

646566

PE11

PE12

PE14

PE13

VDD

PE10

PA3

4 5

PF2

PF1

VBAT

PC14-OSC32_IN (PC14)

PF0

PE5 PE6

PC13

PC15-OSC32_OUT (PC15)

3PE4

2PE3

1PE2

Figure 7. STM32L476Zx, external SMPS device, LQFP144 pinout

(1)

62/270 DS10198 Rev 8

1. The above figure shows the package top view.

Page 63

STM32L476xx Pinouts and pin description

MSv50902V1

VSS PE0 PB8 BOOT0 PB7 PG14 PG12 PD7 PD6 PD1 PD0 VSS

123456789101112

VBAT PE4 PE3 PE1 PB6 PG15 PG11 PD5 PC12 PC10 PA12 PA11

PC15-

OSC32_OUT

PE5 PE2 PB9 PB5 PD4 PC11 PA14 PA13 PA10

PF4

PC14-

OSC32_IN

PE6 PA15 PA9 PA 8

PF6 PF1 PF0 PC6 PC9 PC8

PF8 PF7 PG8 PC7

PH1-

OSC_OUT

PH0-OSC_IN PG3 PG5

PC2 PC0 PC1 PD11 PD14 PG2

VSSA VREF- PA0 PB14 PD10 PD15

VREF+ VDDA PA1 PA 6 PB2 PE11 PB11 PB12 PD8 PD9

OPAMP1

_VINM

PA2 PA 4

OPAMP2

_VINM

PB0 PF13 PE8 PE12 PE13 PE14 PB10 PB15

VSS PA3 PA5 PA 7 PC5 PB1 PF14 PE7 PF15 PE10 PE15 VSS

PC13 PB4 PG13 PG10

PB3 PG9

PD3 PD2

VSS VDDUSBVDDIO2 VDDPF2 VSS

PF5 PG6VDDIO2 PG7VSS VSSPF3 VDD

PF10 PD13VDD PG4VSS VSSPF9 VDD

VSS PD12VDD VDDNRST

PE9 PB13PF11 PG1PC3 PC4

PF12 PG0

VSS

MSv35003V7

PE3 PE1 PB8 BOOT0 PD7 PD5 PB4 PB3 PA15 PA14 PA13 PA12

123456789101112

PE4 PE2 PB9 PB7 PB6 PD6 PD4 PD3 PD1 PC12 PC10 PA11

PC13 PE5 PE0 VDD PB5 PD2 PD0 PC11 VDDUSB PA10

PC14-

OSC32_IN

PE6 VSS PA9 PA8 PC9

PC15-

OSC32_OUT

VBAT VSS PC8 PC7 PC6

PH0-OSC_IN VSS VSS VSS

PH1-

OSC_OUT

VDD VDD VDD

PC0 NRST VDD PD15 PD14 PD13

VSSA/VREF- PC1 PC2 PD12 PD11 PD10

PG15 PC3 PA2 PA 5 PC4 PD9 PD8 PB15 PB14 PB13

VREF+ PA0 PA3 PA6 PC5 PB2 PE8 PE10 PE12 PB10 PB11 PB12

VDDA PA 1

OPAMP1_

VINM

OPAMP2_

VINM

PB0 PB1 PE7 PE9 PE11 PE13 PE14 PE15

PG14 PG13

PF2 PF1 PF0 PG12 PG10 PG9

VSS VSS

VDD VDDIO2

PF4

PG11

PF3

PF5

PG6

PG7

PA4 PA 7 PG8 PF12 PF14 PF15

PF11 PF13

PG5

PG3

PG1

PG0

PG4

PG2

Figure 8. STM32L476Zx UFBGA144 ballout

1. The above figure shows the package top view.

Figure 9. STM32L476Qx UFBGA132 ballout

(1)

1. The above figure shows the package top view.

DS10198 Rev 8 63/270

111

Page 64

Pinouts and pin description STM32L476xx

MSv47486V1

BOOT0

PB7

VDD

PF2

PA5

PA4

PA6

OPAMP2_

VINM

PF3

PF5

PG6

PG7

PE3 PE1 PB8 PD7 PD5 PB4 PB3 PA15 PA14 PA13 PA12

123 56789101112

PE4 PE2 PB9 PB6 PD6 PD4 PD3 PD1 PC12 PC10 PA11

PC13 PE5 PE0 PB5 PD2 PD0 PC11 VDDUSB PA10

PC14-

OSC32_IN

PE6 VSS PA9 PA8 PC9

PC15-

OSC32_OUT

VBAT VSS PC8 PC7 PC6

PH0-OSC_IN VSS VSS VSS

PH1-

OSC_OUT

VDD VDD VDD

PC0 NRST VDD PD15 PD14 PD13

VSSA/VREF- PC1 PC2 PD12 PD11 PD10

PG15 PC3 PA2 PC4 PD9 PD8 PB15 PB14 PB13

VREF+ PA0 PA3 PC5 PB2 PE8 PE10 PE12 PB10 VDD12 PB12

VDDA PA 1

OPAMP1_

VINM

PB0 PB1 PE7 PE9 PE11 PE13 PE14 PE15

VDD12 PG13

PF1 PF0 PG12 PG10 PG9

VSS VSS

VDD VDDIO2

PF4

PG11

PA7 PG8 PF12 PF14 PF15

PF11 PF13

PG5

PG3

PG1

PG0

PG4

PG2

MS31271V3

LQFP100

PA3

VSS

VDD

PA4

PA5

PA6

PA7

PE11

PC4

PC5

PB0

PB1

PB2

PE7

PE8

PE9

PE10

PE12

PE13

PE14

PE15

PB10

PB11

VSS

VDD

26272829303132423334353637383940414344454647484950

VBAT

PE2 PE3 PE4 PE5 PE6

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

VSS

VDD

PH0-OSC_IN

PH1-OSC_OUT

NRST

PC0 PC1 PC2 PC3

VSSA

VREF-

VREF+

VDDA

PA0 PA1 PA2

1 2 3 4 5

7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

75 74 73 72 71

69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

PA11

VDD VSS VDDUSB PA13 PA12

PA10 PA9 PA8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12

PD0

PA14

PA15

PC10

PC11

PC12

PD1

PD2

PD3

PD4

PD5

PD6

PD7

PB3

PB4

PB5

PB6

PB7

BOOT0

PB8

PB9

PE0

PE1

VSS

VDD

7677787980

8283848586878889909192939495969798

100

Figure 10. STM32L476Qx, external SMPS device, UFBGA132 ballout

1. The above figure shows the package top view.

Figure 11. STM32L476Vx LQFP100 pinout

64/270 DS10198 Rev 8

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(1)

Page 65

STM32L476xx Pinouts and pin description

MSv38020V3

VDDUSB PA15 PD2 PG9 PG14 PB3 PB7 VSS

12345678

VSS PA14 PC12 PG10 PG13 VDDIO2 PB6 PC13

PA12 PA13 PC11 PG11 PG12

PC15-

OSC32_OUT

PA11 PA10 PC10

PC9 PA 8 PA9

PC7 PC8

PB15 PB14

PB12 PB13 PB10

PB11

PC6

PA6

PA4

PA7

PA1

PA3

PC3

PC2

PB8

BOOT0

PA5

PA2

PB4 PB5

PA0

VREF+

PC1

PB9

PH1-

OSC_OUT

VDD

VBAT

PC14-

OSC32_IN

VDDA

VSSA/VREF-

PC0

NRST

PH0-OSC_IN

VDD VSS PB2 PB0PB1 PC4PC5 VDD VSS

PD5 PD6 PD7

VDD PD4 PE7

PD9 PD8 PE8

MSv35083V7

VDDUSB PA15 PD2 PG9 PG14 PB3 PB7 VSS

12345678

VSS PA14 PC12 PG10 PG13 VDDIO2 PB6 PC13

PA12 PA13 PC11 PG11 PG12

PC15-

OSC32_OUT

PA11 PA10 PC10

PC9 PA 8 PA9

PC7 PC8

PB15 PB14

PB12 PB13 PB10

PB11

PC6

PA6

PA4

PA7

PA1

PA3

PC3

PC2

PB8

BOOT0

PA5

PA2

PB4 PB5

PA0

VREF+

PC1

PB9

PH1-

OSC_OUT

VDD

VBAT

PC14-

OSC32_IN

VDDA

VSSA/VREF-

PC0

NRST

PH0-OSC_IN

VDD VSS PB2 PB0PB1 PC4PC5 VDD VSS

WLCSP72

Figure 12. STM32L476Mx WLCSP81 ballout

1. The above figure shows the package top view.

Figure 13. STM32L476Jx WLCSP72 ballout

(1)

1. The above figure shows the package top view.

DS10198 Rev 8 65/270

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Pinouts and pin description STM32L476xx

MSv43896V1

VDDUSB PC10 PD2 PG9 PG14 PB3 BOOT0 VSS

12345678

VSS PA14 PC12 PG10 PG13 VDDIO2 PB7 VDD12

PA12 PA13 PA15 PG12 PB4

PC15-

OSC32_OUT

PA11 PA10 PC11

PC9 PA 8 PA9

VDD PC7

PB15 PC6

PB12 PB13 PB11

PB14

PC8

PA5

PA0

PA7

PA2

PA3

PC3

PC2

PB5

PB9

PA4

PA1

PB8 PC13

VDD

VREF+

PC1

PB6

PH1-

OSC_OUT

VDD

VBAT

PC14-

OSC32_IN

VDDA

VSSA/VREF-

PC0

NRST

PH0-OSC_IN

VDD12 VSS PB10 PB1PB0 PC4PB2 PA6 VSS

WLCSP72

MS31272V5

LQFP64

VBAT

PC14-OSC32_IN (PC14)

PC15-OSC32_OUT (PC15)

PH0-OSC_IN (PH0)

PH1-OSC_OUT (PH1)

NRST

PC0

PC1

PC2

PC3

VSSA/VREF-

VDDA/VREF+

PA0

PA1

PA2

PC13

5352515049

646362

2829303132

171819

PA3

VSS

PA5

PC4

PB2

VDD

PA4

PC5

PB11

PA6

PA7

VSS

PB0

PB1

PB10

VDD

VDDUSB

PA13 (JTMS-SWDIO)

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

PC6

PB15

PB14

PB13

PB12

VSS

VDD

VSS

BOOT0

PB5

PC12

PB9

PB8

PB4 (NJTRST)

PC10

PB7

PB6

PA15 (JTDI)

PB3 (JTDO-TRACESWO)

PD2

PC11

PA14 (JTCK-SWCLK)

Figure 14. STM32L476Jx, external SMPS device, WLCSP72 ballout

1. The above figure shows the package top view.

Figure 15. STM32L476Rx LQFP64 pinout

(1)

66/270 DS10198 Rev 8

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Page 67

STM32L476xx Pinouts and pin description

MSv45744V1

LQFP64

VBAT

PC14-OSC32_IN (PC14)

PC15-OSC32_OUT (PC15)

PH0-OSC_IN (PH0)

PH1-OSC_OUT (PH1)

NRST

PC0

PC1

PC2

PC3

VSSA/VREF-

VDDA/VREF+

PA0

PA1

PA2

PC13

5352515049

646362

2829303132

171819

PA3

VSS

PA5

PC4

PB10

VDD

PA4

PB0

VDD12

PA6

PA7

VSS

PB1

PB2

PB11

VDD

VDDUSB

PA13 (JTMS-SWDIO)

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

PC6

PB15

PB14

PB13

PB12

VSS

VDD

VSS

PB8

PB6

PC12

VDD12

PB9

PB5

PC10

BOOT0

PB7

PA15 (JTDI)

PB4 (NJTRST)

PB3 (JTDO-TRACESWO)

PC11

PA14 (JTCK-SWCLK)

Figure 16. STM32L476Rx, external SMPS device, LQFP64 pinout

(1)

Name Abbreviation Definition

Pin name

Pin type

I/O structure

1. The above figure shows the package top view.

Table 15. Legend/abbreviations used in the pinout table

Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name

S Supply pin

I Input only pin

I/O Input / output pin

FT 5 V tolerant I/O

TT 3.6 V tolerant I/O

B Dedicated BOOT0 pin

RST Bidirectional reset pin with embedded weak pull-up resistor

(1)

(2)

(3)

(4)

(5)

I/O, Fm+ capable

I/O, with LCD function supplied by V

I/O, with USB function supplied by V

I/O, with Analog switch function supplied by V

I/O supplied only by V

DS10198 Rev 8 67/270

Option for TT or FT I/Os

DDIO2

LCD

DDUSB

DDA

111

Page 68

Pinouts and pin description STM32L476xx

Table 15. Legend/abbreviations used in the pinout table (continued)

Name Abbreviation Definition

Notes Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset.

Alternate

functions

Additional

functions

1. The related I/O structures in Table 16 are: FT_f, FT_fa, FT_fl, FT_fla.

2. The related I/O structures in Table 16 are: FT_l, FT_fl, FT_lu.

3. The related I/O structures in Table 16 are: FT_u, FT_lu.

4. The related I/O structures in Table 16 are: FT_a, FT_la, FT_fa, FT_fla, TT_a, TT_la.

5. The related I/O structures in Table 16 are: FT_s, FT_fs.

Functions selected through GPIOx_AFR registers

Functions directly selected/enabled through peripheral registers

68/270 DS10198 Rev 8

Page 69

Table 16. STM32L476xx pin definitions

STM32L476xx Pinouts and pin description

DS10198 Rev 8 69/270

Pin Number

Pin functions

Pin name

(function

LQFP64

LQFP64_SMPS

WLCSP72

WLCSP72_SMPS

WLCSP81

LQFP100

UFBGA132

UFBGA132_SMPS

after

reset)

Pin type

LQFP144

LQFP144_SMPS

UFBGA144

I/O structure

Alternate functions Additional functions

Notes

TRACECK, TIM3_ETR,

TSC_G7_IO1,

-----1B2B211C3 PE2 I/OFT_l-

LCD_SEG38, FMC_A23,

SAI1_MCLK_A,

EVENTOUT

TRACED0, TIM3_CH1,

-----2A1A122B3 PE3 I/OFT_l-

TSC_G7_IO2,

LCD_SEG39, FMC_A19,

SAI1_SD_B, EVENTOUT

TRACED1, TIM3_CH2,

-----3B1B133B2 PE4 I/OFT -

DFSDM1_DATIN3, TSC_G7_IO3, FMC_A20, SAI1_FS_A, EVENTOUT

TRACED2, TIM3_CH3,

DFSDM1_CKIN3,

-----4C2C244C2 PE5 I/OFT -

TSC_G7_IO4, FMC_A21,

SAI1_SCK_A,

EVENTOUT

TRACED3, TIM3_CH4,

-----5D2D255D3 PE6 I/OFT -

FMC_A22, SAI1_SD_A,

RTC_TAMP3/WKUP3

EVENTOUT

1 1 B9 B9 B9 6 E2 E2 6 6 B1 VBAT S - - - -

2 2 B8 C7 B8 7 C1 C1 7 7 D4 PC13 I/O FT

(1)

(2)

EVENTOUT

RTC_TAMP1/RTC_TS/

RTC_OUT/WKUP2

Page 70

70/270 DS10198 Rev 8

Table 16. STM32L476xx pin definitions (continued)

Pinouts and pin description STM32L476xx

Pin Number

Pin functions

Pin name

(function

LQFP64

LQFP64_SMPS

WLCSP72

WLCSP72_SMPS

WLCSP81

LQFP100

UFBGA132

UFBGA132_SMPS

LQFP144

LQFP144_SMPS

3 3 C9 C9 C9 8 D1 D1 8 8 D2

after

reset)

UFBGA144

PC14-

OSC32_

Pin type

I/O FT

I/O structure

Alternate functions Additional functions

Notes

(1)

(2)

EVENTOUT OSC32_IN

IN (PC14)

4 4 C8 C8 C8 9 E1 E1 9 9 C1

PC15-

OSC32_

OUT

I/O FT

(1)

(2)

EVENTOUT OSC32_OUT

(PC15)

- - - - - - D6 D6 10 10 E3 PF0 I/O FT_f -

- - - - - - D5 D5 11 11 E2 PF1 I/O FT_f -

----- -D4D41212E4 PF2 I/OFT -

I2C2_SDA, FMC_A0,

EVENTOUT

I2C2_SCL, FMC_A1,

EVENTOUT

I2C2_SMBA, FMC_A2,

EVENTOUT

- - - - - - E4 E4 13 13 F4 PF3 I/O FT_a - FMC_A3, EVENTOUT ADC3_IN6

- - - - - - F3 F3 14 14 D1 PF4 I/O FT_a - FMC_A4, EVENTOUT ADC3_IN7

- - - - - - F4 F4 15 15 F3 PF5 I/O FT_a - FMC_A5, EVENTOUT ADC3_IN8

- - - - - 10 F2 F2 16 16 F6 VSS S - - - -

- - - - - 11 G2 G2 17 17 G5 VDD S - - - -

----- - - -1818E1 PF6 I/OFT_a-

TIM5_ETR, TIM5_CH1,

SAI1_SD_B, EVENTOUT

ADC3_IN9

TIM5_CH2,

----- - - -1919F2 PF7 I/OFT_a-

SAI1_MCLK_B,

ADC3_IN10

EVENTOUT

Page 71

Table 16. STM32L476xx pin definitions (continued)

STM32L476xx Pinouts and pin description

DS10198 Rev 8 71/270

Pin Number

Pin name

(function

after

reset)

Pin type

LQFP64

LQFP64_SMPS

WLCSP72

WLCSP72_SMPS

WLCSP81

LQFP100

UFBGA132

UFBGA132_SMPS

LQFP144

LQFP144_SMPS

UFBGA144

----- - - -2020F1 PF8 I/OFT_a-

----- - - -2121G4 PF9 I/OFT_a-

- - - - - - - - 22 22 G3 PF10 I/O FT_a - TIM15_CH2, EVENTOUT ADC3_IN13

PH0-

5 5 D9 D9 D9 12 F1 F1 23 23 G2

6 6 D8 D8 D8 13 G1 G1 24 24 G1

7 7 E9 E9 E9 14 H2 H2 25 25 H4 NRST I/O RST - - -

8 8 F9 F9 F9 15 H1 H1 26 26 H2 PC0 I/O FT_fla -

9 9 F8 F8 F8 16 J2 J2 27 27 H3 PC1 I/O FT_fla -

OSC_IN

(PH0)

PH1-

OSC_

OUT

(PH1)

I/O FT - EVENTOUT OSC_IN

I/O FT - EVENTOUT OSC_OUT

I/O structure

Alternate functions Additional functions

Notes

TIM5_CH3, SAI1_SCK_B,

EVENTOUT

TIM5_CH4, SAI1_FS_B,

TIM15_CH1, EVENTOUT

LPTIM1_IN1, I2C3_SCL,

DFSDM1_DATIN4,

LPUART1_RX,

LCD_SEG18,

LPTIM2_IN1, EVENTOUT

LPTIM1_OUT, I2C3_SDA,

DFSDM1_CKIN4,

LPUART1_TX,

LCD_SEG19,

EVENTOUT

Pin functions

ADC3_IN11

ADC3_IN12

ADC123_IN1

ADC123_IN2

Page 72

72/270 DS10198 Rev 8

Table 16. STM32L476xx pin definitions (continued)

Pinouts and pin description STM32L476xx

Pin Number

Pin name

(function

after

reset)

Pin type

LQFP64

LQFP64_SMPS

WLCSP72

WLCSP72_SMPS

WLCSP81

LQFP100

UFBGA132

UFBGA132_SMPS

LQFP144

LQFP144_SMPS

UFBGA144

10 10 F7 F7 F7 17 J3 J3 28 28 H1 PC2 I/O FT_la -

11 11 G7 G7 G7 18 K2 K2 29 29 J4 PC3 I/O FT_a -

- - - - - 19 - - 30 30 J1 VSSA S - - - -

- - - - - 20 - - 31 31 J2 VREF- S - - - -

12 12 G9 G9 G9 - J1 J1 - - -

- - G8 G8 G8 21 L1 L1 32 32 K1 VREF+ S - - - VREFBUF_OUT

- - H9 H9 H9 22 M1 M1 33 33 K2 VDDA S - - - -

1313----- ----

14 14 H8 G5 H8 23 L2 L2 34 34 J3 PA0 I/O FT_a -

VSSA/ VREF-

VDDA/

VREF+

S- - - -

I/O structure

Alternate functions Additional functions

Notes

LPTIM1_IN2,

SPI2_MISO,

DFSDM1_CKOUT,

LCD_SEG20,

EVENTOUT

LPTIM1_ETR,

SPI2_MOSI, LCD_VLCD,

SAI1_SD_A,

LPTIM2_ETR,

EVENTOUT

TIM2_CH1, TIM5_CH1,

TIM8_ETR,

USART2_CTS,

UART4_TX,

SAI1_EXTCLK,

TIM2_ETR, EVENTOUT

Pin functions

ADC123_IN3

ADC123_IN4

OPAMP1_VINP,

ADC12_IN5,

RTC_TAMP2/WKUP1

Page 73

Table 16. STM32L476xx pin definitions (continued)

STM32L476xx Pinouts and pin description

DS10198 Rev 8 73/270

Pin Number

Pin name

(function

after

reset)

Pin type

LQFP64

LQFP64_SMPS

WLCSP72

WLCSP72_SMPS

WLCSP81

LQFP100

UFBGA132

UFBGA132_SMPS

LQFP144

LQFP144_SMPS

UFBGA144

----- -M3M3- -L1

15 15 G4 G6 G4 24 M2 M2 35 35 K3 PA1 I/O FT_la

16 16 G6 G4 G6 25 K3 K3 36 36 L2 PA2 I/O FT_la -

17 17 H7 H7 H7 26 L3 L3 37 37 M2 PA3 I/O TT_la -

18 18 J9 J9 J9 27 E3 E3 38 38 F7 VSS S - - - -

OPAMP1

_VINM

I/O structure

ITT- - -

Alternate functions Additional functions

Notes

TIM2_CH2, TIM5_CH2,

(3)

USART2_RTS_DE, UART4_RX, LCD_SEG0,

TIM15_CH1N,

EVENTOUT

TIM2_CH3, TIM5_CH3,

USART2_TX,

LCD_SEG1,

SAI2_EXTCLK,

TIM15_CH1, EVENTOUT

TIM2_CH4, TIM5_CH4,

USART2_RX,

LCD_SEG2, TIM15_CH2,

EVENTOUT

Pin functions

OPAMP1_VINM,

ADC12_IN6

ADC12_IN7,

WKUP4/LSCO

OPAMP1_VOUT,

ADC12_IN8

19 19 J8 H8 J8 28 H3 H3 39 39 G8 VDD S - - - -

SPI1_NSS, SPI3_NSS,

20 20 G5 H6 G5 29 J4 J4 40 40 L3 PA4 I/O TT_a -

USART2_CK,

SAI1_FS_B,

LPTIM2_OUT,

EVENTOUT

ADC12_IN9,

DAC1_OUT1

Page 74

74/270 DS10198 Rev 8

Table 16. STM32L476xx pin definitions (continued)

Pinouts and pin description STM32L476xx

Pin Number

Pin name

(function

after

reset)

Pin type

LQFP64

LQFP64_SMPS

WLCSP72

WLCSP72_SMPS

WLCSP81

LQFP100

UFBGA132

UFBGA132_SMPS

LQFP144

LQFP144_SMPS

UFBGA144

21 21 H6 H5 H6 30 K4 K4 41 41 M3 PA5 I/O TT_a -

22 22 H5 J8 H5 31 L4 L4 42 42 K4 PA6 I/O FT_la -

----- -M4M4- -L4

23 23 H4 H4 H4 32 J5 J5 43 43 M4 PA7 I/O FT_la

OPAMP2

_VINM

I/O structure

ITT- - -

Pin functions

Alternate functions Additional functions

Notes

TIM2_CH1, TIM2_ETR,

TIM8_CH1N, SPI1_SCK,

LPTIM2_ETR,

EVENTOUT

TIM1_BKIN, TIM3_CH1,

TIM8_BKIN, SPI1_MISO,

USART3_CTS,

QUADSPI_BK1_IO3,

LCD_SEG3, TIM1_BKIN_COMP2, TIM8_BKIN_COMP2,

TIM16_CH1, EVENTOUT

TIM1_CH1N, TIM3_CH2,

TIM8_CH1N, SPI1_MOSI,

(3)

QUADSPI_BK1_IO2,

LCD_SEG4, TIM17_CH1,

EVENTOUT

ADC12_IN10,

DAC1_OUT2

OPAMP2_VINP,

ADC12_IN11

OPAMP2_VINM,

ADC12_IN12

24 24 J7 J7 J7 33 K5 K5 44 44 J5 PC4 I/O FT_la -

25 - J6 - J6 34 L5 L5 45 45 M5 PC5 I/O FT_la -

USART3_TX, LCD_SEG22,

EVENTOUT

USART3_RX, LCD_SEG23,

EVENTOUT

COMP1_INM,

ADC12_IN13

COMP1_INP,

ADC12_IN14, WKUP5

Page 75

Table 16. STM32L476xx pin definitions (continued)

STM32L476xx Pinouts and pin description

DS10198 Rev 8 75/270

Pin Number

Pin name

(function

after

reset)

Pin type

LQFP64

LQFP64_SMPS

WLCSP72

WLCSP72_SMPS

WLCSP81

LQFP100

UFBGA132

UFBGA132_SMPS

LQFP144

LQFP144_SMPS

UFBGA144

26 25 J5 J4 J5 35 M5 M5 46 46 L5 PB0 I/O TT_la -

27 26 J4 J5 J4 36 M6 M6 47 47 M6 PB1 I/O FT_la -

28 27 J3 J6 J3 37 L6 L6 48 48 K5 PB2 I/O FT_a -

- - - - - - K6 K6 49 49 J6 PF11 I/O FT - EVENTOUT -

I/O structure

Alternate functions Additional functions

Notes

TIM1_CH2N, TIM3_CH3,

TIM8_CH2N,

USART3_CK,

QUADSPI_BK1_IO1,

LCD_SEG5,

COMP1_OUT,

EVENTOUT

TIM1_CH3N, TIM3_CH4,

TIM8_CH3N, DFSDM1_DATIN0, USART3_RTS_DE,

QUADSPI_BK1_IO0,

LCD_SEG6, LPTIM2_IN1,

EVENTOUT

RTC_OUT, LPTIM1_OUT,

I2C3_SMBA,

DFSDM1_CKIN0,

EVENTOUT

Pin functions

OPAMP2_VOUT,

ADC12_IN15

COMP1_INM,

ADC12_IN16

COMP1_INP

- - - - - - J7 J7 50 50 K6 PF12 I/O FT - FMC_A6, EVENTOUT -

----- - - -5151G6 VSS S - - - -

----- - - -5252H6 VDD S - - - -

----- -K7K75353L6 PF13I/OFT -

DFSDM1_DATIN6,

FMC_A7, EVENTOUT

Page 76

76/270 DS10198 Rev 8

Table 16. STM32L476xx pin definitions (continued)

Pinouts and pin description STM32L476xx

Pin Number

Pin name

(function

after

reset)

Pin type

I/O structure

LQFP64

LQFP64_SMPS

WLCSP72

WLCSP72_SMPS

WLCSP81

LQFP100

UFBGA132

UFBGA132_SMPS

LQFP144

LQFP144_SMPS

UFBGA144

----- -J8J85454M7 PF14I/OFT -

----- -J9J95555M9 PF15I/OFT -

- - - - - - H9 H9 56 56 K7 PG0 I/O FT -

- - - - - - G9 G9 57 57 J7 PG1 I/O FT -

- - - - E6 38 M7 M7 58 58 M8 PE7 I/O FT -

- - - - F6 39 L7 L7 59 59 L7 PE8 I/O FT -

Notes

Pin functions

Alternate functions Additional functions

DFSDM1_CKIN6,

TSC_G8_IO1, FMC_A8,

EVENTOUT

TSC_G8_IO2, FMC_A9,

EVENTOUT

TSC_G8_IO3, FMC_A10,

EVENTOUT

TSC_G8_IO4, FMC_A11,

EVENTOUT

TIM1_ETR,

DFSDM1_DATIN2,

FMC_D4, SAI1_SD_B,

EVENTOUT

TIM1_CH1N,

DFSDM1_CKIN2,

FMC_D5, SAI1_SCK_B,

EVENTOUT

TIM1_CH1,

- - - - - 40 M8 M8 60 60 J8 PE9 I/O FT -

----- -F6F66161G7 VSS S - - - -

----- -G6G66262E7 VDD S - - - -

DFSDM1_CKOUT,

FMC_D6, SAI1_FS_B,

EVENTOUT

Page 77

Table 16. STM32L476xx pin definitions (continued)

STM32L476xx Pinouts and pin description

DS10198 Rev 8 77/270

Pin Number

Pin name

(function

after

reset)

Pin type

LQFP64

LQFP64_SMPS

WLCSP72

WLCSP72_SMPS

WLCSP81

LQFP100

UFBGA132

UFBGA132_SMPS

LQFP144

LQFP144_SMPS

UFBGA144

- - - - - 41 L8 L8 63 63 M10 PE10 I/O FT -

- - - - - 42 M9 M9 64 64 K8 PE11 I/O FT -

- - - - - 43 L9 L9 65 65 L8 PE12 I/O FT -

- - - - - 44 M10 M10 66 66 L9 PE13 I/O FT -

- - - - - 45 M11 M11 67 67 L10 PE14 I/O FT -

I/O structure

Pin functions

Alternate functions Additional functions

Notes

TIM1_CH2N, DFSDM1_DATIN4,

TSC_G5_IO1,

QUADSPI_CLK,

FMC_D7, SAI1_MCLK_B,

EVENTOUT

TIM1_CH2,

DFSDM1_CKIN4,

TSC_G5_IO2,

QUADSPI_NCS,

FMC_D8, EVENTOUT

TIM1_CH3N, SPI1_NSS,

DFSDM1_DATIN5,

TSC_G5_IO3,

QUADSPI_BK1_IO0,

FMC_D9, EVENTOUT

TIM1_CH3, SPI1_SCK,

DFSDM1_CKIN5,

TSC_G5_IO4,

QUADSPI_BK1_IO1,

FMC_D10, EVENTOUT

TIM1_CH4, TIM1_BKIN2,

TIM1_BKIN2_COMP2,

SPI1_MISO,

QUADSPI_BK1_IO2,

FMC_D11, EVENTOUT

Page 78

78/270 DS10198 Rev 8

Table 16. STM32L476xx pin definitions (continued)

Pinouts and pin description STM32L476xx

Pin Number

Pin name

(function

after

reset)

Pin type

LQFP64

LQFP64_SMPS

WLCSP72

WLCSP72_SMPS

WLCSP81

LQFP100

UFBGA132

UFBGA132_SMPS

LQFP144

LQFP144_SMPS

UFBGA144

- - - - - 46 M12 M12 68 68 M11 PE15 I/O FT -

29 28 H3 J3 H3 47 L10 L10 69 69 L11 PB10 I/O FT_fl -

30 29 G3 H3 G3 48 L11 - 70 - K9 PB11 I/O FT_fl -

- 30 - B8 - - - L11 - 70 - VDD12 S - - - -

31 31 J2 J2 J2 49 F12 F12 71 71 H5 VSS S - - - -

I/O structure

Alternate functions Additional functions

Notes

TIM1_BKIN,

TIM1_BKIN_COMP1,

SPI1_MOSI,

QUADSPI_BK1_IO3,

FMC_D12, EVENTOUT

TIM2_CH3, I2C2_SCL,

SPI2_SCK,

DFSDM1_DATIN7,

USART3_TX,

LPUART1_RX,

QUADSPI_CLK,

LCD_SEG10, COMP1_OUT, SAI1_SCK_A,

EVENTOUT

TIM2_CH4, I2C2_SDA,

DFSDM1_CKIN7,

USART3_RX,

LPUART1_TX,

QUADSPI_NCS,

LCD_SEG11, COMP2_OUT,

EVENTOUT

Pin functions

32 32 J1 F1 J1 50 G12 G12 72 72 - VDD S - - - -

Page 79

Table 16. STM32L476xx pin definitions (continued)

STM32L476xx Pinouts and pin description

DS10198 Rev 8 79/270

Pin Number

Pin name

(function

after

reset)

Pin type

LQFP64

LQFP64_SMPS

WLCSP72

WLCSP72_SMPS

WLCSP81

LQFP100

UFBGA132

UFBGA132_SMPS

LQFP144

LQFP144_SMPS

UFBGA144

33 33 H1 H1 H1 51 L12 L12 73 73 K10 PB12 I/O FT_l -

34 34 H2 H2 H2 52 K12 K12 74 74 J9 PB13 I/O FT_fl -

I/O structure

Pin functions

Alternate functions Additional functions

Notes

TIM1_BKIN,

TIM1_BKIN_COMP2,

I2C2_SMBA, SPI2_NSS,

DFSDM1_DATIN1,

USART3_CK,

LPUART1_RTS_DE,

TSC_G1_IO1,

LCD_SEG12,

SWPMI1_IO, SAI2_FS_A, TIM15_BKIN, EVENTOUT

TIM1_CH1N, I2C2_SCL,

SPI2_SCK,

DFSDM1_CKIN1,

USART3_CTS,

LPUART1_CTS,

TSC_G1_IO2,

LCD_SEG13,

SWPMI1_TX, SAI2_SCK_A, TIM15_CH1N,

EVENTOUT

Page 80

80/270 DS10198 Rev 8

Table 16. STM32L476xx pin definitions (continued)

Pinouts and pin description STM32L476xx

Pin Number

Pin name

(function

after

reset)

Pin type

LQFP64

LQFP64_SMPS

WLCSP72

WLCSP72_SMPS

WLCSP81

LQFP100

UFBGA132

UFBGA132_SMPS

LQFP144

LQFP144_SMPS

UFBGA144

35 35 G2 G3 G2 53 K11 K11 75 75 J10 PB14 I/O FT_fl -

36 36 G1 G1 G1 54 K10 K10 76 76 L12 PB15 I/O FT_l -

- - - - F5 55 K9 K9 77 77 K11 PD8 I/O FT_l -

I/O structure

Pin functions

Alternate functions Additional functions

Notes

TIM1_CH2N,

TIM8_CH2N, I2C2_SDA,

SPI2_MISO, DFSDM1_DATIN2, USART3_RTS_DE,

TSC_G1_IO3,

LCD_SEG14, SWPMI1_RX,

SAI2_MCLK_A,

TIM15_CH1, EVENTOUT

RTC_REFIN, TIM1_CH3N,

TIM8_CH3N, SPI2_MOSI,

DFSDM1_CKIN2,

TSC_G1_IO4,

LCD_SEG15,

SWPMI1_SUSPEND,

SAI2_SD_A, TIM15_CH2,

EVENTOUT

USART3_TX,

LCD_SEG28, FMC_D13,

EVENTOUT

- - - - F4 56 K8 K8 78 78 K12 PD9 I/O FT_l -

USART3_RX,

LCD_SEG29, FMC_D14,

SAI2_MCLK_A,

EVENTOUT

Page 81

Table 16. STM32L476xx pin definitions (continued)

STM32L476xx Pinouts and pin description

DS10198 Rev 8 81/270

Pin Number

Pin name

(function

after

reset)

Pin type

LQFP64

LQFP64_SMPS

WLCSP72

WLCSP72_SMPS

WLCSP81

LQFP100

UFBGA132

UFBGA132_SMPS

LQFP144

LQFP144_SMPS

UFBGA144

- - - - - 57 J12 J12 79 79 J11 PD10 I/O FT_l -

- - - - - 58 J11 J11 80 80 H10 PD11 I/O FT_l -

- - - - - 59 J10 J10 81 81 H9 PD12 I/O FT_l -

I/O structure

Pin functions

Alternate functions Additional functions

Notes

USART3_CK,

TSC_G6_IO1,

LCD_SEG30, FMC_D15,

SAI2_SCK_A,

EVENTOUT

USART3_CTS,

TSC_G6_IO2,

LCD_SEG31, FMC_A16,

SAI2_SD_A,

LPTIM2_ETR,

EVENTOUT

TIM4_CH1,

USART3_RTS_DE,

TSC_G6_IO3,

LCD_SEG32, FMC_A17,

SAI2_FS_A, LPTIM2_IN1,

EVENTOUT

TIM4_CH2,

TSC_G6_IO4,

- - - - - 60 H12 H12 82 82 G10 PD13 I/O FT_l -

----- - - -8383E5 VSS S - - - -

----- - - -8484F5 VDD S - - - -

- - - - - 61 H11 H11 85 85 H11 PD14 I/O FT_l -

LCD_SEG33, FMC_A18,

LPTIM2_OUT,

EVENTOUT

TIM4_CH3, LCD_SEG34,

FMC_D0, EVENTOUT

Page 82

82/270 DS10198 Rev 8

Table 16. STM32L476xx pin definitions (continued)

Pinouts and pin description STM32L476xx

Pin Number

Pin name

(function

after

reset)

Pin type

I/O structure

LQFP64

LQFP64_SMPS

WLCSP72

WLCSP72_SMPS

WLCSP81

LQFP100

UFBGA132

UFBGA132_SMPS

LQFP144

LQFP144_SMPS

UFBGA144

- - - - - 62 H10 H10 86 86 J12 PD15 I/O FT_l -

- - - - - - G10 G10 87 87 H12 PG2 I/O FT_s -

----- -F9F98888G11 PG3 I/OFT_s-

- - - - - - F10 F10 89 89 G9 PG4 I/O FT_s -

- - - - - - E9 E9 90 90 G12 PG5 I/O FT_s -

- - - - - - G4 G4 91 91 F10 PG6 I/O FT_s -

Notes

Pin functions

Alternate functions Additional functions

TIM4_CH4, LCD_SEG35,

FMC_D1, EVENTOUT

SPI1_SCK, FMC_A12,

SAI2_SCK_B,

EVENTOUT

SPI1_MISO, FMC_A13,

SAI2_FS_B, EVENTOUT

SPI1_MOSI, FMC_A14,

SAI2_MCLK_B,

EVENTOUT

SPI1_NSS,

LPUART1_CTS,

FMC_A15, SAI2_SD_B,

EVENTOUT

I2C3_SMBA,

LPUART1_RTS_DE,

EVENTOUT

I2C3_SCL,

- - - - - - H4 H4 92 92 F9 PG7 I/O FT_fs -

----- -J6J69393F11 PG8 I/OFT_fs-

----- - - -9494M12 VSS S - - - -

----- - - -9595F8VDDIO2S - - - -

LPUART1_TX, FMC_INT,

EVENTOUT

I2C3_SDA,

LPUART1_RX,

EVENTOUT

Page 83

Table 16. STM32L476xx pin definitions (continued)

STM32L476xx Pinouts and pin description

DS10198 Rev 8 83/270

Pin Number

Pin name

(function

after

reset)

Pin type

LQFP64

LQFP64_SMPS

WLCSP72

WLCSP72_SMPS

WLCSP81

LQFP100

UFBGA132

UFBGA132_SMPS

LQFP144

LQFP144_SMPS

UFBGA144

37 37 F3 G2 F3 63 E12 E12 96 96 E10 PC6 I/O FT_l -

38 38 F1 F2 F1 64 E11 E11 97 97 F12 PC7 I/O FT_l -

39 39 F2 F3 F2 65 E10 E10 98 98 E12 PC8 I/O FT_l -

I/O structure

Pin functions

Alternate functions Additional functions

Notes

TIM3_CH1, TIM8_CH1,

DFSDM1_CKIN3,

TSC_G4_IO1,

LCD_SEG24,

SDMMC1_D6,

SAI2_MCLK_A,

EVENTOUT

TIM3_CH2, TIM8_CH2,

DFSDM1_DATIN3,

TSC_G4_IO2,

LCD_SEG25,

SDMMC1_D7,

SAI2_MCLK_B,

EVENTOUT

TIM3_CH3, TIM8_CH3,

TSC_G4_IO3,

LCD_SEG26,

SDMMC1_D0,

EVENTOUT

40 40 E1 E1 E1 66 D12 D12 99 99 E11 PC9 I/O FT_l -

TIM8_BKIN2, TIM3_CH4,

TIM8_CH4,

TSC_G4_IO4,

OTG_FS_NOE,

LCD_SEG27,

SDMMC1_D1,

SAI2_EXTCLK,

TIM8_BKIN2_COMP1,

EVENTOUT

Page 84

84/270 DS10198 Rev 8

Table 16. STM32L476xx pin definitions (continued)

Pinouts and pin description STM32L476xx

Pin Number

Pin name

(function

after

reset)

Pin type

LQFP64

LQFP64_SMPS

WLCSP72

WLCSP72_SMPS

WLCSP81

LQFP100

UFBGA132

UFBGA132_SMPS

LQFP144

LQFP144_SMPS

UFBGA144

41 41 E2 E2 E2 67 D11 D11 100 100 D12 PA8 I/O FT_l -

42 42 E3 E3 E3 68 D10 D10 101 101 D11 PA9 I/O FT_lu -

43 43 D2 D2 D2 69 C12 C12 102 102 C12 PA10 I/O FT_lu -

44 44 D1 D1 D1 70 B12 B12 103 103 B12 PA11 I/O FT_u -

45 45 C1 C1 C1 71 A12 A12 104 104 B11 PA12 I/O FT_u -

I/O structure

Pin functions

Alternate functions Additional functions

Notes

MCO, TIM1_CH1,

USART1_CK,

OTG_FS_SOF,

LCD_COM0,

LPTIM2_OUT,

EVENTOUT

TIM1_CH2, USART1_TX,

LCD_COM1,

TIM15_BKIN, EVENTOUT

TIM1_CH3, USART1_RX,

OTG_FS_ID, LCD_COM2,

TIM17_BKIN, EVENTOUT

TIM1_CH4, TIM1_BKIN2,

USART1_CTS,

CAN1_RX, OTG_FS_DM,

TIM1_BKIN2_COMP1,

EVENTOUT

TIM1_ETR,

USART1_RTS_DE,

CAN1_TX, OTG_FS_DP,

EVENTOUT

OTG_FS_VBUS

PA13

46 46 C2 C2 C2 72 A11 A11 105 105 C11

47 47 B1 B1 B1 - - - - - E8 VSS S - - - -

(JTMS-

SWDIO)

I/O FT

JTMS-SWDIO, IR_OUT,

(4)

OTG_FS_NOE,

EVENTOUT

Page 85

Table 16. STM32L476xx pin definitions (continued)

STM32L476xx Pinouts and pin description

DS10198 Rev 8 85/270

Pin Number

Pin functions

Pin name

(function

after

reset)

Pin type

LQFP64

LQFP64_SMPS

WLCSP72

WLCSP72_SMPS

WLCSP81

LQFP100

UFBGA132

UFBGA132_SMPS

LQFP144

LQFP144_SMPS

UFBGA144

I/O structure

Alternate functions Additional functions

Notes

48 48 A1 A1 A1 73 C11 C11 106 106 E9 VDDUSB S - - - -

- - - - - 74 F11 F11 107 107 H8 VSS S - - - -

- - - - - 75 G11 G11 108 108 H7 VDD S - - - -

49 49 B2 B2 B2 76 A10 A10 109 109 C10

PA14

(JTCK-

SWCLK)

I/O FT

(4)

JTCK-SWCLK,

EVENTOUT

JTDI, TIM2_CH1,

TIM2_ETR, SPI1_NSS,

SPI3_NSS,

UART4_RTS_DE,

TSC_G3_IO1,

50 50 A2 C3 A2 77 A9 A9 110 110 D10

PA15

(JTDI)

I/O FT_l

(4)

LCD_SEG17,

SAI2_FS_B, EVENTOUT

SPI3_SCK, USART3_TX,

UART4_TX,

TSC_G3_IO2,

51 51 D3 A2 D3 78 B11 B11 111 111 B10 PC10 I/O FT_l -

LCD_COM4/LCD_SEG28

/LCD_SEG40, SDMMC1_D2, SAI2_SCK_B,

EVENTOUT

Page 86

86/270 DS10198 Rev 8

Table 16. STM32L476xx pin definitions (continued)

Pinouts and pin description STM32L476xx

Pin Number

Pin name

(function

after

reset)

Pin type

LQFP64

LQFP64_SMPS

WLCSP72

WLCSP72_SMPS

WLCSP81

LQFP100

UFBGA132

UFBGA132_SMPS

LQFP144

LQFP144_SMPS

UFBGA144

52 52 C3 D3 C3 79 C10 C10 112 112 C9 PC11 I/O FT_l -

53 53 B3 B3 B3 80 B10 B10 113 113 B9 PC12 I/O FT_l -

I/O structure

Pin functions

Alternate functions Additional functions

Notes

SPI3_MISO,

USART3_RX,

UART4_RX,

TSC_G3_IO3,

LCD_COM5/LCD_SEG29

/LCD_SEG41, SDMMC1_D3,

SAI2_MCLK_B,

EVENTOUT

SPI3_MOSI,

USART3_CK,

UART5_TX,

TSC_G3_IO4,

LCD_COM6/LCD_SEG30

/LCD_SEG42,

SDMMC1_CK,

SAI2_SD_B, EVENTOUT

- - - - - 81 C9 C9 114 114 A11 PD0 I/O FT -

- - - - - 82 B9 B9 115 115 A10 PD1 I/O FT -

SPI2_NSS,

DFSDM1_DATIN7,

CAN1_RX, FMC_D2,

EVENTOUT

SPI2_SCK,

DFSDM1_CKIN7,

CAN1_TX, FMC_D3,

EVENTOUT

Page 87

Table 16. STM32L476xx pin definitions (continued)

STM32L476xx Pinouts and pin description

DS10198 Rev 8 87/270

Pin Number

Pin name

(function

after

reset)

Pin type

LQFP64

LQFP64_SMPS

WLCSP72

WLCSP72_SMPS

WLCSP81

LQFP100

UFBGA132

UFBGA132_SMPS

LQFP144

LQFP144_SMPS

UFBGA144

54 - A3A3A3 83 C8 C8 116116 D9 PD2 I/O FT_l -

- - - - - 84 B8 B8 117 117 D8 PD3 I/O FT -

- - - - E5 85 B7 B7 118 118 C8 PD4 I/O FT -

- - - - D4 86 A6 A6 119 119 B8 PD5 I/O FT -

I/O structure

Pin functions

Alternate functions Additional functions

Notes

TIM3_ETR,

USART3_RTS_DE,

UART5_RX, TSC_SYNC, LCD_COM7/LCD_SEG31

/LCD_SEG43,

SDMMC1_CMD,

EVENTOUT

SPI2_MISO, DFSDM1_DATIN0,

USART2_CTS,

FMC_CLK, EVENTOUT

SPI2_MOSI,

DFSDM1_CKIN0,

USART2_RTS_DE,

FMC_NOE, EVENTOUT

USART2_TX, FMC_NWE,

EVENTOUT

- - - - - - - - 120 120 A1 VSS S - - - -

- - - - E4 - - - 121 121 - VDD S - - - -

DFSDM1_DATIN1,

- - - - D5 87 B6 B6 122 122 A9 PD6 I/O FT -

- - - - D6 88 A5 A5 123 123 A8 PD7 I/O FT -

USART2_RX, FMC_NWAIT,

SAI1_SD_A, EVENTOUT

DFSDM1_CKIN1,

USART2_CK, FMC_NE1,

EVENTOUT

Page 88

88/270 DS10198 Rev 8

Table 16. STM32L476xx pin definitions (continued)

Pinouts and pin description STM32L476xx

Pin Number

Pin name

(function

after

reset)

Pin type

LQFP64

LQFP64_SMPS

WLCSP72

WLCSP72_SMPS

WLCSP81

LQFP100

UFBGA132

UFBGA132_SMPS

LQFP144

LQFP144_SMPS

UFBGA144

- - A4 A4 A4 - D9 D9 124 124 C7 PG9 I/O FT_s -

- - B4 B4 B4 - D8 D8 125 125 D7 PG10 I/O FT_s -

- - C4 - C4 - G3 G3 126 126 B7 PG11 I/O FT_s -

- - C5 C4 C5 - D7 D7 127 127 A7 PG12 I/O FT_s -

I/O structure

Pin functions

Alternate functions Additional functions

Notes

SPI3_SCK, USART1_TX,

FMC_NCE/FMC_NE2,

SAI2_SCK_A, TIM15_CH1N,

EVENTOUT

LPTIM1_IN1,

SPI3_MISO,

USART1_RX, FMC_NE3, SAI2_FS_A, TIM15_CH1,

EVENTOUT

LPTIM1_IN2,

SPI3_MOSI,

USART1_CTS,

SAI2_MCLK_A,

TIM15_CH2, EVENTOUT

LPTIM1_ETR, SPI3_NSS,

USART1_RTS_DE,

FMC_NE4, SAI2_SD_A,

EVENTOUT

- - B5 B5 B5 - C7 C7 128 128 D6 PG13 I/O FT_fs -

- - A5 A5 A5 - C6 - 129 129 A6 PG14 I/O FT_fs -

- - - - - - F7 F7 130 130 A12 VSS S - - - -

- - B6 B6 B6 - G7 G7 131 131 E6 VDDIO2 S - - - -

I2C1_SDA, USART1_CK,

FMC_A24, EVENTOUT

I2C1_SCL, FMC_A25,

EVENTOUT

Page 89

Table 16. STM32L476xx pin definitions (continued)

STM32L476xx Pinouts and pin description

DS10198 Rev 8 89/270

Pin Number

Pin name

(function

after

reset)

Pin type

LQFP64

LQFP64_SMPS

WLCSP72

WLCSP72_SMPS

WLCSP81

LQFP100

UFBGA132

UFBGA132_SMPS

LQFP144

LQFP144_SMPS

UFBGA144

I/O structure

- - - - - - K1 K1 132 - B6 PG15 I/O FT_s -

PB3

55 54 A6 A6 A6 89 A8 A8 133 132 C6

(JTDOTRACE

I/O FT_la

SWO)

56 55 C6 C5 C6 90 A7 A7 134 133 D5

PB4

(NJTRST)

I/O FT_la

Pin functions

Alternate functions Additional functions

Notes

LPTIM1_OUT,

I2C1_SMBA, EVENTOUT

JTDO-TRACESWO,

TIM2_CH2, SPI1_SCK,

(4)

SPI3_SCK,

USART1_RTS_DE,

COMP2_INM

LCD_SEG7,

SAI1_SCK_B,

EVENTOUT

NJTRST, TIM3_CH1,

SPI1_MISO, SPI3_MISO,

USART1_CTS,

(4)

UART5_RTS_DE,

TSC_G2_IO1,

COMP2_INP

LCD_SEG8,

SAI1_MCLK_B,

TIM17_BKIN, EVENTOUT

57 56 C7 E7 C7 91 C5 C5 135 134 C5 PB5 I/O FT_la -

LPTIM1_IN1, TIM3_CH2,

I2C1_SMBA, SPI1_MOSI,

SPI3_MOSI,

USART1_CK, UART5_CTS,

TSC_G2_IO2,

LCD_SEG9,

COMP2_OUT,

SAI1_SD_B,

TIM16_BKIN, EVENTOUT

Page 90

90/270 DS10198 Rev 8

Table 16. STM32L476xx pin definitions (continued)

Pinouts and pin description STM32L476xx

Pin Number

Pin name

(function

after

reset)

Pin type

LQFP64

LQFP64_SMPS

WLCSP72

WLCSP72_SMPS

WLCSP81

LQFP100

UFBGA132

UFBGA132_SMPS

LQFP144

LQFP144_SMPS

UFBGA144

58 57 B7 E8 B7 92 B5 B5 136 135 B5 PB6 I/O FT_fa -

59 58 A7 B7 A7 93 B4 B4 137 136 A5 PB7 I/O FT_fla -

I/O structure

Pin functions

Alternate functions Additional functions

Notes

LPTIM1_ETR,

TIM4_CH1, TIM8_BKIN2,

I2C1_SCL,

DFSDM1_DATIN5,

USART1_TX,

TSC_G2_IO3,

TIM8_BKIN2_COMP2,

SAI1_FS_B,

TIM16_CH1N,

EVENTOUT

LPTIM1_IN2, TIM4_CH2,

TIM8_BKIN, I2C1_SDA,

DFSDM1_CKIN5,

USART1_RX, UART4_CTS,

TSC_G2_IO4,

LCD_SEG21, FMC_NL,

TIM8_BKIN_COMP1,

TIM17_CH1N,

EVENTOUT

COMP2_INP

COMP2_INM, PVD_IN

60 59 D7 A7 D7 94 A4 A4 138 137 A4 BOOT0 I - - - -

TIM4_CH3, I2C1_SCL,

DFSDM1_DATIN6,

61 60 E7 C6 E7 95 A3 A3 139 138 A3 PB8 I/O FT_fl -

CAN1_RX, LCD_SEG16,

SDMMC1_D4,

SAI1_MCLK_A,

TIM16_CH1, EVENTOUT

Page 91

Table 16. STM32L476xx pin definitions (continued)

STM32L476xx Pinouts and pin description

DS10198 Rev 8 91/270

Pin Number

Pin functions

Pin name

(function

after

reset)

Pin type

LQFP64

LQFP64_SMPS

WLCSP72

WLCSP72_SMPS

WLCSP81

LQFP100

UFBGA132

UFBGA132_SMPS

LQFP144

LQFP144_SMPS

UFBGA144

I/O structure

Alternate functions Additional functions

Notes

IR_OUT, TIM4_CH4,

I2C1_SDA, SPI2_NSS,

DFSDM1_CKIN6,

62 61 E8 D7 E8 96 B3 B3 140 139 C4 PB9 I/O FT_fl -

CAN1_TX, LCD_COM3,

SDMMC1_D5,

SAI1_FS_A, TIM17_CH1,

EVENTOUT

TIM4_ETR, LCD_SEG36,

- - - - - 97 C3 C3 141 140 A2 PE0 I/O FT_l -

FMC_NBL0, TIM16_CH1,

EVENTOUT

LCD_SEG37,

- - - - - 98 A2 A2 142 141 B4 PE1 I/O FT_l -

FMC_NBL1, TIM17_CH1,

EVENTOUT

- 62 - J1 - - - C6 - 142 - VDD12 S - - - -

63 63 A8 A8 A8 99 D3 D3 143 143 M1 VSS S - - - -

64 64 A9 A9 A9 100 C4 C4 144 144 - VDD S - - - -

1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:

- The speed should not exceed 2 MHz with a maximum load of 30 pF

- These GPIOs must not be used as current sources (e.g. to drive an LED).

2. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to the Backup domain and RTC register descriptions in the RM0351 reference manual.

3. OPAMPx_VINM pins are not available as additional functions on pins PA1 and PA7 on UFBGA packages. On UFBGA packages, use the OPAMPx_VINM dedicated pins.

4. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are activated.

Page 92

92/270 DS10198 Rev 8

Table 17. Alternate function AF0 to AF7

(1)

Pinouts and pin description STM32L476xx

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

Port A

Port

SYS_AF

TIM1/TIM2/ TIM5/TIM8/

LPTIM1

TIM1/TIM2/ TIM3/TIM4/

TIM5

TIM8 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3/DFSDM

USART1/ USART2/

USART3

PA0 - TIM2_CH1 TIM5_CH1 TIM8_ETR - - - USART2_CTS

PA1 - TIM2_CH2 TIM5_CH2 - - - -

USART2_RTS_

PA2 - TIM2_CH3 TIM5_CH3 - - - - USART2_TX

PA3 - TIM2_CH4 TIM5_CH4 - - - - USART2_RX

PA4-----SPI1_NSSSPI3_NSSUSART2_CK

PA5 - TIM2_CH1 TIM2_ETR TIM8_CH1N - SPI1_SCK - -

PA6 - TIM1_BKIN TIM3_CH1 TIM8_BKIN - SPI1_MISO - USART3_CTS

PA7 - TIM1_CH1N TIM3_CH2 TIM8_CH1N - SPI1_MOSI - -

PA8MCOTIM1_CH1---- -USART1_CK

PA9-TIM1_CH2---- -USART1_TX

PA10-TIM1_CH3---- -USART1_RX

PA11 - TIM1_CH4 TIM1_BKIN2 - - - - USART1_CTS

PA12-TIM1_ETR---- -

USART1_RTS_

PA13 JTMS-SWDIO IR_OUT - - - - - -

PA14JTCK-SWCLK----- - -

PA15 JTDI TIM2_CH1 TIM2_ETR - - SPI1_NSS SPI3_NSS -

Page 93

Table 17. Alternate function AF0 to AF7

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

(1)

(continued)

STM32L476xx Pinouts and pin description

DS10198 Rev 8 93/270

Port B

Port

SYS_AF

PB0 - TIM1_CH2N TIM3_CH3 TIM8_CH2N - - - USART3_CK

PB1 - TIM1_CH3N TIM3_CH4 TIM8_CH3N - -

PB2 RTC_OUT LPTIM1_OUT - - I2C3_SMBA - DFSDM1_CKIN0 -

PB3

PB4 NJTRST - TIM3_CH1 - - SPI1_MISO SPI3_MISO USART1_CTS

PB5 - LPTIM1_IN1 TIM3_CH2 - I2C1_SMBA SPI1_MOSI SPI3_MOSI USART1_CK

PB6 - LPTIM1_ETR TIM4_CH1 TIM8_BKIN2 I2C1_SCL -

PB7 - LPTIM1_IN2 TIM4_CH2 TIM8_BKIN I2C1_SDA - DFSDM1_CKIN5 USART1_RX

PB8 - - TIM4_CH3 - I2C1_SCL -

PB9 - IR_OUT TIM4_CH4 - I2C1_SDA SPI2_NSS DFSDM1_CKIN6 -

PB10 - TIM2_CH3 - - I2C2_SCL SPI2_SCK

JTDO-

TRACESWO

TIM1/TIM2/ TIM5/TIM8/

LPTIM1

TIM2_CH2 - - - SPI1_SCK SPI3_SCK

TIM1/TIM2/ TIM3/TIM4/

TIM5

TIM8 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3/DFSDM

DFSDM1_

DATIN0

DFSDM1_

DATIN5

DFSDM1_

DATIN6

DFSDM1_

DATIN7

USART1/ USART2/

USART3

USART3_RTS_

USART1_RTS_

USART1_TX

USART3_TX

PB11 - TIM2_CH4 - - I2C2_SDA - DFSDM1_CKIN7 USART3_RX

PB12 - TIM1_BKIN -

PB13 - TIM1_CH1N - - I2C2_SCL SPI2_SCK DFSDM1_CKIN1 USART3_CTS

PB14 - TIM1_CH2N - TIM8_CH2N I2C2_SDA SPI2_MISO

PB15 RTC_REFIN TIM1_CH3N - TIM8_CH3N - SPI2_MOSI DFSDM1_CKIN2 -

TIM1_BKIN_

COMP2

I2C2_SMBA SPI2_NSS

DFSDM1_

DATIN1

DFSDM1_

DATIN2

USART3_CK

USART3_RTS_

Page 94

94/270 DS10198 Rev 8

Table 17. Alternate function AF0 to AF7

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

(1)

(continued)

Pinouts and pin description STM32L476xx

Port C

Port

SYS_AF

PC0 - LPTIM1_IN1 - - I2C3_SCL -

PC1 - LPTIM1_OUT - - I2C3_SDA - DFSDM1_CKIN4 -

PC2 - LPTIM1_IN2 - - - SPI2_MISO

PC3 - LPTIM1_ETR - - - SPI2_MOSI - -

PC4------ -USART3_TX

PC5------ -USART3_RX

PC6 - - TIM3_CH1 TIM8_CH1 - - DFSDM1_CKIN3 -

PC7 - - TIM3_CH2 TIM8_CH2 - -

PC8 - - TIM3_CH3 TIM8_CH3 - - - -

PC9 - TIM8_BKIN2 TIM3_CH4 TIM8_CH4 - - - -

PC10------SPI3_SCKUSART3_TX

TIM1/TIM2/ TIM5/TIM8/

LPTIM1

TIM1/TIM2/ TIM3/TIM4/

TIM5

TIM8 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3/DFSDM

DFSDM1_

DATIN4

DFSDM1_

CKOUT

DFSDM1_

DATIN3

USART1/ USART2/

USART3

PC11------SPI3_MISOUSART3_RX

PC12------SPI3_MOSIUSART3_CK

PC13------ - -

PC14------ - -

PC15------ - -

Page 95

Table 17. Alternate function AF0 to AF7

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

(1)

(continued)

STM32L476xx Pinouts and pin description

DS10198 Rev 8 95/270

Port D

Port

SYS_AF

PD0-----SPI2_NSS

PD1-----SPI2_SCKDFSDM1_CKIN7-

PD2 - - TIM3_ETR - - - -

PD3-----SPI2_MISO

PD4-----SPI2_MOSIDFSDM1_CKIN0

PD5------ -USART2_TX

PD6------

PD7------DFSDM1_CKIN1USART2_CK

PD8------ -USART3_TX

PD9------ -USART3_RX

TIM1/TIM2/ TIM5/TIM8/

LPTIM1

TIM1/TIM2/ TIM3/TIM4/

TIM5

TIM8 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3/DFSDM

DFSDM1_

DATIN7

DFSDM1_

DATIN0

DFSDM1_

DATIN1

USART1/ USART2/

USART3

USART3_RTS_

USART2_CTS

USART2_RTS_

USART2_RX

PD10------ -USART3_CK

PD11------ -USART3_CTS

PD12 - - TIM4_CH1 - - - -

PD13 - - TIM4_CH2 - - - - -

PD14 - - TIM4_CH3 - - - - -

PD15 - - TIM4_CH4 - - - - -

USART3_RTS_

Page 96

96/270 DS10198 Rev 8

Table 17. Alternate function AF0 to AF7

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

(1)

(continued)

Pinouts and pin description STM32L476xx

Port E

Port

SYS_AF

PE0--TIM4_ETR--- - -

PE1------ - -

PE2 TRACECK - TIM3_ETR - - - - -

PE3 TRACED0 - TIM3_CH1 - - - - -

PE4 TRACED1 - TIM3_CH2 - - -

PE5 TRACED2 - TIM3_CH3 - - - DFSDM1_CKIN3 -

PE6 TRACED3 - TIM3_CH4 - - - - -

PE7-TIM1_ETR----

PE8-TIM1_CH1N----DFSDM1_CKIN2-

PE9-TIM1_CH1----

PE10-TIM1_CH2N----

PE11-TIM1_CH2----

PE12 - TIM1_CH3N - - - SPI1_NSS

TIM1/TIM2/ TIM5/TIM8/

LPTIM1

TIM1/TIM2/ TIM3/TIM4/

TIM5

TIM8 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3/DFSDM

DFSDM1_

DATIN3

DFSDM1_

DATIN2

DFSDM1_

CKOUT

DFSDM1_

DATIN4

DFSDM1_

CKIN4

DFSDM1_

DATIN5

USART1/ USART2/

USART3

PE13 - TIM1_CH3 - - - SPI1_SCK DFSDM1_CKIN5 -

PE14 - TIM1_CH4 TIM1_BKIN2

PE15 - TIM1_BKIN -

TIM1_BKIN2_

COMP2

TIM1_BKIN_

COMP1

- SPI1_MISO - -

- SPI1_MOSI - -

Page 97

Table 17. Alternate function AF0 to AF7

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

(1)

(continued)

STM32L476xx Pinouts and pin description

DS10198 Rev 8 97/270

Port F

Port

SYS_AF

PF0----I2C2_SDA- - -

PF1----I2C2_SCL- - -

PF2----I2C2_SMBA- - -

PF3------ - -

PF4------ - -

PF5------ - -

PF6 - TIM5_ETR TIM5_CH1 - - - - -

PF7 - - TIM5_CH2 - - - - -

PF8 - - TIM5_CH3 - - - - -

PF9 - - TIM5_CH4 - - - - -

PF10------ - -

PF11------ - -

PF12------ - -

PF13------

TIM1/TIM2/ TIM5/TIM8/

LPTIM1

TIM1/TIM2/ TIM3/TIM4/

TIM5

TIM8 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3/DFSDM

DFSDM1_

DATIN6

USART1/ USART2/

USART3

PF14------DFSDM1_CKIN6-

PF15------ - -

Page 98

98/270 DS10198 Rev 8

Table 17. Alternate function AF0 to AF7

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

(1)

(continued)

Pinouts and pin description STM32L476xx

Port G

Port

SYS_AF

PG0------ - -

PG1------ - -

PG2-----SPI1_SCK- -

PG3-----SPI1_MISO- -

PG4-----SPI1_MOSI- -

PG5-----SPI1_NSS- -

PG6----I2C3_SMBA- - -

PG7----I2C3_SCL- - -

PG8----I2C3_SDA- - -

PG9------SPI3_SCKUSART1_TX

PG10-LPTIM1_IN1----SPI3_MISOUSART1_RX

PG11-LPTIM1_IN2----SPI3_MOSIUSART1_CTS

PG12-LPTIM1_ETR----SPI3_NSS

TIM1/TIM2/ TIM5/TIM8/

LPTIM1

TIM1/TIM2/ TIM3/TIM4/

TIM5

TIM8 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3/DFSDM

USART1/ USART2/

USART3

USART1_RTS_

PG13----I2C1_SDA- -USART1_CK

PG14----I2C1_SCL- - -

PG15 - LPTIM1_OUT - - I2C1_SMBA - - -

Port H

1. Please refer to Table 18 for AF8 to AF15.

PH0------ - -

PH1------ - -

Page 99

Table 18. Alternate function AF8 to AF15

(1)

STM32L476xx Pinouts and pin description

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

DS10198 Rev 8 99/270

Port A

Port

UART4, UART5,

LPUART1

CAN1, TSC OTG_FS, QUADSPI LCD

SDMMC1, COMP1,

COMP2, FMC,

SWPMI1

SAI1, SAI2

TIM2, TIM15,

TIM16, TIM17,

LPTIM2

EVENTOUT

PA0 UART4_TX - - - - SAI1_EXTCLK TIM2_ETR EVENTOUT

PA1 UART4_RX - - LCD_SEG0 - - TIM15_CH1N EVENTOUT

PA2 - - - LCD_SEG1 - SAI2_EXTCLK TIM15_CH1 EVENTOUT

PA3 - - - LCD_SEG2 - - TIM15_CH2 EVENTOUT

PA4 - - - - - SAI1_FS_B LPTIM2_OUT EVENTOUT

PA5 - - - - - - LPTIM2_ETR EVENTOUT

PA6 - - QUADSPI_BK1_IO3 LCD_SEG3

TIM1_BKIN_

COMP2

TIM8_BKIN_

COMP2

TIM16_CH1 EVENTOUT

PA7 - - QUADSPI_BK1_IO2 LCD_SEG4 - - TIM17_CH1 EVENTOUT

PA8 - - OTG_FS_SOF LCD_COM0 - - LPTIM2_OUT EVENTOUT

PA9 - - - LCD_COM1 - - TIM15_BKIN EVENTOUT

PA10 - - OTG_FS_ID LCD_COM2 - - TIM17_BKIN EVENTOUT

PA11 - CAN1_RX OTG_FS_DM -

TIM1_BKIN2_

COMP1

- - EVENTOUT

PA12 - CAN1_TX OTG_FS_DP - - - - EVENTOUT

PA13 - - OTG_FS_NOE - - - - EVENTOUT

PA14 - - - - - - - EVENTOUT

PA1 5

UART4_RTS

_DE

TSC_G3_IO1 - LCD_SEG17 - SAI2_FS_B - EVENTOUT

Page 100

100/270 DS10198 Rev 8

Table 18. Alternate function AF8 to AF15

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

(1)

(continued)

Pinouts and pin description STM32L476xx

Port B

Port

PB0 - - QUADSPI_BK1_IO1 LCD_SEG5 COMP1_OUT - - EVENTOUT

PB1 - - QUADSPI_BK1_IO0 LCD_SEG6 - - LPTIM2_IN1 EVENTOUT

PB2 - - - - - - - EVENTOUT

PB3 - - - LCD_SEG7 - SAI1_SCK_B - EVENTOUT

PB4

PB5 UART5_CTS TSC_G2_IO2 - LCD_SEG9 COMP2_OUT SAI1_SD_B TIM16_BKIN EVENTOUT

PB6 - TSC_G2_IO3 - -

PB7 UART4_CTS TSC_G2_IO4 - LCD_SEG21 FMC_NL

PB8 - CAN1_RX - LCD_SEG16 SDMMC1_D4

PB9 - CAN1_TX - LCD_COM3 SDMMC1_D5 SAI1_FS_A TIM17_CH1 EVENTOUT

PB10

PB11 LPUART1_TX - QUADSPI_NCS LCD_SEG11 COMP2_OUT - - EVENTOUT

UART4, UART5,

LPUART1

UART5_RTS

_DE

LPUART1_

CAN1, TSC OTG_FS, QUADSPI LCD

TSC_G2_IO1 - LCD_SEG8 -

- QUADSPI_CLK LCD_SEG10 COMP1_OUT SAI1_SCK_A - EVENTOUT

SDMMC1, COMP1,

COMP2, FMC,

SWPMI1

TIM8_BKIN2_

COMP2

TIM2, TIM15,

SAI1, SAI2

SAI1_MCLK_

SAI1_FS_B TIM16_CH1N EVENTOUT

TIM8_BKIN_

COMP1

SAI1_MCLK_

TIM16, TIM17,

LPTIM2

TIM17_BKIN EVENTOUT

TIM17_CH1N EVENTOUT

TIM16_CH1 EVENTOUT

EVENTOUT

PB12

PB13

PB14 - TSC_G1_IO3 - LCD_SEG14 SWPMI1_RX

PB15 - TSC_G1_IO4 - LCD_SEG15 SWPMI1_SUSPEND SAI2_SD_A TIM15_CH2 EVENTOUT

LPUART1_

RTS_DE

LPUART1_

CTS

TSC_G1_IO1 - LCD_SEG12 SWPMI1_IO SAI2_FS_A TIM15_BKIN EVENTOUT

TSC_G1_IO2 - LCD_SEG13 SWPMI1_TX SAI2_SCK_A TIM15_CH1N EVENTOUT

SAI2_MCLK_

TIM15_CH1 EVENTOUT