ST MICROELECTRONICS STM32L431CBT6 Datasheet

STM32L431xx

UFBGA100 (7×7)

LQFP64 (10x10)

UFBGA64 (5x5)

LQFP48 (7x7)

LQFP100 (14x14)

WLCSP64

UFQFPN32 (5x5)

WLCSP49UFQFPN48 (7x7)

Ultra-low-power Arm® Cortex®-M4 32-bit MCU+FPU, 100DMIPS,

up to 256KB Flash, 64KB SRAM, analog, audio

Datasheet - production data

Features

• Ultra-low-power with FlexPowerControl
– 1.71 V to 3.6 V power supply
– -40 °C to 85/105/125 °C temperature range
– 200 nA in V

32x32-bit backup registers
– 8 nA Shutdown mode (5 wakeup pins)
– 28 nA Standby mode (5 wakeup pins)
– 280 nA Standby mode with RTC
– 1.0 µA Stop 2 mode, 1.28 µA with RTC
– 84 µA/MHz run mode
– Batch acquisition mode (BAM)
– 4 µs wakeup from Stop mode
– Brown out reset (BOR)
– Interconnect matrix

• Core: Arm

®

Adaptive real-time accelerator (ART
Accelerator™) allowing 0-wait-state execution
from Flash memory, frequency up to 80 MHz,
MPU, 100DMIPS and DSP instructions

• Performance benchmark
– 1.25 DMIPS/MHz (Drystone 2.1)
– 273.55 CoreMark

80 MHz)

• Energy benchmark
– 176.7 ULPBench

• Clock Sources
– 4 to 48 MHz crystal oscillator
– 32 kHz crystal oscillator for RTC (LSE)
– Internal 16 MHz factory-trimmed RC (±1%)
– Internal low-power 32 kHz RC (±5%)
– Internal multispeed 100 kHz to 48 MHz

oscillator, auto-trimmed by LSE (better than

±0.25 % accuracy)
– Internal 48 MHz with clock recovery
– 2 PLLs for system clock, audio, ADC

mode: supply for RTC and

BAT

32-bit Cortex®-M4 CPU with FPU,

®

(3.42 CoreMark/MHz @

®

score

• Up to 83 fast I/Os, most 5 V-tolerant

• RTC with HW calendar, alarms and calibration

• Up to 21 capacitive sensing channels: support

touchkey, linear and rotary touch sensors

• 11x timers: 1x 16-bit advanced motor-control,
1x 32-bit and 2x 16-bit general purpose, 2x 16­bit basic, 2x low-power 16-bit timers (available
in Stop mode), 2x watchdogs, SysTick timer

• Memories
– Up to 256 KB single bank Flash,

proprietary code readout protection

– 64 KB of SRAM including 16 KB with

hardware parity check

– Quad SPI memory interface

• Rich analog peripherals (independent supply)
– 1x 12-bit ADC 5 Msps, up to 16-bit with

hardware oversampling, 200 µA/Msps

– 2x 12-bit DAC output channels, low-power

sample and hold
– 1x operational amplifier with built-in PGA
– 2x ultra-low-power comparators

• 16x communication interfaces
– 1x SAI (serial audio interface)
–3x I2C FM+(1 Mbit/s), SMBus/PMBus
– 4x USARTs (ISO 7816, LIN, IrDA, modem)
– 1x LPUART (Stop 2 wake-up)
– 3x SPIs (and 1x Quad SPI)
– CAN (2.0B Active) and SDMMC interface
– SWPMI single wire protocol master I/F
– IRTIM (Infrared interface)

• 14-channel DMA controller

• True random number generator

• CRC calculation unit, 96-bit unique ID

May 2018 DS11453 Rev 3 1/208

This is information on a product in full production.

www.st.com

STM32L431xx

• Development support: serial wire debug
(SWD), JTAG, Embedded Trace Macrocell™

Table 1. Device summary

Reference Part numbers

STM32L431xx

STM32L431CC, STM32L431KC, STM32L431RC, STM32L431VC, STM32L431CB,
STM32L431KB, STM32L431RB

• All packages are ECOPACK2® compliant

2/208 DS11453 Rev 3

STM32L431xx Contents

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1 Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 17

3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.6 Firewall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.7 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.8 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 20

3.9 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.9.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.9.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.9.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.9.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.9.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.9.6 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.10 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.11 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.12 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.13 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.14 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.14.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 37

3.14.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 37

3.15 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.15.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.15.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.15.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.16 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

DS11453 Rev 3 3/208

6

Contents STM32L431xx

3.17 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.18 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.19 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.20 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.21 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.22 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.22.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.22.2 General-purpose timers (TIM2, TIM15, TIM16) . . . . . . . . . . . . . . . . . . . 44

3.22.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.22.4 Low-power timer (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . 44

3.22.5 Infrared interface (IRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.22.6 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.22.7 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.22.8 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.23 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 46

2

3.24 Inter-integrated circuit interface (I

C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.25 Universal synchronous/asynchronous receiver transmitter (USART) . . . 48

3.26 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 49

3.27 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.28 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.29 Single wire protocol master interface (SWPMI) . . . . . . . . . . . . . . . . . . . . 51

3.30 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.31 Secure digital input/output and MultiMediaCards Interface (SDMMC) . . . 52

3.32 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.33 Quad SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.34 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.34.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.34.2 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

4/208 DS11453 Rev 3

STM32L431xx Contents

6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 89

6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 89

6.3.4 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

6.3.6 Wakeup time from low-power modes and voltage scaling

transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 114

6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 119

6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

6.3.10 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

6.3.16 Extended interrupt and event controller input (EXTI) characteristics . . 137

6.3.17 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

6.3.18 Analog-to-Digital converter characteristics . . . . . . . . . . . . . . . . . . . . . 138

6.3.19 Digital-to-Analog converter characteristics . . . . . . . . . . . . . . . . . . . . . 151

6.3.20 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 156

6.3.21 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

6.3.22 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 159

6.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

6.3.24 V

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

BAT

6.3.25 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

6.3.26 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 164

DS11453 Rev 3 5/208

6

Contents STM32L431xx

7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

7.1 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

7.2 UFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

7.3 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

7.4 UFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

7.5 WLCSP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

7.6 WLCSP49 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

7.7 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

7.8 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

7.9 UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

7.10 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

7.10.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

7.10.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 204

8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

6/208 DS11453 Rev 3

STM32L431xx List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2. STM32L431xx family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . 13

Table 3. Access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 18

Table 4. STM32L431xx modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 5. Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 6. STM32L431xx peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 7. DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 8. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 9. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 10. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 11. I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 12. STM32L431xx USART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 13. SAI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 14. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 15. STM32L431xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 16. Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 17. Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 18. STM32L431xx memory map and peripheral register boundary addresses . . . . . . . . . . . . 81

Table 19. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 20. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 21. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 22. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 23. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 24. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 25. Embedded internal voltage reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 26. Current consumption in Run and Low-power run modes, code with data processing

running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . . 94

Table 27. Current consumption in Run and Low-power run modes, code with data processing

running from Flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 28. Current consumption in Run and Low-power run modes, code with data processing

running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 29. Typical current consumption in Run and Low-power run modes, with different codes

running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . . 97

Table 30. Typical current consumption in Run and Low-power run modes, with different codes

running from Flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 31. Typical current consumption in Run and Low-power run modes, with different codes

running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 32. Current consumption in Sleep and Low-power sleep modes, Flash ON . . . . . . . . . . . . . . 99

Table 33. Current consumption in Low-power sleep modes, Flash in power-down . . . . . . . . . . . . . 100

Table 34. Current consumption in Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 35. Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 36. Current consumption in Stop 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 37. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 38. Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 39. Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 40. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 41. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table 42. Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

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9

List of tables STM32L431xx

Table 43. Wakeup time using USART/LPUART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 44. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 45. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Table 46. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Table 47. LSE oscillator characteristics (f

= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

LSE

Table 48. HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Table 49.

MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Table 50. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Table 51. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Table 52. PLL, PLLSAI1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Table 53. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Table 54. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Table 55. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Table 56. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 57. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 58. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Table 59. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Table 60. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Table 61. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Table 62. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Table 63. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Table 64. EXTI Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Table 65. Analog switches booster characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Table 66. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Table 67. Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Table 68. ADC accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Table 69. ADC accuracy - limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Table 70. ADC accuracy - limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Table 71. ADC accuracy - limited test conditions 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Table 72. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Table 73. DAC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Table 74. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Table 75. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Table 76. OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Table 77. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Table 78. V
Table 79. V

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

BAT

charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

BAT

Table 80. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Table 81. IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Table 82. WWDG min/max timeout value at 80 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Table 83. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Table 84. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Table 85. Quad SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Table 86. QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Table 87. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Table 88. SD / MMC dynamic characteristics, VDD=2.7 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . 174

Table 89. eMMC dynamic characteristics, VDD = 1.71 V to 1.9 V . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Table 90. SWPMI electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Table 91. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Table 92. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid

array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

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STM32L431xx List of tables

Table 93. UFBGA100 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 181

Table 94. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Table 95. UFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Table 96. UFBGA64 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . 186

Table 97. WLCSP64 - 64-ball, 3.141 x 3.127 mm, 0.35 mm pitch wafer level chip scale

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Table 98. WLCSP64 recommended PCB design rules (0.35 mm pitch) . . . . . . . . . . . . . . . . . . . . . 189

Table 99. WLCSP49 - 49-ball, 3.141 x 3.127 mm, 0.4 mm pitch wafer level chip scale

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Table 100. WLCSP49 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . 193

Table 101. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Table 102. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Table 103. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Table 104. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Table 105. STM32L431xx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Table 106. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

DS11453 Rev 3 9/208

9

List of figures STM32L431xx

List of figures

Figure 1. STM32L431xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 2. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 3. Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 4. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 5. Voltage reference buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 6. STM32L431Vx LQFP100 pinout
Figure 7. STM32L431Vx UFBGA100 ballout
Figure 8. STM32L431Rx LQFP64 pinout
Figure 9. STM32L431Rx UFBGA64 ballout
Figure 10. STM32L431Rx WLCSP64 pinout
Figure 11. STM32L431Cx WLCSP49 pinout
Figure 12. STM32L431Cx LQFP48 pinout
Figure 13. STM32L431Cx UFQFPN48 pinout
Figure 14. STM32L431Kx UFQFPN32 pinout

Figure 15. STM32L431xx memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 16. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 17. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 18. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 19. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 20. VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 21. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figure 22. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 23. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 24. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 25. HSI16 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 26. Typical current consumption versus MSI frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Figure 27. HSI48 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Figure 28. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Figure 29. I/O AC characteristics definition

Figure 30. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Figure 31. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Figure 32. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Figure 33. 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Figure 34. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Figure 35. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Figure 36. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Figure 37. Quad SPI timing diagram - SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Figure 38. Quad SPI timing diagram - DDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Figure 39. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Figure 40. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Figure 41. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Figure 42. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Figure 43. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . 177

Figure 44. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat

recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Figure 45. LQFP100 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Figure 46. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid

array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

10/208 DS11453 Rev 3

STM32L431xx List of figures

Figure 47. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid

array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Figure 48. UFBGA100 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Figure 49. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 183

Figure 50. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package

recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Figure 51. LQFP64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Figure 52. UFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid

array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Figure 53. UFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid

array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Figure 54. UFBGA64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Figure 55. WLCSP64 - 64-ball, 3.141 x 3.127 mm, 0.35 mm pitch wafer level chip scale

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Figure 56. WLCSP64 - 64-ball, 3.141 x 3.127 mm, 0.35 mm pitch wafer level chip scale

package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Figure 57. WLCSP64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Figure 58. WLCSP49 - 49-ball, 3.141 x 3.127 mm, 0.4 mm pitch wafer level chip scale

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Figure 59. WLCSP49 - 49-ball, 3.141 x 3.127 mm, 0.4 mm pitch wafer level chip scale

package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Figure 60. WLCSP49 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Figure 61. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 194

Figure 62. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package

recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Figure 63. LQFP48 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Figure 64. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Figure 65. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat

package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Figure 66. UFQFPN48 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

Figure 67. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

Figure 68. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat

package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Figure 69. UFQFPN32 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Figure 70. LQFP64 P

max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

D

DS11453 Rev 3 11/208

11

Introduction STM32L431xx

1 Introduction

This datasheet provides the ordering information and mechanical device characteristics of

the STM32L431xx microcontrollers.

This document should be read in conjunction with the STM32L43xxx/44xxx/45xxx/46xxx

reference manual (RM0394). The reference manual is available from the

STMicroelectronics website www.st.com.

For information on the Arm

Reference Manual, available from the www.arm.com website.

®(a)

Cortex®-M4 core, please refer to the Cortex®-M4 Technical

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

12/208 DS11453 Rev 3

STM32L431xx Description

2 Description

The STM32L431xx devices are the ultra-low-power microcontrollers based on the high-

performance Arm

The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all

®

Arm

single-precision data-processing instructions and data types. It also implements a full

®

Cortex®-M4 32-bit RISC core operating at a frequency of up to 80 MHz.

set of DSP instructions and a memory protection unit (MPU) which enhances application

security.

The STM32L431xx devices embed high-speed memories (Flash memory up to 256 Kbyte,

64

Kbyte of SRAM), a Quad SPI flash memories interface (available on all packages) and
an extensive range of enhanced I/Os and peripherals connected to two APB buses, two
AHB buses and a 32-bit multi-AHB bus matrix.

The STM32L431xx devices embed several protection mechanisms for embedded Flash
memory and SRAM: readout protection, write protection, proprietary code readout
protection and Firewall.

The devices offer a fast 12-bit ADC (5 Msps), two comparators, one operational amplifier,
two DAC channels, an internal voltage reference buffer, a low-power RTC, one general­purpose 32-bit timer, one 16-bit PWM timer dedicated to motor control, four general-purpose
16-bit timers, and two 16-bit low-power timers.

In addition, up to 21 capacitive sensing channels are available.

They also feature standard and advanced communication interfaces.

• Three I2Cs

• Three SPIs

• Three USARTs and one Low-Power UART.

• One SAI (Serial Audio Interfaces)

• One SDMMC

• One CAN

• One SWPMI (Single Wire Protocol Master Interface)

The STM32L431xx operates in the -40 to +85 °C (+105 °C junction), -40 to +105 °C
(+125

°C junction) and -40 to +125 °C (+130 °C junction) temperature ranges from a 1.71 to

3.6

V power supply. A comprehensive set of power-saving modes allows the design of low-

power applications.

Some independent power supplies are supported: analog independent supply input for
ADC, DAC, OPAMP and comparators. A VBAT input allows to backup the RTC and backup
registers.

The STM32L431xx family offers nine packages from 32 to 100-pin packages.

Table 2. STM32L431xx family device features and peripheral counts

Peripheral STM32L431Vx STM32L431Rx STM32L431Cx STM32L431Kx

Flash memory 256KB 128KB 256KB 128KB 256KB 128KB 256KB

SRAM 64KB

Quad SPI Yes

DS11453 Rev 3 13/208

54

Description STM32L431xx

Table 2. STM32L431xx family device features and peripheral counts (continued)

Peripheral STM32L431Vx STM32L431Rx STM32L431Cx STM32L431Kx

Timers

Comm.
interfaces

Advanced
control

General
purpose

1 (16-bit)

2 (16-bit)
1 (32-bit)

Basic 2 (16-bit)

Low ­power

SysTick
timer

2 (16-bit)

1

Watchdog
timers
(indepen

2
dent,
window)

SPI 3 2

2

C3 2

I

USART
LPUART

3
1

2
1

SAI 1

CAN 1

SDMMC Yes No

SWPMI Yes

RTC Yes

Tamper pins 3 2 2 1

Random generator Yes

GPIOs
Wakeup pins

Capacitive sensing
Number of channels

12-bit ADC
Number of channels

83

5

52

38 or 39

4

21 12 6 3

1

16

1

16

(1)

3

1

10

12-bit DAC channels 2

Internal voltage
reference buffer

Yes

No

Analog comparator 2

Operational
amplifiers

1

Max. CPU frequency 80 MHz

Operating voltage 1.71 to 3.6 V

26

2

1

10

14/208 DS11453 Rev 3

STM32L431xx Description

Table 2. STM32L431xx family device features and peripheral counts (continued)

Peripheral STM32L431Vx STM32L431Rx STM32L431Cx STM32L431Kx

Operating
temperature

Packages

1. For WLCSP49 package.

Ambient operating temperature: -40 to 85 °C / -40 to 105 °C / -40 to 125 °C

Junction temperature: -40 to 105 °C / -40 to 125 °C / -40 to 130 °C

LQFP100

UFBGA100

WLCSP64

LQFP64

UFBGA64

WLCSP49

LQFP48

UFQFPN48

UFQFPN32

DS11453 Rev 3 15/208

54

Description STM32L431xx

MSv39204V2

Flash

up to

256 KB

GPIO PORT A

AHB/APB2

EXT IT. WKUP

83 AF

PA[15:0]

TIM1 / PWM

3 compl. channels (TIM1_CH[1:3]N),

4 channels (TIM1_CH[1:4]),

ETR, BKIN, BKIN2 as AF

USART1

RX, TX, CK,CTS,

RTS as AF

SPI1

MOSI, MISO,

SCK, NSS as AF

APB260 M Hz

APB1 30MHz

OUT1

ITF

WWDG

RTC_TS

OSC32_IN

OSC32_OUT

smcard

IrDA

16b

SDIO / MMC

D[7:0]

CMD, CK as AF

VBAT = 1.55 to 3.6 V

JTAG & SW

ARM Cortex-M4

80 MHz

FPU

NVIC

ETM

MPU

DMA2

ART

ACCEL/

CACHE

RNG

FIFO

@ VDDA

BOR

Supply

supervision

PVD, PVM

Int

reset

XTAL 32 kHz

MAN AGT

RTC

FCLK

Standby

interface

IWDG

@VBAT

@ VDD

@VDD

AWU

Reset & clock

control

PCLKx

Voltage

regulator

3.3 to 1.2 V

VDD

Power management

@ VDD

RTC_TAMPx

Backup register

AHB bus-matrix

TIM15

2 channels,

1 compl. channel, BKIN as AF

DAC1

DAC2

TIM6

TIM7

TIM2

D-BUS

SRAM 48 KB

APB1 80 MHz (max)

SRAM 16 KB

I-BUS

S-BUS

DMA1

PB[15:0]

PC[15:0]

PD[15:0]

PE[15:0]

PH[1:0],

PH[3]

GPIO PORT B

GPIO PORT C

GPIO PORT D

GPIO PORT E

GPIO PORT H

16b

TIM16

16b

1 channel,

1 compl. channel, BKIN as AF

OUT2

16b

16b

32b

4 channels, ETR as AF

AHB/APB1

OSC_IN

OSC_OUT

HCLKx

XTAL OSC

4- 16MHz

16 external analog inputs

VREF+

USAR T 2M Bps

Temperature sensor

@ VDDA

SAI1

MCLK_A, SD_A, FS_A, SCK_A, EXTCLK

MCLK_B, SD_B, FS_B, SCK_B as AF

Touch sensing controller

7 Groups of

3 channels max as AF

RC HSI

RC LSI

PLL 1&2

MSI

Quad SPI memory interface

D0[3:0],
D1[3:0],
CLK0,
CLK1
CS

COMP1

INP, INM, OUT

COMP2

INP, INM, OUT

@ VDDA

RTC_OUT

AHB1 80 MHz

CRC

APB2 80MHz

AHB2 80 MHz

FIREWALL

VREF Buffer

@ VDDA

@ VDD

VDD = 1.71 to 3.6 V
VSS

TRACECLK

TRACED[3:0]

NJTRST, JTDI,

JTCK/SWCLK

JTDO/SWD, JTDO

ITF

ADC1

HSI48

VDDA, VSSA

VDD, VSS, NRST

CRS

CRS_SYNC

USART2

RX, TX, CK, CTS, RTS as AF

smcard

IrDA

USART3

RX, TX, CK, CTS, RTS as AF

smcard

IrDA

MOSI, MISO, SCK, NSS as AF

SPI2

MOSI, MISO, SCK, NSS as AF

SPI3

I2C1/SMBUS

SCL, SDA, SMBA as AF

SCL, SDA, SMBA as AF

I2C2/SMBUS

SCL, SDA, SMBA as AF

I2C3/SMBUS

FIFO

TX, RX as AF

bxCAN1

VOUT, VINM, VINP

OpAmp1

@VDDA

LPUART1

RX, TX, CTS, RTS as AF

SWPMI1

IO
RX, TX, SUSPEND as AF

LPTIM1

IN1, IN2, OUT, ETR as AF

LPTIM2

IN1, OUT, ETR as AF

Figure 1. STM32L431xx block diagram

Note: AF: alternate function on I/O pins.

16/208 DS11453 Rev 3

STM32L431xx Functional overview

3 Functional overview

3.1 Arm® Cortex®-M4 core with FPU

The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm® processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.

The Arm® Cortex®-M4 with FPU 32-bit RISC processor features exceptional code­efficiency, delivering the high-performance expected from an Arm
usually associated with 8- and 16-bit devices.

The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.

Its single precision FPU speeds up software development by using metalanguage
development tools, while avoiding saturation.

With its embedded Arm® core, the STM32L431xx family is compatible with all Arm® tools
and software.

Figure 1 shows the general block diagram of the STM32L431xx family devices.

®

core in the memory size

3.2 Adaptive real-time memory accelerator (ART Accelerator™)

The ART Accelerator™ is a memory accelerator which is optimized for STM32 industry­standard Arm
the Arm
processor to wait for the Flash memory at higher frequencies.

To release the processor near 100 DMIPS performance at 80MHz, the accelerator
implements an instruction prefetch queue and branch cache, which increases program
execution speed from the 64-bit Flash memory. Based on CoreMark benchmark, the
performance achieved thanks to the ART accelerator is equivalent to 0 wait state program
execution from Flash memory at a CPU frequency up to 80 MHz.

®

®

Cortex®-M4 processors. It balances the inherent performance advantage of

Cortex®-M4 over Flash memory technologies, which normally requires the

3.3 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4
gigabytes of addressable memory.

The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real­time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

DS11453 Rev 3 17/208

54

Functional overview STM32L431xx

3.4 Embedded Flash memory

STM32L431xx devices feature up to 256 Kbyte of embedded Flash memory available for
storing programs and data in single bank architecture. The Flash memory contains 128
pages of 2 Kbyte.

Flexible protections can be configured thanks to option bytes:

• Readout protection (RDP) to protect the whole memory. Three levels are available:

– Level 0: no readout protection

– Level 1: memory readout protection: the Flash memory cannot be read from or

written to if either debug features are connected, boot in RAM or bootloader is
selected

– Level 2: chip readout protection: debug features (Cortex-M4 JTAG and serial

wire), boot in RAM and bootloader selection are disabled (JTAG fuse). This
selection is irreversible.

Table 3. Access status versus readout protection level and execution modes

Area

Main

memory

System

memory

Option

bytes

Backup

registers

SRAM2

1. Erased when RDP change from Level 1 to Level 0.

Protection

level

1 Yes Yes Yes No No No

2 Yes Yes Yes N/A N/A N/A

1 Yes No No Yes No No

2 Yes No No N/A N/A N/A

1 Yes Yes Yes Yes Yes Yes

2 Yes No No N/A N/A N/A

1YesYesN/A

2 Yes Yes N/A N/A N/A N/A

1 Yes Yes Yes

2 Yes Yes Yes N/A N/A N/A

User execution

Read Write Erase Read Write Erase

(1)

(1)

Debug, boot from RAM or boot

from system memory (loader)

No No N/A

No No No

• Write protection (WRP): the protected area is protected against erasing and
programming. Two areas can be selected, with 2-Kbyte granularity.

• Proprietary code readout protection (PCROP): a part of the flash memory can be
protected against read and write from third parties. The protected area is execute-only:
it can only be reached by the STM32 CPU, as an instruction code, while all other
accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited.
The PCROP area granularity is 64-bit wide. An additional option bit (PCROP_RDP)
allows to select if the PCROP area is erased or not when the RDP protection is
changed from Level 1 to Level 0.

(1)

(1)

18/208 DS11453 Rev 3

STM32L431xx Functional overview

The whole non-volatile memory embeds the error correction code (ECC) feature supporting:

• single error detection and correction

• double error detection.

• The address of the ECC fail can be read in the ECC register

3.5 Embedded SRAM

STM32L431xx devices feature 64 Kbyte of embedded SRAM. This SRAM is split into two
blocks:

• 48 Kbyte mapped at address 0x2000 0000 (SRAM1)

• 16 Kbyte located at address 0x1000 0000 with hardware parity check (SRAM2).

This memory is also mapped at address 0x2000 C000, offering a contiguous address
space with the SRAM1 (16 Kbyte aliased by bit band)

This block is accessed through the ICode/DCode buses for maximum performance.
These 16 Kbyte SRAM can also be retained in Standby mode.

The SRAM2 can be write-protected with 1 Kbyte granularity.

The memory can be accessed in read/write at CPU clock speed with 0 wait states.

3.6 Firewall

The device embeds a Firewall which protects code sensitive and secure data from any
access performed by a code executed outside of the protected areas.

Each illegal access generates a reset which kills immediately the detected intrusion.

The Firewall main features are the following:

• Three segments can be protected and defined thanks to the Firewall registers:
– Code segment (located in Flash or SRAM1 if defined as executable protected

area)
– Non-volatile data segment (located in Flash)
– Volatile data segment (located in SRAM1)

• The start address and the length of each segments are configurable:
– Code segment: up to 1024 Kbyte with granularity of 256 bytes
– Non-volatile data segment: up to 1024 Kbyte with granularity of 256 bytes
– Volatile data segment: up to 48 Kbyte with a granularity of 64 bytes

• Specific mechanism implemented to open the Firewall to get access to the protected
areas (call gate entry sequence)

• Volatile data segment can be shared or not with the non-protected code

• Volatile data segment can be executed or not depending on the Firewall configuration

The Flash readout protection must be set to level 2 in order to reach the expected level of
protection.

DS11453 Rev 3 19/208

54

Functional overview STM32L431xx

3.7 Boot modes

At startup, BOOT0 pin or nSWBOOT0 option bit, and BOOT1 option bit are used to select
one of three boot options:

• Boot from user Flash

• Boot from system memory

• Boot from embedded SRAM

BOOT0 value may come from the PH3-BOOT0 pin or from an option bit depending on the
value of a user option bit to free the GPIO pad if needed.

A Flash empty check mechanism is implemented to force the boot from system flash if the
first flash memory location is not programmed and if the boot selection is configured to boot
from main flash.

The boot loader is located in system memory. It is used to reprogram the Flash memory by
using USART, I2C, SPI or CAN.

3.8 Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.

Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link­time and stored at a given memory location.

3.9 Power supply management

3.9.1 Power supply schemes

• VDD = 1.71 to 3.6 V: external power supply for I/Os (V
the system analog such as reset, power management and internal clocks. It is provided
externally through VDD pins.

• V

= 1.62 V (ADCs/COMPs) / 1.8 (DAC/OPAMP) to 3.6 V: external analog power

DDA

supply for ADCs, DAC, OPAMPs, Comparators and Voltage reference buffer. The V
voltage level is independent from the V

• V

= 1.55 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and

BAT

backup registers (through power switch) when V

Note: When the functions supplied by V

to V

.

DD

are not used, this supply should preferably be shorted

DDA

voltage.

DD

is not present.

DD

Note: If these supplies are tied to ground, the I/Os supplied by these power supplies are not 5 V

tolerant (refer to

Tabl e 19: Voltage characteristics).

), the internal regulator and

DDIO1

DDA

Note: V

V

20/208 DS11453 Rev 3

is the I/Os general purpose digital functions supply. V

DDIOx

= VDD.

DDIO1

represents V

DDIOx

DDIO1

, with

STM32L431xx Functional overview

MSv39205V2

Low voltage detector

V

DDA

V

DDA

domain

V

SS

V

DD

V

BAT

A/D converters
Comparators
D/A converters
Operational amplifiers
Voltage reference buffer

V

DD

domain

I/O ring

V

SSA

Reset block
Temp. sensor
PLL, HSI, MSI, HSI48

Standby circuitry
(Wakeup logic, IWDG)

Voltage regulator

V

DDIO1

LSE crystal 32 K osc
BKP registers
RCC BDCR register
RTC

Backup domain

Core
Memories
Digital peripherals

V

CORE

domain

V

CORE

Figure 2. Power supply overview

During power-up and power-down phases, the following power sequence requirements
must be respected:

• When VDD is below 1 V, other power supplies (V

) must remain below VDD +

DDA

300 mV.

• When V

is above 1 V, all power supplies are independent.

DD

During the power-down phase, VDD can temporarily become lower than other supplies only
if the energy provided to the MCU remains below 1

mJ; this allows external decoupling
capacitors to be discharged with different time constants during the power- down transient
phase.

DS11453 Rev 3 21/208

54

Functional overview STM32L431xx

MSv47490V1

0.3

1

V

BOR0

3.6

Operating modePower-on Power-down time

V

V

DDX

(1)

V

DD

Invalid supply area V

DDX

< V

DD

+ 300 mV

V

DDX

independent from V

DD

Figure 3. Power-up/down sequence

1. V

refers to V

DDX

DDA

.

3.9.2 Power supply supervisor

The device has an integrated ultra-low-power brown-out reset (BOR) active in all modes
except Shutdown and ensuring proper operation after power-on and during power down.
The device remains in reset mode when the monitored supply voltage V
specified threshold, without the need for an external reset circuit.

The lowest BOR level is 1.71V at power on, and other higher thresholds can be selected
through option bytes.The device features an embedded programmable voltage detector
(PVD) that monitors the V
interrupt can be generated when V
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.

In addition, the device embeds a Peripheral Voltage Monitor which compares the
independent supply voltage V
peripheral is in its functional supply range.

power supply and compares it to the VPVD threshold. An

DD

DDA

is below a

DD

drops below the VPVD threshold and/or when VDD is

DD

with a fixed threshold in order to ensure that the

22/208 DS11453 Rev 3

STM32L431xx Functional overview

3.9.3 Voltage regulator

Two embedded linear voltage regulators supply most of the digital circuitries: the main
regulator (MR) and the low-power regulator (LPR).

• The MR is used in the Run and Sleep modes and in the Stop 0 mode.

• The LPR is used in Low-Power Run, Low-Power Sleep, Stop 1 and Stop 2 modes. It is

also used to supply the 16 Kbyte SRAM2 in Standby with SRAM2 retention.

• Both regulators are in power-down in Standby and Shutdown modes: the regulator

output is in high impedance, and the kernel circuitry is powered down thus inducing
zero consumption.

The ultralow-power STM32L431xx supports dynamic voltage scaling to optimize its power
consumption in run mode. The voltage from the Main Regulator that supplies the logic
(V

There are two power consumption ranges:

• Range 1 with the CPU running at up to 80 MHz.

• Range 2 with a maximum CPU frequency of 26 MHz. All peripheral clocks are also

) can be adjusted according to the system’s maximum operating frequency.

CORE

limited to 26 MHz.

The V

can be supplied by the low-power regulator, the main regulator being switched

CORE

off. The system is then in Low-power run mode.

• Low-power run mode with the CPU running at up to 2 MHz. Peripherals with

independent clock can be clocked by HSI16.

3.9.4 Low-power modes

The ultra-low-power STM32L431xx supports seven low-power modes to achieve the best
compromise between low-power consumption, short startup time, available peripherals and
available wakeup sources.

DS11453 Rev 3 23/208

54

24/208 DS11453 Rev 3

Mode Regulator

(1)

Table 4. STM32L431xx modes overview

CPU Flash SRAM Clocks DMA & Peripherals

(2)

Wakeup source Consumption

(3)

Functional overview STM32L431xx

Wakeup time

Run

Yes O N

MR range2 All except RNG 84 µA/MHz

LPRun LPR Yes ON

MR range 1

MR range 1

Sleep

No ON

MR range2 All except RNG 26 µA/MHz

LPSleep LPR No ON

MR Range 1

Stop 0

No OFF ON

MR Range 2 108 µA

(4)

(4)

(4)

(4)

ON Any

ON

except

(5)

ON

(5)

ON

except

Any

PLL

Any

Any

PLL

LSE

LSI

All

97 µA/MHz

N/A

All except USB_FS, RNG N/A 94 µA/MHz

All

Any interrupt or

28 µA/MHz

event

All except USB_FS, RNG

Any interrupt or

event

29 µA/MHz 6 cycles

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1,2)

DAC1

OPAMPx (x=1)

USARTx (x=1...3)

LPUART1

I2Cx (x=1...3)

(6)

(6)

(7)

LPTIMx (x=1,2)

***

All other peripherals are

Reset pin, all I/Os

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1..2)

USARTx (x=1...3)

LPUART1

I2Cx (x=1...3)

(6)

(7)

LPTIMx (x=1,2)

SWPMI1

(8)

108 µA

(6)

frozen.

N/A

to Range 1: 4 µs

to Range 2: 64 µs

6 cycles

2.4 µs in SRAM

4.1 µs in Flash

DS11453 Rev 3 25/208

Table 4. STM32L431xx modes overview (continued)

Mode Regulator

Stop 1 LPR No Off ON

Stop 2 LPR No Off ON

(1)

CPU Flash SRAM Clocks DMA & Peripherals

LSE

LSI

LSE

LSI

(2)

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1,2)

DAC1

OPAMPx (x=1)

USARTx (x=1...3)

LPUART1

I2Cx (x=1...3)

(6)

(6)

(7)

LPTIMx (x=1,2)

***

All other peripherals are

frozen.

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1..2)

(7)

I2C3

LPUART1

(6)

LPTIM1

***

All other peripherals are

frozen.

Wakeup source Consumption

Reset pin, all I/Os

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1..2)

USARTx (x=1...3)

LPUART1

(6)

I2Cx (x=1...3)

4.34 µA w/o RTC

(6)

4.63 µA w RTC

(7)

LPTIMx (x=1,2)

SWPMI1

(8)

Reset pin, all I/Os

BOR, PVD, PVM

RTC, IWDG

COMPx (x=1..2)

(7)

I2C3

LPUART1

(6)

1.3 µA w/o RTC

1.4 µA w/RTC

LPTIM1

(3)

Wakeup time

6.3 µs in SRAM

7.8 µs in Flash

6.8 µs in SRAM

8.2 µs in Flash

STM32L431xx Functional overview

26/208 DS11453 Rev 3

Mode Regulator

(1)

Table 4. STM32L431xx modes overview (continued)

CPU Flash SRAM Clocks DMA & Peripherals

(2)

Wakeup source Consumption

(3)

Functional overview STM32L431xx

Wakeup time

Standby

LPR

OFF

Power
ed Off

Off

SRAM

2 ON

Power

ed

Off

LSE

LSI

BOR, RTC, IWDG

***

All other peripherals are

powered off.

***

I/O configuration can be

Reset pin
5 I/Os (WKUPx)
BOR, RTC, IWDG

0.20 µA w/o RTC

0.46 µA w/ RTC

(9)

0.03 µA w/o RTC

0.29 µA w/ RTC

floating, pull-up or pull-down

RTC

***

All other peripherals are

powered off.

***

Shutdown OFF

Power
ed Off

Off

Power

ed

Off

LSE

I/O configuration can be

floating, pull-up or pull-

1. LPR means Main regulator is OFF and Low-power regulator is ON.

2. All peripherals can be active or clock gated to save power consumption.

3. Typical current at V
LPRun/LPSleep.

4. The Flash memory can be put in power-down and its clock can be gated off when executing from SRAM.

5. The SRAM1 and SRAM2 clocks can be gated on or off independently.

6. U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event.

7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.

8. SWPMI1 wakeup by resume from suspend.

9. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5.

10. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode.

= 1.8 V, 25°C. Consumptions values provided running from SRAM, Flash memory Off, 80 MHz in Range 1, 26 MHz in Range 2, 2 MHz in

DD

down

(10)

Reset pin

5 I/Os (WKUPx)

RTC

0.01 µA w/o RTC

(9)

0.20 µA w/ RTC

12.2 µs

262 µs

STM32L431xx Functional overview

By default, the microcontroller is in Run mode after a system or a power Reset. It is up to the
user to select one of the low-power modes described below:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.

• Low-power run mode

This mode is achieved with V

supplied by the low-power regulator to minimize the

CORE

regulator's operating current. The code can be executed from SRAM or from Flash,
and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can
be clocked by HSI16.

• Low-power sleep mode

This mode is entered from the low-power run mode. Only the CPU clock is stopped.
When wakeup is triggered by an event or an interrupt, the system reverts to the low­power run mode.

• Stop 0, Stop 1 and Stop 2 modes

Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the V

domain are stopped, the PLL, the MSI

CORE

RC, the HSI16 RC and the HSE crystal oscillators are disabled. The LSE or LSI is still
running.

The RTC can remain active (Stop mode with RTC, Stop mode without RTC).

Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode
to detect their wakeup condition.

Three Stop modes are available: Stop 0, Stop 1 and Stop 2 modes. In Stop 2 mode,
most of the V

domain is put in a lower leakage mode.

CORE

Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller
wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator
remains ON, allowing a very fast wakeup time but with much higher consumption.

The system clock when exiting from Stop 0, Stop 1 or Stop 2 modes can be either MSI
up to 48 MHz or HSI16, depending on software configuration.

• Standby mode

The Standby mode is used to achieve the lowest power consumption with BOR. The
internal regulator is switched off so that the V

domain is powered off. The PLL, the

CORE

MSI RC, the HSI16 RC and the HSE crystal oscillators are also switched off.

The RTC can remain active (Standby mode with RTC, Standby mode without RTC).

The brown-out reset (BOR) always remains active in Standby mode.

The state of each I/O during standby mode can be selected by software: I/O with
internal pull-up, internal pull-down or floating.

After entering Standby mode, SRAM1 and register contents are lost except for registers
in the Backup domain and Standby circuitry. Optionally, SRAM2 can be retained in
Standby mode, supplied by the low-power Regulator (Standby with SRAM2 retention
mode).

The device exits Standby mode when an external reset (NRST pin), an IWDG reset,
WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm,
periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE).

The system clock after wakeup is MSI up to 8 MHz.

DS11453 Rev 3 27/208

54

Functional overview STM32L431xx

• Shutdown mode

The Shutdown mode allows to achieve the lowest power consumption. The internal
regulator is switched off so that the V

domain is powered off. The PLL, the HSI16,

CORE

the MSI, the LSI and the HSE oscillators are also switched off.

The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).

The BOR is not available in Shutdown mode. No power voltage monitoring is possible
in this mode, therefore the switch to Backup domain is not supported.

SRAM1, SRAM2 and register contents are lost except for registers in the Backup
domain.

The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin
event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic
wakeup, timestamp, tamper).

The system clock after wakeup is MSI at 4 MHz.

28/208 DS11453 Rev 3

STM32L431xx Functional overview

Table 5. Functionalities depending on the working mode

(1)

Stop 0/1 Stop 2 Standby Shutdown

Peripheral Run Sleep

Low-

power

run

Low-

power

sleep

VBAT

-

-

Wakeup capability

Wakeup capability

-

Wakeup capability

-

Wakeup capability

CPU Y - Y - - --------

Flash memory (up to
256 KB)

SRAM1 (48 KB) Y Y

SRAM2 (16 KB) Y Y

Quad SPI O O O O -

Backup Registers Y Y Y Y Y

Brown-out reset
(BOR)

(2)

O

(2)

O

(3)

(3)

(2)

O

YY

YY

(2)

O

(3)

(3)

- --------

Y -Y------

Y -Y-O

(4)

----

--------

-Y-Y-Y-Y

YYYYYYYYYY- --

Programmable
Voltage Detector

OOOOO

OOO- ----

(PVD)

Peripheral Voltage
Monitor (PVMx;

OOOOO

OOO- ----

x=1,3,4)

DMA OOOO-

--------

High Speed Internal
(HSI16)

OOOO

(5)

(5)

-

------

Oscillator RC48 O O - - - --------

High Speed External
(HSE)

Low Speed Internal
(LSI)

Low Speed External
(LSE)

Multi-Speed Internal
(MSI)

Clock Security
System (CSS)

Clock Security
System on LSE

OOOO-

OOOOO

OOOOO

OOOO-

OOOO-

OOOOO

--------

-O-O----

-O-O-O-O

--------

--------

OOOOO- --

RTC / Auto wakeup O O O O O OOOOOOOO

Number of RTC
Tamper pins

USARTx (x=1,2,3) O O O O O

33333O3O3O3O3

(6)O(6)

- ------

DS11453 Rev 3 29/208

54

Functional overview STM32L431xx

Table 5. Functionalities depending on the working mode

Stop 0/1 Stop 2 Standby Shutdown

Low-

Peripheral Run Sleep

power

run

Low-power UART
(LPUART)

OOOOO

I2Cx (x=1,2) O O O O O

I2C3 OOOOO

SPIx (x=1,2,3) O O O O -

CAN OOOO-

SDMMC1 O O O O -

SWPMI1 OOOO-

SAIx (x=1) O O O O -

ADCx (x=1) O O O O -

DAC1 O O O O O

Low-

power

sleep

-

(6)O(6)O(6)O(6)

(7)O(7)

(7)O(7)O(7)O(7)

--------

--------

--------

O- ------

--------

--------

--------

(1)

(continued)

-

Wakeup capability

Wakeup capability

-

Wakeup capability

-

Wakeup capability

- ----

- ------

- ----

VBAT

VREFBUF O O O O O

OPAMPx (x=1) O O O O O

COMPx (x=1,2) O O O O O

Temperature sensor O O O O -

Timers (TIMx) O O O O -

Low-power timer 1
(LPTIM1)

Low-power timer 2
(LPTIM2)

Independent
watchdog (IWDG)

Window watchdog
(WWDG)

OOOOO

OOOOO

OOOOO

OOOO-

--------

--------

OOO- ----

--------

--------

OOO- ----

O- ------

OOOOO- --

--------

SysTick timer O O O O - --------

Touch sensing
controller (TSC)

Random number
generator (RNG)

OOOO-

(8)

O

(8)

O

-----------

--------

CRC calculation unit O O O O - --------

GPIOs OOOOO

OOO

(9)

5

pins

(10)

(11)

5

pins

(10)

-

30/208 DS11453 Rev 3