ST MICROELECTRONICS STM32L152RET6 Datasheet

STM32L151xE STM32L152xE

LQFP144 (20 × 20 mm)
LQFP100 (14 × 14 mm)
LQFP64 (10 × 10 mm)

UFBGA132

(7 × 7 mm)

WLCSP104

(0.4 mm pitch)

Ultra-low-power 32-bit MCU Arm®-based Cortex®-M3 with 512KB

Flash, 80KB SRAM, 16KB EEPROM, LCD, USB, ADC, DAC

Datasheet - production data

Features

Includes ST state-of-the-art patented
technology

• Ultra-low-power platform
– 1.65 V to 3.6 V power supply
– -40 °C to 105 °C temperature range
– 290 nA Standby mode (3 wakeup pins)
– 1.11 µA Standby mode + RTC
– 560 nA Stop mode (16 wakeup lines)
– 1.4 µA Stop mode + RTC
– 11 µA Low-power run mode down to 4.6 µA

in Low-power sleep mode
– 195 µA/MHz Run mode
– 10 nA ultra-low I/O leakage
– 8 µs wakeup time

• Core: Arm

®

Cortex®-M3 32-bit CPU
– From 32 kHz up to 32 MHz max
– 1.25 DMIPS/MHz (Dhrystone 2.1)
– Memory protection unit

• Up to 34 capacitive sensing channels

• CRC calculation unit, 96-bit unique ID

• Reset and supply management

– Low-power, ultrasafe BOR (brownout reset)

with 5 selectable thresholds
– Ultra-low-power POR/PDR
– Programmable voltage detector (PVD)

• Clock sources
– 1 to 24 MHz crystal oscillator
– 32 kHz oscillator for RTC with calibration
– Internal 16 MHz oscillator factory trimmed

RC(+/-1%) with PLL option
– Internal low-power 37 kHz oscillator
– Internal multispeed low-power 65 kHz to

4.2 MHz oscillator

– PLL for CPU clock and USB (48 MHz)

• Pre-programmed bootloader

– USB and USART supported

• Up to 116 fast I/Os (102 I/Os 5V tolerant), all
mappable on 16 external interrupt vectors

• Memories
– 512 Kbytes of Flash memory with ECC

(with 2 banks of 256 Kbytes enabling RWW

capability)
– 80 Kbytes of RAM
– 16 Kbytes of true EEPROM with ECC
– 128-byte backup register

• LCD driver (except STM32L151xE devices) up
to 8x40 segments, contrast adjustment,
blinking mode, step-up converter

• Rich analog peripherals (down to 1.8 V)
– 2x operational amplifiers
– 12-bit ADC 1 Msps up to 40 channels
– 12-bit DAC 2 ch with output buffers
– 2x ultra-low-power comparators

(window mode and wake up capability)

• DMA controller 12x channels

• 11x peripheral communication interfaces

– 1x USB 2.0 (internal 48 MHz PLL)
– 5x USARTs
– Up to 8x SPIs (2x I2S, 3x 16 Mbit/s)
– 2x I

2

Cs (SMBus/PMBus)

• 11x timers: 1x 32-bit, 6x 16-bit with up to 4
IC/OC/PWM channels, 2x 16-bit basic timers,
2x watchdog timers (independent and window)

• Development support: serial wire debug, JTAG
and trace

April 2021 DS10002 Rev 10 1/136

This is information on a product in full production.

www.st.com

STM32L151xE STM32L152xE

Table 1. Device summary

Reference Part number

STM32L151xE STM32L151QE, STM32L151RE, STM32L151VE, STM32L151ZE

STM32L152xE STM32L152QE, STM32L152RE, STM32L152VE, STM32L152ZE

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STM32L151xE STM32L152xE Contents

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

2.2 Ultra-low-power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.2.1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.2.2 Shared peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.2.3 Common system strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.2.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.1 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

®

3.2 Arm

Cortex®-M3 core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.3 Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.3.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.3.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.3.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.3.4 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.4 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.5 Low-power real-time clock and backup registers . . . . . . . . . . . . . . . . . . . 23

3.6 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.7 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.8 DMA (direct memory access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.9 LCD (liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.10 ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.10.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.10.2 Internal voltage reference (V

) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

REFINT

3.11 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.12 Operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.13 Ultra-low-power comparators and reference voltage . . . . . . . . . . . . . . . . 27

3.14 System configuration controller and routing interface . . . . . . . . . . . . . . . 27

3.15 Touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

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Contents STM32L151xE STM32L152xE

3.16 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.16.1 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM9, TIM10 and

TIM11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.16.2 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.16.3 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.16.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.16.5 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.17 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.17.1 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.17.2 Universal synchronous/asynchronous receiver transmitter (USART) . . 29

3.17.3 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.17.4 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.17.5 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.18 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 30

3.19 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.19.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.19.2 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6.1.7 Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

6.1.8 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

6.3.2 Embedded reset and power control block characteristics . . . . . . . . . . . 62

6.3.3 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 64

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6.3.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

6.3.5 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

6.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

6.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

6.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

6.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

6.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

6.3.11 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

6.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

6.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

6.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

6.3.15 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

6.3.16 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

6.3.17 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

6.3.18 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

6.3.19 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 110

6.3.20 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

6.3.21 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

6.3.22 LCD controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

7.1 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

7.2 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118

7.3 WLCSP104 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

7.4 UFBGA132 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

7.5 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

7.6 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

7.6.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

9 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

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5

List of tables STM32L151xE STM32L152xE

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2. Ultra-low-power STM32L151xE and STM32L152xE device features and peripheral

counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 3. Functionalities depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . 15

Table 4. CPU frequency range depending on dynamic voltage scaling . . . . . . . . . . . . . . . . . . . . . . 16

Table 5. Functionalities depending on the working mode (from Run/active down to

standby) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 6. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 7. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 8. STM32L151xE and STM32L152xE pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 9. Alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 10. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 11. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 12. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 13. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 14. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 15. Embedded internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 16. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 17. Current consumption in Run mode, code with data processing running from Flash. . . . . . 66

Table 18. Current consumption in Run mode, code with data processing running from RAM . . . . . . 67

Table 19. Current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 20. Current consumption in Low-power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 21. Current consumption in Low-power sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 22. Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 23. Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 73

Table 24. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 25. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 26. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 27. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 28. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 29. LSE oscillator characteristics (f

Table 30. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 31. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 32. MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 33. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 34. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 35. Flash memory and data EEPROM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 36. Flash memory and data EEPROM endurance and retention . . . . . . . . . . . . . . . . . . . . . . . 86

Table 37. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 38. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 39. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 40. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 41. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 42. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 43. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 44. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 45. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 46. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

LSE

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Table 47. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 48. SCL frequency (f

= 32 MHz, VDD = VDD_I2C = 3.3 V). . . . . . . . . . . . . . . . . . . . . . . . 96

PCLK1

Table 49. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 50. USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 51. USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 52. USB: full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 53. I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Table 54. ADC clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 55. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 56. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 57. Maximum source impedance R

max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

AIN

Table 58. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 59. Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Table 60. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Table 61. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Table 62. Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Table 63. Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 64. LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 65. LQFP64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Table 66. LQPF100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Table 67. WLCSP104 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 68. WLCSP104 recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Table 69. UFBGA132 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Table 70. LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Table 71. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Table 72. STM32L151xE and STM32L152xE Ordering information scheme. . . . . . . . . . . . . . . . . . 132

Table 73. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

DS10002 Rev 10 7/136

7

List of figures STM32L151xE STM32L152xE

List of figures

Figure 1. Ultra-low-power STM32L151xE and STM32L152xE block diagram. . . . . . . . . . . . . . . . . . 13

Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 3. STM32L15xRE LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 4. STM32L15xVE LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 5. STM32L15xVEY WLCSP104 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 6. STM32L15xQE UFBGA132 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 7. STM32L15xZE LQFP144 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 8. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 9. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 10. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 11. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 12. Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 13. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 14. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 15. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 16. HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 17. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 18. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 19. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 20. I

Figure 21. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Figure 22. SPI timing diagram - slave mode and CPHA = 1
Figure 23. SPI timing diagram - master mode

Figure 24. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 25. I
Figure 26. I

Figure 27. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 28. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 29. Maximum dynamic current consumption on V

Figure 30. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Figure 31. LQFP64 outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 32. LQFP64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 33. LQFP64 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 34. LQFP100 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 35. LQFP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 36. LQFP100 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 37. WLCSP104 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 38. WLCSP104 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Figure 39. WLCSP104 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Figure 40. UFBGA132 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 41. UFBGA132 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Figure 42. UFBGA132 top view example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Figure 43. LQFP144 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Figure 44. LQFP144 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Figure 45. LQFP144 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Figure 46. Thermal resistance suffix 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Figure 47. Thermal resistance suffix 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

2

C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

(1)

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

2

S slave timing diagram (Philips protocol)

2

S master timing diagram (Philips protocol)

(1)

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

supply pin during ADC

REF+

conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

8/136 DS10002 Rev 10

STM32L151xE STM32L152xE Introduction

1 Introduction

This datasheet provides the ordering information and mechanical device characteristics of

the STM32L151xE and STM32L152xE ultra-low-power Arm

®

Cortex®-M3 based
microcontroller product line. STM32L151xE and STM32L152xE devices are
microcontrollers with a Flash memory density of 512

Kbytes.

The ultra-low-power STM32L151xE and STM32L152xE family includes devices in 5
different package types: from 64 pins to 144 pins. Depending on the device chosen,
different sets of peripherals are included, the description below gives an overview of the
complete range of peripherals proposed in this family.

These features make the ultra-low-power STM32L151xE and STM32L152xE
microcontroller family suitable for a wide range of applications:

• Medical and handheld equipment

• Application control and user interface

• PC peripherals, gaming, GPS and sport equipment

• Alarm systems, wired and wireless sensors, video intercom

• Utility metering

This STM32L151xE and STM32L152xE datasheet must be read in conjunction with the
STM32L1xxxx reference manual (RM0038). The application note “Getting started with
STM32L1xxxx hardware development” (AN3216) gives a hardware implementation
overview. Both documents are available from the STMicroelectronics website www.st.com.

For information on the Arm

®(a)

Cortex®-M3 core, refer to the Arm® Cortex®-M3 technical
reference manual, available from the www.arm.com website. Figure 1 shows the general
block diagram of the device family.

For information on the device errata with respect to the datasheet and reference manual,
refer to the STM32L15xE errata sheet (ES0235), available on the STMicroelectronics
website www.st.com.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

DS10002 Rev 10 9/136

56

Description STM32L151xE STM32L152xE

2 Description

The ultra-low-power STM32L151xE and STM32L152xE devices incorporate the
connectivity power of the universal serial bus (USB) with the high-performance Arm

®

Cortex
protection unit (MPU), high-speed embedded memories (Flash memory up to 512
and RAM up to 80 Kbytes), and an extensive range of enhanced I/Os and peripherals
connected to two APB buses.

The STM32L151xE and STM32L152xE devices offer two operational amplifiers, one 12-bit
ADC, two DACs, two ultra-low-power comparators, one general-purpose 32-bit timer, six
general-purpose 16-bit timers and two basic timers, which can be used as time bases.

Moreover, the STM32L151xE and STM32L152xE devices contain standard and advanced
communication interfaces: up to two I2Cs, three SPIs, two I2S, three USARTs, two UARTs
and an USB. The STM32L151xE and STM32L152xE devices offer up to 34
sensing channels to simply add a touch sensing functionality to any application.

They also include a real-time clock and a set of backup registers that remain powered in
Standby mode.

Finally, the integrated LCD controller (except STM32L151xE devices) has a built-in LCD
voltage generator that allows to drive up to 8 multiplexed LCDs with the contrast
independent of the supply voltage.

The ultra-low-power STM32L151xE and STM32L152xE devices operate from a 1.8 to 3.6 V
power supply (down to 1.65
supply without BOR option. They are available in the -40 to +85 °C and -40 to +105 °C
temperature ranges. A comprehensive set of power-saving modes allows the design of low­power applications.

-M3 32-bit RISC core operating at a frequency of 32 MHz (33.3 DMIPS), a memory

capacitive

V at power down) with BOR and from a 1.65 to 3.6 V power

®

Kbytes

10/136 DS10002 Rev 10

STM32L151xE STM32L152xE Description

2.1 Device overview

Table 2. Ultra-low-power STM32L151xE and STM32L152xE device features and peripheral

Flash (Kbytes) 512

Data EEPROM (Kbytes) 16

RAM (Kbytes) 80

counts

Peripheral STM32L15xRE STM32L15xVE STM32L15xQE STM32L15xZE

32 bit 1

Timers

General-purpose 6

Basic 2

SPI 8(3)

(1)

I2S 2

Communication
interfaces

2

I

C 2

USART 5

USB 1

GPIOs 51 83 109 115

Operational amplifiers 2

12-bit synchronized ADC
Number of channels

12-bit DAC
Number of channels

(2)

LCD
COM x SEG

1

21

1

4x32 or 8x28

25

1

40

1

1

40

2
2

1

4x44 or 8x40

Comparators 2

Capacitive sensing channels 23 33 34

Max. CPU frequency 32 MHz

Operating voltage

Operating temperatures

Packages LQFP64

1. 5 SPIs are USART configured in synchronous mode emulating SPI master.

2. STM32L152xx devices only.

1.8 V to 3.6 V (down to 1.65 V at power-down) with BOR option

1.65 V to 3.6 V without BOR option

Ambient operating temperature: -40 °C to 85 °C / -40 °C to 105 °C

Junction temperature: –40 to + 110 °C

LQFP100,

WLCSP104

UFBGA132 LQFP144

DS10002 Rev 10 11/136

56

Description STM32L151xE STM32L152xE

2.2 Ultra-low-power device continuum

The ultra-low-power family offers a large choice of cores and features. From proprietary 8­bit to up to Cortex-M3, including the Cortex-M0+, the STM32Lx series are the best choice to
answer the user needs, in terms of ultra-low-power features. The STM32 ultra-low-power
series are the best fit, for instance, for gas/water meter, keyboard/mouse or fitness and
healthcare, wearable applications. Several built-in features like LCD drivers, dual-bank
memory, Low-power run mode, op-amp, AES 128-bit, DAC, USB crystal-less and many
others clearly allow very cost-optimized applications to be built by reducing BOM.

Note: STMicroelectronics as a reliable and long-term manufacturer ensures as much as possible

the pin-to-pin compatibility between any STM8Lxxxxx and STM32Lxxxxx devices and
between any of the STM32Lx and STM32Fx series. Thanks to this unprecedented
scalability, the old applications can be upgraded to respond to the latest market features and
efficiency demand.

2.2.1 Performance

All the families incorporate highly energy-efficient cores with both Harvard architecture and
pipelined execution: advanced STM8 core for STM8L families and Arm Cortex-M3 core for
STM32L family. In addition specific care for the design architecture has been taken to
optimize the mA/DMIPS and mA/MHz ratios.

This allows the ultra-low-power performance to range from 5 up to 33.3 DMIPs.

2.2.2 Shared peripherals

STM8L15xxx, STM32L15xxx and STM32L162xx share identical peripherals which ensure a
very easy migration from one family to another:

• Analog peripherals: ADC, DAC and comparators

• Digital peripherals: RTC and some communication interfaces

2.2.3 Common system strategy.

To offer flexibility and optimize performance, the STM8L15xxx, STM32L15xxx and
STM32L162xx family uses a common architecture:

• Same power supply range from 1.65 V to 3.6 V

• Architecture optimized to reach ultra-low consumption both in low-power modes and

Run mode

• Fast startup strategy from low-power modes

• Flexible system clock

• Ultrasafe reset: same reset strategy including power-on reset, power-down reset,

brownout reset and programmable voltage detector

2.2.4 Features

ST ultra-low-power continuum also lies in feature compatibility:

• More than 15 packages with pin count from 20 to 144 pins and size down to 3 x 3 mm

• Memory density ranging from 2 to 512 Kbytes

12/136 DS10002 Rev 10

STM32L151xE STM32L152xE Functional overview

MSv34186V1

POWER

VOLT. REG.

12bit ADC

EXT.IT
WKUP

WinWATCHDOG

JTAG & SW

Fmax: 32 MHz

JTDI

NJTRST

NRST

USB2.0 FS device

SRAM 80K

2x(8x16b i t )

I2C2

TIMER2

TIMER3

XTAL OSC

1-24 MHz

XTAL 32 kHz

EEPROM 64 bit

Backup interface

TIMER4

RTC V2

AWU

RC HSI

obl

USB SRAM 512 B

Trace Controller ETM

USART1

USART2

SPI2/I2S

Backup

Reg 128

I2C1

USART3

RC MSI

Standby
interface

WDG 32K

BOR / Bgap

SPI1

IF

@V DDA

PVD

GPIO PORT C

GPIO PORT D

GPIO PORT E

LCD 8x40

12bit DAC1

FIFIIF

12bit DAC2

DAC_OUT1 as AF

DAC_OUT2 as AF

MPU

GP Comp

PU / PD

PDR

PDR

TIMER6

TIMER7

General purpose

timers

LCD Booster

GPIO PORT H

RC LSI

TIMERS (32 bits)

2x(8x16b i t )

SPI3/I2S

TRACECK, TRACED0, TRACED1, TRACED2, TRACED4

System

Cap. sens

Supply
monitoring

@VDDA

@VDDA

@VDDA

@VDDA

Supply monitoring

Cap. sensing

GPIO PORT B

GPIO PORT A

APB2: Fmax = 32 MHz

APB1: Fmax = 32 MHz

PLL &
Clock
Mgmt

VINP
a
VOUT

VINP
VINM
VOUT

RTC_OUT

AHB/APB2 AHB/APB1

JTCK / SWCLK
JTMS / SWDAT

JTDO
as AF

512 KB PROGRAM

16 KB DATA

8KB BOOT

DUAL BANK

@ VDD 33

VDD CORE

Vref

M3 CPU

GP DMA2 5 channels

GP DMA 7 channels

AHBPCLK
APBPCLK

HCLK

FCLK

@ VDD33

VDD33=1.65V to 3.6V

Vss

OSC_IN

OSC_OUT

TAMPER

4 channels

4 channels

4 channels

4 channels

RX, TX, CTS, RTS,

SmartCard as AF

RX, TX, CTS, RTS,

SmartCard as AF

MOSI, MISO, SCK,NSS,WS, CK

MCK, SD as AF

MOSI, MISO, SCK,NSS,WS, CK

MCK, SD as AF

SCL, SDA

As AF

SCL, SDA, SMBus, PMBus
As AF

USB_DP

USB_DM

Px

SEGx

COMx

OPAMP1

OPAMP2

COMPx_INx

VDDA /

VSSA

PA[15:0]

115 AF

PH[2:0]

PB[15:0]

PC[15:0]

PD[15:0]

PE[15:0]

TIMER9

TIMER10

TIMER11

2 channels

1 channel

1 channel

MOSI, MISO,

SCK, NSS as AF

RX, TX, CTS, RTS,

SmartCard as AF

40 AF

VDDREF_ADC*

VSSREF_ADC*

pbus

ibus

Dbus

BOR

Int

AHB: Fmax = 32 MHz

Bus Matrix 5M / 5S

VLCD = 2.5V to 3.6V

VLCD

@VDD33

Temp sensor

OSC32_IN

OSC32_OUT

NVIC

EEPROM

Interface

GPIO PORT F

GPIO PORT G

PF[15:0]

PG[15:0]

USART4

RX, TX as AF

USART5

RX, TX as AF

3 Functional overview

Figure 1. Ultra-low-power STM32L151xE and STM32L152xE block diagram

56

DS10002 Rev 10 13/136

Functional overview STM32L151xE STM32L152xE

3.1 Low-power modes

The ultra-low-power STM32L151xE and STM32L152xE devices support dynamic voltage
scaling to optimize its power consumption in run mode. The voltage from the internal low­drop regulator that supplies the logic can be adjusted according to the system’s maximum
operating frequency and the external voltage supply.

There are three power consumption ranges:

• Range 1 (VDD range limited to 1.71 V - 3.6 V), with the CPU running at up to 32 MHz

• Range 2 (full V

• Range 3 (full V

only with the multispeed internal RC oscillator clock source)

Seven low-power modes are provided to achieve the best compromise between low-power
consumption, short startup time and available wakeup sources:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs. Sleep mode power consumption at
16 MHz is about 1 mA with all peripherals off.

• Low-power run mode

This mode is achieved with the multispeed internal (MSI) RC oscillator set to the MSI
range 0 or MSI range 1 clock range (maximum 131 kHz), execution from SRAM or
Flash memory, and internal regulator in low-power mode to minimize the regulator's
operating current. In low-power run mode, the clock frequency and the number of
enabled peripherals are both limited.

• Low-power sleep mode

This mode is achieved by entering Sleep mode with the internal voltage regulator in
Low-power mode to minimize the regulator’s operating current. In Low-power sleep
mode, both the clock frequency and the number of enabled peripherals are limited; a
typical example would be to have a timer running at 32 kHz.

When wakeup is triggered by an event or an interrupt, the system reverts to the run
mode with the regulator on.

• Stop mode with RTC

Stop mode achieves the lowest power consumption while retaining the RAM and
register contents and real time clock. All clocks in the V
PLL, MSI RC, HSI RC and HSE crystal oscillators are disabled. The LSE or LSI is still
running. The voltage regulator is in the low-power mode.

The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI
line source can be one of the 16 external lines. It can be the PVD output, the
Comparator 1 event or Comparator 2 event (if internal reference voltage is on), it can
be the RTC alarm(s), the USB wakeup, the RTC tamper events, the RTC timestamp
event or the RTC wakeup.

range), with a maximum CPU frequency of 16 MHz

DD

range), with a maximum CPU frequency limited to 4 MHz (generated

DD

domain are stopped, the

CORE

14/136 DS10002 Rev 10

STM32L151xE STM32L152xE Functional overview

• Stop mode without RTC

Stop mode achieves the lowest power consumption while retaining the RAM and
register contents. All clocks are stopped, the PLL, MSI RC, HSI and LSI RC, LSE and
HSE crystal oscillators are disabled. The voltage regulator is in the low-power mode.
The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI
line source can be one of the 16 external lines. It can be the PVD output, the
Comparator 1 event or Comparator 2 event (if internal reference voltage is on). It can
also be wakened by the USB wakeup.

• Standby mode with RTC

Standby mode is used to achieve the lowest power consumption and real time clock.
The internal voltage regulator is switched off so that the entire V

CORE

domain is
powered off. The PLL, MSI RC, HSI RC and HSE crystal oscillators are also switched
off. The LSE or LSI is still running. After entering Standby mode, the RAM and register
contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG,
RTC, LSI, LSE Crystal 32K osc, RCC_CSR).

The device exits Standby mode in 60 µs when an external reset (NRST pin), an IWDG
reset, a rising edge on one of the three WKUP pins, RTC alarm (Alarm A or Alarm B),
RTC tamper event, RTC timestamp event or RTC Wakeup event occurs.

• Standby mode without RTC

Standby mode is used to achieve the lowest power consumption. The internal voltage
regulator is switched off so that the entire V

domain is powered off. The PLL, MSI

CORE

RC, HSI and LSI RC, HSE and LSE crystal oscillators are also switched off. After
entering Standby mode, the RAM and register contents are lost except for registers in
the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32K osc,
RCC_CSR).

The device exits Standby mode in 60 µs when an external reset (NRST pin) or a rising
edge on one of the three WKUP pin occurs.

Note: The RTC, the IWDG, and the corresponding clock sources are not stopped automatically by

entering Stop or Standby mode.

Table 3. Functionalities depending on the operating power supply range

-

Operating power supply

range

= V

V

DD

V

DD=VDDA

V

DD=VDDA

= 1.65 to 1.71 V Not functional Not functional Range 2 or Range 3

DDA

= 1.71 to 1.8 V

= 1.8 to 2.0 V

(2)

(2)

Functionalities depending on the operating power supply

DAC and ADC

operation

Not functional Not functional

Conversion time up

to 500 Ksps

USB

Not functional

range

(1)

Dynamic voltage scaling

range

Range 1, Range 2 or

Range 3

Range 1, Range 2 or

Range 3

DS10002 Rev 10 15/136

56

Functional overview STM32L151xE STM32L152xE

Table 3. Functionalities depending on the operating power supply range (continued)

-

Operating power supply

range

VDD=V

V

DD=VDDA

1. The GPIO speed also depends from VDD voltage and the user has to refer to Table 44: I/O AC

characteristics for more information about I/O speed.

2. CPU frequency changes from initial to final must respect “F
due to current consumption peak when frequency increases. It must also respect 5 µs delay between two
changes. For example to switch from 4.2 MHz to 32 MHz, the user can switch from 4.2 MHz to 16 MHz,
wait 5 µs, then switch from 16 MHz to 32 MHz.

3. Must be USB compliant from I/O voltage standpoint, the minimum V

= 2.0 to 2.4 V

DDA

= 2.4 to 3.6 V

Table 4. CPU frequency range depending on dynamic voltage scaling

Functionalities depending on the operating power supply

DAC and ADC

operation

Conversion time up

to 500 Ksps

Conversion time up

to 1 Msps

USB

Functional

Functional

initial < 4*F

CPU

range

(3)

(3)

is 3.0 V.

DD

(1)

Dynamic voltage scaling

range

Range 1, Range 2 or

Range 3

Range 1, Range 2 or

Range 3

final” to limit V

CPU

CORE

CPU frequency range Dynamic voltage scaling range

drop

16 MHz to 32 MHz (1ws)

32 kHz to 16 MHz (0ws)

8 MHz to 16 MHz (1ws)

32 kHz to 8 MHz (0ws)

2.1MHz to 4.2 MHz (1ws)
32 kHz to 2.1 MHz (0ws)

Range 1

Range 2

Range 3

16/136 DS10002 Rev 10

STM32L151xE STM32L152xE Functional overview

Table 5. Functionalities depending on the working mode (from Run/active down to

standby)

Stop Standby

Wakeup

-

capability

-

Wakeup

capability

Ips Run/Active Sleep

Low-

power

Run

Low-

power

Sleep

CPU Y -- Y -- -- -- -- --

Flash Y Y Y Y -- -- -- --

RAM Y Y Y Y Y -- -- --

Backup Registers Y Y Y Y Y -- Y --

EEPROM Y Y Y Y Y -- -- --

Brown-out rest
(BOR)

YYYYYYY--

DMA Y Y Y Y -- -- -- --

Programmable
Voltage Detector

YYYYYYY--

(PVD)

Power On Reset
(POR)

Power Down Rest
(PDR)

High Speed
Internal (HSI)

High Speed
External (HSE)

YYYYYYY--

YYYYY--Y--

Y Y -- -- -- -- -- --

Y Y -- -- -- -- -- --

Low Speed Internal
(LSI)

Low Speed
External (LSE)

Multi-Speed
Internal (MSI)

Inter-Connect
Controller

YYYYY--Y--

YYYYY--Y--

Y Y Y Y -- -- -- --

Y Y Y Y -- -- -- --

RTC Y Y Y Y Y Y Y --

RTC Tamper Y Y Y Y Y Y Y Y

Auto WakeUp
(AWU)

YYYYYYYY

LCD Y Y Y Y Y -- -- --

USB Y Y -- -- -- Y -- --

USART Y Y Y Y Y

(1)

-- --

SPI Y Y Y Y -- -- -- --

I2C Y Y -- -- --

(1)

-- --

DS10002 Rev 10 17/136

56

Functional overview STM32L151xE STM32L152xE

Table 5. Functionalities depending on the working mode (from Run/active down to

standby) (continued)

Low-

Ips Run/Active Sleep

ADC Y Y -- -- -- -- -- --

DAC Y Y Y Y Y -- -- --

Tempsensor Y Y Y Y Y -- -- --

OP amp Y Y Y Y Y -- -- --

Comparators Y Y Y Y Y Y -- --

16-bit and 32-bit
Timers

IWDG Y Y Y Y Y Y Y Y

WWDG Y Y Y Y -- -- -- --

Touch sensing Y Y -- -- -- -- -- --

Systic Timer Y Y Y Y - -- -- --

GPIOs Y Y Y Y Y Y -- 3 pins

Wakeup time to
Run mode

Consumption

=1.8 to 3.6 V

V

DD

(Typ)

1. The startup on communication line wakes the CPU which was made possible by an EXTI, this induces a delay before
entering run mode.

Y Y Y Y -- -- -- --

0 µs 0.4 µs 3 µs 46 µs < 8 µs 58 µs

Down to 195

µA/MHz (from

Flash)

Down to 38

µA/MHz (from

Flash)

power

Run

Down to

11 µ A

Low-

power

Sleep

Down to

4.6 µA

Stop Standby

Wakeup

-

capability

0.53 µA

(no RTC)

=1.8V

V

DD

1.2 µA

(with RTC)

V

=1.8V

DD

0.56 µA

(no RTC)

V

=3.0V

DD

1.4 µA

(with RTC)

V

=3.0V

DD

-

Wakeup

capability

0.285 µA
(no RTC)

VDD=1.8V

0.97 µA

(with RTC)

VDD=1.8V

0.29 µA

(no RTC)

VDD=3.0V

1.11 µA

(with RTC)

VDD=3.0V

3.2 Arm® Cortex®-M3 core with MPU

The Arm® Cortex®-M3 processor is the industry leading processor for embedded systems. It
has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.

The Arm® Cortex®-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an Arm core in the memory size usually
associated with 8- and 16-bit devices.

18/136 DS10002 Rev 10

STM32L151xE STM32L152xE Functional overview

The memory protection unit (MPU) improves system reliability by defining the memory
attributes (such as read/write access permissions) for different memory regions. It provides
up to eight different regions and an optional predefined background region.

Owing to its embedded Arm core, the STM32L151xE and STM32L152xE devices are
compatible with all Arm tools and software.

Nested vectored interrupt controller (NVIC)

The ultra-low-power STM32L151xE and STM32L152xE devices embed a nested vectored
interrupt controller able to handle up to 56 maskable interrupt channels (not including the 16
interrupt lines of Arm

• Closely coupled NVIC gives low-latency interrupt processing

• Interrupt entry vector table address passed directly to the core

• Closely coupled NVIC core interface

• Allows early processing of interrupts

• Processing of late arriving, higher-priority interrupts

• Support for tail-chaining

• Processor state automatically saved on interrupt entry, and restored on interrupt exit,

with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt
latency.

®

Cortex®-M3) and 16 priority levels.

3.3 Reset and supply management

3.3.1 Power supply schemes

• VDD = 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided
externally through V

• V

SSA

, V

= 1.65 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs

DDA

and PLL (minimum voltage to be applied to V
and V

must be connected to V

SSA

3.3.2 Power supply supervisor

The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR) that can be coupled with a brownout reset (BOR) circuitry.

The device exists in two versions:

• The version with BOR activated at power-on operates between 1.8 V and 3.6 V.

• The other version without BOR operates between 1.65 V and 3.6 V.

After the VDD threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or
not at power-on), the option byte loading process starts, either to confirm or modify default
thresholds, or to disable the BOR permanently: in this case, the V

1.65 V (whatever the version, BOR active or not, at power-on).

When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever
the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the
power ramp-up must guarantee that 1.65
POR area.

DD

pins.

and VSS, respectively.

DD

V is reached on VDD at least 1 ms after it exits the

is 1.8 V when the ADC is used). V

DDA

min value becomes

DD

DDA

DS10002 Rev 10 19/136

56

Functional overview STM32L151xE STM32L152xE

Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To
reduce the power consumption in Stop mode, it is possible to automatically switch off the
internal reference voltage (V
V

is below a specified threshold, V

DD

) in Stop mode. The device remains in reset mode when

REFINT

POR/PDR

or V

, without the need for any external

BOR

reset circuit.

Note: The start-up time at power-on is typically 3.3 ms when BOR is active at power-up, the start-

up time at power-on can be decreased down to 1

ms typically for devices with BOR inactive

at power-up.

The device features an embedded programmable voltage detector (PVD) that monitors the
V

DD/VDDA

levels between 1.85
interrupt can be generated when V
V

DD/VDDA

power supply and compares it to the V

V and 3.05 V, chosen by software, with a step around 200 mV. An

drops below the V

is higher than the V

DD/VDDA

threshold. The interrupt service routine can then generate

PVD

threshold. This PVD offers 7 different

PVD

threshold and/or when

PVD

a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

3.3.3 Voltage regulator

The regulator has three operation modes: main (MR), low-power (LPR) and power down.

• MR is used in Run mode (nominal regulation)

• LPR is used in the Low-power run, Low-power sleep and Stop modes

• Power down is used in Standby mode. The regulator output is high impedance, the

kernel circuitry is powered down, inducing zero consumption but the contents of the
registers and RAM are lost except for the standby circuitry (wakeup logic, IWDG, RTC,
LSI, LSE crystal 32K osc, RCC_CSR).

3.3.4 Boot modes

At startup, boot pins are used to select one of three boot options:

• Boot from Flash memory

• Boot from System memory

• Boot from embedded RAM

The boot from Flash usually boots at the beginning of the Flash (bank 1). An additional boot
mechanism is available through user option byte, to allow booting from bank 2 when bank 2
contains valid code. This dual boot capability can be used to easily implement a secure field
software update mechanism.

The boot loader is located in System memory. It is used to reprogram the Flash memory by
using USART1, USART2 or USB. See Application note “STM32 microcontroller system
memory boot mode” (AN2606) for details.

20/136 DS10002 Rev 10

STM32L151xE STM32L152xE Functional overview

3.4 Clock management

The clock controller distributes the clocks coming from different oscillators to the core and
the peripherals. It also manages clock gating for low-power modes and ensures clock
robustness. It features:

• Clock prescaler: to get the best trade-off between speed and current consumption, the
clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler.

• Safe clock switching: clock sources can be changed safely on the fly in run mode
through a configuration register.

• Clock management: to reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.

• System clock source: three different clock sources can be used to drive the master
clock SYSCLK:

– 1-24 MHz high-speed external crystal (HSE), that can supply a PLL

– 16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can

supply a PLL

– Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 7

frequencies (65 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1 MHz, 4.2 MHz).
When a 32.768 kHz clock source is available in the system (LSE), the MSI
frequency can be trimmed by software down to a ±0.5% accuracy.

• Auxiliary clock source: two ultra-low-power clock sources that can be used to drive
the LCD controller and the real-time clock:

– 32.768 kHz low-speed external crystal (LSE)

– 37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.

The LSI clock can be measured using the high-speed internal RC oscillator for
greater precision.

• RTC and LCD clock sources: the LSI, LSE or HSE sources can be chosen to clock
the RTC and the LCD, whatever the system clock.

• USB clock source: the embedded PLL has a dedicated 48 MHz clock output to supply
the USB interface.

• Startup clock: after reset, the microcontroller restarts by default with an internal 2 MHz
clock (MSI). The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.

• Clock security system (CSS): this feature can be enabled by software. If a HSE clock
failure occurs, the master clock is automatically switched to HSI and a software
interrupt is generated if enabled.

• Clock-out capability (MCO: microcontroller clock output): it outputs one of the
internal clocks for external use by the application.

Several prescalers allow the configuration of the AHB frequency, each APB (APB1 and
APB2) domains. The maximum frequency of the AHB and the APB domains is 32 MHz. See

Figure 2 for details on the clock tree.

DS10002 Rev 10 21/136

56

Functional overview STM32L151xE STM32L152xE

MS18583V1

LSI RC

LSE OSC

HSI RC

HSE
OSC

@V33

@V

DDCORE

@V33

level shifters

level shifters

PLL

X 3,4,6,8,12

@V33

level shifters

LSE tempo

1 MHz clock

detector

@V33

LS

Watchdog

ck_pllin

source
control

Clock

Wat ch dog

enable

RTC enable

ck_hsi
ck_hse

HSE present or not

LSI tempo

ck_pll

AHB

prescaler

/ 1,2,..512

APB2

/ 1,2,4,8,16

APB1

/ 1,2,4,8,16

ck_usb = Vco / 2 (Vco must be at 96 MHz)

/ 8

CK_TIMSYS

CK_CPU

CK_FCLK

CK_PWR

CK_USB48

CK_TIMTGO

CK_APB1

CK_APB2

usben and (not deepsleep)

timer9en and (not deepsleep)

apb1 periphen and (not deepsleep)

apb2 periphen and (not deepsleep)

not (sleep or

deepsleep)

not (sleep or

deepsleep

not deepsleep

not deepsleep

Standby supplied voltage domain

System

clock

MCO

if (APB1 presc = 1)

x1

else

x2

16,24,32,48

ck_lse

CK_LCD

/ 2, 3, 4

1 MHz

@V

DDCORE

@V

DDCORE

@V

DDCORE

/ 1,2,4,8,16

LCD enable

MSI RC

@V33

@V

DDCORE

level shifters

ck_msi

ck_lsi

CK_ADC

ADC enable

LS LS LS LS

LS

LS

/ 2,4,8,16

prescaler prescaler

Radio Sleep Timer

RTC

Radio Sleep Timer enable

Figure 2. Clock tree

22/136 DS10002 Rev 10

STM32L151xE STM32L152xE Functional overview

3.5 Low-power real-time clock and backup registers

The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain
the sub-second, second, minute, hour (12/24 hour), week day, date, month, year, in BCD
(binary-coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the
month are made automatically. The RTC provides two programmable alarms and
programmable periodic interrupts with wakeup from Stop and Standby modes.

The programmable wakeup time ranges from 120 µs to 36 hours.

The RTC can be calibrated with an external 512 Hz output, and a digital compensation
circuit helps reduce drift due to crystal deviation.

The RTC can also be automatically corrected with a 50/60Hz stable powerline.

The RTC calendar can be updated on the fly down to sub second precision, which enables
network system synchronization.

A time stamp can record an external event occurrence, and generates an interrupt.

There are thirty-two 32-bit backup registers provided to store 128 bytes of user application
data. They are cleared in case of tamper detection.

Three pins can be used to detect tamper events. A change on one of these pins can reset
backup register and generate an interrupt. To prevent false tamper event, like ESD event,
these three tamper inputs can be digitally filtered.

3.6 GPIOs (general-purpose inputs/outputs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions, and can be individually
remapped using dedicated AFIO registers. All GPIOs are high current capable. The
alternate function configuration of I/Os can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/O registers. The I/O controller is
connected to the AHB with a toggling speed of up to 16 MHz.

External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 24 edge detector lines used to generate
interrupt/event requests. Each line can be individually configured to select the trigger event
(rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 115 GPIOs can be connected
to the 16 external interrupt lines. The 8 other lines are connected to RTC, PVD, USB,
comparator events or capacitive sensing acquisition.

DS10002 Rev 10 23/136

56

Functional overview STM32L151xE STM32L152xE

3.7 Memories

The STM32L151xE and STM32L152xE devices have the following features:

• 80 Kbytes of embedded RAM accessed (read/write) at CPU clock speed with 0 wait
states. With the enhanced bus matrix, operating the RAM does not lead to any
performance penalty during accesses to the system bus (AHB and APB buses).

• The non-volatile memory is divided into three arrays:

– 512 Kbytes of embedded Flash program memory

– 16 Kbytes of data EEPROM

– Options bytes

Flash program and data EEPROM are divided into two banks, this enables writing in
one bank while running code or reading data in the other bank.

The options bytes are used to write-protect or read-out protect the memory (with 4
Kbytes granularity) and/or readout-protect the whole memory with the following
options:

– Level 0: no readout protection

– Level 1: memory readout protection, the Flash memory cannot be read from or

written to if either debug features are connected or boot in RAM is selected

– Level 2: chip readout protection, debug features (Arm Cortex-M3 JTAG and serial

wire) and boot in RAM selection disabled (JTAG fuse)

The whole non-volatile memory embeds the error correction code (ECC) feature.

3.8 DMA (direct memory access)

The flexible 12-channel, general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management, avoiding the generation of interrupts when the controller
reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with software trigger
support for each channel. Configuration is done by software and transfer sizes between
source and destination are independent.

The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose timers,
DAC and ADC.

24/136 DS10002 Rev 10

STM32L151xE STM32L152xE Functional overview

3.9 LCD (liquid crystal display)

The LCD drives up to 8 common terminals and 44 segment terminals to drive up to 320
pixels.

• Internal step-up converter to guarantee functionality and contrast control irrespective of
V

. This converter can be deactivated, in which case the V

DD

the voltage to the LCD

• Supports static, 1/2, 1/3, 1/4 and 1/8 duty

• Supports static, 1/2, 1/3 and 1/4 bias

• Phase inversion to reduce power consumption and EMI

• Up to 8 pixels can be programmed to blink

• Unneeded segments and common pins can be used as general I/O pins

• LCD RAM can be updated at any time owing to a double-buffer

• The LCD controller can operate in Stop mode

pin is used to provide

LCD

3.10 ADC (analog-to-digital converter)

A 12-bit analog-to-digital converters is embedded into STM32L151xE and STM32L152xE
devices with up to 40 external channels, performing conversions in single-shot or scan
mode. In scan mode, automatic conversion is performed on a selected group of analog
inputs with up to 28 external channels in a group.

The ADC can be served by the DMA controller.

An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all scanned channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.

The events generated by the general-purpose timers (TIMx) can be internally connected to
the ADC start triggers, to allow the application to synchronize A/D conversions and timers.
An injection mode allows high priority conversions to be done by interrupting a scan mode
which runs in as a background task.

The ADC includes a specific low-power mode. The converter is able to operate at maximum
speed even if the CPU is operating at a very low frequency and has an auto-shutdown
function. The ADC’s runtime and analog front-end current consumption are thus minimized
whatever the MCU operating mode.

3.10.1 Temperature sensor

The temperature sensor (TS) generates a voltage V
temperature.

The temperature sensor is internally connected to the ADC_IN16 input channel which is
used to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.

that varies linearly with

SENSE

To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are

DS10002 Rev 10 25/136

56

Functional overview STM32L151xE STM32L152xE

stored by ST in the system memory area, accessible in read-only mode. See Tab le 60:

Temperature sensor calibration values.

3.10.2 Internal voltage reference (V

The internal voltage reference (V
ADC and Comparators. V
enables accurate monitoring of the V
available for ADC). The precise voltage of V
ST during production test and stored in the system memory area. It is accessible in read­only mode. See

Tabl e 15: Embedded internal reference voltage calibration values.

REFINT

REFINT

is internally connected to the ADC_IN17 input channel. It

REFINT

DD

)

) provides a stable (bandgap) voltage output for the

value (when no external voltage, VREF+, is

REFINT

3.11 DAC (digital-to-analog converter)

The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs. The chosen design structure is composed of integrated
resistor strings and an amplifier in non-inverting configuration.

This dual digital Interface supports the following features:

• Two DAC converters: one for each output channel

• 8-bit or 12-bit monotonic output

• Left or right data alignment in 12-bit mode

• Synchronized update capability

• Noise-wave generation

• Triangular-wave generation

• Dual DAC channels, independent or simultaneous conversions

• DMA capability for each channel (including the underrun interrupt)

• External triggers for conversion

• Input reference voltage V

Eight DAC trigger inputs are used in the STM32L151xE and STM32L152xE devices. The
DAC channels are triggered through the timer update outputs that are also connected to
different DMA channels.

REF+

is individually measured for each part by

3.12 Operational amplifier

The STM32L151xE and STM32L152xE devices embed two operational amplifiers with
external or internal follower routing capability (or even amplifier and filter capability with
external components). When one operational amplifier is selected, one external ADC
channel is used to enable output measurement.

The operational amplifiers feature:

• Low input bias current

• Low offset voltage

• Low-power mode

• Rail-to-rail input

26/136 DS10002 Rev 10

STM32L151xE STM32L152xE Functional overview

3.13 Ultra-low-power comparators and reference voltage

The STM32L151xE and STM32L152xE devices embed two comparators sharing the same
current bias and reference voltage. The reference voltage can be internal or external
(coming from an I/O).

• One comparator with fixed threshold

• One comparator with rail-to-rail inputs, fast or slow mode. The threshold can be one of

the following:

– DAC output

– External I/O

– Internal reference voltage (V

Both comparators can wake up from Stop mode, and be combined into a window
comparator.

The internal reference voltage is available externally via a low-power / low-current output
buffer (driving current capability of 1

µA typical).

) or a sub-multiple (1/4, 1/2, 3/4)

REFINT

3.14 System configuration controller and routing interface

The system configuration controller provides the capability to remap some alternate
functions on different I/O ports.

The highly flexible routing interface allows the application firmware to control the routing of
different I/Os to the TIM2, TIM3 and TIM4 timer input captures. It also controls the routing of
internal analog signals to ADC1, COMP1 and COMP2 and the internal reference voltage
V

REFINT

.

3.15 Touch sensing

The STM32L151xE and STM32L152xE devices provide a simple solution for adding
capacitive sensing functionality to any application. Thesedevices offer up to 34 capacitive
sensing channels distributed over 11 analog I/O groups. Both software and timer capacitive
sensing acquisition modes are supported.

Capacitive sensing technology is able to detect the presence of a finger near a sensor which
is protected from direct touch by a dielectric (glass, plastic...). The capacitive variation
introduced by the finger (or any conductive object) is measured using a proven
implementation based on a surface charge transfer acquisition principle. It consists of
charging the sensor capacitance and then transferring a part of the accumulated charges
into a sampling capacitor until the voltage across this capacitor has reached a specific
threshold. The capacitive sensing acquisition only requires few external components to
operate. This acquisition is managed directly by the GPIOs, timers and analog I/O groups
(see

Section 3.14: System configuration controller and routing interface).

Reliable touch sensing functionality can be quickly and easily implemented using the free
STM32L1xx STMTouch touch sensing firmware library.

DS10002 Rev 10 27/136

56

Functional overview STM32L151xE STM32L152xE

3.16 Timers and watchdogs

The ultra-low-power STM32L151xE and STM32L152xE devices include seven general­purpose timers, two basic timers, and two watchdog timers.

Tabl e 6 compares the features of the general-purpose and basic timers.

Table 6. Timer feature comparison

Timer

TIM2,
TIM3,

TIM4

TIM5 32-bit

TIM9 16-bit

TIM10,

TIM11

TIM6,

TIM7

Counter

resolution

16-bit

16-bit Up

16-bit Up

Counter type Prescaler factor

Up, down,

up/down

Up, down,

up/down

Up, down,

up/down

Any integer between

1 and 65536

Any integer between

1 and 65536

Any integer between

1 and 65536

Any integer between

1 and 65536

Any integer between

1 and 65536

DMA

request

generation

Yes 4 No

Yes 4 No

No 2 No

No 1 No

Yes 0 No

Capture/compare

channels

Complementary

outputs

3.16.1 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM9, TIM10 and TIM11)

There are seven synchronizable general-purpose timers embedded in the STM32L151xE
and STM32L152xE devices (see

TIM2, TIM3, TIM4, TIM5

Tabl e 6 for differences).

TIM2, TIM3, TIM4 are based on 16-bit auto-reload up/down counter. TIM5 is based on a 32­bit auto-reload up/down counter. They include a 16-bit prescaler. They feature four
independent channels each for input capture/output compare, PWM or one-pulse mode
output. This gives up to 16 input captures/output compares/PWMs on the largest packages.

TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together or with the TIM10,
TIM11 and TIM9 general-purpose timers via the Timer Link feature for synchronization or
event chaining. Their counter can be frozen in debug mode. Any of the general-purpose
timers can be used to generate PWM outputs.

TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation.

These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.

TIM10, TIM11 and TIM9

TIM10 and TIM11 are based on a 16-bit auto-reload upcounter. TIM9 is based on a 16-bit
auto-reload up/down counter. They include a 16-bit prescaler. TIM10 and TIM11 feature one
independent channel, whereas TIM9 has two independent channels for input capture/output
compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3,
TIM4, TIM5 full-featured general-purpose timers.

28/136 DS10002 Rev 10

STM32L151xE STM32L152xE Functional overview

They can also be used as simple time bases and be clocked by the LSE clock source
(32.768 kHz) to provide time bases independent from the main CPU clock.

3.16.2 Basic timers (TIM6 and TIM7)

These timers are mainly used for DAC trigger generation. They can also be used as generic
16-bit time bases.

3.16.3 SysTick timer

This timer is dedicated to the OS, but could also be used as a standard downcounter. It is
based on a 24-bit downcounter with autoreload capability and a programmable clock
source. It features a maskable system interrupt generation when the counter reaches 0.

3.16.4 Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 37 kHz internal RC and, as it operates independently of the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes. The counter
can be frozen in debug mode.

3.16.5 Window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.

3.17 Communication interfaces

3.17.1 I²C bus

Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support
standard and fast modes.

They support dual slave addressing (7-bit only) and both 7- and 10-bit addressing in master
mode. A hardware CRC generation/verification is embedded.

They can be served by DMA and they support SM Bus 2.0/PM Bus.

3.17.2 Universal synchronous/asynchronous receiver transmitter (USART)

The three USART and two UART interfaces are able to communicate at speeds of up to 4
Mbit/s. They support IrDA SIR ENDEC and have LIN Master/Slave capability. The three
USARTs provide hardware management of the CTS and RTS signals and are ISO 7816
compliant.

All USART/UART interfaces can be served by the DMA controller.

DS10002 Rev 10 29/136

56

Functional overview STM32L151xE STM32L152xE

3.17.3 Serial peripheral interface (SPI)

Up to three SPIs are able to communicate at up to 16 Mbits/s in slave and master modes in
full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes.

The SPIs can be served by the DMA controller.

3.17.4 Inter-integrated sound (I2S)

Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can
operate in master or slave mode, and can be configured to operate with a 16-/32-bit
resolution as input or output channels. Audio sampling frequencies from 8 kHz up to 192
kHz are supported. When either or both of the I2S interfaces is/are configured in master
mode, the master clock can be output to the external DAC/CODEC at 256 times the
sampling frequency.

The I2Ss can be served by the DMA controller.

3.17.5 Universal serial bus (USB)

The STM32L151xE and STM32L152xE devices embed a USB device peripheral compatible
with the USB full-speed 12
function interface. It has software-configurable endpoint setting and supports
suspend/resume. The dedicated 48
clock source must use a HSE crystal oscillator).

Mbit/s. The USB interface implements a full-speed (12 Mbit/s)

MHz clock is generated from the internal main PLL (the

3.18 CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link­time and stored at a given memory location.

30/136 DS10002 Rev 10

STM32L151xE STM32L152xE Functional overview

3.19 Development support

3.19.1 Serial wire JTAG debug port (SWJ-DP)

The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG JTMS and JTCK pins are shared with SWDAT and SWCLK, respectively, and a
specific sequence on the JTMS pin is used to switch between JTAG-DP and SW-DP.

The JTAG port can be permanently disabled with a JTAG fuse.

3.19.2 Embedded Trace Macrocell™

The Arm
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32L151xE and STM32L152xE device through a small number of ETM pins to an
external hardware trace port analyzer (TPA) device. The TPA is connected to a host
computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and
data flow activity can be recorded and then formatted for display on the host computer
running debugger software. TPA hardware is commercially available from common
development tool vendors. It operates with third party debugger software tools.

®

Embedded Trace Macrocell provides a greater visibility of the instruction and data

DS10002 Rev 10 31/136

56

Pin descriptions STM32L151xE STM32L152xE

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

48

47
46
45
44
43

42

41

40

39

38

37

36

35

34

33

17 18 19 20 21 22 23 24 29 30 31 3225 26 27 28

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

V

LCD

PC13-WKUP2

PC14-OSC32_IN

PC15-OSC32_OUT

PH0 -OSC_IN

PH1- OSC_OUT

NRST

PC0
PC1
PC2
PC3

VSSA

VDDA

PA0-WKUP 1

PA1
PA2

VDD_3

VSS_3

PB9

PB8

BOOT0

PB7

PB6

PB5

PB4

PB3

PD2

PC12

PC11

PC10

PA15

PA14

VDD_2
VSS_

2

PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
PB15
PB14
PB13
PB12

PA3

VSS_4

VDD_4

PA4

PA5

PA6

PA7

PC4

PC5

PB0

PB1

PB2

PB10

PB11

VSS_1

VDD_1

LQFP64

ai15693c

4 Pin descriptions

Figure 3. STM32L15xRE LQFP64 pinout

32/136 DS10002 Rev 10

1. This figure shows the package top view.

STM32L151xE STM32L152xE Pin descriptions

Figure 4. STM32L15xVE LQFP100 pinout

VDD_3

VSS_3

PE1

PE0

PB9

PB8

BOOT0

PB7

PB6

PB5

PB4

PB3

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

PC12

PC11

PC10

PA15

PA14

PE2
PE3
PE4
PE5

PE6-WKUP3

V

PC13-WKUP2

PC14-OSC32_IN

PC15-OSC32_OUT

VSS_5

VDD_5

PH0-OSC_IN

PH1-OSC_OUT

NRST

PC0
PC1
PC2
PC3

VSSA

VREF-

VREF+

VDDA

PA0-WKU P1

LCD

PA1
PA2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

26272829303132333435363738394041424344454647484950

PA3

PA4

VSS_4

VDD_4

1. This figure shows the package top view.

100999897969594939291908988878685848382818079787776

75

VDD_2

74

VSS_2

73

PH2

72

PA1 3

71

PA1 2

70

PA11

69

PA1 0

68

PA9

67

PA8

66

PC9

65

PC8

64

LQFP100

PA5

PA6

PA7

PB0

PB1

PB2

PE7

PE8

PC4

PC5

PE9

PE10

PE11

PE12

PE13

PE14

PE15

PB10

PB11

VSS_1

63
62
61
60
59
58
57
56
55
54
53
52
51

VDD_1

PC7
PC6
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12

ai15692c

DS10002 Rev 10 33/136

56

Pin descriptions STM32L151xE STM32L152xE

MSv41009V1

A

B

E

D

C

F

G

H

765438

J

K

L

M

9

12

PD4

PD5

PD2

PA13

PA8

PD15

PD12

PD7

PD6

PA14

PD11

PD8

PB4

PB3

PB6

PB5

PB7

BOOT0

PE0

PE1

VDD_3

PB9

VDDA

PA6

PE3

VLCD

VSS_3

VREF+

PA3

PE4

PH0
OSCIN

VREF-

NRST

PE2

PE6
WKUP3

PC0

PC14
OSC32IN

VSS_5

PC3

PD3

PC9

PC10

PD1

PB8

PB13

VDD_1

PB11

PE12

PB12

PE15

PE14

PE9

PE10

PE13

PE11

PE8

PB0

PB1

PE7

PB2

PA4

PA7

PC4

PC5

PA2

VSS_4

VDD_4

PA5

PE5

PC13
WKUP2

PC15
OSC32OUT

PC2

PC1

VSSA

PA0
WKUP1

PA1

VDD_4

VDD_3

VDD_5

PH1
OSCOUT

VSS_2

PA11

PH2

PA15

PC6

VDD_2

PA9

PC7

PD14

PD10

PB14

VSS_1

PD0

PC11

PC12

VSS_2

PA12

PA10

PC8

PD13

PD9

PB15

VSS_1

PB10

Figure 5. STM32L15xVEY WLCSP104 ballout

1. This figure shows the package top view.

34/136 DS10002 Rev 10

STM32L151xE STM32L152xE Pin descriptions

MS33002V1

A

B

E

D

C

F

G

H

PE3

PC15­OSC32
_OUT

PC14­OSC32
_IN

PE4

PC0

PE1

PE5

PE2

PE6-

WKUP3

VLCD

VSS_5

VDD_5

NRST

PB8

PB9

PE0

VSS_6

PF4

PF6

VDD_6

BOOT0

PB7

VSS_3

PD7

PB6

PB5

PD5

PD6

PB4

PD4

PG14

PG12

PG13

PF0

7654321

PC13­WKUP2

PH0
OSC_IN

PH1
OSC_
OUT

VDD_3

VDD_9

PF2

PF1

VSS_9

J

VSSA

PC1 PC2 PA 4 PA7 PF9 PF12

PB3

PD3

PD2

VSS_10

VDD_10

PA15

PD1

PG10

PG1

PG0

PA14

PC12

PC11

PD15

PA13

PC10

PA12

PA11

PH2

VDD_2

PD14

PC9

PC6

PA10

VDD_1

PD13

VSS_1

PA8

PC7

VSS_2

PD0

PG2

PG3

PG5

PG9

PA9

PC8

PG4

PF14 PF15 PD12 PD11 PD10

VREF+

PC3

PA0-

WKUP1

PA2

PA3

PA5

PA6

PC5

PF11

PB2

PF13

PE8

NC

PC4

VDDA

PA1

OPAMP1

_VINM

OPAMP2

_VINM

PB0 PB1 PE7

PD9

PE10

PD8

PE12

PB10

PB14

PB11

PB13

PB12

PB15

PE9 PE11 PE13 PE14 PE15

K

L

M

PF3

PF5

PF7

PF8

12111098

Figure 6. STM32L15xQE UFBGA132 ballout

1. This figure shows the package top view.

DS10002 Rev 10 35/136

56

Pin descriptions STM32L151xE STM32L152xE

MS18581V2

V

DD_3VSS_3

PE1

PE0

PB9

PB8

BOOT0

PB7

PB6

PB5

PB4

PB3

PG15

V

DD_11VSS_11

PG14

PG13

PG12

PG11

PG10

PG9

PD7

PD6

V

DD_10VSS_10

PD5

PD4

PD3

PD2

PD1

PD0

PC12

PC11

PC10

PA 15

PA 14

PE2

V

DD_2

PE3

V

SS_2

PE4
PE5

PA 13

PE6-WKUP3

PA 12
PA 11

PC13-WKUP2

PA 10

PC14-OSC32_IN

PA 9

PC15-OSC32_OUT

PA 8

PF0

PC9

PF1

PC8

PF2

PC7

PF3

PC6

PF4

V

DD_9

PF5

V

SS_9

V

SS_5

PG8

V

DD_5

PG7

PF6

PG6

PF7

PG5

PF8

PG4

PF9

PG3

PF10

PG2

OSC_IN

PD15

OSC_OUT

PD14

NRST

V

DD_8

PC0

V

SS_8

PC1

PD13

PC2

PD12

PC3

PD11

V

SSA

PD10

V

REF-

PD9

V

REF+

PD8

V

DDA

PB15

PA 0 -W KUP 1

PB14

PA 1

PB13

PA 2

PB12

PA 3

V

SS_4

V

DD_4

PA 4

PA 5

PA 6

PA 7

PC4

PC5

PB0

PB1

PB2

PF11

PF12

VSS_6

V

DD_6

PF13

PF14

PF15

PG0

PG1

PE7

PE8

PE9

V

SS_7

V

DD_7

PE10

PE11

PE12

PE13

PE14

PE15

PB10

PB11

V

SS_1

V

DD_1

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

109
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

108

107

106

105

104

103

102

101

100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84

3738394041424344454647484950515253545556575859

60

72

LQFP144

120

119

118

117

116

115

114

113

112

111

110

6162636465666768697071

26
27
28
29
30
31
32
33
34
35
36

83
82
81
80
79
78
77
76
75
74
73

V

LCD

PH2

Figure 7. STM32L15xZE LQFP144 pinout

1. This figure shows the package top view.

36/136 DS10002 Rev 10

STM32L151xE STM32L152xE Pin descriptions

I/O structure

Pin

functions

Table 7. Legend/abbreviations used in the pinout table

Name Abbreviation Definition

Pin name

Pin type

Notes

Alternate
functions

Additional

functions

Unless otherwise specified in brackets below the pin name, the pin function
during and after reset is the same as the actual pin name

S Supply pin

I Input only pin

I/O Input / output pin

FT 5 V tolerant I/O

TC Standard 3.3 V I/O

B Dedicated BOOT0 pin

RST Bidirectional reset pin with embedded weak pull-up resistor

Unless otherwise specified by a note, all I/Os are set as floating inputs during
and after reset

Functions selected through GPIOx_AFR registers

Functions directly selected/enabled through peripheral registers

Pins

LQFP144

UFBGA132

LQFP100

1 B2 1 - D6 PE2 I/O FT PE2

2 A1 2 - D7 PE3 I/O FT PE3

Table 8. STM32L151xE and STM32L152xE pin definitions

LQFP64

(1)

Pin name

Pin Type

WLCSP104

function

I / O structure

Main

(after

reset)

(2)

Alternate functions

TIM3_ETR/LCD_SEG38/

TRACECLK

TIM3_CH1/LCD_SEG39/

TRACED0

Pin functions

Additional

functions

3 B1 3 - C8 PE4 I/O FT PE4 TIM3_CH2/TRACED1 -

4 C2 4 - B9 PE5 I/O FT PE5 TIM9_CH1/TRACED2 -

5D25-E6

6E261E7 V

PE6-

WKUP3

LCD

(3)

I/O FT PE6 TIM9_CH2/TRACED3

S- V

LCD

--

WKUP3/

RTC_TAMP3

WKUP2/RTC_TA

7 C1 7 2 C9 PC13-WKUP2 I/O FT PC13 -

MP1/RTC_TS/

RTC_OUT

-

-

DS10002 Rev 10 37/136

56

Pin descriptions STM32L151xE STM32L152xE

Table 8. STM32L151xE and STM32L152xE pin definitions (continued)

Pins

LQFP144

UFBGA132

LQFP64

LQFP100

WLCSP104

8D183D8

9E194D9

Pin name

PC14-

OSC32_IN

(4)

PC15-

OSC32_OUT

(1)

Pin Type

function

I / O structure

Main

(after

reset)

(2)

Alternate functions

I/O TC PC14 - OSC32_IN

I/O TC PC15 - OSC32_OUT

Pin functions

Additional

functions

10 D6 - - - PF0 I/O FT PF0 - -

11 D5 - - - PF1 I/O FT PF1 - -

12 D4 - - - PF2 I/O FT PF2 - -

13 E4 - - - PF3 I/O FT PF3 - -

14 F3 - - - PF4 I/O FT PF4 - -

15 F4 - - - PF5 I/O FT PF5 - -

16 F2 10 - E8 V

17 G2 11 - E9 V

SS_5

DD_5

S- V

S- V

SS_5

DD_5

--

--

18 G3 - - - PF6 I/O FT PF6 TIM5_CH1/TIM5_ETR ADC_IN27

19 G4 - - - PF7 I/O FT PF7 TIM5_CH2

ADC_IN28/

COMP1_INP

20 H4 - - - PF8 I/O FT PF8 TIM5_CH3

21 J6 - - - PF9 I/O FT PF9 TIM5_CH4

22 - - - - PF10 I/O FT PF10 -

(5)

23 F1 12 5 F8 PH0-OSC_IN

24 G1 13 6 F9

PH1-

OSC_OUT

I/O TC PH0 - OSC_IN

I/O TC PH1 - OSC_OUT

(5)

ADC_IN29/

COMP1_INP

ADC_IN30/

COMP1_INP

ADC_IN31/

COMP1_INP

25 H2 14 7 F7 NRST I/O RST NRST - -

26 H1 15 8 F6 PC0 I/O FT PC0 LCD_SEG18

27 J2 16 9 H9 PC1 I/O FT PC1 LCD_SEG19

28 - 17 10 G9 PC2 I/O FT PC2 LCD_SEG20

ADC_IN10/

COMP1_INP

ADC_IN11/

COMP1_INP

ADC_IN12/

COMP1_INP

38/136 DS10002 Rev 10

STM32L151xE STM32L152xE Pin descriptions

Table 8. STM32L151xE and STM32L152xE pin definitions (continued)

Pins

(1)

Pin name

LQFP144

UFBGA132

LQFP64

LQFP100

WLCSP104

Pin Type

function

I / O structure

Main

(after

reset)

(2)

Alternate functions

- J3 - - - PC2 I/O FT PC2 LCD_SEG20

Pin functions

Additional

functions

ADC_IN12/

COMP1_INP

- K1 - - - NC I - NC - -

29 K2 18 11 G8 PC3 I/O TC PC3 LCD_SEG21

30 J1 19 12 J9 V

31 - 20 - H8 V

32 L1 21 - G7 V

33 M1 22 13 G6 V

SSA

REF-

REF+

DDA

S- V

S- V

S- V

S- V

SSA

REF-

REF+

DDA

--

--

--

--

TIM2_CH1_ETR/

34 L2 23 14 K9 PA0-WKUP1 I/O FT PA0

TIM5_CH1/

USART2_CTS

ADC_IN13/

COMP1_INP

WKUP1/RTC_TA

MP2/ADC_IN0/

COMP1_INP

35 M2 24 15 L9 PA1 I/O FT PA1

36 - 25 16 J8 PA2 I/O FT PA2

- K3 - - - PA 2 I/O FT PA2

- M3 - - - OPAMP1_VINM I TC

OPAMP1_

VINM

37 L3 26 17 H7 PA3 I/O TC PA3

38 - 27 18 K8 V

39 - 28 19

L8,
M9

V

SS_4

DD_4

S- V

S- V

SS_4

DD_4

40 J4 29 20 J7 PA4 I/O TC PA4

TIM2_CH2/TIM5_CH2/

USART2_RTS/

LCD_SEG0

TIM2_CH3/TIM5_CH3/

TIM9_CH1/

USART2_TX/LCD_SEG1

TIM2_CH3/TIM5_CH3/

TIM9_CH1/

USART2_TX/LCD_SEG1

--

TIM2_CH4/TIM5_CH4/

TIM9_CH2/

USART2_RX/LCD_SEG2

--

--

SPI1_NSS/SPI3_NSS/

I2S3_WS/

USART2_CK

ADC_IN1/

COMP1_INP/

OPAMP1_VINP

ADC_IN2/

COMP1_INP/

OPAMP1_VINM

ADC_IN2/

COMP1_INP

ADC_IN3/

COMP1_INP/

OPAMP1_VOUT

ADC_IN4/

DAC_OUT1/

COMP1_INP

DS10002 Rev 10 39/136

56

Pin descriptions STM32L151xE STM32L152xE

Table 8. STM32L151xE and STM32L152xE pin definitions (continued)

Pins

(1)

Pin name

LQFP144

UFBGA132

LQFP64

LQFP100

WLCSP104

Pin Type

Main

function

(after

reset)

I / O structure

41 K4 30 21 M8 PA5 I/O TC PA5

(2)

Alternate functions

TIM2_CH1_ETR/

SPI1_SCK

Pin functions

TIM3_CH1/TIM10_CH1/S

42 L4 31 22 H6 PA6 I/O FT PA6

PI1_MISO/

LCD_SEG3

TIM3_CH2/TIM11_CH1/

43 - 32 23 K7 PA7 I/O FT PA7

SPI1_MOSI/

LCD_SEG4

TIM3_CH2/TIM11_CH1/

- J5 - - - PA7 I/O FT PA7

SPI1_MOSI/

LCD_SEG4

- M4 - - - OPAMP2_VINM I TC

OPAMP2_

VINM

--

44 K5 33 24 L7 PC4 I/O FT PC4 LCD_SEG22

45 L5 34 25 M7 PC5 I/O FT PC5 LCD_SEG23

Additional

functions

ADC_IN5/

DAC_OUT2/

COMP1_INP

ADC_IN6/

COMP1_INP/

OPAMP2_VINP

ADC_IN7/

COMP1_INP/

OPAMP2_VINM

ADC_IN7/

COMP1_INP

ADC_IN14/

COMP1_INP

ADC_IN15/

COMP1_INP

ADC_IN8/

46 M5 35 26 J6 PB0 I/O TC PB0 TIM3_CH3/LCD_SEG5

COMP1_INP/

OPAMP2_VOUT/

VREF_OUT

ADC_IN9/

47 M6 36 27 K6 PB1 I/O FT PB1 TIM3_CH4/LCD_SEG6

COMP1_INP/

VREF_OUT

48 L6 37 28 M6 PB2 I/O FT

PB2/

BOOT1

BOOT1 ADC_IN0b

49 K6 - - - PF11 I/O FT PF11 - ADC_IN1b

50 J7 - - - PF12 I/O FT PF12 - ADC_IN2b

51 E3 - - - V

52 H3 - - - V

SS_6

DD_6

S- V

S- V

SS_6

DD_6

--

--

53 K7 - - - PF13 I/O FT PF13 - ADC_IN3b

54 J8 - - - PF14 I/O FT PF14 - ADC_IN6b

55 J9 - - - PF15 I/O FT PF15 - ADC_IN7b

40/136 DS10002 Rev 10

STM32L151xE STM32L152xE Pin descriptions

Table 8. STM32L151xE and STM32L152xE pin definitions (continued)

Pins

(1)

Pin name

LQFP144

UFBGA132

LQFP64

LQFP100

WLCSP104

Pin Type

function

I / O structure

Main

(after

reset)

(2)

Alternate functions

Pin functions

Additional

functions

56 H9 - - - PG0 I/O FT PG0 - ADC_IN8b

57 G9 - - - PG1 I/O FT PG1 - ADC_IN9b

58 M7 38 - L6 PE7 I/O TC PE7 -

59 L7 39 - M5 PE8 I/O TC PE8 -

60 M8 40 - M4 PE9 I/O TC PE9 TIM2_CH1_ETR

61 - - - - V

62 - - - - V

SS_7

DD_7

S- V

S- V

SS_7

DD_7

--

--

63 L8 41 - J5 PE10 I/O TC PE10 TIM2_CH2

ADC_IN22/

COMP1_INP

ADC_IN23/

COMP1_INP

ADC_IN24/

COMP1_INP

ADC_IN25/

COMP1_INP

64 M9 42 - L5 PE11 I/O FT PE11 TIM2_CH3 -

65 L9 43 - M3 PE12 I/O FT PE12 TIM2_CH4/SPI1_NSS -

66 M10 44 - K5 PE13 I/O FT PE13 SPI1_SCK -

67 M11 45 - L4 PE14 I/O FT PE14 SPI1_MISO -

68 M12 46 - K4 PE15 I/O FT PE15 SPI1_MOSI -

TIM2_CH3/I2C2_SCL/

69 L10 47 29 M2 PB10 I/O FT PB10

USART3_TX/

LCD_SEG10

TIM2_CH4/I2C2_SDA/

70 L11 48 30 L3 PB11 I/O FT PB11

USART3_RX/

LCD_SEG11

71 F12 49 31

72 G12 50 32 K3 V

L2,
M1

V

SS_1

DD_1

S- V

S- V

SS_1

DD_1

--

--

TIM10_CH1/I2C2_SMBA/

73 L12 51 33 J4 PB12 I/O FT PB12

SPI2_NSS/I2S2_WS/

USART3_CK/

ADC_IN18/

COMP1_INP

LCD_SEG12

-

-

DS10002 Rev 10 41/136

56

Pin descriptions STM32L151xE STM32L152xE

Table 8. STM32L151xE and STM32L152xE pin definitions (continued)

Pins

(1)

Pin name

LQFP144

UFBGA132

LQFP64

LQFP100

WLCSP104

Pin Type

Main

function

(after

reset)

I / O structure

74 K12 52 34 J3 PB13 I/O FT PB13

75 K11 53 35 L1 PB14 I/O FT PB14

76 K10 54 36 K2 PB15 I/O FT PB15

77 K9 55 - H4 PD8 I/O FT PD8

78 K8 56 - J2 PD9 I/O FT PD9

79 J12 57 - K1 PD10 I/O FT PD10

80 J11 58 - G4 PD11 I/O FT PD11

(2)

Alternate functions

TIM9_CH1/SPI2_SCK/

I2S2_CK/

USART3_CTS/

LCD_SEG13

TIM9_CH2/SPI2_MISO/

USART3_RTS/

LCD_SEG14

TIM11_CH1/SPI2_MOSI/

I2S2_SD/

LCD_SEG15

USART3_TX/

LCD_SEG28

USART3_RX/

LCD_SEG29

USART3_CK/

LCD_SEG30

USART3_CTS/

LCD_SEG31

Pin functions

Additional

functions

ADC_IN19/

COMP1_INP

ADC_IN20/

COMP1_INP

ADC_IN21/

COMP1_INP/

RTC_REFIN

-

-

-

-

TIM4_CH1/

81 J10 59 - H3 PD12 I/O FT PD12

USART3_RTS/

-

LCD_SEG32

82 H12 60 - H2 PD13 I/O FT PD13 TIM4_CH2/LCD_SEG33 -

83 - - - - V

84 - - - - V

SS_8

DD_8

S- V

S- V

SS_8

DD_8

--

--

85 H11 61 - J1 PD14 I/O FT PD14 TIM4_CH3/LCD_SEG34 -

86 H10 62 - G3 PD15 I/O FT PD15 TIM4_CH4/LCD_SEG35 -

87 G10 - - - PG2 I/O FT PG2 - ADC_IN10b

88 F9 - - - PG3 I/O FT PG3 - ADC_IN11b

89 F10 - - - PG4 I/O FT PG4 - ADC_IN12b

90 E9 - - - PG5 I/O FT PG5 - -

91 - - - - PG6 I/O FT PG6 - -

92 - - - - PG7 I/O FT PG7 - -

93 - - - - PG8 I/O FT PG8 - -

42/136 DS10002 Rev 10

STM32L151xE STM32L152xE Pin descriptions

Table 8. STM32L151xE and STM32L152xE pin definitions (continued)

Pins

Pin name

LQFP144

UFBGA132

LQFP64

LQFP100

WLCSP104

94 F6 - - - V

95 G6 - - - V

SS_9

DD_9

(1)

Pin Type

S- V

S- V

Main

function

(after

reset)

I / O structure

SS_9

DD_9

96 E12 63 37 H1 PC6 I/O FT PC6

97 E11 64 38 G1 PC7 I/O FT PC7

(2)

Alternate functions

TIM3_CH1/I2S2_MCK/

LCD_SEG24

TIM3_CH2/I2S3_MCK/

LCD_SEG25

Pin functions

Additional

functions

--

--

98 E10 65 39 G2 PC8 I/O FT PC8 TIM3_CH3/LCD_SEG26 -

99 D12 66 40 F4 PC9 I/O FT PC9 TIM3_CH4/LCD_SEG27 -

100 D11 67 41 F3 PA8 I/O FT PA8

101 D10 68 42 F1 PA9 I/O FT PA9

USART1_CK/MCO/

LCD_COM0

USART1_TX /

LCD_COM1

-

-

-

-

102 C12 69 43 F2 PA10 I/O FT PA10

103 B12 70 44 E1 PA11 I/O FT PA11

104 A12 71 45 E2 PA12 I/O FT PA12

105 A11 72 46 E3 PA13 I/O FT

JTMS-

SWDIO

USART1_RX /

LCD_COM2

USART1_CTS/

SPI1_MISO

USART1_RTS/

SPI1_MOSI

USB_DM

USB_DP

JTMS-SWDIO -

106 C11 73 - D1 PH2 I/O FT PH2 - -

107 F11 74 47

108 G11 75 48 C1 V

D2,

A1

V

SS_2

DD_2

109 A10 76 49 D3 PA14 I/O FT

S- V

S- V

SS_2

DD_2

JTCK-

SWCLK

--

--

JTCK-SWCLK -

TIM2_CH1_ETR/

110 A 9 77 5 0 B1 PA 15 I/O FT JTDI

SPI1_NSS/SPI3_NSS/

I2S3_WS/LCD_SEG17/

JTDI

SPI3_SCK/I2S3_CK/

111 B11 78 51 E4 PC10 I/O FT PC10

USART3_TX/ UART4_TX/

LCD_SEG28/

LCD_SEG40/LCD_COM4

-

-

-

DS10002 Rev 10 43/136

56

Pin descriptions STM32L151xE STM32L152xE

Table 8. STM32L151xE and STM32L152xE pin definitions (continued)

Pins

(1)

Pin name

LQFP144

UFBGA132

LQFP64

LQFP100

WLCSP104

Pin Type

function

I / O structure

Main

(after

reset)

(2)

Alternate functions

Pin functions

Additional

functions

SPI3_MISO/USART3_RX/

112 C10 79 52 C2 PC11 I/O FT PC11

UART4_RX/

LCD_SEG29/

LCD_SEG41/LCD_COM5

SPI3_MOSI/I2S3_SD/

USART3_CK/

113 B10 80 53 B2 PC12 I/O FT PC12

UART5_TX/LCD_SEG30/

LCD_SEG42/

LCD_COM6

114 C9 81 - A2 PD0 I/O FT PD0

TIM9_CH1/SPI2_NSS/

I2S2_WS

115 B9 82 - D4 PD1 I/O FT PD1 SPI2_SCK/I2S2_CK -

TIM3_ETR/UART5_RX/

116 C8 83 54 C3 PD2 I/O FT PD2

LCD_SEG31/

LCD_SEG43/LCD_COM7

-

-

-

-

117 B8 84 - C4 PD3 I/O FT PD3

118 B7 85 - A3 PD4 I/O FT PD4

SPI2_MISO/

USART2_CTS

SPI2_MOSI/I2S2_SD/

USART2_RTS

119 A6 86 - B3 PD5 I/O FT PD5 USART2_TX -

120 F7 - - - V

121 G7 - - - V

SS_10

DD_10

S- V

S- V

SS_10

DD_10

--

--

122 B6 87 - B4 PD6 I/O FT PD6 USART2_RX -

123 A5 88 - A4 PD7 I/O FT PD7 TIM9_CH2/USART2_CK -

124 D9 - - - PG9 I/O FT PG9 - -

125 D8 - - - PG10 I/O FT PG10 - -

126 - - - - PG11 I/O FT PG11 - -

127 D7 - - - PG12 I/O FT PG12 - -

128 C7 - - - PG13 I/O FT PG13 - -

129 C6 - - - PG14 I/O FT PG14 - -

130 - - - - V

131 - - - - V

SS_11

DD_11

S- V

S- V

SS_11

DD_11

--

--

-

-

44/136 DS10002 Rev 10

STM32L151xE STM32L152xE Pin descriptions

Table 8. STM32L151xE and STM32L152xE pin definitions (continued)

Pins

(1)

Pin name

LQFP144

UFBGA132

LQFP64

LQFP100

WLCSP104

Pin Type

function

I / O structure

Main

(after

reset)

(2)

Alternate functions

Pin functions

Additional

functions

132 - - - - PG15 I/O FT PG15 - -

TIM2_CH2/SPI1_SCK/

133 A8 89 55 B5 PB3 I/O FT JTDO

SPI3_SCK/ I2S3_CK/

COMP2_INM

LCD_SEG7/JTDO

TIM3_CH1/SPI1_MISO/

134 A7 90 56 A5 PB4 I/O FT NJTRST

SPI3_MISO/

COMP2_INP

LCD_SEG8/NJTRST

TIM3_CH2/I2C1_SMBA/

135 C5 91 57 A6 PB5 I/O FT PB5

SPI1_MOSI/

SPI3_MOSI/I2S3_SD/

COMP2_INP

LCD_SEG9

136 B5 92 58 C5 PB6 I/O FT PB6

TIM4_CH1/I2C1_SCL/

USART1_TX

COMP2_INP

137 B4 93 59 B6 PB7 I/O FT PB7

TIM4_CH2/I2C1_SDA/

USART1_RX

COMP2_INP/

PVD_IN

138 A4 94 60 A7 BOOT0 I B BOOT0 - -

TIM4_CH3/TIM10_CH1/

139 A3 95 61 D5 PB8 I/O FT PB8

I2C1_SCL/

-

LCD_SEG16

TIM4_CH4/

140 B3 96 62 C6 PB9 I/O FT PB9

TIM11_CH1/I2C1_SDA/

-

LCD_COM3

141 C3 97 - B7 PE0 I/O FT PE0

TIM4_ETR/TIM10_CH1/

LCD_SEG36

-

142 A2 98 - A8 PE1 I/O FT PE1 TIM11_CH1/LCD_SEG37 -

143 D3 99 63 C7 V

144 C4 100 64

1. I = input, O = output, S = supply.

2. Function availability depends on the chosen device.

3. Applicable to STM32L152xE devices only. In STM32L151xE devices, this pin should be connected to V

4. The PC14 and PC15 I/Os are only configured as OSC32_IN/OSC32_OUT when the LSE oscillator is ON (by setting the
LSEON bit in the RCC_CSR register). The LSE oscillator pins OSC32_IN/OSC32_OUT can be used as general-purpose
PH0/PH1 I/Os, respectively, when the LSE oscillator is off (after reset, the LSE oscillator is off). The LSE has priority over
the GPIO function. For more details, refer to Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins section
in the STM32L151xx, STM32L152xx and STM32L162xx reference manual (RM0038).

B8,

A9

V

SS_3

DD_3

S- V

S- V

SS_3

DD_3

--

--

.

DD

DS10002 Rev 10 45/136

56

Pin descriptions STM32L151xE STM32L152xE

5. The PH0 and PH1 I/Os are only configured as OSC_IN/OSC_OUT when the HSE oscillator is ON (by setting the HSEON
bit in the RCC_CR register). The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose PH0/PH1 I/Os,
respectively, when the HSE oscillator is off ( after reset, the HSE oscillator is off). The HSE has priority over the GPIO
function.

46/136 DS10002 Rev 10

Alternate functions

STM32L151xE STM32L152xE Pin descriptions

Table 9. Alternate function input/output

Digital alternate function number

DS10002 Rev 10 47/136

AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFIO6 AFIO7 AFIO8

.

AFIO11

.

.

AFIO14 AFIO15

.

Port name

Alternate function

SYSTEM TIM2

BOOT0 BOOT0 - - - - - - - - - - - -

NRST NRST - - - - - - - - - - - - -

PA0 -WK UP 1 -

PA1 - TIM2_CH2 TIM5_CH2 - - - - USART2_RTS - - SEG0 - TIMx_IC2

PA2 - TIM2_CH3 TIM5_CH3 TIM9_CH1 - - - USART2_TX - - SEG1 - TIMx_IC3

PA3 - TIM2_CH4 TIM5_CH4 TIM9_CH2 - - - USART2_RX - - SEG2 - TIMx_IC4

PA4 - - - - - SPI1_NSS

PA5 -

PA6 - - TIM3_CH1 TIM10_CH1 - SPI1_MISO - - - - SEG3 - TIMx_IC3

PA7 - - TIM3_CH2 TIM11_CH1 - SPI1_MOSI - - - - SEG4 - TIMx_IC4

PA8 MCO - - - - - - USART1_CK - - COM0 - TIMx_IC1

PA9 - - - - - - - USART1_TX - - COM1 - TIMx_IC2

PA10 - - - - - - - USART1_RX - - COM2 - TIMx_IC3

TIM2_CH1_
ETR

TIM2_CH1_
ETR

TIM3/4/5TIM9/

10/11

TIM5_CH1 - - - - USART2_CTS - - - - TIMx_IC1

- - - SPI1_SCK - - - - - - TIMx_IC2

I2C1/2 SPI1/2 SPI3

SPI3_NSS
I2S3_WS

USART1/2/3UART4/

USART2_CK - - - - TIMx_IC1

- LCD - CPRI SYSTEM

5

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

48/136 DS10002 Rev 10

Table 9. Alternate function input/output (continued)

Digital alternate function number

Pin descriptions STM32L151xE STM32L152xE

AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFIO6 AFIO7 AFIO8

.

AFIO11

.

.

AFIO14 AFIO15

.

Port name

Alternate function

SYSTEM TIM2

PA11 - - - - - SPI1_MISO - USART1_CTS - - - - TIMx_IC4

PA12 - - - - - SPI1_MOSI - USART1_RTS - - - - TIMx_IC1

PA1 3

PA1 4

PA15 JTDI

PB0 - - TIM3_CH3 - - - - - - - SEG5 - -

PB1 - - TIM3_CH4 - - - - - - - SEG6 - -

PB2 BOOT1 - - - - - - - - - - - -

PB3 JTDO TIM2_CH2 - - - SPI1_SCK

PB4 NJTRST - TIM3_CH1 - - SPI1_MISO SPI3_MISO - - - SEG8 - -

PB5 - - TIM3_CH2 -

PB6 - - TIM4_CH1 - I2C1_SCL - - USART1_TX - - - - -

PB7 - - TIM4_CH2 - I2C1_SDA - - USART1_RX - - - -

PB8 - - TIM4_CH3 TIM10_CH1 I2C1_SCL - - - - - SEG16 - -

JTMS­SWDIO

JTCK­SWCLK

TIM2_CH1_
ETR

TIM3/4/5TIM9/

10/11

- - - - - - - - - - - TIMx_IC2

- - - - - - - - - - - TIMx_IC3

- - - SPI1_NSS

I2C1/2 SPI1/2 SPI3

SPI3_NSS
I2S3_WS

SPI3_SCK
I2S3_CK

I2C1_
SMBA

SPI1_MOSI

SPI3_MOSI
I2S3_SD

USART1/2/3UART4/

- - - SEG17 - TIMx_IC4

---SEG7 --

---SEG9 --

- LCD - CPRI SYSTEM

5

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVEN
TOUT

EVEN
TOUT

EVEN
TOUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

Table 9. Alternate function input/output (continued)

Digital alternate function number

STM32L151xE STM32L152xE Pin descriptions

DS10002 Rev 10 49/136

AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFIO6 AFIO7 AFIO8

.

AFIO11

.

.

AFIO14 AFIO15

.

Port name

Alternate function

SYSTEM TIM2

PB9 - - TIM4_CH4 TIM11_CH1 I2C1_SDA - - - - - COM3 - -

PB10 - TIM2_CH3 - - I2C2_SCL - - USART3_TX - - SEG10 - -

PB11 - TIM2_CH4 - - I2C2_SDA - - USART3_RX - - SEG11 - -

PB12 - - - TIM10_CH1

PB13 - - - TIM9_CH1 -

PB14 - - - TIM9_CH2 - SPI2_MISO - USART3_RTS - - SEG14 - -

PB15 - - - TIM11_CH1 -

PC0 - - - - - - - - - - SEG18 - TIMx_IC1

PC1 - - - - - - - - - - SEG19 - TIMx_IC2

PC2 - - - - - - - - - - SEG20 - TIMx_IC3

PC3 - - - - - - - - - - SEG21 - TIMx_IC4

PC4 - - - - - - - - - - SEG22 - TIMx_IC1

PC5 - - - - - - - - - - SEG23 - TIMx_IC2

PC6 - - TIM3_CH1 - - I2S2_MCK - - - - SEG24 - TIMx_IC3

TIM3/4/5TIM9/

10/11

I2C1/2 SPI1/2 SPI3

I2C2_SM
BA

SPI2_NSS
I2S2_WS

SPI2_SCK
I2S2_CK

SPI2_MOSI
I2S2_SD

USART1/2/3UART4/

- USART3_CK - - SEG12 - -

- USART3_CTS - - SEG13 - -

----SEG15 --

- LCD - CPRI SYSTEM

5

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

50/136 DS10002 Rev 10

Table 9. Alternate function input/output (continued)

Digital alternate function number

Pin descriptions STM32L151xE STM32L152xE

AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFIO6 AFIO7 AFIO8

.

AFIO11

.

.

AFIO14 AFIO15

.

Port name

Alternate function

SYSTEM TIM2

PC7 - - TIM3_CH2 - - - I2S3_MCK - - - SEG25 - TIMx_IC4

PC8 - - TIM3_CH3 - - - - - - - SEG26 - TIMx_IC1

PC9 - - TIM3_CH4 - - - - - - - SEG27 - TIMx_IC2

PC10 - - - - - -

PC11 - - - - - - SPI3_MISO USART3_RX UART4_RX -

PC12 - - - - - -

PC13-WKUP2 - - - - - - - - - - - - TIMx_IC2

PC14
OSC32_IN

PC15
OSC32_OUT

PD0 - - - TIM9_CH1 -

PD1 - - - - -

PD2 - - TIM3_ETR - - - - - UART5_RX -

PD3 - - - - - SPI2_MISO - USART2_CTS - - - - TIMx_IC4

------- - ----TIMx_IC3

------- - ----TIMx_IC4

TIM3/4/5TIM9/

10/11

I2C1/2 SPI1/2 SPI3

SPI3_SCK
I2S3_CK

SPI3_MOSI
I2S3_SD

SPI2_NSS
I2S2_WS

SPI2 SCK
I2S2_CK

USART1/2/3UART4/

USART3_TX UART4_TX -

USART3_CK UART5_TX -

------TIMx_IC1

------TIMx_IC2

- LCD - CPRI SYSTEM

5

COM4/
SEG28/
SEG40

COM5/
SEG29
/SEG41

COM6/
SEG30/
SEG42

COM7/
SEG31/
SEG43

- TIMx_IC3

- TIMx_IC4

- TIMx_IC1

- TIMx_IC3

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

Table 9. Alternate function input/output (continued)

Digital alternate function number

STM32L151xE STM32L152xE Pin descriptions

DS10002 Rev 10 51/136

AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFIO6 AFIO7 AFIO8

.

AFIO11

.

.

AFIO14 AFIO15

.

Port name

Alternate function

SYSTEM TIM2

PD4 - - - - -

PD5 - - - - - - - USART2_TX - - - - TIMx_IC2

PD6 - - - - - - - USART2_RX - - - - TIMx_IC3

PD7 - - - TIM9_CH2 - - - USART2_CK - - - - TIMx_IC4

PD8 - - - - - - - USART3_TX - - SEG28 - TIMx_IC1

PD9 - - - - - - - USART3_RX - - SEG29 - TIMx_IC2

PD10 - - - - - - - USART3_CK - - SEG30 - TIMx_IC3

PD11 - - - - - - - USART3_CTS - - SEG31 - TIMx_IC4

PD12 - - TIM4_CH1 - - - - USART3_RTS - - SEG32 - TIMx_IC1

PD13 - - TIM4_CH2 - - - - - - - SEG33 - TIMx_IC2

PD14 - - TIM4_CH3 - - - - - - - SEG34 - TIMx_IC3

PD15 - - TIM4_CH4 - - - - - - - SEG35 - TIMx_IC4

PE0 - - TIM4_ETR TIM10_CH1 - - - - - - SEG36 - TIMx_IC1

PE1 - - - TIM11_CH1 - - - - - - SEG37 - TIMx_IC2

TIM3/4/5TIM9/

10/11

I2C1/2 SPI1/2 SPI3

SPI2_MOSI
I2S2_SD

USART1/2/3UART4/

- USART2_RTS - - - - TIMx_IC1

- LCD - CPRI SYSTEM

5

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

52/136 DS10002 Rev 10

Table 9. Alternate function input/output (continued)

Digital alternate function number

Pin descriptions STM32L151xE STM32L152xE

AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFIO6 AFIO7 AFIO8

.

AFIO11

.

.

AFIO14 AFIO15

.

Port name

Alternate function

SYSTEM TIM2

PE2 TRACECK - TIM3_ETR - - - - - - - SEG 38 - TIMx_IC3

PE3 TRACED0 - TIM3_CH1 - - - - - - - SEG 39 - TIMx_IC4

PE4 TRACED1 - TIM3_CH2 - - - - - - - - - TIMx_IC1

PE5 TRACED2 - - TIM9_CH1 - - - - - - - - TIMx_IC2

PE6­WKUP3

PE7 - - - - - - - - - - - - TIMx_IC4

PE8 - - - - - - - - - - - - TIMx_IC1

PE9 -

PE10 - TIM2_CH2 - - - - - - - - - - TIMx_IC3

PE11 - TIM2_CH3 - - - - - - - - - - TIMx_IC4

PE12 - TIM2_CH4 - - - SPI1_NSS - - - - - - TIMx_IC1

PE13 - - - - - SPI1_SCK - - - - - - TIMx_IC2

PE14 - - - - - SPI1_MISO - - - - - - TIMx_IC3

PE15 - - - - - SPI1_MOSI - - - - - - TIMx_IC4

TRACED3 - - TIM9_CH2 - - - - - - - - TIMx_IC3

TIM2_CH1_
ETR

TIM3/4/5TIM9/

10/11

----- - ----TIMx_IC2

I2C1/2 SPI1/2 SPI3

USART1/2/3UART4/

5

- LCD - CPRI SYSTEM

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

Table 9. Alternate function input/output (continued)

Digital alternate function number

STM32L151xE STM32L152xE Pin descriptions

DS10002 Rev 10 53/136

AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFIO6 AFIO7 AFIO8

.

AFIO11

.

.

AFIO14 AFIO15

.

Port name

Alternate function

SYSTEM TIM2

PF0 - - - - - - - - - - - - -

PF1 - - - - - - - - - - - - -

PF2 - - - - - - - - - - - - -

PF3 - - - - - - - - - - - - -

PF4 - - - - - - - - - - - - -

PF5 - - - - - - - - - - - - -

PF6 - - TIM5_ETR - - - - - - - - - -

PF7 - - TIM5_CH2 - - - - - - - - - -

PF8 - - TIM5_CH3 - - - - - - - - - -

PF9 - - TIM5_CH4 - - - - - - - - - -

PF10 - - - - - - - - - - - - -

PF11 - - - - - - - - - - - - -

PF12 - - - - - - - - - - - - -

PF13 - - - - - - - - - - - - -

TIM3/4/5TIM9/

10/11

I2C1/2 SPI1/2 SPI3

USART1/2/3UART4/

5

- LCD - CPRI SYSTEM

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

54/136 DS10002 Rev 10

Table 9. Alternate function input/output (continued)

Digital alternate function number

Pin descriptions STM32L151xE STM32L152xE

AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFIO6 AFIO7 AFIO8

.

AFIO11

.

.

AFIO14 AFIO15

.

Port name

Alternate function

SYSTEM TIM2

PF14 - - - - - - - - - - - - -

PF15 - - - - - - - - - - - - -

PG0 - - - - - - - - - - - - -

PG1 - - - - - - - - - - - - -

PG2 - - - - - - - - - - - - -

PG3 - - - - - - - - - - - - -

PG4 - - - - - - - - - - - - -

PG5 - - - - - - - - - - - - -

PG6 - - - - - - - - - - - - -

PG7 - - - - - - - - - - - - -

PG8 - - - - - - - - - - - - -

PG9 - - - - - - - - - - - - -

PG10 - - - - - - - - - - - - -

PG11 - - - - - - - - - - - - -

TIM3/4/5TIM9/

10/11

I2C1/2 SPI1/2 SPI3

USART1/2/3UART4/

5

- LCD - CPRI SYSTEM

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

Table 9. Alternate function input/output (continued)

Digital alternate function number

STM32L151xE STM32L152xE Pin descriptions

DS10002 Rev 10 55/136

AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFIO6 AFIO7 AFIO8

.

AFIO11

.

.

AFIO14 AFIO15

.

Port name

Alternate function

SYSTEM TIM2

PG12 - - - - - - - - - - - - -

PG13 - - - - - - - - - - - - -

PG14 - - - - - - - - - - - - -

PG15 - - - - - - - - - - - - -

PH0OSC_IN - - - - - - - - - - - - - -

PH1OSC_OUT - - - - - - - - - - - - - -

PH2 - - - - - - - - - - - - - -

TIM3/4/5TIM9/

10/11

I2C1/2 SPI1/2 SPI3

USART1/2/3UART4/

5

- LCD - CPRI SYSTEM

EVENT
OUT

EVENT
OUT

EVENT
OUT

EVENT
OUT

Memory mapping STM32L151xE STM32L152xE

MS33003V4

reserved

reserved

APB memory space

CRC

Reserved

RTC

WWDG

IWDG

SPI2

USART2

USART3

SYSCFG

TIM9

TIM11

reserved

ADC

USART1

reserved

SPI3

SPI1

I2C1

PWR

TIM10

I2C2

EXTI

RCC

DMA2

USB Registers

DMA1

0

1

2

3

4

5

6

7

0x6000 0000

Peripherals

SRAM

Cortex-M3 Internal

Peripherals

512 byte USB

TIM6

TIM7

LCD

0x4000 1000

0x4000 1400

0x4000 2400

0x4000 1C00

DAC1 & 2

Port A

Port B

Port C

Port D

Port E

Port H

Port F

0x4002 1C00

0x4002 1800
0x4002 1400

0x4002 1000

0x4002 0C00

0x4002 0800
0x4002 0400

COMP + RI

Flash memory

reserved

System memory

Aliased to Flash or system
memory depending on
BOOT pins

0x0000 0000

EEPROM

reserved

UART5

UART4

Port G

Non-

volatile

memory

Bank 1

Flash memory

Bank 2

Data EEPROM

Bank 2

Bank 1

System memory

Bank 2

Bytes

reserved

Bytes

0xFFFF FFFF

0xE010 0000

0xE000 0000

0xC000 0000

0xA000 0000

0x8000 0000

0x1FF0 2000

0x4000 0000

0x2000 0000

0x0000 0000

0x1FF8 009F
0x1FF8 0080

0x1FF8 0020

0x1FF8 0000

0x1FF0 0000

0x1FF0 1000

0x0808 4000

0x0808 2000

0x0808 0000

0x0804 0000

0x0800 0000

0x4002 6000

0x4002 67FF

0x4002 6400

0x4002 3800

0x4002 4000

0x4002 3C00

0x4002 3400

0x4002 0000

0x4002 3000

0x4002 2000

0x4001 3C00

0x4001 3000

0x4001 3800

0x4001 3400

0x4001 0400

0x4001 2C00

0x4001 2800

0x4001 2400

0x4001 1400

0x4001 1000

0x4001 0C00

0x4001 0800

0x4001 0000

0x4000 8000

0x4001 7C00

0x4000 7800
0x4000 7400

0x4000 7000

0x4000 6400
0x4000 6000

0x4000 5C00

0x4000 5800

0x4000 5400

0x4000 5000

0x4000 4C00

0x4000 4800

0x4000 4400

0x4000 4000

0x4000 3C00

0x4000 3800
0x4000 3400

0x4000 3000

0x4000 2C00

0x4000 2800

0x4000 0C00

0x4000 0800

0x4000 0000

0x4000 0400

reserved

reserved

reserved

Data

Bank 1

reserved

reserved

reserved

reserved

reserved

reserved

Flash Interface

Option

Bank 2

Option

Bank 1

reserved

TIM2

TIM3

TIM4

TIM5

5 Memory mapping

56/136 DS10002 Rev 10

Figure 8. Memory map

STM32L151xE STM32L152xE Electrical characteristics

ai17851c

C = 50 pF

MCU pin

ai17852d

MCU pin

V

IN

6 Electrical characteristics

6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

6.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T
the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes. Based on characterization, the minimum and maximum
values refer to sample tests and represent the mean value plus or minus three times the
standard deviation (mean

6.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.6 V (for the

1.65

V ≤ V

tested.

≤ 3.6 V voltage range). They are given only as design guidelines and are not

DD

±3σ).

= 25 °C and TA = TAmax (given by

A

Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated

6.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.

6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 9.

6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 10.

Figure 9. Pin loading conditions Figure 10. Pin input voltage

(mean ±2σ).

DS10002 Rev 10 57/136

114

Electrical characteristics STM32L151xE STM32L152xE

MS32461V3

Analog:

OSC,PLL,COMP,

….

V

DD

GP I/Os

OUT

IN

Kernel logic

(CPU,

Digital &

Memories)

Standby-power circuitry

(LSE,RTC,Wake-up

logic, RTC backup

registers)

N × 100 nF +
1 × 4.7 μF

Regulator

V

SS

V

DDA

V

REF+

V

REF-

V

SSA

ADC/
DAC

Level shifter

IO

Logic

V

DD

100 nF
+ 1 μF

V

REF

100 nF
+ 1 μF

V

DDA

N – number of

V

DD

/V

SS

pairs

6.1.6 Power supply scheme

Figure 11. Power supply scheme

58/136 DS10002 Rev 10

STM32L151xE STM32L152xE Electrical characteristics

MS32462V2

V

DD1/2/.../N

N x 100 nF
+ 1 x 10 μF

Step-up
Converter

V

SS1/2/.../N

V

DD

100 nF

V

LCD

V

LCD

C

EXT

LCD

VSEL

Option 1

Option 2

N x 100 nF

+1 x 10 μF

N x V

SS

N x V

DD

V

SSA

100 nF

+1 μF

A

+

-

V

REF+

V

REF-

V

DDA

V

LCD

MS33028V1

6.1.7 Optional LCD power supply scheme

Figure 12. Optional LCD power supply scheme

1. Option 1: LCD power supply is provided by a dedicated VLCD supply source, VSEL switch is open.

2. Option 2: LCD power supply is provided by the internal step-up converter, VSEL switch is closed, an
external capacitance is needed for correct behavior of this converter.

6.1.8 Current consumption measurement

Figure 13. Current consumption measurement scheme

DS10002 Rev 10 59/136

114

Electrical characteristics STM32L151xE STM32L152xE

6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Tab le 10: Voltage characteristics,

Tabl e 11: Current characteristics, and Table 12: Thermal characteristics may cause

permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.

Symbol Ratings Min Max Unit

Table 10. Voltage characteristics

VDD–V

(2)

V

IN

|ΔV

DDx

− VSS| Variations between all different ground pins

|V

SSX

V

REF+ –VDDA

V

ESD(HBM)

1. All main power (VDD, V
permitted range.

maximum must always be respected. Refer to Table 11 for maximum allowed injected current values.

2. V

IN

3. Include V

External main supply voltage

SS

(including V

DDA

and VDD)

(1)

Input voltage on five-volt tolerant pin V

Input voltage on any other pin V

| Variations between different V

Allowed voltage difference for V

power pins - 50

DD

(3)

> V

REF+

DDA

Electrostatic discharge voltage
(human body model)

REF-

pin.

) and ground (VSS, V

DDA

Table 11. Current characteristics

) pins must always be connected to the external power supply, in the

SSA

–0.3 4.0

− 0.3 VDD+4.0

SS

− 0.3 4.0

SS

-50

-0.4V

see Section 6.3.11 -

Symbol Ratings Max. Unit

(1)

(1)

(1)

(1)

100

100

70

-70

I

VDD(Σ)

I

VSS(Σ)

I

VDD(PIN)

I

VSS(PIN)

(2)

Total current into sum of all V

Total current out of sum of all V

Maximum current into each V

power lines (source)

DD_x

ground lines (sink)

SS_x

power pin (source)

DD_x

Maximum current out of each VSS_x ground pin (sink)

Output current sunk by any I/O and control pin 25

I

IO

ΣI

IO(PIN)

INJ(PIN)

ΣI

INJ(PIN)

(3)

I

1. All main power (VDD, V
permitted range.

2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.

3. Negative injection disturbs the analog performance of the device. See note in Section 6.3.17.

Output current sourced by any I/O and control pin - 25

(6)

(2)

(2)

60

-60

± 5

± 25

Total output current sunk by sum of all IOs and control pins

Total output current sourced by sum of all IOs and control pins

(5)

(4)

, RST and B pins -5/+0

Injected current on five-volt tolerant I/O

Injected current on any other pin

Total injected current (sum of all I/O and control pins)

) and ground (VSS, V

DDA

) pins must always be connected to the external power supply, in the

SSA

mA

V

mV

60/136 DS10002 Rev 10

STM32L151xE STM32L152xE Electrical characteristics

4. Positive current injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. I
exceeded. Refer to Table 10 for maximum allowed input voltage values.

5. A positive injection is induced by V
exceeded. Refer to Table 10: Voltage characteristics for the maximum allowed input voltage values.

6. When several inputs are submitted to a current injection, the maximum ΣI
negative injected currents (instantaneous values).

> VDD while a negative injection is induced by V

IN

INJ(PIN)

< VSS. I

IN

is the absolute sum of the positive and

INJ(PIN)

must never be

INJ(PIN)

must never be

Table 12. Thermal characteristics

Symbol Ratings Value Unit

T

STG

T

J

Storage temperature range –65 to +150 °C

Maximum junction temperature 150 °C

6.3 Operating conditions

6.3.1 General operating conditions

Symbol Parameter Conditions Min Max Unit

f

HCLK

PCLK1

f

PCLK2

V

Internal AHB clock frequency - 0 32

Internal APB1 clock frequency - 0 32

Internal APB2 clock frequency - 0 32

Standard operating voltage

DD

Analog operating voltage
(ADC and DAC not used)

(1)

V

DDA

Analog operating voltage
(ADC or DAC used)

V

I/O input voltage

IN

Table 13. General operating conditions

BOR detector disabled 1.65 3.6

BOR detector enabled, at
power on

BOR detector disabled, after
power on

Must be the same voltage as

(2)

V

DD

FT pins; 2.0 V ≤ V

FT pins; V

< 2.0 V -0.3 5.25

DD

BOOT0 pin 0 5.5

-0.3 5.5

DD

MHzf

1.8 3.6

1.65 3.6

1.65 3.6

1.8 3.6

(3)

(3)

V

V

V

Any other pin -0.3 V

UFBGA132 package - 333

LQFP144 package - 500

Power dissipation at TA = 85 °C for

P

D

suffix 6 or TA = 105 °C for suffix 7

(4)

LQFP100 package - 465

LQFP64 package - 435

WLCSP104 package - 435

Ambient temperature for 6 suffix version Maximum power dissipation

(5)

–40 85

TA

Ambient temperature for 7 suffix version Maximum power dissipation –40 105

DS10002 Rev 10 61/136

DD

+0.3

mW

°C

114

Electrical characteristics STM32L151xE STM32L152xE

Table 13. General operating conditions (continued)

Symbol Parameter Conditions Min Max Unit

TJ Junction temperature range

6 suffix version –40 105

7 suffix version –40 110

1. When the ADC is used, refer to Table 55: ADC characteristics.

2. It is recommended to power V
V

can be tolerated during power-up .

DDA

3. To sustain a voltage higher than VDD+0.3V, the internal pull-up/pull-down resistors must be disabled.

is lower, higher PD values are allowed as long as TJ does not exceed TJ max (see Table 71: Thermal characteristics

4. If T

A

on page 130).

5. In low-power dissipation state, T
max (see Table 71: Thermal characteristics on page 130).

and V

DD

can be extended to -40°C to 105°C temperature range as long as TJ does not exceed T

A

from the same source. A maximum difference of 300 mV between VDD and

DDA

6.3.2 Embedded reset and power control block characteristics

The parameters given in the following table are derived from the tests performed under the
conditions summarized in

Table 14. Embedded reset and power control block characteristics

Symbol Parameter Conditions Min Typ Max Unit

VDD rise time rate

(1)

t

VDD

V

fall time rate

DD

T

RSTTEMPO

V

POR/PDR

(1)

Reset temporization

Power on/power down reset
threshold

Tabl e 13.

BOR detector enabled 0 -

∞

BOR detector disabled 0 - 1000

BOR detector enabled 20 - ∞

BOR detector disabled 0 - 1000

V

rising, BOR enabled - 2 3.3

DD

rising, BOR disabled

V

DD

(2)

0.4 0.7 1.6

Falling edge 1 1.5 1.65

Rising edge 1.3 1.5 1.65

°C

J

µs/V

ms

V

BOR0

Brown-out reset threshold 0

Rising edge 1.69 1.76 1.8

Falling edge 1.87 1.93 1.97

Falling edge 1.67 1.7 1.74

V

BOR1

Brown-out reset threshold 1

Rising edge 1.96 2.03 2.07

Falling edge 2.22 2.30 2.35

V

BOR2

Brown-out reset threshold 2

Rising edge 2.31 2.41 2.44

62/136 DS10002 Rev 10

V

STM32L151xE STM32L152xE Electrical characteristics

Table 14. Embedded reset and power control block characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit

V

V

V

V

V

V

V

V

V

BOR3

BOR4

PVD0

PVD1

PVD2

PVD3

PVD4

PVD5

PVD6

Brown-out reset threshold 3

Brown-out reset threshold 4

Programmable voltage detector
threshold 0

PVD threshold 1

PVD threshold 2

PVD threshold 3

PVD threshold 4

PVD threshold 5

PVD threshold 6

Falling edge 2.45 2.55 2.6

Rising edge 2.54 2.66 2.7

Falling edge 2.68 2.8 2.85

Rising edge 2.78 2.9 2.95

Falling edge 1.8 1.85 1.88

Rising edge 1.88 1.94 1.99

Falling edge 1.98 2.04 2.09

Rising edge 2.08 2.14 2.18

Falling edge 2.20 2.24 2.28

V

Rising edge 2.28 2.34 2.38

Falling edge 2.39 2.44 2.48

Rising edge 2.47 2.54 2.58

Falling edge 2.57 2.64 2.69

Rising edge 2.68 2.74 2.79

Falling edge 2.77 2.83 2.88

Rising edge 2.87 2.94 2.99

Falling edge 2.97 3.05 3.09

Rising edge 3.08 3.15 3.20

BOR0 threshold - 40 -

V

hyst

1. Guaranteed by characterization results.

2. Valid for device version without BOR at power up. See option “D” in Ordering information scheme for more details.

Hysteresis voltage

All BOR and PVD
thresholds excepting BOR0

- 100 -

mV

DS10002 Rev 10 63/136

114

Electrical characteristics STM32L151xE STM32L152xE

6.3.3 Embedded internal reference voltage

The parameters given in Tab le 16 are based on characterization results, unless otherwise
specified.

VREFINT_CAL

Table 15. Embedded internal reference voltage calibration values

Calibration value name Description Memory address

Raw data acquired at
temperature of 30 °C ±5 °C
V

= 3 V ±10 mV

DDA

0x1FF8 00F8 - 0x1FF8 00F9

Table 16. Embedded internal reference voltage

Symbol Parameter Conditions Min Typ Max Unit

Coeff

Coeff

(3)

(3)

(3)

(1)

Internal reference voltage – 40 °C < TJ < +110 °C 1.202 1.224 1.242 V

Internal reference current
consumption

--1.42.3µA

Internal reference startup time - - 2 3 ms

V

and V

DDA

V

Accuracy of factory-measured V
value

factory measure

REFINT

(2)

voltage during

REF+

Including uncertainties

REF

due to ADC and
V

DDA/VREF+

- 2.99 3 3.01 V

-- ±5mV

values

Temperature coefficient –40 °C < TJ < +110 °C - 25 100 ppm/°C

Long-term stability 1000 hours, T= 25 °C - - 1000 ppm

(3)

Voltage coefficient 3.0 V < V

ADC sampling time when reading

(3)

the internal reference voltage

Startup time of reference voltage

(3)

buffer for ADC

Consumption of reference voltage

(3)

buffer for ADC

(3)

VREF_OUT output current

(3)

VREF_OUT output load - - - 50 pF

(4)

Consumption of reference voltage
buffer for VREF_OUT and COMP

(3)

1/4 reference voltage - 24 25 26

(3)

1/2 reference voltage - 49 50 51

(3)

3/4 reference voltage - 74 75 76

value is individually measured in production and stored in dedicated EEPROM bytes.

REF

< 3.6 V - - 2000 ppm/V

DDA

-4--µs

---10µs

- - 13.5 25 µA

---1µA

- - 730 1200 nA

V

REFINT out

I

REFINT

T

VREFINT

V

VREF_MEAS

A

VREF_MEAS

T

A

V

DDCoeff

T

S_vrefint

T

ADC_BUF

I

BUF_ADC

I

VREF_OUT

C

VREF_OUT

I

LPBUF

V

REFINT_DIV1

V

REFINT_DIV2

V

REFINT_DIV3

1. Guaranteed by test in production.

2. The internal V

3. Guaranteed by characterization results.

4. To guarantee less than 1% VREF_OUT deviation.

V

REFINT

%

64/136 DS10002 Rev 10

STM32L151xE STM32L152xE Electrical characteristics

6.3.4 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, temperature, I/O pin loading, device software configuration, operating
frequencies, I/O pin switching rate, program location in memory and executed binary code.
The current consumption is measured as described in

measurement scheme.

All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to the Dhrystone 2.1 code, unless
otherwise specified. The current consumption values are derived from tests performed
under ambient temperature T

= 25 °C and VDD supply voltage conditions summarized in

A

Tabl e 13: General operating conditions, unless otherwise specified.

The MCU is placed under the following conditions:

• All I/O pins are configured in analog input mode

• All peripherals are disabled except when explicitly mentioned.

• The Flash memory access time, 64-bit access and prefetch is adjusted depending on

f

frequency and voltage range to provide the best CPU performance.

HCLK

• When the peripherals are enabled f

APB1

= f

• When PLL is ON, the PLL inputs are equal to HSI = 16 MHz (if internal clock is used) or
HSE = 16 MHz (if HSE bypass mode is used).

• The HSE user clock applied to OSCI_IN input follows the characteristic specified in

Table 26: High-speed external user clock characteristics.

• For maximum current consumption V

• For typical current consumption V

DD

DD

= V

= V

DDA

specified otherwise.

Figure 13: Current consumption

= f

APB2

= 3.6 V is applied to all supply pins.

DDA

AHB

.

= 3.0 V is applied to all supply pins if not

DS10002 Rev 10 65/136

114

Electrical characteristics STM32L151xE STM32L152xE

Table 17. Current consumption in Run mode, code with data processing running from

Flash

Symbol Parameter Conditions f

Range 3, V

CORE

=1.2

V VOS[1:0] = 11

f

I

DD

(Run
from
Flash)

Supply
current in
Run mode,
code
executed
from Flash

= f

HSE

16 MHz included,

= f

f

HSE

above 16 MHz (PLL

(2)

ON)

HSI clock source
(16 MHz)

HCLK

HCLK

up to

/2

Range 2, V

CORE

V VOS[1:0] = 10

Range 1, V

CORE

V VOS[1:0] = 01

Range 2, V

CORE

V VOS[1:0] = 10

Range 1, V

CORE

=1.5

=1.8

=1.5

=1.8

V VOS[1:0] = 01

MSI clock, 65 kHz

Range 3, V

CORE

=1.2

V VOS[1:0] = 11

MSI clock, 4.2 MHz 4.2 MHz 820 1200

1. Guaranteed by characterization results, unless otherwise specified.

2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).

HCLK

Typ Max

1 MHz 225 500

4 MHz 780 1200

4 MHz 0.98 1.6

8 MHz 1.85 2.9

16 MHz 3.6 5.2

8 MHz 2.2 3.5

16 MHz 4.4 6.5

32 MHz 8.6 12

16 MHz 3.6 5.2

32 MHz 8.7 12.3

65 kHz 42 145

(1)

Unit

µA2 MHz 420 750

mA

µAMSI clock, 524 kHz 524 kHz 135 250

66/136 DS10002 Rev 10

STM32L151xE STM32L152xE Electrical characteristics

Table 18. Current consumption in Run mode, code with data processing running from

RAM

Symbol Parameter Conditions f

Range 3,

=1.2 V

V

CORE

VOS[1:0] = 11

IDD
(Run
from
RAM)

Supply current
in Run mode,
code executed
from RAM,
Flash switched
off

= f

f

HSE

16 MHz included,

= f

f

HSE

above 16 MHz
(PLL ON)

HSI clock source
(16 MHz)

HCLK

HCLK

(2)

up to

/2

Range 2,

=1.5 V

V

CORE

VOS[1:0] = 10

Range 1,

=1.8 V

V

CORE

VOS[1:0] = 01

Range 2,

=1.5 V

V

CORE

VOS[1:0] = 10

Range 1,
V

=1.8 V

CORE

VOS[1:0] = 01

HCLK

Typ M ax

1 MHz 200 470

4 MHz 685 1200

4 MHz 0.80 1.5

8 MHz 1.6 3

16 MHz 3.1 5

8 MHz 1.9 3.5

16 MHz 3.7 5.55

32 MHz 7.55 10.9

16 MHz 3.15 4.8

32 MHz 7.75 11.7

(1)

Unit

µA2 MHz 360 780

mA

MSI clock, 65 kHz

MSI clock, 4.2 MHz 4.2 MHz 715 1100

1. Guaranteed by characterization results, unless otherwise specified.

2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).

Range 3,
V

=1.2 V

CORE

VOS[1:0] = 11

65 kHz 40 130

µAMSI clock, 524 kHz 524 kHz 115 215

DS10002 Rev 10 67/136

114

Electrical characteristics STM32L151xE STM32L152xE

Table 19. Current consumption in Sleep mode

Symbol Parameter Conditions f

Range 3,
V

=1.2 V

CORE

VOS[1:0] = 11

f

Supply current
in Sleep

= f

HSE

16 MHz included,

= f

f

HSE

above 16 MHz (PLL

(2)

ON)

HCLK

HCLK

up to

/2

Range 2,

=1.5 V

V

CORE

VOS[1:0] = 10

Range 1,

=1.8 V

V

CORE

VOS[1:0] = 01

mode, Flash
OFF

HSI clock source
(16 MHz)

Range 2,
V

=1.5 V

CORE

VOS[1:0] = 10

Range 1,
V

=1.8 V

CORE

VOS[1:0] = 01

MSI clock, 65 kHz

MSI clock, 524 kHz 524 kHz 33 110

MSI clock, 4.2 MHz 4.2 MHz 150 273

Range 3,
V

=1.2 V

CORE

VOS[1:0] = 11

IDD (Sleep)

Range 3,
V

=1.2 V

CORE

VOS[1:0] = 11

Supply current
in Sleep
mode, Flash
ON

= f

f

HSE

16 MHz included,
f

= f

HSE

above 16 MHz (PLL

(2)

ON)

HCLK

HCLK

up to

/2

Range 2,

=1.5 V

V

CORE

VOS[1:0] = 10

Range 1,

=1.8 V

V

CORE

VOS[1:0] = 01

Range 2,

=1.5 V

V

CORE

HSI clock source
(16 MHz)

VOS[1:0] = 10

Range 1,
V

=1.8 V

CORE

VOS[1:0] = 01

Supply current
in Sleep
mode, Flash
ON

1. Guaranteed by characterization results, unless otherwise specified.

2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register)

MSI clock, 65 kHz

MSI clock, 524 kHz 524 kHz 45 125

MSI clock, 4.2 MHz 4.2 MHz 160 290

Range 3,

=1.2V

V

CORE

VOS[1:0] = 11

HCLK

Typ Ma x

1 MHz 51 220

2 MHz 81 300

4 MHz 140 380

4 MHz 175 500

8 MHz 330 700

16 MHz 625 1100

8 MHz 395 800

16 MHz 760 1250

32 MHz 1700 2700

16 MHz 670 1100

32 MHz 1750 2700

65 kHz 19 92

1 MHz 63 250

2 MHz 93 300

4 MHz 155 380

4 MHz 190 500

8 MHz 340 700

16 MHz 640 1120

8 MHz 410 800

16 MHz 770 1300

32 MHz 1750 2700

16 MHz 690 1160

32 MHz 1750 2800

65 kHz 31 105

(1)

Unit

µA

68/136 DS10002 Rev 10

STM32L151xE STM32L152xE Electrical characteristics

Table 20. Current consumption in Low-power run mode

Symbol Parameter Conditions Typ Max

TA = -40 °C to 25 °C 11 16

MSI clock, 65 kHz

= 32 kHz

f

All

HCLK

peripherals
OFF, code
executed
from RAM,
Flash

MSI clock, 65 kHz

= 65 kHz

f

HCLK

switched
OFF, V
from 1.65 V
to 3.6 V

DD

MSI clock, 131 kHz
f

HCLK

= 131 kHz

Supply

I

DD (LP

Run)

current in
Low-power
run mode

MSI clock, 65 kHz

= 32 kHz

f

HCLK

All
peripherals
OFF, code
executed
from Flash,

MSI clock, 65 kHz

= 65 kHz

f

HCLK

VDD from

1.65 V to

3.6 V

Max allowed

I

max

DD

(LP Run)

current in
Low-power
run mode

1. Guaranteed by characterization results, unless otherwise specified.

from

V

DD

1.65 V to

3.6 V

MSI clock, 131 kHz
f

= 131 kHz

HCLK

- - - 200

= 85 °C 36.2 40

T

A

= 105 °C 65.4 102

T

A

TA =-40 °C to 25 °C 16.5 23

= 85 °C 41.9 48

T

A

= 105 °C 72.1 108

T

A

TA = -40 °C to 25 °C 30 45

= 55 °C 36.1 48

T

A

= 85 °C 55.7 66

T

A

T

= 105 °C 86.6 125

A

TA = -40 °C to 25 °C 26 40.5

T

= 85 °C 53.2 67

A

= 105 °C 92.1 120

T

A

TA = -40 °C to 25 °C 33 49

T

= 85 °C 60.2 75

A

= 105 °C 95.6 130

T

A

T

= -40 °C to 25 °C 48.5 71

A

T

= 55 °C 54.7 75

A

= 85 °C 76.1 95

T

A

= 105 °C 112 140

T

A

(1)

Unit

µA

DS10002 Rev 10 69/136

114

Electrical characteristics STM32L151xE STM32L152xE

Table 21. Current consumption in Low-power sleep mode

Symbol Parameter Conditions Typ Max

MSI clock, 65 kHz
f

HCLK

= 32 kHz

TA = -40 °C to 25 °C 5.5 -

Flash OFF

T

= -40 °C to 25 °C 18.5 21

A

= 85 °C 26.8 29

T

A

= 105 °C 37 47

T

A

T

= -40 °C to 25 °C 18.5 21

A

= 85 °C 27.2 29

T

A

= 105 °C 37.3 47

T

A

= -40 °C to 25 °C 21.5 25

T

A

= 55 °C 23.7 26

T

A

T

= 85 °C 29.8 32

A

= 105 °C 39.7 50

T

A

I

DD

(LP Sleep)

Supply
current in
Low-power
sleep mode

All peripherals

DD

from

OFF, V

1.65 V to 3.6 V

MSI clock, 65 kHz
f

= 32 kHz

HCLK

Flash ON

MSI clock, 65 kHz
f

= 65 kHz,

HCLK

Flash ON

MSI clock, 131 kHz

= 131 kHz,

f

HCLK

Flash ON

TA = -40 °C to 25 °C 18.5 21

TIM9 and
USART1
enabled, Flash

DD

from

ON, V

1.65 V to 3.6 V

MSI clock, 65 kHz
f

= 32 kHz

HCLK

MSI clock, 65 kHz

= 65 kHz

f

HCLK

MSI clock, 131 kHz
f

= 131 kHz

HCLK

T

= 85 °C 26.8 29

A

= 105 °C 38.3 47

T

A

TA = -40 °C to 25 °C 18.5 21

T

= 85 °C 27.2 29

A

= 105 °C 38.5 47

T

A

T

= -40 °C to 25 °C 21.5 25

A

T

= 55 °C 23.7 26

A

= 85 °C 29.8 32

T

A

= 105 °C 41.2 50

T

A

Max

max

I

DD

(LP Sleep)

allowed
current in
Low-power

from 1.65 V

V

DD

to 3.6 V

---200

sleep mode

1. Guaranteed by characterization results, unless otherwise specified.

(1)

Unit

µA

70/136 DS10002 Rev 10

STM32L151xE STM32L152xE Electrical characteristics

Table 22. Typical and maximum current consumptions in Stop mode

Symbol Parameter Conditions Typ Max

= -40°C to 25°C

T

RTC clocked by LSI
or LSE external clock
(32.768kHz),
regulator in LP mode,
HSI and HSE OFF
(no independent
watchdog)

LCD
OFF

LCD

ON

(static

duty)

A

= 1.8 V

V

DD

= -40°C to 25°C 1.4 4

T

A

= 55°C 3.02 6

T

A

T

= 85°C 7.44 11

A

= 105°C 15.5 27

T

A

TA = -40°C to 25°C 1.5 6

T

= 55°C 4.65 7

A

= 85°C 9.07 13

T

A

(2)

= 105°C 15.6 31

T

A

1.18 -

TA = -40°C to 25°C 3.9 10

(Stop

I

DD

with RTC)

Supply current in
Stop mode with RTC
enabled

LCD

ON (1/8

duty)

LCD
OFF

= 55°C 5.19 11

T

A

(3)

T

= 85°C 9.8 17

A

= 105°C 18.4 48

T

A

T

= -40°C to 25°C 1.65 -

A

T

= 55°C 3.32 -

A

= 85°C 7.83 -

T

A

= 105°C 16 -

T

A

TA = -40°C to 25°C 1.75 -

RTC clocked by LSE
external quartz
(32.768kHz),
regulator in LP mode,
HSI and HSE OFF
(no independent
watchdog

(4)

LCD

ON

(static

duty)

LCD

ON (1/8

duty)

LCD
OFF

= 55°C 4.9 -

T

A

= 85°C 9.41 -

T

A

(2)

T

= 105°C 15.8 -

A

TA = -40°C to 25°C 4.1 -

= 55°C 5.53 -

T

A

(3)

T

= 85°C 10 -

A

= 105°C 18.5 -

T

A

= -40°C to 25°C

T

A

= 1.8V

V

DD

= -40°C to 25°C

T

A

VDD = 3.0V

1.33 -

1.62 -

(1)

Unit

µA

T

= -40°C to 25°C

A

VDD = 3.6V

1.87 -

DS10002 Rev 10 71/136

114

Electrical characteristics STM32L151xE STM32L152xE

Table 22. Typical and maximum current consumptions in Stop mode (continued)

Symbol Parameter Conditions Typ Max

Regulator in LP mode, HSI and
HSE OFF, independent

= -40°C to 25°C 1.8 2.2

T

A

watchdog and LSI enabled

Supply current in

I

DD

(Stop)

Stop mode (RTC
disabled)

Regulator in LP mode, LSI, HSI
and HSE OFF (no independent
watchdog)

I

DD

(WU from

Stop)

1. Guaranteed by characterization results, unless otherwise specified.

2. LCD enabled with external VLCD, static duty, division ratio = 256, all pixels active, no LCD connected.

3. LCD enabled with external VLCD, 1/8 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD connected.

4. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF
loading capacitors.

5. When MSI = 64 kHz, the RMS current is measured over the first 15 µs following the wakeup event. For the remaining part
of the wakeup period, the current corresponds the Run mode current.

Supply current during
wakeup from Stop
mode

MSI = 4.2 MHz

MSI = 65 kHz

(5)

= -40°C to 25°C 0.560 1.5

T

A

T

= 55°C 2.18 4

A

= 85°C 6.6 12

T

A

= 105°C 14.9 26

T

A

2-

TA = -40°C to 25°C

1.45 -

(1)

Unit

µA

mAMSI = 1.05 MHz 1.45 -

72/136 DS10002 Rev 10

STM32L151xE STM32L152xE Electrical characteristics

Table 23. Typical and maximum current consumptions in Standby mode

(2)

(2)

(1)

Unit

µA

Symbol Parameter Conditions Typ Max

T

= -40 °C to 25 °C

I

DD

(Standby

with RTC)

I

DD

(Standby)

IDD

(WU from

Standby)

Supply current in
Standby mode with RTC
enabled

Supply current in
Standby mode (RTC
disabled)

Supply current during
wakeup time from
Standby mode

RTC clocked by LSI (no
independent watchdog)

RTC clocked by LSE
external quartz (no
independent
watchdog)

(3)

Independent watchdog
and LSI enabled

Independent watchdog
and LSI OFF

-T

A

= 1.8 V

V

DD

= -40 °C to 25 °C 1.11 1.9

T

A

= 55 °C 1.72 2.2

T

A

T

= 85 °C 2.12 4

A

= 105 °C 2.54 8.3

T

A

TA = -40 °C to 25 °C

= 1.8 V

V

DD

= -40 °C to 25 °C 1.28 -

T

A

= 55 °C 2.01 -

T

A

T

= 85 °C 2.5 -

A

= 105 °C 2.98 -

T

A

= -40 °C to 25 °C 1 1.7

T

A

TA = -40 °C to 25 °C 0.29 1

T

= 55 °C 0.96 1.3

A

= 85 °C 1.38 3

T

A

= 105 °C 1.98 7

T

A

= -40 °C to 25 °C 1 - mA

A

0.865 -

0.97 -

1. Guaranteed by characterization results, unless otherwise specified.

2. Guaranteed by test in production.

3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8pF
loading capacitors.

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in the following table. The MCU
is placed under the following conditions:

• all I/O pins are in input mode with a static value at VDD or VSS (no load)

• all peripherals are disabled unless otherwise mentioned

• the given value is calculated by measuring the current consumption

– with all peripherals clocked off

– with only one peripheral clocked on

DS10002 Rev 10 73/136

114

Electrical characteristics STM32L151xE STM32L152xE

APB1

Table 24. Peripheral current consumption

Typical consumption, VDD = 3.0 V, TA = 25 °C

Peripheral

Range 1,

V

=

CORE

1.8 V

VOS[1:0] = 01

TIM2 12.0 10.0 8.0 10.0

TIM3 10.5 8.8 7.0 8.8

TIM4 10.4 8.8 7.0 8.8

TIM5 13.8 11.5 9.1 11.5

TIM6 3.9 3.0 2.5 3.0

TIM7 3.8 3.3 2.6 3.3

LCD 4.2 3.6 2.8 3.6

WWDG 2.9 2.5 2.1 2.5

SPI2 5.4 4.4 3.5 4.4

SPI3 5.5 4.6 3.7 4.6

USART2 7.6 6.2 4.9 6.2

USART3 7.6 6.2 5.0 6.2

Range 2,

V

=

CORE

1.5 V

VOS[1:0] = 10

Range 3,

V

=

CORE

1.2 V

VOS[1:0] = 11

(1)

Low-power

sleep and run

Unit

µA/MHz

(f

HCLK

)

USART4 7.3 6.1 4.8 6.1

USART5 7.6 6.3 5.0 6.3

I2C1 7.3 6.1 4.8 6.1

I2C2 7.2 5.9 4.7 5.9

USB 13.0 11.2 8.9 11.2

PWR 2.6 2.3 1.9 2.3

DAC 5.9 5.0 4.0 5.0

COMP 3.9 3.3 2.6 3.3

74/136 DS10002 Rev 10

STM32L151xE STM32L152xE Electrical characteristics

APB2

AHB

Table 24. Peripheral current consumption

(1)

(continued)

Typical consumption, VDD = 3.0 V, TA = 25 °C

Peripheral

Range 1,

V

=

CORE

1.8 V

VOS[1:0] = 01

Range 2,

V

=

CORE

1.5 V

VOS[1:0] = 10

Range 3,

V

=

CORE

1.2 V

VOS[1:0] = 11

SYSCFG & RI 2.9 2.4 2.0 2.4

TIM9 8.2 6.9 5.5 6.9

TIM10 6.2 5.1 4.1 5.1

TIM11 6.2 5.1 4.1 5.1

(2)

ADC

9.5 7.9 6.2 7.9

SPI1 4.8 3.9 3.2 3.9

USART1 8.2 6.9 5.4 6.9

GPIOA 6.3 5.3 4.1 5.3

GPIOB 6.3 5.3 4.1 5.3

GPIOC 6.3 5.2 4.1 5.2

GPIOD 8.1 6.8 5.4 6.8

GPIOE 6.7 5.7 4.5 5.7

GPIOF 5.9 4.9 3.9 4.9

GPIOG 7.2 6.1 4.9 6.1

GPIOH 1.7 1.4 1.1 1.4

Low-power

sleep and run

Unit

µA/MHz

(f

HCLK

)

CRC 0.8 0.7 0.5 0.7

FLASH 21.6 18.1 16.0 -

(3)

DMA1 16.8 14.5 11.5 14.5

DMA2 15.7 13.6 10.8 13.6

All enabled 222 184 160 165.9

I

DD (RTC)

I

DD (LCD)

I

DD (ADC)

I

DD (DAC)

I

DD (COMP1)

(4)

(5)

0.4

3.1

1450

340

0.16

µA

Slow mode 2

I

DD (COMP2)

I

DD (PVD / BOR)

I

DD (IWDG)

1. Data based on differential IDD measurement between all peripherals OFF an one peripheral with clock enabled, in the
following conditions: f
power run/sleep), f
both cases. No I/O pins toggling.

2. HSI oscillator is OFF for this measure.

Fast mode 5

(6)

= 32 MHz (range 1), f

HCLK

= f

HCLK

, f

APB1

APB2

= f

HCLK

= 16 MHz (range 2), f

HCLK

, default prescaler value for each peripheral. The CPU is in Sleep mode in

2.6

0.25

= 4 MHz (range 3), f

HCLK

= 64kHz (Low-

HCLK

DS10002 Rev 10 75/136

114

Electrical characteristics STM32L151xE STM32L152xE

3. In Low-power sleep and run mode, the Flash memory must always be in power-down mode.

4. Data based on a differential I
consumption not included).

5. Data based on a differential I
VDD/2. DAC is in buffered mode, output is left floating.

6. Including supply current of internal reference voltage.

DD measurement between ADC in reset configuration and continuous ADC conversion (HSI

DD measurement between DAC in reset configuration and continuous DAC conversion of

6.3.5 Wakeup time from low-power mode

The wakeup times given in the following table are measured with the MSI RC oscillator. The
clock source used to wake up the device depends on the current operating mode:

• Sleep mode: the clock source is the clock that was set before entering Sleep mode

• Stop mode: the clock source is the MSI oscillator in the range configured before

entering Stop mode

• Standby mode: the clock source is the MSI oscillator running at 2.1 MHz

All timings are derived from tests performed under the conditions summarized in Tab le 13.

Symbol Parameter Conditions Typ Max

Table 25. Low-power mode wakeup timings

(1)

Unit

t

WUSLEEP

t

WUSLEEP_LP

t

WUSTOP

t

WUSTDBY

Wakeup from Sleep mode f

Wakeup from Low-power sleep
mode, f

HCLK

= 262 kHz

Wakeup from Stop mode,
regulator in Run mode

ULP bit = 1 and FWU bit = 1

Wakeup from Stop mode,
regulator in low-power mode

ULP bit = 1 and FWU bit = 1

Wakeup from Standby mode
ULP bit = 1 and FWU bit = 1

Wakeup from Standby mode
FWU bit = 0

= 32 MHz 0.4 -

HCLK

f

= 262 kHz

HCLK

Flash enabled

f

= 262 kHz

HCLK

Flash switched OFF

= f

f

HCLK

f

HCLK

= 4.2 MHz 8.2 -

MSI

= f

= 4.2 MHz

MSI

Voltage range 1 and 2

f

= f

HCLK

= 4.2 MHz

MSI

Voltage range 3

= f

f

HCLK

f

HCLK

f

HCLK

f

HCLK

f

HCLK

f

HCLK

f

HCLK

f

HCLK

= 2.1 MHz 10.2 13.4

MSI

= f

= 1.05 MHz 16 20

MSI

= f

= 524 kHz 31 37

MSI

= f

= 262 kHz 57 66

MSI

= f

= 131 kHz 112 123

MSI

= MSI = 65 kHz 221 236

= MSI = 2.1 MHz 58 104

= MSI = 2.1 MHz 2.6 3.25 ms

46 -

46 -

7.7 8.9

8.2 13.1

µs

1. Guaranteed by characterization, unless otherwise specified

76/136 DS10002 Rev 10

STM32L151xE STM32L152xE Electrical characteristics

MS19214V2

V

HSEH

t

f(HSE)

90%

10%

T

HSE

t

t

r(HSE)

V

HSEL

t

w(HSEH)

t

w(HSEL)

6.3.6 External clock source characteristics

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.The
external clock signal has to respect the I/O characteristics in
recommended clock input waveform is shown in Figure 14.

Symbol Parameter Conditions Min Typ Max Unit

Table 26. High-speed external user clock characteristics

Section 6.3.12. However, the

(1)

f

HSE_ext

V

HSEH

V

HSEL

t

w(HSEH)

t

w(HSEL)

t

r(HSE)

t

f(HSE)

C

in(HSE)

1. Guaranteed by design.

User external clock source
frequency

OSC_IN input pin high level voltage

OSC_IN input pin low level voltage V

OSC_IN high or low time 12 - -

OSC_IN rise or fall time - - 20

OSC_IN input capacitance - 2.6 - pF

Figure 14. High-speed external clock source AC timing diagram

CSS is on or

PLL is used

CSS is off, PLL

not used

-

1832MHz

0832MHz

0.7V

SS

DD

-V

-0.3V

DD

DD

V

ns

DS10002 Rev 10 77/136

114

Electrical characteristics STM32L151xE STM32L152xE

MS19215V2

V

LSEH

t

f(LSE)

90%

10%

T

LSE

t

t

r(LSE)

V

LSEL

t

w(LSEH)

t

w(LSEL)

Low-speed external user clock generated from an external source

The characteristics given in the following table result from tests performed using a low­speed external clock source, and under the conditions summarized in

Symbol Parameter Conditions Min Typ Max Unit

Table 27. Low-speed external user clock characteristics

Table 13.

(1)

f

LSE_ext

V

LSEH

V

LSEL

t

w(LSEH)

t

w(LSEL)

t

r(LSE)

t

f(LSE)

C

IN(LSE)

1. Guaranteed by design.

User external clock source
frequency

OSC32_IN input pin high level
voltage

OSC32_IN input pin low level
voltage

OSC32_IN high or low time 465 - -

OSC32_IN rise or fall time - - 10

OSC32_IN input capacitance - - 0.6 - pF

Figure 15. Low-speed external clock source AC timing diagram

1 32.768 1000 kHz

0.7V

DD

-V

DD

V

-

V

SS

-0.3V

DD

ns

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 1 to 24 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).

78/136 DS10002 Rev 10

Table 28. In

STM32L151xE STM32L152xE Electrical characteristics

Table 28. HSE oscillator characteristics

(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

f

OSC_IN

R

F

Oscillator frequency - 1 - 24 MHz

Feedback resistor - - 200 - kΩ

Recommended load
capacitance versus

C

equivalent serial
resistance of the crystal

(3)

(RS)

RS = 30 Ω -20 - pF

VDD= 3.3 V,

I

HSE

HSE driving current

V

= V

IN

with 30 pF

SS

-- 3 mA

load

C = 20 pF

f

= 16 MHz

I

DD(HSE)

g

m

t

SU(HSE)

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

2. Guaranteed by characterization results.

3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid
environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into
account if the MCU is used in tough humidity conditions.

4. t

SU(HSE)

reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

HSE oscillator power
consumption

Oscillator
transconductance

(4)

Startup time VDD is stabilized - 1 - ms

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is

OSC

C = 10 pF

= 16 MHz

f

OSC

Startup 3.5 - - mA /V

--

--

2.5 (startup)

0.7 (stabilized)

2.5 (startup)

0.46 (stabilized)

mA

For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5

pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match

the requirements of the crystal or resonator (see

Figure 16). CL1 and C

are usually the

L2

same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of C

and CL2. PCB and MCU pin capacitance must be included (10 pF

L1

can be used as a rough estimate of the combined pin and board capacitance) when sizing
C

and CL2. Refer to the application note AN2867 “Oscillator design guide for ST

L1

microcontrollers” available from the ST website www.st.com.

DS10002 Rev 10 79/136

114

Electrical characteristics STM32L151xE STM32L152xE

OSC_OUT

OSC_IN

f

HSE

to core

C

L1

C

L2

R

F

STM32

Resonator

Consumption

control

g

m

R

m

C

m

L

m

C

O

Resonator

ai18235b

Figure 16. HSE oscillator circuit diagram

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).

Symbol Parameter Conditions Min Typ Max Unit

Table 29. LSE oscillator characteristics (f

= 32.768 kHz)

LSE

Table 29. In

(1)

f

C

I

LSE

R

(2)

LSE

Low speed external oscillator
frequency

Feedback resistor - - 1.2 - MΩ

F

Recommended load capacitance
versus equivalent serial
resistance of the crystal (R

LSE driving current V

(3)

)

S

DD

- - 32.768 - kHz

RS = 30 kΩ -8 -pF

= 3.3 V, V

IN

= V

--1.1µA

SS

VDD = 1.8 V - 450 -

I

DD (LSE)

g

t

SU(LSE)

LSE oscillator current
consumption

Oscillator transconductance - 3 - - µA/V

m

(4)

Startup time VDD is stabilized - 1 - s

= 3.0 V - 600 -

DD

= 3.6V - 750 -

V

DD

1. Guaranteed by characterization results.

2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator
design guide for ST microcontrollers”.

3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with
small R

4. t

32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary
significantly with the crystal manufacturer.

80/136 DS10002 Rev 10

value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details.

S

is the startup time measured from the moment it is enabled (by software) to a stabilized

SU(LSE)

nAV

STM32L151xE STM32L152xE Electrical characteristics

ai17853b

OSC3 2_ OU T

OSC32_IN

f

LSE

CL1

R

F

STM32L1xx

32.768 kHz
resonator

CL2

Resonator with
integrated capacitors

Bias

controlled

gain

Note: For CL1 and CL2, it is recommended to use high-quality ceramic capacitors in the 5 pF to

15

pF range selected to match the requirements of the crystal or resonator (see Figure 17).
CL1 and C
capacitance which is the series combination of C
Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + C
C

is the pin capacitance and board or trace PCB-related capacitance. Typically, it is

stray

are usually the same size. The crystal manufacturer typically specifies a load

L2,

and CL2.

L1

stray

where

between 2 pF and 7 pF.

Caution: To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended

to use a resonator with a load capacitance C

≤ 7 pF. Never use a resonator with a load

L

capacitance of 12.5 pF.
Example: if the user chooses a resonator with a load capacitance of C
C

= 2 pF, then CL1 = CL2 = 8 pF.

stray

= 6 pF and

L

Figure 17. Typical application with a 32.768 kHz crystal

DS10002 Rev 10 81/136

114

Electrical characteristics STM32L151xE STM32L152xE

6.3.7 Internal clock source characteristics

The parameters given in Tab le 30 are derived from tests performed under the conditions
summarized in Table 13.

High-speed internal (HSI) RC oscillator

Symbol Parameter Conditions Min Typ Max Unit

Table 30. HSI oscillator characteristics

f

HSI

TRIM

ACC

t

SU(HSI)

I

DD(HSI)

1. The trimming step differs depending on the trimming code. It is usually negative on the codes which are

multiples of 16 (0x00, 0x10, 0x20, 0x30...0xE0).

2. Guaranteed by characterization results.

3. Guaranteed by test in production.

Frequency VDD = 3.0 V - 16 - MHz

HSI user-trimmed

(1)(2)

resolution

Accuracy of the

(2)

factory-calibrated

HSI

HSI oscillator

HSI oscillator

(2)

startup time

HSI oscillator

(2)

power consumption

Trimming code is not a multiple of 16 - ± 0.4 0.7 %

Trimming code is a multiple of 16 - - ± 1.5 %

= 3.0 V, TA = 25 °C -1

V

DDA

= 3.0 V, TA = 0 to 55 °C -1.5 - 1.5 %

V

DDA

= 3.0 V, TA = -10 to 70 °C -2 - 2 %

V

DDA

V

= 3.0 V, TA = -10 to 85 °C -2.5 - 2 %

DDA

= 3.0 V, TA = -10 to 105 °C -4 - 2 %

V

DDA

V

= 1.65 V to 3.6 V

DDA

TA = -40 to 105 °C

(3)

-1

-4 - 3 %

- - 3.7 6 µs

- - 100 140 µA

(3)

Low-speed internal (LSI) RC oscillator

%

Table 31. LSI oscillator characteristics

Symbol Parameter Min Typ Max Unit

(1)

f

LSI

D

LSI

t

su(LSI)

I

DD(LSI)

1. Guaranteed by test in production.

2. This is a deviation for an individual part, once the initial frequency has been measured.

3. Guaranteed by design.

LSI frequency 26 38 56 kHz

LSI oscillator frequency drift

(2)

0°C ≤ TA ≤ 105°C

(3)

LSI oscillator startup time - - 200 µs

(3)

LSI oscillator power consumption - 400 510 nA

82/136 DS10002 Rev 10

-10 - 4 %

STM32L151xE STM32L152xE Electrical characteristics

Multi-speed internal (MSI) RC oscillator

Symbol Parameter Condition Typ Max Unit

f

MSI

ACC

D

TEMP(MSI)

D

VOLT(MSI)

Frequency after factory calibration, done at

= 3.3 V and TA = 25 °C

V

DD

Frequency error after factory calibration - ±0.5 - %

MSI

MSI oscillator frequency drift

(1)

0 °C ≤ TA ≤ 105 °C

MSI oscillator frequency drift

(1)

1.65 V ≤ VDD ≤ 3.6 V, TA = 25 °C

Table 32. MSI oscillator characteristics

MSI range 0 65.5 -

MSI range 1 131 -

kHz

MSI range 2 262 -

MSI range 3 524 -

MSI range 4 1.05 -

MHzMSI range 5 2.1 -

MSI range 6 4.2 -

- ±3-%

--2.5%/V

MSI range 0 0.75 -

I

DD(MSI)

t

SU(MSI)

(2)

MSI oscillator power consumption

MSI oscillator startup time

MSI range 1 1 -

MSI range 2 1.5 -

MSI range 3 2.5 -

MSI range 4 4.5 -

MSI range 5 8 -

MSI range 6 15 -

MSI range 0 30 -

MSI range 1 20 -

MSI range 2 15 -

MSI range 3 10 -

MSI range 4 6 -

MSI range 5 5 -

MSI range 6,
Voltage range 1

3.5 -

and 2

MSI range 6,
Voltage range 3

5-

µA

µs

DS10002 Rev 10 83/136

114

Electrical characteristics STM32L151xE STM32L152xE

Table 32. MSI oscillator characteristics (continued)

Symbol Parameter Condition Typ Max Unit

MSI range 0 - 40

MSI range 1 - 20

MSI range 2 - 10

MSI range 3 - 4

t

STAB(MSI)

(2)

MSI oscillator stabilization time

MSI range 4 - 2.5

MSI range 5 - 2

MSI range 6,
Voltage range 1
and 2

MSI range 3,
Voltage range 3

Any range to
range 5

f

OVER(MSI)

MSI oscillator frequency overshoot

Any range to
range 6

1. This is a deviation for an individual part, once the initial frequency has been measured.

2. Guaranteed by characterization results.

µs

-2

-3

-4

MHz

-6

84/136 DS10002 Rev 10

STM32L151xE STM32L152xE Electrical characteristics

6.3.8 PLL characteristics

The parameters given in Tab le 33 are derived from tests performed under the conditions
summarized in Table 13.

Symbol Parameter

PLL input clock

f

PLL_IN

f

PLL_OUT

PLL input clock duty cycle 45 - 55 %

PLL output clock 2 - 32 MHz

PLL lock time

t

LOCK

PLL input = 16 MHz
PLL VCO = 96 MHz

Jitter Cycle-to-cycle jitter - - ±

I

(PLL) Current consumption on V

DDA

(PLL) Current consumption on V

I

DD

1. Guaranteed by characterization results.

2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with

the range defined by f

PLL_OUT

Table 33. PLL characteristics

Min Typ Max

(2)

DDA

DD

.

2- 24MHz

-115 160 µs

-220 450

-120 150

Val ue

(1)

600 ps

Unit

µA

6.3.9 Memory characteristics

The characteristics are given at TA = -40 to 105 °C unless otherwise specified.

RAM memory

Symbol Parameter Conditions Min Typ Max Unit

VRM Data retention mode

1. Minimum supply voltage without losing data stored in RAM (in Stop mode or under Reset) or in hardware
registers (only in Stop mode).

Table 34. RAM and hardware registers

(1)

STOP mode (or RESET) 1.65 - - V

DS10002 Rev 10 85/136

114

Electrical characteristics STM32L151xE STM32L152xE

Flash memory and data EEPROM

Symbol Parameter Conditions Min Typ Max

Table 35. Flash memory and data EEPROM characteristics

(1)

Unit

V

t

Operating voltage

DD

Read / Write / Erase

Programming/ erasing
time for byte / word /

prog

double word / half-page

-1.65-3.6V

Erasing - 3.28 3.94

Programming - 3.28 3.94

Average current during
the whole programming /
erase operation

I

DD

Maximum current (peak)

TA = 25 °C, VDD = 3.6 V

during the whole
programming / erase
operation

1. Guaranteed by design.

Table 36. Flash memory and data EEPROM endurance and retention

Symbol Parameter Conditions

Cycling (erase / write)

N

CYC

Program memory

(2)

Cycling (erase / write)

T

= -40°C to

A

105 °C

EEPROM data memory

Data retention (program memory) after
10 kcycles at T

Data retention (EEPROM data memory)
after 300 kcycles at T

(2)

t

RET

Data retention (program memory) after
10 kcycles at T

Data retention (EEPROM data memory)
after 300 kcycles at T

1. Guaranteed by characterization results.

2. Characterization is done according to JEDEC JESD22-A117.

= 85 °C

A

= 105 °C

A

= 85 °C

A

= 105 °C

A

T

T

RET

RET

= +85 °C

= +105 °C

ms

- 600 - µA

-1.52.5mA

Val ue

Unit

Min

10

(1)

Typ M ax

--

kcycles

300

--

30 - -

30 - -

years

10 - -

10 - -

86/136 DS10002 Rev 10

STM32L151xE STM32L152xE Electrical characteristics

6.3.10 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until

a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

• FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V

V

through a 100 pF capacitor, until a functional disturbance occurs. This test is

SS

compliant with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed.

The test results are given in Tab le 37. They are based on the EMS levels and classes
defined in application note AN1709.

Table 37. EMS characteristics

DD

and

Symbol Parameter Conditions

= 3.3 V, LQFP144, TA = +25 °C,

V

V

V

FESD

EFTB

Voltage limits to be applied on any I/O pin to
induce a functional disturbance

Fast transient voltage burst limits to be
applied through 100 pF on VDD and V
pins to induce a functional disturbance

SS

DD

f

= 32 MHz

HCLK

conforms to IEC 61000-4-2

V

= 3.3 V, LQFP144, TA = +25 °C,

DD

f

= 32 MHz

HCLK

conforms to IEC 61000-4-4

Level/
Class

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It must be noted that good EMC
performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• Corrupted program counter

• Unexpected reset

• Critical data corruption (control registers...)

4B

4A

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1
second.

DS10002 Rev 10 87/136

114

Electrical characteristics STM32L151xE STM32L152xE

To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC

61967-2 standard which specifies the test board and the pin loading.

Table 38. EMI characteristics

Max vs. frequency range

Symbol Parameter Conditions

= 3.6 V,

V

DD

Monitored

frequency band

0.1 to 30 MHz -14 -6 -4

TA = 25 °C,

S

EMI

Peak level

LQFP144 package
compliant with IEC
61967-2

130 MHz to 1GHz -7 -1 9

SAE EMI Level 1 2 2.5 -

6.3.11 Electrical sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114, ANSI/ESD STM5.3.1. standard.

Symbol Ratings Conditions Class

Table 39. ESD absolute maximum ratings

4 MHz

voltage
range 3

16 MHz

voltage

range 2

32 MHz
voltage
range 1

Maximum

(1)

value

Unit

dBµV30 to 130 MHz -11 0 9

Unit

Electrostatic

V

ESD(HBM)

discharge voltage
(human body model)

Electrostatic

V

ESD(CDM)

discharge voltage
(charge device model)

1. Guaranteed by characterization results.

= +25 °C, conforming

T

A

to JESD22-A114

= +25 °C, conforming

T

A

to ANSI/ESD STM5.3.1.

88/136 DS10002 Rev 10

LQFP144

and

WLCSP104

packages

packages

except

LQFP144

and

WLCSP104

2 2000 V

C3 250

V

C4 500

STM32L151xE STM32L152xE Electrical characteristics

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up
performance:

• A supply overvoltage is applied to each power supply pin

• A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Symbol Parameter Conditions Class

Table 40. Electrical sensitivities

LU Static latch-up class T

= +105 °C conforming to JESD78A II level A

A

6.3.12 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above V
in order to give an indication of the robustness of the microcontroller in cases when
abnormal injection accidentally happens, susceptibility tests are performed on a sample
basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of –5 µA/+0 µA range), or other functional failure (for example reset occurrence oscillator
frequency deviation, LCD levels).

The test results are given in the Tab le 41.

Symbol Description

I

INJ

1. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject
negative currents.

2. Injection is not possible.

(for standard pins) must be avoided during normal product operation. However,

DD

Table 41. I/O current injection susceptibility

Injected current on all 5 V tolerant (FT) pins -5

Injected current on any other pin -5

Functional susceptibility

Negative

injection

(1)

(1)

Positive

injection

(2)

NA

(2)

+5

Unit

mAInjected current on BOOT0 -0 NA

DS10002 Rev 10 89/136

114

Electrical characteristics STM32L151xE STM32L152xE

6.3.13 I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Tab le 48 are derived from tests
performed under the conditions summarized in Table 13. All I/Os are CMOS and TTL
compliant.

Symbol Parameter Conditions Min Typ

V

V

V

I

Input low level voltage

IL

Input high level voltage

IH

I/O Schmitt trigger voltage

hys

hysteresis

Input leakage current

lkg

(2)

Table 42. I/O static characteristics

TC and FT I/O - - 0.3 V

BOOT0 - - 0.14 V

(4)

TC I/O 0.45 V

FT I/O 0.39 V

BOOT0 0.15 V

TC and FT I/O - 10% V

BOOT0 - 0.01 -

V

≤ V

IN

≤ V

DD

SS

I/Os with LCD

≤ V

V

SS

IN

≤ V

DD

I/Os with analog

switches

V

≤ V

IN

≤ V

DD

SS

I/Os with analog

switches and LCD

V

≤ V

IN

≤ V

DD

SS

I/Os with USB

DD

DD

DD

+0.38

+0.59

+0.56

(2)

(2)

(2)

--

--

--

(3)

DD

Max Unit

(1)(2)

DD

(2)

DD

V

-

--±50

--±50

--±50

nA

--±250

V

≤ V

FT I/O

≤ V

V

IN

V

IN

IN

= V

= V

IN

≤ V

≤ 5V

SS

DD

DD

--±50

--±10µA

25 45 65 kΩ

25 45 65 kΩ

SS

TC and FT I/Os

V

DD

R

R

C

1. Guaranteed by test in production.

2. Guaranteed by design.

3. With a minimum of 200 mV.

4. The max. value may be exceeded if negative current is injected on adjacent pins.

5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution to the series resistance is minimum (~10% order).

Weak pull-up equivalent

PU

PD

IO

(5)(1)

resistor

Weak pull-down equivalent

(5)

resistor

I/O pin capacitance - - 5 - pF

90/136 DS10002 Rev 10

STM32L151xE STM32L152xE Electrical characteristics

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20

mA with the non-standard VOL/V

specifications given in Tab le 43.

OH

In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in

• The sum of the currents sourced by all the I/Os on V
consumption of the MCU sourced on V
I

(see Tab l e 11 ).

VDD(Σ)

• The sum of the currents sunk by all the I/Os on V
consumption of the MCU sunk on V
I

(see Table 11).

VSS(Σ)

SS

Section 6.2:

plus the maximum Run

cannot exceed the absolute maximum rating

DD,

DD,

plus the maximum Run

SS

cannot exceed the absolute maximum rating

Output voltage levels

Unless otherwise specified, the parameters given in Tab le 43 are derived from tests
performed under the conditions summarized in Table 13. All I/Os are CMOS and TTL
compliant.

Symbol Parameter Conditions Min Max Unit

(1)(2)

V

OL

V

OH

V

OL

V

OH

V

OL

V

OH

1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 11

and the sum of IIO (I/O ports and control pins) must not exceed I

2. Guaranteed by test in production.

3. The IIO current sourced by the device must always respect the absolute maximum rating specified in

Table 11 and the sum of IIO (I/O ports and control pins) must not exceed I

4. Guaranteed by characterization results.

Output low level voltage for an I/O pin

(2)(3)

Output high level voltage for an I/O pin VDD-0.4 -

(3)(4)

Output low level voltage for an I/O pin

(3)(4)

Output high level voltage for an I/O pin VDD-0.45 -

(1)(4)

Output low level voltage for an I/O pin

(3)(4)

Output high level voltage for an I/O pin VDD-1.3 -

Table 43. Output voltage characteristics

I

= 8 mA

IO

2.7 V < VDD < 3.6 V

I

= 4 mA

IO

1.65 V < VDD < 3.6 V

I

= 20 mA

IO

VSS

< 3.6 V

DD

.

VDD

.

2.7 V < V

-0.4

-0.45
V

-1.3

DS10002 Rev 10 91/136

114

Electrical characteristics STM32L151xE STM32L152xE

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in Figure 18 and

Tabl e 44, respectively.

Unless otherwise specified, the parameters given in Tab le 44 are derived from tests
performed under the conditions summarized in Table 13.

Table 44. I/O AC characteristics

(1)

OSPEEDRx

[1:0] bit

(1)

value

00

01

10

11

Symbol Parameter Conditions Min Max

f

max(IO)out

t

f(IO)out

t

r(IO)out

f

max(IO)out

t

f(IO)out

t

r(IO)out

F

max(IO)out

t

f(IO)out

t

r(IO)out

F

max(IO)out

t

f(IO)out

t

r(IO)out

Maximum frequency

(3)

Output rise and fall time

Maximum frequency

(3)

Output rise and fall time

Maximum frequency

(3)

Output rise and fall time

Maximum frequency

(3)

Output rise and fall time

CL = 50 pF, V

= 50 pF, V

C

L

C

= 50 pF, V

L

= 50 pF, V

C

L

CL = 50 pF, V

= 50 pF, V

C

L

CL = 50 pF, V

= 50 pF, V

C

L

CL = 50 pF, V

= 50 pF, V

C

L

C

= 50 pF, V

L

= 50 pF, V

C

L

CL = 30 pF, V

= 50 pF, V

C

L

C

= 30 pF, V

L

C

= 50 pF, V

L

= 2.7 V to 3.6 V - 400

DD

= 1.65 V to 2.7 V - 400

DD

= 2.7 V to 3.6 V - 625

DD

= 1.65 V to 2.7 V - 625

DD

= 2.7 V to 3.6 V - 2

DD

= 1.65 V to 2.7 V - 1

DD

= 2.7 V to 3.6 V - 125

DD

= 1.65 V to 2.7 V - 250

DD

= 2.7 V to 3.6 V - 10

DD

= 1.65 V to 2.7 V - 2

DD

= 2.7 V to 3.6 V - 25

DD

= 1.65 V to 2.7 V - 125

DD

= 2.7 V to 3.6 V - 50

DD

= 1.65 V to 2.7 V - 8

DD

= 2.7 V to 3.6 V - 5

DD

= 1.65 V to 2.7 V - 30

DD

(2)

MHz

MHz

MHz

Pulse width of external

-t

EXTIpw

signals detected by the

-8-

EXTI controller

1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32L151xx, STM32L152xx and STM32L162xx
reference manual for a description of GPIO Port configuration register.

2. Guaranteed by design.

3. The maximum frequency is defined in Figure 18.

Unit

kHz

ns

ns

ns

ns

92/136 DS10002 Rev 10

STM32L151xE STM32L152xE Electrical characteristics

ai14131c

10%

90%

50%

t

r(IO)out

OUTPUT

EXTERNAL

ON 50pF

Maximum frequency is achieved if (tr + tf) ≤ 2/3)T and if the duty cycle is (45-55%)

10%

50%

90%

when loaded by 50pF

T

t

f(IO)out

Figure 18. I/O AC characteristics definition

6.3.14 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R

Unless otherwise specified, the parameters given in Tab le 45 are derived from tests
performed under the conditions summarized in Table 13.

(see Tab le 45)

PU

Table 45. NRST pin characteristics

Symbol Parameter Conditions Min Typ Max Unit

NRST input low level

V

IL(NRST)

V

IH(NRST)

V

OL(NRST)

V

hys(NRST)

V

F(NRST)

V

NF(NRST)

1. Guaranteed by design.

2. With a minimum of 200 mV.

3. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is around 10%.

(1)

voltage

NRST input high

(1)

level voltage

NRST output low

(1)

2.7 V < V

level voltage

1.65 V < V

NRST Schmitt trigger

(1)

voltage hysteresis

R

PU

Weak pull-up
equivalent resistor

NRST input filtered

(1)

(3)

pulse

NRST input not

(3)

filtered pulse

---0.3 V

- 0.39V

IOL = 2 mA

< 3.6 V

DD

= 1.5 mA

I

OL

< 2.7 V

DD

--10%V

V

= V

IN

SS

+0.59 - -

DD

--

--

(2)

DD

25 45 65 kΩ

DD

0.4

-mV

---50ns

- 350 - - ns

V

DS10002 Rev 10 93/136

114

Electrical characteristics STM32L151xE STM32L152xE

ai17854b

STM32L1xx

R

PU

NRST

(2)

V

DD

Filter

Internal reset

0.1 μF

External reset circuit(1)

Figure 19. Recommended NRST pin protection

1. The reset network protects the device against parasitic resets. 0.1 uF capacitor must be placed as close as
possible to the chip.

2. The user must ensure that the level on the NRST pin can go below the V

Table 45. Otherwise the reset is not taken into account by the device.

max level specified in

IL(NRST)

6.3.15 TIM timer characteristics

The parameters given in the Table 46 are guaranteed by design.

Refer to Section 6.3.13: I/O port characteristics for details on the input/output ction
characteristics (output compare, input capture, external clock, PWM output).

Table 46. TIMx

(1)

characteristics

Symbol Parameter Conditions Min Max Unit

-1-t

t

res(TIM)

f

EXT

Res

t

COUNTER

Timer resolution time

f

Timer external clock
frequency on CH1 to CH4

Timer resolution - - 16 bit

TIM

f

TIMxCLK

16-bit counter clock

= 32 MHz 31.25 - ns

TIMxCLK

-0f

TIMxCLK

= 32 MHz 0 16 MHz

- 1 65536 t
period when internal clock
is selected (timer’s
prescaler disabled)

f

TIMxCLK

= 32 MHz 0.0312 2048 µs

/2 MHz

- - 65536 × 65536 t

t

MAX_COUNT

1. TIMx is used as a general term to refer to the TIM2, TIM3 and TIM4 timers.

Maximum possible count

f

TIMxCLK

= 32 MHz - 134.2 s

TIMxCLK

TIMxCLK

TIMxCLK

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STM32L151xE STM32L152xE Electrical characteristics

6.3.16 Communications interfaces

I2C interface characteristics

2

The device
protocol with the following restrictions: SDA and SCL are not “true” open-drain I/O pins.
When configured as open-drain, the PMOS connected between the I/O pin and V
disabled, but is still present.

The I2C characteristics are described in Tab le 47. Refer also to Section 6.3.13: I/O port

characteristics

I

C interface meets the requirements of the standard I2C communication

for more details on the input/output ction characteristics (SDA and SCL)

Table 47. I2C characteristics

DD

is

.

Symbol Parameter

t

w(SCLL)

t

w(SCLH)

t

su(SDA)

t

h(SDA)

t

r(SDA)

t

r(SCL)

t

f(SDA)

t

f(SCL)

t

h(STA)

t

su(STA)

t

su(STO)

t

w(STO:STA)

C

SCL clock low time 4.7 - 1.3 -

SCL clock high time 4.0 - 0.6 -

SDA setup time 250 - 100 -

SDA data hold time - 3450

SDA and SCL rise time - 1000 - 300

SDA and SCL fall time - 300 - 300

Start condition hold time 4.0 - 0.6 -

Repeated Start condition
setup time

Stop condition setup time 4.0 - 0.6 - μs

Stop to Start condition time
(bus free)

Capacitive load for each bus

b

line

Standard mode

I2C

(1)(2)

Fast mode I2C

(1)(2)

Unit

Min Max Min Max

(3)

-900

(3)

4.7 - 0.6 -

4.7 - 1.3 - μs

- 400 - 400 pF

µs

ns

µs

Pulse width of spikes that

t

SP

are suppressed by the

050

(4)

050

(4)

analog filter

Guaranteed by design.

1.

2. f

3.

4. The minimum width of the spikes filtered by the analog filter is above t

must be at least 2 MHz to achieve standard mode I²C frequencies. It must be at least 4 MHz to

PCLK1

achieve fast mode I²C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I²C fast
mode clock.

The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL
signal.

.

SP(max)

DS10002 Rev 10 95/136

ns

114

Electrical characteristics STM32L151xE STM32L152xE

ai17855c

START

SDA

R

S

R

P

I

2

C bus

R

P

R

S

V

DD_I2C

V

DD_I2C

STM32L1xx

SDA

SCL

t

f(SDA)

t

r(SDA)

SCL

t

h(STA)

t

w(SCKH)

t

w(SCKL)

t

su(SDA)

t

r(SCK)

t

f(SCK)

t

h(SDA)

START REPEATED

START

t

su(STA)

t

su(STO)

STOP

t

su(STA:STO)

Figure 20. I2C bus AC waveforms and measurement circuit

1. RS = series protection resistor.

= external pull-up resistor.

2. R

P

3. V

4.

is the I2C bus power supply.

DD_I2C

Measurement points are done at CMOS levels: 0.3V

Table 48. SCL frequency (f

PCLK1

and 0.7V

DD

DD.

= 32 MHz, VDD = V

DD_I2C

= 3.3 V)

(1)(2)

I2C_CCR value

f

(kHz)

SCL

R

= 4.7 kΩ

P

400 0x801B

300 0x8024

200 0x8035

100 0x00A0

50 0x0140

20 0x0320

1. RP = External pull-up resistance, f

2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the
tolerance on the achieved speed is ±2%. These variations depend on the accuracy of the external
components used to design the application.

SCL

= I2C speed.

96/136 DS10002 Rev 10

STM32L151xE STM32L152xE Electrical characteristics

SPI characteristics

Unless otherwise specified, the parameters given in the following table are derived from
tests performed under the conditions summarized in

Refer to Section 6.3.12: I/O current injection characteristics for more details on the
input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

Symbol Parameter Conditions Min Max

f

1/t

t

r(SCK)

t

f(SCK)

SCK

c(SCK)

SPI clock frequency

(2)

SPI clock rise and fall time Capacitive load: C = 30 pF - 6 ns

(2)

DuCy(SCK) SPI slave input clock duty cycle Slave mode 30 70 %

Table 49. SPI characteristics

Master mode - 16

Slave mode - 16

Slave transmitter - 12

Table 13.

(1)

(3)

(2)

Unit

MHz

t

su(NSS)

t

h(NSS)

t

w(SCKH)

t

w(SCKL)

t

su(MI)

t

su(SI)

(2)

t

h(MI)

(2)

t

h(SI)

t

a(SO)

t

v(SO)

t

v(MO)

t

h(SO)

t

h(MO)

1. The characteristics above are given for voltage range 1.

2. Guaranteed by characterization results.

3. The maximum SPI clock frequency in slave transmitter mode is given for an SPI slave input clock duty cycle (DuCy(SCK))
ranging between 40 to 60%.

4. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data.

NSS setup time Slave mode 4t

NSS hold time Slave mode 2t

(2)

SCK high and low time Master mode t

(2)

(2)

Data input setup time

(2)

Master mode 5 -

Slave mode 6 -

SCK

Master mode 5 -

Data input hold time

Slave mode 5 -

(4)

Data output access time Slave mode 0 3t

(2)

Data output valid time Slave mode - 33

(2)

Data output valid time Master mode - 6.5

(2)

Data output hold time

(2)

Slave mode 17 -

Master mode 0.5 -

HCLK

HCLK

/2 − 5t

SCK

-

-

/2 +3

HCLK

ns

DS10002 Rev 10 97/136

114

Electrical characteristics STM32L151xE STM32L152xE

SCK input

(SI)

MSB IN

BIT1 IN

LSB IN

BIT6 OUT

MSB OUT

LSB OUT

NSS input

MOSI

INPUT

MISO

OUTPUT

(SI)

ai14135b

NSS input

t

SU(NSS)

tc(SCK)

th(NSS)

SCK input

CPHA=1
CPOL=0

CPHA=1
CPOL=1

t

w(SCKH)

tw(SCKL)

ta(SO)

tv(SO)

th(SO)

tr(SCK)
tf(SCK)

tdis(SO)

MISO

OUTPUT

MOSI

INPUT

t

su(SI)

th(SI)

MSB OUT

MSB IN

BIT6 OUT

LSB OUT

LSB IN

BIT 1 IN

Figure 21. SPI timing diagram - slave mode and CPHA = 0

Figure 22. SPI timing diagram - slave mode and CPHA = 1

1. Measurement points are done at CMOS levels: 0.3V

and 0.7V

DD

(1)

DD.

98/136 DS10002 Rev 10

STM32L151xE STM32L152xE Electrical characteristics

ai14136c

SCK Output

CPHA=0

MOSI

OUTPUT

MISO

INP UT

CPHA=0

LSB OUT

LSB IN

CPOL=0

CPOL=1

B I T1 OUT

NSS input

t

c(SCK)

t

w(SCKH)

t

w(SCKL)

t

r(SCK)

t

f(SCK)

t

h(MI)

High

SCK Output

CPHA=1

CPHA=1

CPOL=0

CPOL=1

t

su(MI)

t

v(MO)

t

h(MO)

MSB IN

BIT6 IN

MSB OUT

Figure 23. SPI timing diagram - master mode

(1)

1. Measurement points are done at CMOS levels: 0.3V

and 0.7V

DD

DD.

DS10002 Rev 10 99/136

114

Electrical characteristics STM32L151xE STM32L152xE

ai14137b

Cross over

points

Differential

data lines

V

CRS

VSS

tf tr

USB characteristics

The USB interface is USB-IF certified (full speed).

Symbol Parameter Max Unit

t

STARTUP

1. Guaranteed by design.

(1)

USB transceiver startup time 1 µs

Table 50. USB startup time

Table 51. USB DC electrical characteristics

Symbol Parameter Conditions Min.

Input levels

V

V

DI

CM

V

SE

USB operating voltage - 3.0 3.6 V

DD

(2)

Differential input sensitivity I(USB_DP, USB_DM) 0.2 -

(2)

Differential common mode range Includes V

(2)

Single ended receiver threshold - 1.3 2.0

range 0.8 2.5

DI

Output levels

(3)

V

OL

V

OH

1. All the voltages are measured from the local ground potential.

2. Guaranteed by characterization results.

3. Guaranteed by test in production.

R

4.

Static output level low RL of 1.5 kΩ to 3.6 V

(3)

Static output level high RL of 15 kΩ to V

is the load connected on the USB drivers.

L

SS

(4)

(4)

Figure 24. USB timings: definition of data signal rise and fall time

(1)

Max.

(1)

-0.3

2.8 3.6

Unit

VV

V

Table 52. USB: full speed electrical characteristics

Driver characteristics

Symbol Parameter Conditions Min Max Unit

t

t

t

rfm

V

CRS

100/136 DS10002 Rev 10

Rise time

r

Fall Time

f

Rise/ fall time matching tr/t

Output signal crossover voltage - 1.3 2.0 V

(2)

(2)

(1)

CL = 50 pF

420ns

CL = 50 pF 4 20 ns

f

90 110 %