STM32L151xE STM32L152xE
LQFP144 (20 × 20 mm)
LQFP100 (14 × 14 mm)
LQFP64 (10 × 10 mm)
UFBGA132
(7 × 7 mm)
WLCSP104
(0.4 mm pitch)
Ultra-low-power 32-bit MCU Arm®-based Cortex®-M3 with 512KB
Flash, 80KB SRAM, 16KB EEPROM, LCD, USB, ADC, DAC
Datasheet - production data
Features
Includes ST state-of-the-art patented
technology
• Ultra-low-power platform
– 1.65 V to 3.6 V power supply
– -40 °C to 105 °C temperature range
– 290 nA Standby mode (3 wakeup pins)
– 1.11 µA Standby mode + RTC
– 560 nA Stop mode (16 wakeup lines)
– 1.4 µA Stop mode + RTC
– 11 µA Low-power run mode down to 4.6 µA
in Low-power sleep mode
– 195 µA/MHz Run mode
– 10 nA ultra-low I/O leakage
– 8 µs wakeup time
• Core: Arm
®
Cortex®-M3 32-bit CPU
– From 32 kHz up to 32 MHz max
– 1.25 DMIPS/MHz (Dhrystone 2.1)
– Memory protection unit
• Up to 34 capacitive sensing channels
• CRC calculation unit, 96-bit unique ID
• Reset and supply management
– Low-power, ultrasafe BOR (brownout reset)
with 5 selectable thresholds
– Ultra-low-power POR/PDR
– Programmable voltage detector (PVD)
• Clock sources
– 1 to 24 MHz crystal oscillator
– 32 kHz oscillator for RTC with calibration
– Internal 16 MHz oscillator factory trimmed
RC(+/-1%) with PLL option
– Internal low-power 37 kHz oscillator
– Internal multispeed low-power 65 kHz to
4.2 MHz oscillator
– PLL for CPU clock and USB (48 MHz)
• Pre-programmed bootloader
– USB and USART supported
• Up to 116 fast I/Os (102 I/Os 5V tolerant), all
mappable on 16 external interrupt vectors
• Memories
– 512 Kbytes of Flash memory with ECC
(with 2 banks of 256 Kbytes enabling RWW
capability)
– 80 Kbytes of RAM
– 16 Kbytes of true EEPROM with ECC
– 128-byte backup register
• LCD driver (except STM32L151xE devices) up
to 8x40 segments, contrast adjustment,
blinking mode, step-up converter
• Rich analog peripherals (down to 1.8 V)
– 2x operational amplifiers
– 12-bit ADC 1 Msps up to 40 channels
– 12-bit DAC 2 ch with output buffers
– 2x ultra-low-power comparators
(window mode and wake up capability)
• DMA controller 12x channels
• 11x peripheral communication interfaces
– 1x USB 2.0 (internal 48 MHz PLL)
– 5x USARTs
– Up to 8x SPIs (2x I2S, 3x 16 Mbit/s)
– 2x I
2
Cs (SMBus/PMBus)
• 11x timers: 1x 32-bit, 6x 16-bit with up to 4
IC/OC/PWM channels, 2x 16-bit basic timers,
2x watchdog timers (independent and window)
• Development support: serial wire debug, JTAG
and trace
April 2021 DS10002 Rev 10 1/136
This is information on a product in full production.
www.st.com
STM32L151xE STM32L152xE
Table 1. Device summary
Reference Part number
STM32L151xE STM32L151QE, STM32L151RE, STM32L151VE, STM32L151ZE
STM32L152xE STM32L152QE, STM32L152RE, STM32L152VE, STM32L152ZE
2/136 DS10002 Rev 10
STM32L151xE STM32L152xE Contents
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.2 Ultra-low-power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.2 Shared peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.3 Common system strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
®
3.2 Arm
Cortex®-M3 core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3 Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3.4 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5 Low-power real-time clock and backup registers . . . . . . . . . . . . . . . . . . . 23
3.6 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.7 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.8 DMA (direct memory access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.9 LCD (liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.10 ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.10.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.10.2 Internal voltage reference (V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
REFINT
3.11 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.12 Operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.13 Ultra-low-power comparators and reference voltage . . . . . . . . . . . . . . . . 27
3.14 System configuration controller and routing interface . . . . . . . . . . . . . . . 27
3.15 Touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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Contents STM32L151xE STM32L152xE
3.16 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.16.1 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM9, TIM10 and
TIM11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.16.2 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.16.3 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.16.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.16.5 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.17 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.17.1 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.17.2 Universal synchronous/asynchronous receiver transmitter (USART) . . 29
3.17.3 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.17.4 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.17.5 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.18 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 30
3.19 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.19.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.19.2 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.1.7 Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.1.8 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.3.2 Embedded reset and power control block characteristics . . . . . . . . . . . 62
6.3.3 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 64
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6.3.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.3.5 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.3.11 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.3.15 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.3.16 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.3.17 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.3.18 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.3.19 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.3.20 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.3.21 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.3.22 LCD controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
7.1 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
7.2 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
7.3 WLCSP104 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
7.4 UFBGA132 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
7.5 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
7.6 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
7.6.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
9 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
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List of tables STM32L151xE STM32L152xE
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table 2. Ultra-low-power STM32L151xE and STM32L152xE device features and peripheral
counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Functionalities depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . 15
Table 4. CPU frequency range depending on dynamic voltage scaling . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Functionalities depending on the working mode (from Run/active down to
standby) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 6. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 7. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 8. STM32L151xE and STM32L152xE pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 9. Alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 10. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 11. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 12. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 13. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 14. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 15. Embedded internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 16. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 17. Current consumption in Run mode, code with data processing running from Flash. . . . . . 66
Table 18. Current consumption in Run mode, code with data processing running from RAM . . . . . . 67
Table 19. Current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 20. Current consumption in Low-power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 21. Current consumption in Low-power sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 22. Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 23. Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 73
Table 24. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 25. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 26. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 27. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 28. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 29. LSE oscillator characteristics (f
Table 30. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 31. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 32. MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 33. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 34. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 35. Flash memory and data EEPROM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 36. Flash memory and data EEPROM endurance and retention . . . . . . . . . . . . . . . . . . . . . . . 86
Table 37. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 38. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 39. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 40. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 41. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 42. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 43. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 44. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 45. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 46. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
LSE
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Table 47. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 48. SCL frequency (f
= 32 MHz, VDD = VDD_I2C = 3.3 V). . . . . . . . . . . . . . . . . . . . . . . . 96
PCLK1
Table 49. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 50. USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 51. USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 52. USB: full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 53. I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 54. ADC clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 55. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 56. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 57. Maximum source impedance R
max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
AIN
Table 58. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 59. Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 60. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 61. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 62. Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 63. Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 64. LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 65. LQFP64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 66. LQPF100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 67. WLCSP104 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 68. WLCSP104 recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 69. UFBGA132 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 70. LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 71. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 72. STM32L151xE and STM32L152xE Ordering information scheme. . . . . . . . . . . . . . . . . . 132
Table 73. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
DS10002 Rev 10 7/136
7
List of figures STM32L151xE STM32L152xE
List of figures
Figure 1. Ultra-low-power STM32L151xE and STM32L152xE block diagram. . . . . . . . . . . . . . . . . . 13
Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 3. STM32L15xRE LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 4. STM32L15xVE LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 5. STM32L15xVEY WLCSP104 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 6. STM32L15xQE UFBGA132 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 7. STM32L15xZE LQFP144 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 8. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 9. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 10. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 11. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 12. Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 13. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 14. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 15. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 16. HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 17. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 18. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 19. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 20. I
Figure 21. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 22. SPI timing diagram - slave mode and CPHA = 1
Figure 23. SPI timing diagram - master mode
Figure 24. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 25. I
Figure 26. I
Figure 27. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 28. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 29. Maximum dynamic current consumption on V
Figure 30. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 31. LQFP64 outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 32. LQFP64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 33. LQFP64 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 34. LQFP100 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 35. LQFP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 36. LQFP100 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 37. WLCSP104 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 38. WLCSP104 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 39. WLCSP104 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 40. UFBGA132 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 41. UFBGA132 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 42. UFBGA132 top view example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 43. LQFP144 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 44. LQFP144 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 45. LQFP144 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 46. Thermal resistance suffix 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 47. Thermal resistance suffix 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
2
C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
(1)
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
2
S slave timing diagram (Philips protocol)
2
S master timing diagram (Philips protocol)
(1)
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
supply pin during ADC
REF+
conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
8/136 DS10002 Rev 10
STM32L151xE STM32L152xE Introduction
1 Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32L151xE and STM32L152xE ultra-low-power Arm
®
Cortex®-M3 based
microcontroller product line. STM32L151xE and STM32L152xE devices are
microcontrollers with a Flash memory density of 512
Kbytes.
The ultra-low-power STM32L151xE and STM32L152xE family includes devices in 5
different package types: from 64 pins to 144 pins. Depending on the device chosen,
different sets of peripherals are included, the description below gives an overview of the
complete range of peripherals proposed in this family.
These features make the ultra-low-power STM32L151xE and STM32L152xE
microcontroller family suitable for a wide range of applications:
• Medical and handheld equipment
• Application control and user interface
• PC peripherals, gaming, GPS and sport equipment
• Alarm systems, wired and wireless sensors, video intercom
• Utility metering
This STM32L151xE and STM32L152xE datasheet must be read in conjunction with the
STM32L1xxxx reference manual (RM0038). The application note “Getting started with
STM32L1xxxx hardware development” (AN3216) gives a hardware implementation
overview. Both documents are available from the STMicroelectronics website www.st.com.
For information on the Arm
®(a)
Cortex®-M3 core, refer to the Arm® Cortex®-M3 technical
reference manual, available from the www.arm.com website. Figure 1 shows the general
block diagram of the device family.
For information on the device errata with respect to the datasheet and reference manual,
refer to the STM32L15xE errata sheet (ES0235), available on the STMicroelectronics
website www.st.com.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
DS10002 Rev 10 9/136
56
Description STM32L151xE STM32L152xE
2 Description
The ultra-low-power STM32L151xE and STM32L152xE devices incorporate the
connectivity power of the universal serial bus (USB) with the high-performance Arm
®
Cortex
protection unit (MPU), high-speed embedded memories (Flash memory up to 512
and RAM up to 80 Kbytes), and an extensive range of enhanced I/Os and peripherals
connected to two APB buses.
The STM32L151xE and STM32L152xE devices offer two operational amplifiers, one 12-bit
ADC, two DACs, two ultra-low-power comparators, one general-purpose 32-bit timer, six
general-purpose 16-bit timers and two basic timers, which can be used as time bases.
Moreover, the STM32L151xE and STM32L152xE devices contain standard and advanced
communication interfaces: up to two I2Cs, three SPIs, two I2S, three USARTs, two UARTs
and an USB. The STM32L151xE and STM32L152xE devices offer up to 34
sensing channels to simply add a touch sensing functionality to any application.
They also include a real-time clock and a set of backup registers that remain powered in
Standby mode.
Finally, the integrated LCD controller (except STM32L151xE devices) has a built-in LCD
voltage generator that allows to drive up to 8 multiplexed LCDs with the contrast
independent of the supply voltage.
The ultra-low-power STM32L151xE and STM32L152xE devices operate from a 1.8 to 3.6 V
power supply (down to 1.65
supply without BOR option. They are available in the -40 to +85 °C and -40 to +105 °C
temperature ranges. A comprehensive set of power-saving modes allows the design of lowpower applications.
-M3 32-bit RISC core operating at a frequency of 32 MHz (33.3 DMIPS), a memory
capacitive
V at power down) with BOR and from a 1.65 to 3.6 V power
®
Kbytes
10/136 DS10002 Rev 10
STM32L151xE STM32L152xE Description
2.1 Device overview
Table 2. Ultra-low-power STM32L151xE and STM32L152xE device features and peripheral
Flash (Kbytes) 512
Data EEPROM (Kbytes) 16
RAM (Kbytes) 80
counts
Peripheral STM32L15xRE STM32L15xVE STM32L15xQE STM32L15xZE
32 bit 1
Timers
General-purpose 6
Basic 2
SPI 8(3)
(1)
I2S 2
Communication
interfaces
2
I
C 2
USART 5
USB 1
GPIOs 51 83 109 115
Operational amplifiers 2
12-bit synchronized ADC
Number of channels
12-bit DAC
Number of channels
(2)
LCD
COM x SEG
1
21
1
4x32 or 8x28
25
1
40
1
1
40
2
2
1
4x44 or 8x40
Comparators 2
Capacitive sensing channels 23 33 34
Max. CPU frequency 32 MHz
Operating voltage
Operating temperatures
Packages LQFP64
1. 5 SPIs are USART configured in synchronous mode emulating SPI master.
2. STM32L152xx devices only.
1.8 V to 3.6 V (down to 1.65 V at power-down) with BOR option
1.65 V to 3.6 V without BOR option
Ambient operating temperature: -40 °C to 85 °C / -40 °C to 105 °C
Junction temperature: –40 to + 110 °C
LQFP100,
WLCSP104
UFBGA132 LQFP144
DS10002 Rev 10 11/136
56
Description STM32L151xE STM32L152xE
2.2 Ultra-low-power device continuum
The ultra-low-power family offers a large choice of cores and features. From proprietary 8bit to up to Cortex-M3, including the Cortex-M0+, the STM32Lx series are the best choice to
answer the user needs, in terms of ultra-low-power features. The STM32 ultra-low-power
series are the best fit, for instance, for gas/water meter, keyboard/mouse or fitness and
healthcare, wearable applications. Several built-in features like LCD drivers, dual-bank
memory, Low-power run mode, op-amp, AES 128-bit, DAC, USB crystal-less and many
others clearly allow very cost-optimized applications to be built by reducing BOM.
Note: STMicroelectronics as a reliable and long-term manufacturer ensures as much as possible
the pin-to-pin compatibility between any STM8Lxxxxx and STM32Lxxxxx devices and
between any of the STM32Lx and STM32Fx series. Thanks to this unprecedented
scalability, the old applications can be upgraded to respond to the latest market features and
efficiency demand.
2.2.1 Performance
All the families incorporate highly energy-efficient cores with both Harvard architecture and
pipelined execution: advanced STM8 core for STM8L families and Arm Cortex-M3 core for
STM32L family. In addition specific care for the design architecture has been taken to
optimize the mA/DMIPS and mA/MHz ratios.
This allows the ultra-low-power performance to range from 5 up to 33.3 DMIPs.
2.2.2 Shared peripherals
STM8L15xxx, STM32L15xxx and STM32L162xx share identical peripherals which ensure a
very easy migration from one family to another:
• Analog peripherals: ADC, DAC and comparators
• Digital peripherals: RTC and some communication interfaces
2.2.3 Common system strategy.
To offer flexibility and optimize performance, the STM8L15xxx, STM32L15xxx and
STM32L162xx family uses a common architecture:
• Same power supply range from 1.65 V to 3.6 V
• Architecture optimized to reach ultra-low consumption both in low-power modes and
Run mode
• Fast startup strategy from low-power modes
• Flexible system clock
• Ultrasafe reset: same reset strategy including power-on reset, power-down reset,
brownout reset and programmable voltage detector
2.2.4 Features
ST ultra-low-power continuum also lies in feature compatibility:
• More than 15 packages with pin count from 20 to 144 pins and size down to 3 x 3 mm
• Memory density ranging from 2 to 512 Kbytes
12/136 DS10002 Rev 10
STM32L151xE STM32L152xE Functional overview
MSv34186V1
POWER
VOLT. REG.
12bit ADC
EXT.IT
WKUP
WinWATCHDOG
JTAG & SW
Fmax: 32 MHz
JTDI
NJTRST
NRST
USB2.0 FS device
SRAM 80K
2x(8x16b i t )
I2C2
TIMER2
TIMER3
XTAL OSC
1-24 MHz
XTAL 32 kHz
EEPROM 64 bit
Backup interface
TIMER4
RTC V2
AWU
RC HSI
obl
USB SRAM 512 B
Trace Controller ETM
USART1
USART2
SPI2/I2S
Backup
Reg 128
I2C1
USART3
RC MSI
Standby
interface
WDG 32K
BOR / Bgap
SPI1
IF
@V DDA
PVD
GPIO PORT C
GPIO PORT D
GPIO PORT E
LCD 8x40
12bit DAC1
FIFIIF
12bit DAC2
DAC_OUT1 as AF
DAC_OUT2 as AF
MPU
GP Comp
PU / PD
PDR
PDR
TIMER6
TIMER7
General purpose
timers
LCD Booster
GPIO PORT H
RC LSI
TIMERS (32 bits)
2x(8x16b i t )
SPI3/I2S
TRACECK, TRACED0, TRACED1, TRACED2, TRACED4
System
Cap. sens
Supply
monitoring
@VDDA
@VDDA
@VDDA
@VDDA
Supply monitoring
Cap. sensing
GPIO PORT B
GPIO PORT A
APB2: Fmax = 32 MHz
APB1: Fmax = 32 MHz
PLL &
Clock
Mgmt
VINP
a
VOUT
VINP
VINM
VOUT
RTC_OUT
AHB/APB2 AHB/APB1
JTCK / SWCLK
JTMS / SWDAT
JTDO
as AF
512 KB PROGRAM
16 KB DATA
8KB BOOT
DUAL BANK
@ VDD 33
VDD CORE
Vref
M3 CPU
GP DMA2 5 channels
GP DMA 7 channels
AHBPCLK
APBPCLK
HCLK
FCLK
@ VDD33
VDD33=1.65V to 3.6V
Vss
OSC_IN
OSC_OUT
TAMPER
4 channels
4 channels
4 channels
4 channels
RX, TX, CTS, RTS,
SmartCard as AF
RX, TX, CTS, RTS,
SmartCard as AF
MOSI, MISO, SCK,NSS,WS, CK
MCK, SD as AF
MOSI, MISO, SCK,NSS,WS, CK
MCK, SD as AF
SCL, SDA
As AF
SCL, SDA, SMBus, PMBus
As AF
USB_DP
USB_DM
Px
SEGx
COMx
OPAMP1
OPAMP2
COMPx_INx
VDDA /
VSSA
PA[15:0]
115 AF
PH[2:0]
PB[15:0]
PC[15:0]
PD[15:0]
PE[15:0]
TIMER9
TIMER10
TIMER11
2 channels
1 channel
1 channel
MOSI, MISO,
SCK, NSS as AF
RX, TX, CTS, RTS,
SmartCard as AF
40 AF
VDDREF_ADC*
VSSREF_ADC*
pbus
ibus
Dbus
BOR
Int
AHB: Fmax = 32 MHz
Bus Matrix 5M / 5S
VLCD = 2.5V to 3.6V
VLCD
@VDD33
Temp sensor
OSC32_IN
OSC32_OUT
NVIC
EEPROM
Interface
GPIO PORT F
GPIO PORT G
PF[15:0]
PG[15:0]
USART4
RX, TX as AF
USART5
RX, TX as AF
3 Functional overview
Figure 1. Ultra-low-power STM32L151xE and STM32L152xE block diagram
56
DS10002 Rev 10 13/136
Functional overview STM32L151xE STM32L152xE
3.1 Low-power modes
The ultra-low-power STM32L151xE and STM32L152xE devices support dynamic voltage
scaling to optimize its power consumption in run mode. The voltage from the internal lowdrop regulator that supplies the logic can be adjusted according to the system’s maximum
operating frequency and the external voltage supply.
There are three power consumption ranges:
• Range 1 (VDD range limited to 1.71 V - 3.6 V), with the CPU running at up to 32 MHz
• Range 2 (full V
• Range 3 (full V
only with the multispeed internal RC oscillator clock source)
Seven low-power modes are provided to achieve the best compromise between low-power
consumption, short startup time and available wakeup sources:
• Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs. Sleep mode power consumption at
16 MHz is about 1 mA with all peripherals off.
• Low-power run mode
This mode is achieved with the multispeed internal (MSI) RC oscillator set to the MSI
range 0 or MSI range 1 clock range (maximum 131 kHz), execution from SRAM or
Flash memory, and internal regulator in low-power mode to minimize the regulator's
operating current. In low-power run mode, the clock frequency and the number of
enabled peripherals are both limited.
• Low-power sleep mode
This mode is achieved by entering Sleep mode with the internal voltage regulator in
Low-power mode to minimize the regulator’s operating current. In Low-power sleep
mode, both the clock frequency and the number of enabled peripherals are limited; a
typical example would be to have a timer running at 32 kHz.
When wakeup is triggered by an event or an interrupt, the system reverts to the run
mode with the regulator on.
• Stop mode with RTC
Stop mode achieves the lowest power consumption while retaining the RAM and
register contents and real time clock. All clocks in the V
PLL, MSI RC, HSI RC and HSE crystal oscillators are disabled. The LSE or LSI is still
running. The voltage regulator is in the low-power mode.
The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI
line source can be one of the 16 external lines. It can be the PVD output, the
Comparator 1 event or Comparator 2 event (if internal reference voltage is on), it can
be the RTC alarm(s), the USB wakeup, the RTC tamper events, the RTC timestamp
event or the RTC wakeup.
range), with a maximum CPU frequency of 16 MHz
DD
range), with a maximum CPU frequency limited to 4 MHz (generated
DD
domain are stopped, the
CORE
14/136 DS10002 Rev 10
STM32L151xE STM32L152xE Functional overview
• Stop mode without RTC
Stop mode achieves the lowest power consumption while retaining the RAM and
register contents. All clocks are stopped, the PLL, MSI RC, HSI and LSI RC, LSE and
HSE crystal oscillators are disabled. The voltage regulator is in the low-power mode.
The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI
line source can be one of the 16 external lines. It can be the PVD output, the
Comparator 1 event or Comparator 2 event (if internal reference voltage is on). It can
also be wakened by the USB wakeup.
• Standby mode with RTC
Standby mode is used to achieve the lowest power consumption and real time clock.
The internal voltage regulator is switched off so that the entire V
CORE
domain is
powered off. The PLL, MSI RC, HSI RC and HSE crystal oscillators are also switched
off. The LSE or LSI is still running. After entering Standby mode, the RAM and register
contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG,
RTC, LSI, LSE Crystal 32K osc, RCC_CSR).
The device exits Standby mode in 60 µs when an external reset (NRST pin), an IWDG
reset, a rising edge on one of the three WKUP pins, RTC alarm (Alarm A or Alarm B),
RTC tamper event, RTC timestamp event or RTC Wakeup event occurs.
• Standby mode without RTC
Standby mode is used to achieve the lowest power consumption. The internal voltage
regulator is switched off so that the entire V
domain is powered off. The PLL, MSI
CORE
RC, HSI and LSI RC, HSE and LSE crystal oscillators are also switched off. After
entering Standby mode, the RAM and register contents are lost except for registers in
the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32K osc,
RCC_CSR).
The device exits Standby mode in 60 µs when an external reset (NRST pin) or a rising
edge on one of the three WKUP pin occurs.
Note: The RTC, the IWDG, and the corresponding clock sources are not stopped automatically by
entering Stop or Standby mode.
Table 3. Functionalities depending on the operating power supply range
-
Operating power supply
range
= V
V
DD
V
DD=VDDA
V
DD=VDDA
= 1.65 to 1.71 V Not functional Not functional Range 2 or Range 3
DDA
= 1.71 to 1.8 V
= 1.8 to 2.0 V
(2)
(2)
Functionalities depending on the operating power supply
DAC and ADC
operation
Not functional Not functional
Conversion time up
to 500 Ksps
USB
Not functional
range
(1)
Dynamic voltage scaling
range
Range 1, Range 2 or
Range 3
Range 1, Range 2 or
Range 3
DS10002 Rev 10 15/136
56
Functional overview STM32L151xE STM32L152xE
Table 3. Functionalities depending on the operating power supply range (continued)
-
Operating power supply
range
VDD=V
V
DD=VDDA
1. The GPIO speed also depends from VDD voltage and the user has to refer to Table 44: I/O AC
characteristics for more information about I/O speed.
2. CPU frequency changes from initial to final must respect “F
due to current consumption peak when frequency increases. It must also respect 5 µs delay between two
changes. For example to switch from 4.2 MHz to 32 MHz, the user can switch from 4.2 MHz to 16 MHz,
wait 5 µs, then switch from 16 MHz to 32 MHz.
3. Must be USB compliant from I/O voltage standpoint, the minimum V
= 2.0 to 2.4 V
DDA
= 2.4 to 3.6 V
Table 4. CPU frequency range depending on dynamic voltage scaling
Functionalities depending on the operating power supply
DAC and ADC
operation
Conversion time up
to 500 Ksps
Conversion time up
to 1 Msps
USB
Functional
Functional
initial < 4*F
CPU
range
(3)
(3)
is 3.0 V.
DD
(1)
Dynamic voltage scaling
range
Range 1, Range 2 or
Range 3
Range 1, Range 2 or
Range 3
final” to limit V
CPU
CORE
CPU frequency range Dynamic voltage scaling range
drop
16 MHz to 32 MHz (1ws)
32 kHz to 16 MHz (0ws)
8 MHz to 16 MHz (1ws)
32 kHz to 8 MHz (0ws)
2.1MHz to 4.2 MHz (1ws)
32 kHz to 2.1 MHz (0ws)
Range 1
Range 2
Range 3
16/136 DS10002 Rev 10
STM32L151xE STM32L152xE Functional overview
Table 5. Functionalities depending on the working mode (from Run/active down to
standby)
Stop Standby
Wakeup
-
capability
-
Wakeup
capability
Ips Run/Active Sleep
Low-
power
Run
Low-
power
Sleep
CPU Y -- Y -- -- -- -- --
Flash Y Y Y Y -- -- -- --
RAM Y Y Y Y Y -- -- --
Backup Registers Y Y Y Y Y -- Y --
EEPROM Y Y Y Y Y -- -- --
Brown-out rest
(BOR)
YYYYYYY--
DMA Y Y Y Y -- -- -- --
Programmable
Voltage Detector
YYYYYYY--
(PVD)
Power On Reset
(POR)
Power Down Rest
(PDR)
High Speed
Internal (HSI)
High Speed
External (HSE)
YYYYYYY--
YYYYY--Y--
Y Y -- -- -- -- -- --
Y Y -- -- -- -- -- --
Low Speed Internal
(LSI)
Low Speed
External (LSE)
Multi-Speed
Internal (MSI)
Inter-Connect
Controller
YYYYY--Y--
YYYYY--Y--
Y Y Y Y -- -- -- --
Y Y Y Y -- -- -- --
RTC Y Y Y Y Y Y Y --
RTC Tamper Y Y Y Y Y Y Y Y
Auto WakeUp
(AWU)
YYYYYYYY
LCD Y Y Y Y Y -- -- --
USB Y Y -- -- -- Y -- --
USART Y Y Y Y Y
(1)
-- --
SPI Y Y Y Y -- -- -- --
I2C Y Y -- -- --
(1)
-- --
DS10002 Rev 10 17/136
56
Functional overview STM32L151xE STM32L152xE
Table 5. Functionalities depending on the working mode (from Run/active down to
standby) (continued)
Low-
Ips Run/Active Sleep
ADC Y Y -- -- -- -- -- --
DAC Y Y Y Y Y -- -- --
Tempsensor Y Y Y Y Y -- -- --
OP amp Y Y Y Y Y -- -- --
Comparators Y Y Y Y Y Y -- --
16-bit and 32-bit
Timers
IWDG Y Y Y Y Y Y Y Y
WWDG Y Y Y Y -- -- -- --
Touch sensing Y Y -- -- -- -- -- --
Systic Timer Y Y Y Y - -- -- --
GPIOs Y Y Y Y Y Y -- 3 pins
Wakeup time to
Run mode
Consumption
=1.8 to 3.6 V
V
DD
(Typ)
1. The startup on communication line wakes the CPU which was made possible by an EXTI, this induces a delay before
entering run mode.
Y Y Y Y -- -- -- --
0 µs 0.4 µs 3 µs 46 µs < 8 µs 58 µs
Down to 195
µA/MHz (from
Flash)
Down to 38
µA/MHz (from
Flash)
power
Run
Down to
11 µ A
Low-
power
Sleep
Down to
4.6 µA
Stop Standby
Wakeup
-
capability
0.53 µA
(no RTC)
=1.8V
V
DD
1.2 µA
(with RTC)
V
=1.8V
DD
0.56 µA
(no RTC)
V
=3.0V
DD
1.4 µA
(with RTC)
V
=3.0V
DD
-
Wakeup
capability
0.285 µA
(no RTC)
VDD=1.8V
0.97 µA
(with RTC)
VDD=1.8V
0.29 µA
(no RTC)
VDD=3.0V
1.11 µA
(with RTC)
VDD=3.0V
3.2 Arm® Cortex®-M3 core with MPU
The Arm® Cortex®-M3 processor is the industry leading processor for embedded systems. It
has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The Arm® Cortex®-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an Arm core in the memory size usually
associated with 8- and 16-bit devices.
18/136 DS10002 Rev 10
STM32L151xE STM32L152xE Functional overview
The memory protection unit (MPU) improves system reliability by defining the memory
attributes (such as read/write access permissions) for different memory regions. It provides
up to eight different regions and an optional predefined background region.
Owing to its embedded Arm core, the STM32L151xE and STM32L152xE devices are
compatible with all Arm tools and software.
Nested vectored interrupt controller (NVIC)
The ultra-low-power STM32L151xE and STM32L152xE devices embed a nested vectored
interrupt controller able to handle up to 56 maskable interrupt channels (not including the 16
interrupt lines of Arm
• Closely coupled NVIC gives low-latency interrupt processing
• Interrupt entry vector table address passed directly to the core
• Closely coupled NVIC core interface
• Allows early processing of interrupts
• Processing of late arriving, higher-priority interrupts
• Support for tail-chaining
• Processor state automatically saved on interrupt entry, and restored on interrupt exit,
with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
®
Cortex®-M3) and 16 priority levels.
3.3 Reset and supply management
3.3.1 Power supply schemes
• VDD = 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided
externally through V
• V
SSA
, V
= 1.65 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs
DDA
and PLL (minimum voltage to be applied to V
and V
must be connected to V
SSA
3.3.2 Power supply supervisor
The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR) that can be coupled with a brownout reset (BOR) circuitry.
The device exists in two versions:
• The version with BOR activated at power-on operates between 1.8 V and 3.6 V.
• The other version without BOR operates between 1.65 V and 3.6 V.
After the VDD threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or
not at power-on), the option byte loading process starts, either to confirm or modify default
thresholds, or to disable the BOR permanently: in this case, the V
1.65 V (whatever the version, BOR active or not, at power-on).
When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever
the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the
power ramp-up must guarantee that 1.65
POR area.
DD
pins.
and VSS, respectively.
DD
V is reached on VDD at least 1 ms after it exits the
is 1.8 V when the ADC is used). V
DDA
min value becomes
DD
DDA
DS10002 Rev 10 19/136
56
Functional overview STM32L151xE STM32L152xE
Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To
reduce the power consumption in Stop mode, it is possible to automatically switch off the
internal reference voltage (V
V
is below a specified threshold, V
DD
) in Stop mode. The device remains in reset mode when
REFINT
POR/PDR
or V
, without the need for any external
BOR
reset circuit.
Note: The start-up time at power-on is typically 3.3 ms when BOR is active at power-up, the start-
up time at power-on can be decreased down to 1
ms typically for devices with BOR inactive
at power-up.
The device features an embedded programmable voltage detector (PVD) that monitors the
V
DD/VDDA
levels between 1.85
interrupt can be generated when V
V
DD/VDDA
power supply and compares it to the V
V and 3.05 V, chosen by software, with a step around 200 mV. An
drops below the V
is higher than the V
DD/VDDA
threshold. The interrupt service routine can then generate
PVD
threshold. This PVD offers 7 different
PVD
threshold and/or when
PVD
a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
3.3.3 Voltage regulator
The regulator has three operation modes: main (MR), low-power (LPR) and power down.
• MR is used in Run mode (nominal regulation)
• LPR is used in the Low-power run, Low-power sleep and Stop modes
• Power down is used in Standby mode. The regulator output is high impedance, the
kernel circuitry is powered down, inducing zero consumption but the contents of the
registers and RAM are lost except for the standby circuitry (wakeup logic, IWDG, RTC,
LSI, LSE crystal 32K osc, RCC_CSR).
3.3.4 Boot modes
At startup, boot pins are used to select one of three boot options:
• Boot from Flash memory
• Boot from System memory
• Boot from embedded RAM
The boot from Flash usually boots at the beginning of the Flash (bank 1). An additional boot
mechanism is available through user option byte, to allow booting from bank 2 when bank 2
contains valid code. This dual boot capability can be used to easily implement a secure field
software update mechanism.
The boot loader is located in System memory. It is used to reprogram the Flash memory by
using USART1, USART2 or USB. See Application note “STM32 microcontroller system
memory boot mode” (AN2606) for details.
20/136 DS10002 Rev 10
STM32L151xE STM32L152xE Functional overview
3.4 Clock management
The clock controller distributes the clocks coming from different oscillators to the core and
the peripherals. It also manages clock gating for low-power modes and ensures clock
robustness. It features:
• Clock prescaler: to get the best trade-off between speed and current consumption, the
clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler.
• Safe clock switching: clock sources can be changed safely on the fly in run mode
through a configuration register.
• Clock management: to reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
• System clock source: three different clock sources can be used to drive the master
clock SYSCLK:
– 1-24 MHz high-speed external crystal (HSE), that can supply a PLL
– 16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can
supply a PLL
– Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 7
frequencies (65 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1 MHz, 4.2 MHz).
When a 32.768 kHz clock source is available in the system (LSE), the MSI
frequency can be trimmed by software down to a ±0.5% accuracy.
• Auxiliary clock source: two ultra-low-power clock sources that can be used to drive
the LCD controller and the real-time clock:
– 32.768 kHz low-speed external crystal (LSE)
– 37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.
The LSI clock can be measured using the high-speed internal RC oscillator for
greater precision.
• RTC and LCD clock sources: the LSI, LSE or HSE sources can be chosen to clock
the RTC and the LCD, whatever the system clock.
• USB clock source: the embedded PLL has a dedicated 48 MHz clock output to supply
the USB interface.
• Startup clock: after reset, the microcontroller restarts by default with an internal 2 MHz
clock (MSI). The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.
• Clock security system (CSS): this feature can be enabled by software. If a HSE clock
failure occurs, the master clock is automatically switched to HSI and a software
interrupt is generated if enabled.
• Clock-out capability (MCO: microcontroller clock output): it outputs one of the
internal clocks for external use by the application.
Several prescalers allow the configuration of the AHB frequency, each APB (APB1 and
APB2) domains. The maximum frequency of the AHB and the APB domains is 32 MHz. See
Figure 2 for details on the clock tree.
DS10002 Rev 10 21/136
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Functional overview STM32L151xE STM32L152xE
MS18583V1
LSI RC
LSE OSC
HSI RC
HSE
OSC
@V33
@V
DDCORE
@V33
level shifters
level shifters
PLL
X 3,4,6,8,12
@V33
level shifters
LSE tempo
1 MHz clock
detector
@V33
LS
Watchdog
ck_pllin
source
control
Clock
Wat ch dog
enable
RTC enable
ck_hsi
ck_hse
HSE present or not
LSI tempo
ck_pll
AHB
prescaler
/ 1,2,..512
APB2
/ 1,2,4,8,16
APB1
/ 1,2,4,8,16
ck_usb = Vco / 2 (Vco must be at 96 MHz)
/ 8
CK_TIMSYS
CK_CPU
CK_FCLK
CK_PWR
CK_USB48
CK_TIMTGO
CK_APB1
CK_APB2
usben and (not deepsleep)
timer9en and (not deepsleep)
apb1 periphen and (not deepsleep)
apb2 periphen and (not deepsleep)
not (sleep or
deepsleep)
not (sleep or
deepsleep
not deepsleep
not deepsleep
Standby supplied voltage domain
System
clock
MCO
if (APB1 presc = 1)
x1
else
x2
16,24,32,48
ck_lse
CK_LCD
/ 2, 3, 4
1 MHz
@V
DDCORE
@V
DDCORE
@V
DDCORE
/ 1,2,4,8,16
LCD enable
MSI RC
@V33
@V
DDCORE
level shifters
ck_msi
ck_lsi
CK_ADC
ADC enable
LS LS LS LS
LS
LS
/ 2,4,8,16
prescaler prescaler
Radio Sleep Timer
RTC
Radio Sleep Timer enable
Figure 2. Clock tree
22/136 DS10002 Rev 10
STM32L151xE STM32L152xE Functional overview
3.5 Low-power real-time clock and backup registers
The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain
the sub-second, second, minute, hour (12/24 hour), week day, date, month, year, in BCD
(binary-coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the
month are made automatically. The RTC provides two programmable alarms and
programmable periodic interrupts with wakeup from Stop and Standby modes.
The programmable wakeup time ranges from 120 µs to 36 hours.
The RTC can be calibrated with an external 512 Hz output, and a digital compensation
circuit helps reduce drift due to crystal deviation.
The RTC can also be automatically corrected with a 50/60Hz stable powerline.
The RTC calendar can be updated on the fly down to sub second precision, which enables
network system synchronization.
A time stamp can record an external event occurrence, and generates an interrupt.
There are thirty-two 32-bit backup registers provided to store 128 bytes of user application
data. They are cleared in case of tamper detection.
Three pins can be used to detect tamper events. A change on one of these pins can reset
backup register and generate an interrupt. To prevent false tamper event, like ESD event,
these three tamper inputs can be digitally filtered.
3.6 GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions, and can be individually
remapped using dedicated AFIO registers. All GPIOs are high current capable. The
alternate function configuration of I/Os can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/O registers. The I/O controller is
connected to the AHB with a toggling speed of up to 16 MHz.
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 24 edge detector lines used to generate
interrupt/event requests. Each line can be individually configured to select the trigger event
(rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 115 GPIOs can be connected
to the 16 external interrupt lines. The 8 other lines are connected to RTC, PVD, USB,
comparator events or capacitive sensing acquisition.
DS10002 Rev 10 23/136
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Functional overview STM32L151xE STM32L152xE
3.7 Memories
The STM32L151xE and STM32L152xE devices have the following features:
• 80 Kbytes of embedded RAM accessed (read/write) at CPU clock speed with 0 wait
states. With the enhanced bus matrix, operating the RAM does not lead to any
performance penalty during accesses to the system bus (AHB and APB buses).
• The non-volatile memory is divided into three arrays:
– 512 Kbytes of embedded Flash program memory
– 16 Kbytes of data EEPROM
– Options bytes
Flash program and data EEPROM are divided into two banks, this enables writing in
one bank while running code or reading data in the other bank.
The options bytes are used to write-protect or read-out protect the memory (with 4
Kbytes granularity) and/or readout-protect the whole memory with the following
options:
– Level 0: no readout protection
– Level 1: memory readout protection, the Flash memory cannot be read from or
written to if either debug features are connected or boot in RAM is selected
– Level 2: chip readout protection, debug features (Arm Cortex-M3 JTAG and serial
wire) and boot in RAM selection disabled (JTAG fuse)
The whole non-volatile memory embeds the error correction code (ECC) feature.
3.8 DMA (direct memory access)
The flexible 12-channel, general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management, avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with software trigger
support for each channel. Configuration is done by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose timers,
DAC and ADC.
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STM32L151xE STM32L152xE Functional overview
3.9 LCD (liquid crystal display)
The LCD drives up to 8 common terminals and 44 segment terminals to drive up to 320
pixels.
• Internal step-up converter to guarantee functionality and contrast control irrespective of
V
. This converter can be deactivated, in which case the V
DD
the voltage to the LCD
• Supports static, 1/2, 1/3, 1/4 and 1/8 duty
• Supports static, 1/2, 1/3 and 1/4 bias
• Phase inversion to reduce power consumption and EMI
• Up to 8 pixels can be programmed to blink
• Unneeded segments and common pins can be used as general I/O pins
• LCD RAM can be updated at any time owing to a double-buffer
• The LCD controller can operate in Stop mode
pin is used to provide
LCD
3.10 ADC (analog-to-digital converter)
A 12-bit analog-to-digital converters is embedded into STM32L151xE and STM32L152xE
devices with up to 40 external channels, performing conversions in single-shot or scan
mode. In scan mode, automatic conversion is performed on a selected group of analog
inputs with up to 28 external channels in a group.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all scanned channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers (TIMx) can be internally connected to
the ADC start triggers, to allow the application to synchronize A/D conversions and timers.
An injection mode allows high priority conversions to be done by interrupting a scan mode
which runs in as a background task.
The ADC includes a specific low-power mode. The converter is able to operate at maximum
speed even if the CPU is operating at a very low frequency and has an auto-shutdown
function. The ADC’s runtime and analog front-end current consumption are thus minimized
whatever the MCU operating mode.
3.10.1 Temperature sensor
The temperature sensor (TS) generates a voltage V
temperature.
The temperature sensor is internally connected to the ADC_IN16 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
that varies linearly with
SENSE
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
DS10002 Rev 10 25/136
56
Functional overview STM32L151xE STM32L152xE
stored by ST in the system memory area, accessible in read-only mode. See Tab le 60:
Temperature sensor calibration values.
3.10.2 Internal voltage reference (V
The internal voltage reference (V
ADC and Comparators. V
enables accurate monitoring of the V
available for ADC). The precise voltage of V
ST during production test and stored in the system memory area. It is accessible in readonly mode. See
Tabl e 15: Embedded internal reference voltage calibration values.
REFINT
REFINT
is internally connected to the ADC_IN17 input channel. It
REFINT
DD
)
) provides a stable (bandgap) voltage output for the
value (when no external voltage, VREF+, is
REFINT
3.11 DAC (digital-to-analog converter)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs. The chosen design structure is composed of integrated
resistor strings and an amplifier in non-inverting configuration.
This dual digital Interface supports the following features:
• Two DAC converters: one for each output channel
• 8-bit or 12-bit monotonic output
• Left or right data alignment in 12-bit mode
• Synchronized update capability
• Noise-wave generation
• Triangular-wave generation
• Dual DAC channels, independent or simultaneous conversions
• DMA capability for each channel (including the underrun interrupt)
• External triggers for conversion
• Input reference voltage V
Eight DAC trigger inputs are used in the STM32L151xE and STM32L152xE devices. The
DAC channels are triggered through the timer update outputs that are also connected to
different DMA channels.
REF+
is individually measured for each part by
3.12 Operational amplifier
The STM32L151xE and STM32L152xE devices embed two operational amplifiers with
external or internal follower routing capability (or even amplifier and filter capability with
external components). When one operational amplifier is selected, one external ADC
channel is used to enable output measurement.
The operational amplifiers feature:
• Low input bias current
• Low offset voltage
• Low-power mode
• Rail-to-rail input
26/136 DS10002 Rev 10
STM32L151xE STM32L152xE Functional overview
3.13 Ultra-low-power comparators and reference voltage
The STM32L151xE and STM32L152xE devices embed two comparators sharing the same
current bias and reference voltage. The reference voltage can be internal or external
(coming from an I/O).
• One comparator with fixed threshold
• One comparator with rail-to-rail inputs, fast or slow mode. The threshold can be one of
the following:
– DAC output
– External I/O
– Internal reference voltage (V
Both comparators can wake up from Stop mode, and be combined into a window
comparator.
The internal reference voltage is available externally via a low-power / low-current output
buffer (driving current capability of 1
µA typical).
) or a sub-multiple (1/4, 1/2, 3/4)
REFINT
3.14 System configuration controller and routing interface
The system configuration controller provides the capability to remap some alternate
functions on different I/O ports.
The highly flexible routing interface allows the application firmware to control the routing of
different I/Os to the TIM2, TIM3 and TIM4 timer input captures. It also controls the routing of
internal analog signals to ADC1, COMP1 and COMP2 and the internal reference voltage
V
REFINT
.
3.15 Touch sensing
The STM32L151xE and STM32L152xE devices provide a simple solution for adding
capacitive sensing functionality to any application. Thesedevices offer up to 34 capacitive
sensing channels distributed over 11 analog I/O groups. Both software and timer capacitive
sensing acquisition modes are supported.
Capacitive sensing technology is able to detect the presence of a finger near a sensor which
is protected from direct touch by a dielectric (glass, plastic...). The capacitive variation
introduced by the finger (or any conductive object) is measured using a proven
implementation based on a surface charge transfer acquisition principle. It consists of
charging the sensor capacitance and then transferring a part of the accumulated charges
into a sampling capacitor until the voltage across this capacitor has reached a specific
threshold. The capacitive sensing acquisition only requires few external components to
operate. This acquisition is managed directly by the GPIOs, timers and analog I/O groups
(see
Section 3.14: System configuration controller and routing interface).
Reliable touch sensing functionality can be quickly and easily implemented using the free
STM32L1xx STMTouch touch sensing firmware library.
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Functional overview STM32L151xE STM32L152xE
3.16 Timers and watchdogs
The ultra-low-power STM32L151xE and STM32L152xE devices include seven generalpurpose timers, two basic timers, and two watchdog timers.
Tabl e 6 compares the features of the general-purpose and basic timers.
Table 6. Timer feature comparison
Timer
TIM2,
TIM3,
TIM4
TIM5 32-bit
TIM9 16-bit
TIM10,
TIM11
TIM6,
TIM7
Counter
resolution
16-bit
16-bit Up
16-bit Up
Counter type Prescaler factor
Up, down,
up/down
Up, down,
up/down
Up, down,
up/down
Any integer between
1 and 65536
Any integer between
1 and 65536
Any integer between
1 and 65536
Any integer between
1 and 65536
Any integer between
1 and 65536
DMA
request
generation
Yes 4 No
Yes 4 No
No 2 No
No 1 No
Yes 0 No
Capture/compare
channels
Complementary
outputs
3.16.1 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM9, TIM10 and TIM11)
There are seven synchronizable general-purpose timers embedded in the STM32L151xE
and STM32L152xE devices (see
TIM2, TIM3, TIM4, TIM5
Tabl e 6 for differences).
TIM2, TIM3, TIM4 are based on 16-bit auto-reload up/down counter. TIM5 is based on a 32bit auto-reload up/down counter. They include a 16-bit prescaler. They feature four
independent channels each for input capture/output compare, PWM or one-pulse mode
output. This gives up to 16 input captures/output compares/PWMs on the largest packages.
TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together or with the TIM10,
TIM11 and TIM9 general-purpose timers via the Timer Link feature for synchronization or
event chaining. Their counter can be frozen in debug mode. Any of the general-purpose
timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
TIM10, TIM11 and TIM9
TIM10 and TIM11 are based on a 16-bit auto-reload upcounter. TIM9 is based on a 16-bit
auto-reload up/down counter. They include a 16-bit prescaler. TIM10 and TIM11 feature one
independent channel, whereas TIM9 has two independent channels for input capture/output
compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3,
TIM4, TIM5 full-featured general-purpose timers.
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STM32L151xE STM32L152xE Functional overview
They can also be used as simple time bases and be clocked by the LSE clock source
(32.768 kHz) to provide time bases independent from the main CPU clock.
3.16.2 Basic timers (TIM6 and TIM7)
These timers are mainly used for DAC trigger generation. They can also be used as generic
16-bit time bases.
3.16.3 SysTick timer
This timer is dedicated to the OS, but could also be used as a standard downcounter. It is
based on a 24-bit downcounter with autoreload capability and a programmable clock
source. It features a maskable system interrupt generation when the counter reaches 0.
3.16.4 Independent watchdog (IWDG)
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 37 kHz internal RC and, as it operates independently of the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes. The counter
can be frozen in debug mode.
3.16.5 Window watchdog (WWDG)
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.17 Communication interfaces
3.17.1 I²C bus
Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support
standard and fast modes.
They support dual slave addressing (7-bit only) and both 7- and 10-bit addressing in master
mode. A hardware CRC generation/verification is embedded.
They can be served by DMA and they support SM Bus 2.0/PM Bus.
3.17.2 Universal synchronous/asynchronous receiver transmitter (USART)
The three USART and two UART interfaces are able to communicate at speeds of up to 4
Mbit/s. They support IrDA SIR ENDEC and have LIN Master/Slave capability. The three
USARTs provide hardware management of the CTS and RTS signals and are ISO 7816
compliant.
All USART/UART interfaces can be served by the DMA controller.
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Functional overview STM32L151xE STM32L152xE
3.17.3 Serial peripheral interface (SPI)
Up to three SPIs are able to communicate at up to 16 Mbits/s in slave and master modes in
full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes.
The SPIs can be served by the DMA controller.
3.17.4 Inter-integrated sound (I2S)
Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can
operate in master or slave mode, and can be configured to operate with a 16-/32-bit
resolution as input or output channels. Audio sampling frequencies from 8 kHz up to 192
kHz are supported. When either or both of the I2S interfaces is/are configured in master
mode, the master clock can be output to the external DAC/CODEC at 256 times the
sampling frequency.
The I2Ss can be served by the DMA controller.
3.17.5 Universal serial bus (USB)
The STM32L151xE and STM32L152xE devices embed a USB device peripheral compatible
with the USB full-speed 12
function interface. It has software-configurable endpoint setting and supports
suspend/resume. The dedicated 48
clock source must use a HSE crystal oscillator).
Mbit/s. The USB interface implements a full-speed (12 Mbit/s)
MHz clock is generated from the internal main PLL (the
3.18 CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
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