ST MICROELECTRONICS STM32L053C8T6 Datasheet

STM32L053C6 STM32L053C8

LQFP64 10x10 mm

LQFP48 7x7 mm

TFBGA64 5x5 mm

UFQFPN48

(7x7 mm)

STM32L053R6 STM32L053R8

Ultra-low-power 32-bit MCU Arm®-based Cortex®-M0+, up to 64KB

Flash, 8KB SRAM, 2KB EEPROM, LCD, USB, ADC, DAC

Datasheet - production data

Features

•

Ultra-low-power platform
– 1.65 V to 3.6 V power supply
–

-

40 to 125 °C temperature range
– 0.27 µA Standby mode (2 wakeup pins)
– 0.4 µA Stop mode (16 wakeup lines)
– 0.8 µA Stop mode + RTC + 8-Kbyte RAM

retention
– 88 µA/MHz in Run mode
– 3.5 µs wakeup time (from RAM)
– 5 µs wakeup time (from Flash memory)

•

Core: Arm® 32-bit Cortex®-M0+ with MPU
– From 32 kHz up to 32 MHz max.
– 0.95 DMIPS/MHz

•

Memories
–

Up to

64-Kbyte Flash memory with ECC
– 8-Kbyte RAM
– 2 Kbytes of data EEPROM with ECC
– 20-byte backup register
– Sector protection against R/W operation

•

Up to 51 fast I/Os (45 I/Os 5V tolerant)

•

Reset and supply management
– Ultra-safe, low-power BOR (brownout reset)

with 5 selectable thresholds
– Ultra-low-power POR/PDR
– Programmable voltage detector (PVD)

•

Clock sources
– 1 to 25 MHz crystal oscillator

– 32 kHz oscillator for RTC with calibration
– High speed internal 16 MHz factory-trimmed RC

(+/- 1%)
– Internal low-power 37 kHz RC
– Internal multispeed low-power 65 kHz to

4.2 MHz RC

– PLL for CPU clock

•

Pre-programmed bootloader
– USART, SPI supported

•

Development support
– Serial wire debug supported

•

LCD driver for up to 8×28segments
– Support contrast adjustment
– Support blinking mode

– Step-up converted on board

•

Rich Analog peripherals
– 12-bit ADC 1.14 Msps up to 16 channels (down

to 1.65 V)

– 12-bit 1 channel DAC with output buffers (down

to 1.8 V)

– 2x ultra-low-power comparators (window mode

and wake up capability, down to 1.65 V)

•

Up to 24 capacitive sensing channels supporting
touchkey, linear and rotary touch sensors

•

7-channel DMA controller, supporting ADC, SPI,
I2C, USART, DAC, Timers

•

8x peripheral communication interfaces
– 1x USB 2.0 crystal-less, battery charging

detection and LPM

– 2x USART (ISO 7816, IrDA), 1x UART (low

power)
– Up to 4x SPI 16 Mbits/s
– 2x I2C (SMBus/PMBus)

•

9x timers: 1x 16-bit with up to 4 channels, 2x 16-bit
with up to 2 channels, 1x 16-bit ultra-low-power
timer, 1x SysTick, 1x RTC, 1x 16-bit basic for DAC,
and 2x watchdogs (independent/window)

•

CRC calculation unit, 96-bit unique ID

•

True RNG and firewall protection

•

All packages are ECOPACK2

FBGA

June 2019 DS10152 Rev 9 1/136

This is information on a product in full production.

www.st.com

Contents STM32L053x6 STM32L053x8

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

2.2 Ultra-low-power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.1 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.3 Arm® Cortex®-M0+ core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.4 Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.4.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.4.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.4.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.5 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.6 Low-power real-time clock and backup registers . . . . . . . . . . . . . . . . . . . 25

3.7 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.8 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.9 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.10 Direct memory access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.11 Liquid crystal display (LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.12 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.13 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.13.1 Internal voltage reference (V

3.13.2 V

voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

LCD

) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

REFINT

3.14 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.15 Ultra-low-power comparators and reference voltage . . . . . . . . . . . . . . . . 29

3.16 System configuration controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.17 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.18 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.18.1 General-purpose timers (TIM2, TIM21 and TIM22) . . . . . . . . . . . . . . . . 31

3.18.2 Low-power Timer (LPTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

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3.18.3 Basic timer (TIM6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.18.4 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.18.5 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.18.6 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.19 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.19.1 I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.19.2 Universal synchronous/asynchronous receiver transmitter (USART) . . 34

3.19.3 Low-power universal asynchronous receiver transmitter (LPUART) . . . 34

3.19.4 Serial peripheral interface (SPI)/Inter-integrated sound (I2S) . . . . . . . . 35

3.19.5 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.20 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.21 Cyclic redundancy check (CRC) calculation unit . . . . . . . . . . . . . . . . . . . 36

3.22 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

6.1.7 Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

6.1.8 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6.3.2 Embedded reset and power control block characteristics . . . . . . . . . . . 58

6.3.3 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 59

6.3.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

6.3.5 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

6.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

DS10152 Rev 9 3/136

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Contents STM32L053x6 STM32L053x8

6.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

6.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

6.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

6.3.11 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

6.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

6.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

6.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

6.3.15 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

6.3.16 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

6.3.17 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

6.3.18 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

6.3.19 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

6.3.20 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

6.3.21 LCD controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

7.1 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

7.2 TFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118

7.3 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

7.4 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

7.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

7.5.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

4/136 DS10152 Rev 9

STM32L053x6 STM32L053x8 List of tables

List of tables

Table 1. Ultra-low-power STM32L053x6/x8 device features and peripheral counts. . . . . . . . . . . . . 11

Table 2. Functionalities depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . 16

Table 3. CPU frequency range depending on dynamic voltage scaling . . . . . . . . . . . . . . . . . . . . . . 16

Table 4. Functionalities depending on the working mode

(from Run/active down to standby) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 5. STM32L0xx peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 6. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 7. Internal voltage reference measured values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 8. Capacitive sensing GPIOs available on STM32L053x6/8 devices . . . . . . . . . . . . . . . . . . . 30

Table 9. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 10. Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 11. STM32L053x6/8 I

Table 12. USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 13. SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 14. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 15. STM32L053x6/8 pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 16. Alternate function port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 17. Alternate function port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 18. Alternate function port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 19. Alternate function port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 20. Alternate function port H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 21. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 22. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 23. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 24. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 25. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 26. Embedded internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 27. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 28. Current consumption in Run mode, code with data processing running from Flash. . . . . . 61

Table 29. Current consumption in Run mode vs code type,

code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 30. Current consumption in Run mode, code with data processing running from RAM . . . . . . 63

Table 31. Current consumption in Run mode vs code type,

code with data processing running from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 32. Current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 33. Current consumption in Low-power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 34. Current consumption in Low-power sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 35. Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 36. Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 68

Table 37. Average current consumption during Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 38. Peripheral current consumption in Run or Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 39. Peripheral current consumption in Stop and Standby mode . . . . . . . . . . . . . . . . . . . . . . . 71

Table 40. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 41. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 42. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 43. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 44. LSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 45. 16 MHz HSI16 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

2

C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

DS10152 Rev 9 5/136

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List of tables STM32L053x6 STM32L053x8

Table 46. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 47. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 48. MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 49. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 50. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 51. Flash memory and data EEPROM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 52. Flash memory and data EEPROM endurance and retention . . . . . . . . . . . . . . . . . . . . . . . 81

Table 53. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 54. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 55. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 56. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 57. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 58. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 59. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 60. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 61. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 62. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 63. R

max for f

AIN

= 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

ADC

Table 64. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 65. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 66. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 67. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 68. Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 69. Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Table 70. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 71. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 72. SPI characteristics in voltage Range 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 73. SPI characteristics in voltage Range 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 74. SPI characteristics in voltage Range 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Table 75. I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 76. USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table 77. USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table 78. USB: full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Table 79. LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Table 80. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Table 81. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball grid

array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Table 82. TFBGA64 recommended PCB design rules (0.5 mm pitch BGA). . . . . . . . . . . . . . . . . . . 119

Table 83. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data. . . . . . . . . . . 122

Table 84. UFQFPN48 - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Table 85. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Table 86. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

6/136 DS10152 Rev 9

STM32L053x6 STM32L053x8 List of figures

List of figures

Figure 1. STM32L053x6/8 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 3. STM32L053x6/8 LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 4. STM32L053x6/8 TFBGA64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 5. STM32L053x6/8 LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 6. STM32L053x6/8 UFQFPN48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 7. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 8. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 9. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 10. Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 11. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 12. IDD vs VDD, at TA= 25/55/85/105 °C, Run mode, code running from

Flash memory, Range 2, HSE, 1WS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 13. IDD vs VDD, at TA= 25/55/85/105 °C, Run mode, code running from

Flash memory, Range 2, HSI16, 1WS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 14. IDD vs VDD, at TA= 25/55/ 85/105/125 °C, Low-power run mode, code running

from RAM, Range 3, MSI (Range 0) at 64 KHz, 0 WS . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 15. IDD vs VDD, at TA= 25/55/ 85/105/125 °C, Stop mode with RTC enabled

and running on LSE Low drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 16. IDD vs VDD, at TA= 25/55/85/105/125 °C, Stop mode with RTC disabled,

all clocks OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 17. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 18. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 19. HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 20. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 21. HSI16 minimum and maximum value versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 22. VIH/VIL versus VDD (CMOS I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 23. VIH/VIL versus VDD (TTL I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 24. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 25. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 26. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 27. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 28. Power supply and reference decoupling (V
Figure 29. Power supply and reference decoupling (V

Figure 30. 12-bit buffered/non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 31. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 32. SPI timing diagram - slave mode and CPHA = 1
Figure 33. SPI timing diagram - master mode
Figure 34. I
Figure 35. I

2

S slave timing diagram (Philips protocol)

2

S master timing diagram (Philips protocol)

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 36. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Figure 37. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 114

Figure 38. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint . . . . . . . . . . 116

Figure 39. LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 40. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball

grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 41. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball

,grid array recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

not connected to V

REF+

connected to V

REF+

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

DDA

) . . . . . . . . . . . . . 95

DDA

). . . . . . . . . . . . . . . . . 96

DS10152 Rev 9 7/136

8

List of figures STM32L053x6 STM32L053x8

Figure 42. TFBGA64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 43. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 121

Figure 44. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat recommended footprint . . . . . . . . . . . . 122

Figure 45. LQFP48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Figure 46. UFQFPN48 - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 47. UFQFPN48 - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat

package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Figure 48. UFQFPN48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Figure 49. Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

8/136 DS10152 Rev 9

STM32L053x6 STM32L053x8 Introduction

1 Introduction

The ultra-low-power STM32L053x6/8 are offered in 4 different package types: from 48 pins

to 64 pins. Depending on the device chosen, different sets of peripherals are included, the

description below gives an overview of the complete range of peripherals proposed in this

family.

These features make the ultra-low-power STM32L053x6/8 microcontrollers suitable for a

wide range of applications:

• Gas/water meters and industrial sensors

• Healthcare and fitness equipment

• Remote control and user interface

• PC peripherals, gaming, GPS equipment

• Alarm system, wired and wireless sensors, video intercom

This STM32L053x6/8 datasheet should be read in conjunction with the STM32L0x3xx

reference manual (RM0367).

For information on the Arm

Reference Manual, available from the www.arm.com website.

®(a)

Cortex®-M0+ core please refer to the Cortex®-M0+ Technical

Figure 1 shows the general block diagram of the device family.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

DS10152 Rev 9 9/136

36

Description STM32L053x6 STM32L053x8

2 Description

The ultra-low-power STM32L053x6/8 microcontrollers incorporate the connectivity power of

the universal serial bus (USB 2.0 crystal-less) with the high-performance Arm Cortex-M0+

32-bit RISC core operating at a 32 MHz frequency, a memory protection unit (MPU), high-

speed embedded memories (up to

EEPROM and

The STM32L053x6/8 devices provide high power efficiency for a wide range of

performance. It is achieved with a large choice of internal and external clock sources, an

internal voltage adaptation and several low-power modes.

The STM32L053x6/8 devices offer several analog features, one 12-bit ADC with hardware

oversampling, one DAC, two ultra-low-power comparators, several timers, one low-power

timer (LPTIM), three general-purpose 16-bit timers and one basic timer, one RTC and one

SysTick which can be used as timebases. They also feature two watchdogs, one watchdog

with independent clock and window capability and one window watchdog based on bus

clock.

Moreover, the STM32L053x6/8 devices embed standard and advanced communication

interfaces: up to two I2C, two SPIs, one I2S, two USARTs, a low-power UART (LPUART),

and a crystal-less USB. The devices offer up to 24 capacitive sensing channels to simply

add touch sensing functionality to any application.

8

Kbytes of RAM) plus an extensive range of enhanced I/Os and peripherals.

64

Kbytes of Flash program memory, 2 Kbytes of data

The STM32L053x6/8 also include a real-time clock and a set of backup registers that

remain powered in Standby mode.

Finally, their integrated LCD controller has a built-in LCD voltage generator that allows to

drive up to 8 multiplexed LCDs with contrast independent of the supply voltage.

The ultra-low-power STM32L053x6/8 devices operate from a 1.8 to 3.6 V power supply

(down to 1.65 V at power down) with BOR and from a 1.65 to 3.6 V power supply without

BOR option. They are available in the -40 to +125 °C temperature range. A comprehensive

set of power-saving modes allows the design of low-power applications.

10/136 DS10152 Rev 9

STM32L053x6 STM32L053x8 Description

2.1 Device overview

Table 1. Ultra-low-power STM32L053x6/x8 device features and peripheral counts

Peripheral STM32L053C6 STM32L053R6 STM32L053C8 STM32L053R8

Flash (Kbytes) 32 64

Data EEPROM (Kbytes) 22

RAM (Kbytes) 88

General-purpose 33

Timers

Basic 11

LPTIMER 11

RTC/SYSTICK/IWDG/WWDG 1/1/1/1 1/1/1/1

SPI/I2S 4(2)

(1)

/1 4(2)

(1)

/1

I2C 22

Communication
interfaces

USART 22

LPUART 11

USB/(VDD_USB) 1/(1) 1/(1)

GPIOs 37 51

(2)

37 51

Clocks: HSE/LSE/HSI/MSI/LSI 1/1/1/1/1 1/1/1/1/1

12-bit synchronized ADC
Number of channels

12-bit DAC
Number of channels

LCD
COM x SEG

1

10

1

4x18

1

16

1
1

1

4x32 or 8x28

(2)

(2)

1

10

1

4x18

1
1

4x32 or 8x28

16

(2)

1

(2)

1

(2)

Comparators 22

Capacitive sensing channels 17 24

(2)

17 24

(2)

Max. CPU frequency 32 MHz

Operating voltage

Operating temperatures

Packages

1. 2 SPI interfaces are USARTs operating in SPI master mode.

2. TFBGA64 has one GPIO, one LCD COM x SEG, one ADC input and one capacitive sensing channel less than LQFP64.

1.8 V to 3.6 V (down to 1.65 V at power-down) with BOR option

1.65 V to 3.6 V without BOR option

Ambient temperature: –40 to +125 °C
Junction temperature: –40 to +130 °C

LQFP48,

UFQFPN48

LQFP64,

TFBGA64

LQFP48,

UFQFPN48

LQFP64,

TFBGA64

DS10152 Rev 9 11/136

36

Description STM32L053x6 STM32L053x8

MSv33794V1

CORTEX M0+ CPU

Fmax:32MHz

SWD

MPU

NVIC

GPIO PORT A

GPIO PORT B

GPIO PORT C

GPIO PORT D

GPIO PORT H

Temp

sensor

RESET & CLK

FLASH

EEPROM

BOOT

RAM

DMA1

AHB: Fmax 32MHz

TSC

CRC

RNG

BRIDGE

A
P
B
2

FIREWALL

DBG

EXTI

ADC1

SPI1

USART1

TIM21

COMP1

LSE

TIM22

BRIDGE

A
P
B
1

CRS

TIM6

RAM 1K

DAC1

I2C1

I2C2

USART2

USB 2.0 FS

LPUART1

SPI2/I2S

TIM2

LCD1

IWDG

RTC

WWDG

LPTIM1

BCKP REG

HSE HSI 16M

PLL

MSI

LSI

HSI 48M

PMU

REGULATOR

VDD

VDDA

VREF_OUT

NRST

PVD_IN

OSC32_IN,

OSC32_OUT

OSC_IN,

OSC_OUT

WKUPx

PA[0:15]

PH[0:1]

PD[2]

PC[0:15]

PB[0:15]

AINx

MISO, MOSI,
SCK, NSS

RX, TX, RTS,
CTS, CK

2ch

2ch

INP, INM, OUT

IN1, IN2,
ETR, OUT

DP, DM, OE,
CRS_SYNC,
VDD_USB

OUT1

SCL, SDA,
SMBA

SCL, SDA,
SMBA

RX, TX, RTS,
CTS, CK

RX, TX, RTS,
CTS

MISO/MCK,
MOSI/SD,
SCK/CK, NSS/
WS

4ch

COMx, SEGx,
LCD_VLCD1

SWD

COMP2

INP, INM, OUT

Figure 1. STM32L053x6/8 block diagram

12/136 DS10152 Rev 9

STM32L053x6 STM32L053x8 Description

2.2 Ultra-low-power device continuum

The ultra-low-power family offers a large choice of core and features, from 8-bit proprietary

core up to Arm

®

Cortex®-M4, including Arm® Cortex®-M3 and Arm® Cortex®-M0+. The
STM32Lx series are the best choice to answer your needs in terms of ultra-low-power
features. The STM32 ultra-low-power series are the best solution for applications such as
gaz/water meter, keyboard/mouse or fitness and healthcare application. Several built-in
features like LCD drivers, dual-bank memory, low-power run mode, operational amplifiers,
128-bit AES, DAC, crystal-less USB and many other definitely help you building a highly
cost optimized application by reducing BOM cost. STMicroelectronics, as a reliable and
long-term manufacturer, ensures as much as possible pin-to-pin compatibility between all
STM8Lx and STM32Lx on one hand, and between all STM32Lx and STM32Fx on the other
hand. Thanks to this unprecedented scalability, your legacy application can be upgraded to
respond to the latest market feature and efficiency requirements.

DS10152 Rev 9 13/136

36

Functional overview STM32L053x6 STM32L053x8

3 Functional overview

3.1 Low-power modes

The ultra-low-power STM32L053x6/8 support dynamic voltage scaling to optimize its power
consumption in Run mode. The voltage from the internal low-drop regulator that supplies
the logic can be adjusted according to the system’s maximum operating frequency and the
external voltage supply.

There are three power consumption ranges:

• Range 1 (V

• Range 2 (full V

• Range 3 (full V

Seven low-power modes are provided to achieve the best compromise between low-power
consumption, short startup time and available wakeup sources:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs. Sleep mode power consumption at
16 MHz is about 1 mA with all peripherals off.

• Low-power run mode

This mode is achieved with the multispeed internal (MSI) RC oscillator set to the low­speed clock (max 131 kHz), execution from SRAM or Flash memory, and internal
regulator in low-power mode to minimize the regulator's operating current. In Low­power run mode, the clock frequency and the number of enabled peripherals are both
limited.

• Low-power sleep mode

This mode is achieved by entering Sleep mode with the internal voltage regulator in
low-power mode to minimize the regulator’s operating current. In Low-power sleep
mode, both the clock frequency and the number of enabled peripherals are limited; a
typical example would be to have a timer running at 32 kHz.

When wakeup is triggered by an event or an interrupt, the system reverts to the Run
mode with the regulator on.

Stop mode with RTC

The Stop mode achieves the lowest power consumption while retaining the RAM and
register contents and real time clock. All clocks in the V
PLL, MSI RC, HSE crystal and HSI RC oscillators are disabled. The LSE or LSI is still
running. The voltage regulator is in the low-power mode.

Some peripherals featuring wakeup capability can enable the HSI RC during Stop
mode to detect their wakeup condition.

The device can be woken up from Stop mode by any of the EXTI line, in 3.5 µs, the
processor can serve the interrupt or resume the code. The EXTI line source can be any
GPIO. It can be the PVD output, the comparator 1 event or comparator 2 event
(if internal reference voltage is on), it can be the RTC alarm/tamper/timestamp/wakeup
events, the USB/USART/I2C/LPUART/LPTIMER wakeup events.

range limited to 1.71-3.6 V), with the CPU running at up to 32 MHz

DD

range), with a maximum CPU frequency of 16 MHz

DD

range), with a maximum CPU frequency limited to 4.2 MHz

DD

domain are stopped, the

CORE

14/136 DS10152 Rev 9

STM32L053x6 STM32L053x8 Functional overview

• Stop mode without RTC

The Stop mode achieves the lowest power consumption while retaining the RAM and
register contents. All clocks are stopped, the PLL, MSI RC, HSI and LSI RC, HSE and
LSE crystal oscillators are disabled.

Some peripherals featuring wakeup capability can enable the HSI RC during Stop
mode to detect their wakeup condition.

The voltage regulator is in the low-power mode. The device can be woken up from Stop
mode by any of the EXTI line, in 3.5 µs, the processor can serve the interrupt or
resume the code. The EXTI line source can be any GPIO. It can be the PVD output, the
comparator 1 event or comparator 2 event (if internal reference voltage is on). It can
also be wakened by the USB/USART/I2C/LPUART/LPTIMER wakeup events.

• Standby mode with RTC

The Standby mode is used to achieve the lowest power consumption and real time
clock. The internal voltage regulator is switched off so that the entire V

CORE

domain is
powered off. The PLL, MSI RC, HSE crystal and HSI RC oscillators are also switched
off. The LSE or LSI is still running. After entering Standby mode, the RAM and register
contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG,
RTC, LSI, LSE Crystal 32 KHz oscillator, RCC_CSR register).

The device exits Standby mode in 60 µs when an external reset (NRST pin), an IWDG
reset, a rising edge on one of the three WKUP pins, RTC alarm (Alarm A or Alarm B),
RTC tamper event, RTC timestamp event or RTC Wakeup event occurs.

• Standby mode without RTC

The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire V

domain is powered off. The

CORE

PLL, MSI RC, HSI and LSI RC, HSE and LSE crystal oscillators are also switched off.
After entering Standby mode, the RAM and register contents are lost except for
registers in the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32 KHz
oscillator, RCC_CSR register).

The device exits Standby mode in 60 µs when an external reset (NRST pin) or a rising
edge on one of the three WKUP pin occurs.

Note: The RTC, the IWDG, and the corresponding clock sources are not stopped automatically by

entering Stop or Standby mode.The LCD is not stopped automatically by entering Stop
mode.

DS10152 Rev 9 15/136

36

Functional overview STM32L053x6 STM32L053x8

Table 2. Functionalities depending on the operating power supply range

Functionalities depending on the operating power supply

range

Operating power supply

range

(1)

DAC and ADC

operation

Dynamic voltage

scaling range

USB

V

= 1.65 to 1.71 V

DD

= 1.71 to 1.8 V

V

DD

VDD = 1.8 to 2.0 V

(2)

(2)

VDD = 2.0 to 2.4 V

VDD = 2.4 to 3.6 V

1. GPIO speed depends on VDD voltage range. Refer to Table 60: I/O AC characteristics for more information
about I/O speed.

2. CPU frequency changes from initial to final must respect "fcpu initial <4*fcpu final". It must also respect 5
μs delay between two changes. For example to switch from 4.2 MHz to 32 MHz, you can switch from 4.2
MHz to 16 MHz, wait 5 μs, then switch from 16 MHz to 32 MHz.

3. To be USB compliant from the I/O voltage standpoint, the minimum V

Table 3. CPU frequency range depending on dynamic voltage scaling

ADC only, conversion

time up to 570 ksps

ADC only, conversion

time up to 1.14 Msps

Conversion time up to

1.14 Msps

Conversion time up to

1.14 Msps

Conversion time up to

1.14 Msps

Range 2 or

range 3

Range 1, range 2 or

range 3

Range1, range 2 or

range 3

Range 1, range 2 or

range 3

Range 1, range 2 or

range 3

is 3.0 V.

DD_USB

Not functional

Functional

Functional

Functional

Functional

(3)

(3)

(3)

(3)

CPU frequency range Dynamic voltage scaling range

16 MHz to 32 MHz (1ws)

32 kHz to 16 MHz (0ws)

8 MHz to 16 MHz (1ws)

32 kHz to 8 MHz (0ws)

Range 1

Range 2

32 kHz to 4.2 MHz (0ws) Range 3

16/136 DS10152 Rev 9

STM32L053x6 STM32L053x8 Functional overview

IPs Run/Active Sleep

Table 4. Functionalities depending on the working mode

(from Run/active down to standby)

Low-

power

run

Low-

power

sleep

(1)

Stop Standby

Wakeup

capability

CPU Y -- Y -- -- --

Flash memory O O O O -- --

RAM Y Y Y Y Y --

Backup registers Y Y Y Y Y Y

EEPROM O O O O -- --

Brown-out reset
(BOR)

OOOOOOOO

DMA O O O O -- --

Programmable
Voltage Detector

OOOOOO-

(PVD)

Power-on/down
reset (POR/PDR)

High Speed
Internal (HSI)

High Speed
External (HSE)

Low Speed Internal
(LSI)

YYYYYYYY

OO----

(2)

OOOO-- --

OOOOO O

Wakeup

capability

--

Low Speed
External (LSE)

Multi-Speed
Internal (MSI)

Inter-Connect
Controller

OOOOO O

OOYY-- --

YYYYY --

RTC O O O O O O O

RTC Tamper O O O O O O O O

Auto WakeUp
(AWU)

OOOOOOOO

LCD O O O O O --

USB O O -- -- -- O --

USART O O O O O

LPUART O O O O O

(3)

(3)

O--

O--

SPI O O O O -- --

I2C O O -- -- O

(4)

O--

ADC O O -- -- -- --

DS10152 Rev 9 17/136

36

Functional overview STM32L053x6 STM32L053x8

Table 4. Functionalities depending on the working mode

(from Run/active down to standby) (continued)

IPs Run/Active Sleep

Low-

power

run

Low-

power

sleep

(1)

Stop Standby

Wakeup

capability

Wakeup

capability

DAC O O O O O --

Temperature
sensor

OOOOO --

Comparators O O O O O O --

16-bit timers O O O O -- --

LPTIMER O O O O O O

IWDG O O O O O O O O

WWDG O O O O -- --

Touch sensing
controller (TSC)

O O -- -- -- --

SysTick Timer O O O O --

GPIOs O O O O O O 2 pins

Wakeup time to
Run mode

0 µs 0.36 µs 3 µs 32 µs 3.5 µs 50 µs

0.4 µA (No
=1.8 V

DD

0.8 µA (with
=1.8 V

DD

0.4 µA (No
=3.0 V

DD

Consumption
VDD=1.8 to 3.6 V
(Typ)

Down to

140 µA/MHz

(from Flash

memory)

Down to
37 µA/MHz
(from Flash

memory)

Down to

8 µA

Down to

4.5 µA

RTC) V

RTC) V

RTC) V

1 µA (with RTC)

V

=3.0 V

DD

1. Legend:
“Y” = Yes (enable).
“O” = Optional can be enabled/disabled by software)
“-” = Not available

2. Some peripherals with wakeup from Stop capability can request HSI to be enabled. In this case, HSI is woken up by the
peripheral, and only feeds the peripheral which requested it. HSI is automatically put off when the peripheral does not need
it anymore.

3. UART and LPUART reception is functional in Stop mode. It generates a wakeup interrupt on Start. To generate a wakeup
on address match or received frame event, the LPUART can run on LSE clock while the UART has to wake up or keep
running the HSI clock.

4. I2C address detection is functional in Stop mode. It generates a wakeup interrupt in case of address match. It will wake up
the HSI during reception.

0.28 µA (No

RTC) VDD=1.8 V

0.65 µA (with

RTC) VDD=1.8 V

0.29 µA (No

RTC) VDD=3.0 V

0.85 µA (with

RTC) VDD=3.0 V

18/136 DS10152 Rev 9

STM32L053x6 STM32L053x8 Functional overview

3.2 Interconnect matrix

Several peripherals are directly interconnected. This allows autonomous communication
between peripherals, thus saving CPU resources and power consumption. In addition,
these hardware connections allow fast and predictable latency.

Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power
run, Low-power sleep and Stop modes.

Table 5. STM32L0xx peripherals interconnect matrix

Interconnect

source

COMPx

TIMx TIMx

RTC

All clock

source

USB CRS/HSI48

Interconnect

destination

TIM2,TIM21,

TIM22

LPTIM

TIM21

LPTIM

TIMx

Interconnect action Run Sleep

Timer input channel,

trigger from analog

signals comparison

Timer input channel,

trigger from analog

signals comparison

Timer triggered by other

timer

Timer triggered by Auto

wake-up

Timer triggered by RTC

event

Clock source used as

input channel for RC

measurement and

trimming

the clock recovery

system trims the HSI48

based on USB SOF

YY Y Y -

YY Y Y Y

YY Y Y -

YY Y Y -

YY Y Y Y

YY Y Y -

YY - - -

Low-

power

run

Low-

power

sleep

Stop

GPIO

TIMx

LPTIM

ADC,DAC Conversion trigger Y Y Y Y -

Timer input channel and

trigger

Timer input channel and

trigger

DS10152 Rev 9 19/136

YY Y Y -

YY Y Y Y

36

Functional overview STM32L053x6 STM32L053x8

3.3 Arm® Cortex®-M0+ core with MPU

The Cortex-M0+ processor is an entry-level 32-bit Arm Cortex processor designed for a
broad range of embedded applications. It offers significant benefits to developers, including:

• a simple architecture that is easy to learn and program

• ultra-low power, energy-efficient operation

• excellent code density

• deterministic, high-performance interrupt handling

• upward compatibility with Cortex-M processor family

• platform security robustness, with integrated Memory Protection Unit (MPU).

The Cortex-M0+ processor is built on a highly area and power optimized 32-bit processor
core, with a 2-stage pipeline Von Neumann architecture. The processor delivers exceptional
energy efficiency through a small but powerful instruction set and extensively optimized
design, providing high-end processing hardware including a single-cycle multiplier.

The Cortex-M0+ processor provides the exceptional performance expected of a modern 32­bit architecture, with a higher code density than other 8-bit and 16-bit microcontrollers.

Owing to its embedded Arm core, the STM32L053x6/8 are compatible with all Arm tools and
software.

Nested vectored interrupt controller (NVIC)

The ultra-low-power STM32L053x6/8 embed a nested vectored interrupt controller able to
handle up to 32 maskable interrupt channels and 4 priority levels.

The Cortex-M0+ processor closely integrates a configurable Nested Vectored Interrupt
Controller (NVIC), to deliver industry-leading interrupt performance. The NVIC:

• includes a Non-Maskable Interrupt (NMI)

• provides zero jitter interrupt option

• provides four interrupt priority levels

The tight integration of the processor core and NVIC provides fast execution of Interrupt
Service Routines (ISRs), dramatically reducing the interrupt latency. This is achieved
through the hardware stacking of registers, and the ability to abandon and restart load­multiple and store-multiple operations. Interrupt handlers do not require any assembler
wrapper code, removing any code overhead from the ISRs. Tail-chaining optimization also
significantly reduces the overhead when switching from one ISR to another.

To optimize low-power designs, the NVIC integrates with the sleep modes, that include a
deep sleep function that enables the entire device to enter rapidly stop or standby mode.

This hardware block provides flexible interrupt management features with minimal interrupt
latency.

20/136 DS10152 Rev 9

STM32L053x6 STM32L053x8 Functional overview

3.4 Reset and supply management

3.4.1 Power supply schemes

• VDD = 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided
externally through V

• V

SSA

, V

= 1.65 to 3.6 V: external analog power supplies for ADC, DAC, reset

DDA

blocks, RCs and PLL (minimum voltage to be applied to V

• V

used). V

DD_USB

and V

DDA

= 1.65 to 3.6V: external power supply for USB transceiver, USB_DM (PA11)
and USB_DP (PA12). To guarantee a correct voltage level for USB communication
V

DD_USB

must be above 3.0V. If USB is not used this pin must be tied to VDD or VSS.
On packages without VDD_USB pin, V
voltage.

3.4.2 Power supply supervisor

The devices have an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR) that can be coupled with a brownout reset (BOR) circuitry.

Two versions are available:

• The version with BOR activated at power-on operates between 1.8 V and 3.6 V.

• The other version without BOR operates between 1.65 V and 3.6 V.

pins.

DD

is 1.8 V when the DAC is

must be connected to VDD and VSS, respectively.

SSA

DD_USB

voltage is internally connected to VDD

DDA

After the V

threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or

DD

not at power-on), the option byte loading process starts, either to confirm or modify default
thresholds, or to disable the BOR permanently: in this case, the VDD min value becomes

1.65 V (whatever the version, BOR active or not, at power-on).

When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever
the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the
power ramp-up should guarantee that 1.65 V is reached on V

at least 1 ms after it exits

DD

the POR area.

Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To
reduce the power consumption in Stop mode, it is possible to automatically switch off the
internal reference voltage (V
V

is below a specified threshold, V

DD

) in Stop mode. The device remains in reset mode when

REFINT

POR/PDR

or V

, without the need for any external

BOR

reset circuit.

Note: The start-up time at power-on is typically 3.3 ms when BOR is active at power-up, the start-

up time at power-on can be decreased down to 1 ms typically for devices with BOR inactive
at power-up.

The devices feature an embedded programmable voltage detector (PVD) that monitors the
V

DD/VDDA

power supply and compares it to the V

threshold. This PVD offers 7 different

PVD

levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An
interrupt can be generated when V
V

DD/VDDA

is higher than the V

PVD

DD/VDDA

threshold. The interrupt service routine can then generate

drops below the V

threshold and/or when

PVD

a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

DS10152 Rev 9 21/136

36

Functional overview STM32L053x6 STM32L053x8

3.4.3 Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR) and power down.

• MR is used in Run mode (nominal regulation)

• LPR is used in the Low-power run, Low-power sleep and Stop modes

• Power down is used in Standby mode. The regulator output is high impedance, the

kernel circuitry is powered down, inducing zero consumption but the contents of the
registers and RAM are lost except for the standby circuitry (wakeup logic, IWDG, RTC,
LSI, LSE crystal 32 KHz oscillator, RCC_CSR).

3.5 Clock management

The clock controller distributes the clocks coming from different oscillators to the core and
the peripherals. It also manages clock gating for low-power modes and ensures clock
robustness. It features:

• Clock prescaler

To get the best trade-off between speed and current consumption, the clock frequency
to the CPU and peripherals can be adjusted by a programmable prescaler.

• Safe clock switching

Clock sources can be changed safely on the fly in Run mode through a configuration
register.

• Clock management

To reduce power consumption, the clock controller can stop the clock to the core,
individual peripherals or memory.

• System clock source

Three different clock sources can be used to drive the master clock SYSCLK:

– 1-25 MHz high-speed external crystal (HSE), that can supply a PLL

– 16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can

supply a PLLMultispeed internal RC oscillator (MSI), trimmable by software, able
to generate 7 frequencies (65 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1
MHz, 4.2 MHz). When a 32.768 kHz clock source is available in the system (LSE),
the MSI frequency can be trimmed by software down to a ±0.5% accuracy.

• Auxiliary clock source

Two ultra-low-power clock sources that can be used to drive the LCD controller and the
real-time clock:

– 32.768 kHz low-speed external crystal (LSE)

– 37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.

The LSI clock can be measured using the high-speed internal RC oscillator for
greater precision.

• RTC and LCD clock sources

The LSI, LSE or HSE sources can be chosen to clock the RTC and the LCD, whatever
the system clock.

• USB clock source

A 48 MHz clock trimmed through the USB SOF supplies the USB interface.

22/136 DS10152 Rev 9

STM32L053x6 STM32L053x8 Functional overview

• Startup clock

After reset, the microcontroller restarts by default with an internal 2 MHz clock (MSI).
The prescaler ratio and clock source can be changed by the application program as
soon as the code execution starts.

• Clock security system (CSS)

This feature can be enabled by software. If an HSE clock failure occurs, the master
clock is automatically switched to HSI and a software interrupt is generated if enabled.

Another clock security system can be enabled, in case of failure of the LSE it provides
an interrupt or wakeup event which is generated if enabled.

• Clock-out capability (MCO: microcontroller clock output)

It outputs one of the internal clocks for external use by the application.

Several prescalers allow the configuration of the AHB frequency, each APB (APB1 and
APB2) domains. The maximum frequency of the AHB and the APB domains is 32 MHz. See

Figure 2 for details on the clock tree.

DS10152 Rev 9 23/136

36

Functional overview STM32L053x6 STM32L053x8

MS32912V2

Legend:
HSE = High-speed external clock signal
HSI = High-speed internal clock signal
LSI = Low-speed internal clock signal
LSE = Low-speed external clock signal
MSI = Multispeed internal clock signal

Watchdog LS

LSI RC

LSE OSC

RTC

LSI tempo

@V33

/ 1,2,4,8,16

HSI16 RC

Level shifters

HSE OSC

Level shifters

RC 48MHz

Level shifters

LSU

1 MHz Clock

Detector

LSD

Clock

Recovery

System

/ 8

LSE tempo

MSI RC

Level shifters

/ 2,4,8,16

/ 2,3,4

Level shifters

PLL

X

3,4,6,8,12,16,

24,32,48

APB1

PRESC

/ 1,2,4,8,16

AHB

PRESC

/ 1,2,…, 512

Clock
Source
Control

usb_en

@V33

@V33

@V33

@V33

@V33

@V18

@V18

@V18

@V18

@V18

rng_en

48MHz

USBCLK

48MHz RNG

I2C1CLK

LPUART/

UARTCLK

LPTIMCLK

LSE

HSI16

SYSCLK

PCLK

LSI

Peripheral

clock enable

PCLK1 to APB1

peripherals

not (sleep or

deepsleep)

not (sleep or

deepsleep)

not deepsleep

not deepsleep

HCLK

SysTick

Timer

CK_PWR

FCLK

PLLCLK

HSE

HSI16

MSI

LSE

LSI

Dedicated 48MHz PLL output

HSE present or not

@V33

@V

DDCORE

ck_rchs

/ 1,4

HSI16

HSI48

MSI

1 MHz

ck_pllin

Enable Watchdog

RTC2 enable

LCD enable

ADC enable

ADCCLK

LCDCLK

LSU LSD LSD

MCO

MCOSEL

PLLSRC

HSI48MSEL

RTCSEL

System

Clock

32 MHz

max.

If (APB1 presc=1) x1

else x2)

to TIMx

Peripheral

clock enable

Peripheral

clock enable

Peripheral

clock enable

APB2

PRESC

/ 1,2,4,8,16

Peripheral

clock enable

PCLK2 to APB2

peripherals

32 MHz

max.

If (APB2 presc=1) x1

else x2)

to TIMx

Peripheral

clock enable

LSD

Figure 2. Clock tree

24/136 DS10152 Rev 9

STM32L053x6 STM32L053x8 Functional overview

3.6 Low-power real-time clock and backup registers

The real time clock (RTC) and the 5 backup registers are supplied in all modes including
standby mode. The backup registers are five 32-bit registers used to store 20 bytes of user
application data. They are not reset by a system reset, or when the device wakes up from
Standby mode.

The RTC is an independent BCD timer/counter. Its main features are the following:

• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format

• Automatically correction for 28, 29 (leap year), 30, and 31 day of the month

• Two programmable alarms with wake up from Stop and Standby mode capability

• Periodic wakeup from Stop and Standby with programmable resolution and period

• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to

synchronize it with a master clock.

• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.

• Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal
inaccuracy

• 2 anti-tamper detection pins with programmable filter. The MCU can be woken up from
Stop and Standby modes on tamper event detection.

• Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be
woken up from Stop and Standby modes on timestamp event detection.

The RTC clock sources can be:

• A 32.768 kHz external crystal

• A resonator or oscillator

• The internal low-power RC oscillator (typical frequency of 37 kHz)

• The high-speed external clock

3.7 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions, and can be individually
remapped using dedicated alternate function registers. All GPIOs are high current capable.
Each GPIO output, speed can be slowed (40 MHz, 10 MHz, 2 MHz, 400 kHz). The alternate
function configuration of I/Os can be locked if needed following a specific sequence in order
to avoid spurious writing to the I/O registers. The I/O controller is connected to a dedicated
IO bus with a toggling speed of up to 32 MHz.

Extended interrupt/event controller (EXTI)

The extended interrupt/event controller consists of 28 edge detector lines used to generate
interrupt/event requests. Each line can be individually configured to select the trigger event
(rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 51 GPIOs can be connected
to the 16 configurable interrupt/event lines. The 12 other lines are connected to PVD, RTC,
USB, USARTs, LPUART, LPTIMER or comparator events.

DS10152 Rev 9 25/136

36

Functional overview STM32L053x6 STM32L053x8

3.8 Memories

The STM32L053x6/8 devices have the following features:

• 8 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states. With the enhanced bus matrix, operating the RAM does not lead to any
performance penalty during accesses to the system bus (AHB and APB buses).

• The non-volatile memory is divided into three arrays:

– 32 or 64 Kbytes of embedded Flash program memory

– 2 Kbytes of data EEPROM

– Information block containing 32 user and factory options bytes plus 4 Kbytes of

system memory

The user options bytes are used to write-protect or read-out protect the memory (with
4 Kbyte granularity) and/or readout-protect the whole memory with the following options:

• Level 0: no protection

• Level 1: memory readout protected.

The Flash memory cannot be read from or written to if either debug features are
connected or boot in RAM is selected

• Level 2: chip readout protected, debug features (Cortex-M0+ serial wire) and boot in
RAM selection disabled (debugline fuse)

The firewall protects parts of code/data from access by the rest of the code that is executed
outside of the protected area. The granularity of the protected code segment or the non­volatile data segment is 256 bytes (Flash memory or EEPROM) against 64 bytes for the
volatile data segment (RAM).

The whole non-volatile memory embeds the error correction code (ECC) feature.

3.9 Boot modes

At startup, BOOT0 pin and nBOOT1 option bit are used to select one of three boot options:

• Boot from Flash memory

• Boot from System memory

• Boot from embedded RAM

The boot loader is located in System memory. It is used to reprogram the Flash memory by
using SPI1(PA4, PA5, PA6, PA7) or SPI2 (PB12, PB13, PB14, PB15), USART1(PA9,
PA10) or USART2(PA2, PA3). See STM32™ microcontroller system memory boot mode
AN2606 for details.

26/136 DS10152 Rev 9

STM32L053x6 STM32L053x8 Functional overview

3.10 Direct memory access (DMA)

The flexible 7-channel, general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management, avoiding the generation of interrupts when the controller
reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with software trigger
support for each channel. Configuration is done by software and transfer sizes between
source and destination are independent.

The DMA can be used with the main peripherals: SPI, I

2

C, USART, LPUART,

general-purpose timers, DAC, and ADC.

3.11 Liquid crystal display (LCD)

The LCD drives up to 8 common terminals and 32 segment terminals to drive up to 224
pixels.

• Internal step-up converter to guarantee functionality and contrast control irrespective of
V

. This converter can be deactivated, in which case the V

DD

the voltage to the LCD

• Supports static, 1/2, 1/3, 1/4 and 1/8 duty

• Supports static, 1/2, 1/3 and 1/4 bias

• Phase inversion to reduce power consumption and EMI

• Up to 8 pixels can be programmed to blink

• Unneeded segments and common pins can be used as general I/O pins

• LCD RAM can be updated at any time owing to a double-buffer

• The LCD controller can operate in Stop mode

• V

rails decoupling capability

LCD

pin is used to provide

LCD

3.12 Analog-to-digital converter (ADC)

A native 12-bit, extended to 16-bit through hardware oversampling, analog-to-digital
converter is embedded into STM32L053x6/8 device. It has up to 16 external channels and 3
internal channels (temperature sensor, voltage reference, V
Three channels, PA0, PA4 and PA5, are fast channels, while the others are standard
channels.

The ADC performs conversions in single-shot or scan mode. In scan mode, automatic
conversion is performed on a selected group of analog inputs.

The ADC frequency is independent from the CPU frequency, allowing maximum sampling
rate of 1.14 MSPS even with a low CPU speed. The ADC consumption is low at all
frequencies (~25 µA at 10 kSPS, ~200 µA at 1MSPS). An auto-shutdown function
guarantees that the ADC is powered off except during the active conversion phase.

The ADC can be served by the DMA controller. It can operate from a supply voltage down to

1.65 V.

The ADC features a hardware oversampler up to 256 samples, this improves the resolution
to 16 bits (see AN2668).

DS10152 Rev 9 27/136

voltage measurement).

LCD

36

Functional overview STM32L053x6 STM32L053x8

An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all scanned channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.

The events generated by the general-purpose timers (TIMx) can be internally connected to
the ADC start triggers, to allow the application to synchronize A/D conversions and timers.

3.13 Temperature sensor

The temperature sensor (T

) generates a voltage V

SENSE

that varies linearly with

SENSE

temperature.

The temperature sensor is internally connected to the ADC_IN18 input channel which is
used to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.

To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.

Calibration value name Description Memory address

TSENSE_CAL1

TSENSE_CAL2

Table 6. Temperature sensor calibration values

TS ADC raw data acquired at
temperature of 30 °C,
V

= 3 V

DDA

TS ADC raw data acquired at
temperature of 130 °C
V

= 3 V

DDA

0x1FF8 007A - 0x1FF8 007B

0x1FF8 007E - 0x1FF8 007F

3.13.1 Internal voltage reference (V

The internal voltage reference (V
ADC and Comparators. V

REFINT

enables accurate monitoring of the V
for ADC). The precise voltage of V

REFINT

is internally connected to the ADC_IN17 input channel. It

REFINT

REFINT

DD

)

) provides a stable (bandgap) voltage output for the

value (when no external voltage, V

is individually measured for each part by ST during

production test and stored in the system memory area. It is accessible in read-only mode.

Calibration value name Description Memory address

VREFINT_CAL

28/136 DS10152 Rev 9

Table 7. Internal voltage reference measured values

Raw data acquired at
temperature of 25 °C

= 3 V

V

DDA

, is available

REF+

0x1FF8 0078 - 0x1FF8 0079

STM32L053x6 STM32L053x8 Functional overview

3.13.2 V

voltage monitoring

LCD

This embedded hardware feature allows the application to measure the V
using the internal ADC channel ADC_IN16. As the V
and thus outside the ADC input range, the ADC input is connected to LCD_VLCD1 (which
provides 1/3V

when the LCD is configured 1/3Bias and 1/4V

LCD

configured 1/4Bias or 1/2Bias).

3.14 Digital-to-analog converter (DAC)

One 12-bit buffered DAC can be used to convert digital signal into analog voltage signal
output. An optional amplifier can be used to reduce the output signal impedance.

This digital Interface supports the following features:

• One data holding register

• Left or right data alignment in 12-bit mode

• Synchronized update capability

• Noise-wave generation

• Triangular-wave generation

• DMA capability (including the underrun interrupt)

• External triggers for conversion

• Input reference voltage V

Four DAC trigger inputs are used in the STM32L053x6/8. The DAC channel is triggered
through the timer update outputs that are also connected to different DMA channels.

REF+

supply voltage

voltage may be higher than V

LCD

LCD

LCD

when the LCD is

DDA

,

3.15 Ultra-low-power comparators and reference voltage

The STM32L053x6/8 embed two comparators sharing the same current bias and reference
voltage. The reference voltage can be internal or external (coming from an I/O).

• One comparator with ultra low consumption

• One comparator with rail-to-rail inputs, fast or slow mode.

• The threshold can be one of the following:

– DAC output

– External I/O pins

– Internal reference voltage (V

– submultiple of Internal reference voltage(1/4, 1/2, 3/4) for the rail to rail

comparator.

Both comparators can wake up the devices from Stop mode, and be combined into a
window comparator.

The internal reference voltage is available externally via a low-power / low-current output
buffer (driving current capability of 1 µA typical).

REFINT

)

DS10152 Rev 9 29/136

36

Functional overview STM32L053x6 STM32L053x8

3.16 System configuration controller

The system configuration controller provides the capability to remap some alternate
functions on different I/O ports.

The highly flexible routing interface allows the application firmware to control the routing of
different I/Os to the TIM2, TIM21, TIM22 and LPTIM timer input captures. It also controls the
routing of internal analog signals to the USB internal oscillator, ADC, COMP1 and COMP2
and the internal reference voltage V

REFINT

.

3.17 Touch sensing controller (TSC)

The STM32L053x6/8 provide a simple solution for adding capacitive sensing functionality to
any application. These devices offer up to 24 capacitive sensing channels distributed over 8
analog I/O groups.

Capacitive sensing technology is able to detect the presence of a finger near a sensor which
is protected from direct touch by a dielectric (such as glass, plastic). The capacitive variation
introduced by the finger (or any conductive object) is measured using a proven
implementation based on a surface charge transfer acquisition principle. It consists of
charging the sensor capacitance and then transferring a part of the accumulated charges
into a sampling capacitor until the voltage across this capacitor has reached a specific
threshold. To limit the CPU bandwidth usage, this acquisition is directly managed by the
hardware touch sensing controller and only requires few external components to operate.

The touch sensing controller is fully supported by the STMTouch touch sensing firmware
library, which is free to use and allows touch sensing functionality to be implemented reliably
in the end application.

Table 8. Capacitive sensing GPIOs available on STM32L053x6/8 devices

Group

1

2

3

Capacitive sensing

signal name

TSC_G1_IO1 PA0

TSC_G1_IO2 PA1 TSC_G5_IO2 PB4

TSC_G1_IO3 PA2 TSC_G5_IO3 PB6

TSC_G1_IO4 PA3 TSC_G5_IO4 PB7

TSC_G2_IO1 PA4

TSC_G2_IO2 PA5 TSC_G6_IO2 PB12

TSC_G2_IO3 PA6 TSC_G6_IO3 PB13

TSC_G2_IO4 PA7 TSC_G6_IO4 PB14

TSC_G3_IO1 PC5

TSC_G3_IO2 PB0 TSC_G7_IO2 PC1

TSC_G3_IO3 PB1 TSC_G7_IO3 PC2

TSC_G3_IO4 PB2 TSC_G7_IO4 PC3

Pin

name

(1)

Group

5

6

7

Capacitive sensing

signal name

TSC_G5_IO1 PB3

TSC_G6_IO1 PB11

TSC_G7_IO1 PC0

Pin

name

30/136 DS10152 Rev 9