ST MICROELECTRONICS STM32L052R8T6 Datasheet

STM32L052x6 STM32L052x8

UFQFPN32

(5x5 mm)

UFQFPN48

(7x7 mm)

LQFP32 (7x7 mm)
LQFP48 (7x7 mm)

LQFP64 (10x10 mm)

Standard and

thin WLCSP36

(2.61x2.88 mm)

TFBGA64

(5x5 mm)

FBGA

Ultra-low-power 32-bit MCU Arm®-based Cortex®-M0+, up to 64 KB

Flash memory, 8 KB SRAM, 2 KB EEPROM, USB, ADC, DAC

Datasheet - production data

Features

•

Ultra-low-power platform
– 1.65 V to 3.6 V power supply
–

-

40 to 125 °C temperature range
– 0.27 µA Standby mode (2 wakeup pins)
– 0.4 µA Stop mode (16 wakeup lines)
– 0.8 µA Stop mode + RTC + 8-Kbyte RAM

retention
– 88 µA/MHz in Run mode
– 3.5 µs wakeup time (from RAM)
– 5 µs wakeup time (from Flash memory)

•

Core: Arm® 32-bit Cortex®-M0+ with MPU
– From 32 kHz up to 32 MHz max.
– 0.95 DMIPS/MHz

•

Memories
–

Up to

64-Kbyte Flash memory with ECC
– 8-Kbyte RAM
– 2 Kbytes of data EEPROM with ECC
– 20-byte backup register
– Sector protection against R/W operation

•

Up to 51 fast I/Os (45 I/Os 5V tolerant)

•

Reset and supply management
– Ultra-safe, low-power BOR (brownout reset)

with 5 selectable thresholds
– Ultra-low-power POR/PDR
– Programmable voltage detector (PVD)

•

Clock sources
– 1 to 25 MHz crystal oscillator

– 32 kHz oscillator for RTC with calibration
– High speed internal 16 MHz factory-trimmed RC

(+/- 1%)
– Internal low-power 37 kHz RC
– Internal multispeed low-power 65 kHz to

4.2 MHz RC
– Internal self calibration of 48 MHz RC for USB
– PLL for CPU clock

•

Pre-programmed bootloader
– USART, SPI supported

•

Development support
– Serial wire debug supported

•

Rich Analog peripherals
– 12-bit ADC 1.14 Msps up to 16 channels (down

to 1.65 V)

– 12-bit 1 channel DAC with output buffers (down

to 1.8 V)

– 2x ultra-low-power comparators (window mode

and wake up capability, down to 1.65 V)

•

Up to 24 capacitive sensing channels supporting
touchkey, linear and rotary touch sensors

•

7-channel DMA controller, supporting ADC, SPI,
I2C, USART, DAC, Timers

•

8x peripheral communication interfaces
– 1x USB 2.0 crystal-less, battery charging

detection and LPM

– 2x USART (ISO 7816, IrDA), 1x UART (low

power)
– Up to 4x SPI 16 Mbits/s
– 2x I2C (SMBus/PMBus)

•

9x timers: 1x 16-bit with up to 4 channels, 2x 16-bit
with up to 2 channels, 1x 16-bit ultra-low-power
timer, 1x SysTick, 1x RTC, 1x 16-bit basic for DAC,
and 2x watchdogs (independent/window)

•

CRC calculation unit, 96-bit unique ID

•

True RNG and firewall protection

•

All packages are ECOPACK2

Table 1. Device summary

Reference Part number

STM32L052x6

STM32L052x8

STM32L052C6, STM32L052K6,
STM32L052R6, STM32L052T6

STM32L052C8, STM32L052K8,
STM32L052R8, STM32L052T8

June 2019 DS10182 Rev 9 1/150

This is information on a product in full production.

www.st.com

Contents STM32L052x6 STM32L052x8

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.2 Ultra-low-power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.2 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.3 Arm® Cortex®-M0+ core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.4 Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.4.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.4.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.4.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.5 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.6 Low-power real-time clock and backup registers . . . . . . . . . . . . . . . . . . . 27

3.7 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.8 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.9 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.10 Direct memory access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.11 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.12 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.12.1 Internal voltage reference (V

) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

REFINT

3.13 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.14 Ultra-low-power comparators and reference voltage . . . . . . . . . . . . . . . . 31

3.15 System configuration controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.16 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.17 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.17.1 General-purpose timers (TIM2, TIM21 and TIM22) . . . . . . . . . . . . . . . . 33

3.17.2 Low-power Timer (LPTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.17.3 Basic timer (TIM6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.17.4 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

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3.17.5 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.17.6 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.18 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.18.1 I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.18.2 Universal synchronous/asynchronous receiver transmitter (USART) . . 35

3.18.3 Low-power universal asynchronous receiver transmitter (LPUART) . . . 36

3.18.4 Serial peripheral interface (SPI)/Inter-integrated sound (I2S) . . . . . . . . 36

3.18.5 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.19 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.20 Cyclic redundancy check (CRC) calculation unit . . . . . . . . . . . . . . . . . . . 37

3.21 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6.3.2 Embedded reset and power control block characteristics . . . . . . . . . . . 60

6.3.3 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 61

6.3.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

6.3.5 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

6.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

6.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

6.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

6.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

6.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

DS10182 Rev 9 3/150

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Contents STM32L052x6 STM32L052x8

6.3.11 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

6.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

6.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

6.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

6.3.15 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

6.3.16 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

6.3.17 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

6.3.18 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

6.3.19 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

6.3.20 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

7.1 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

7.2 TFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

7.3 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

7.4 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

7.5 Standard WLCSP36 package information . . . . . . . . . . . . . . . . . . . . . . . 128

7.6 Thin WLCSP36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

7.7 LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

7.8 UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

7.9 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

7.9.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

4/150 DS10182 Rev 9

STM32L052x6 STM32L052x8 List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Ultra-low-power STM32L052x6/x8 device features and peripheral counts. . . . . . . . . . . . . 12

Table 3. Functionalities depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . 18

Table 4. CPU frequency range depending on dynamic voltage scaling . . . . . . . . . . . . . . . . . . . . . . 18

Table 5. Functionalities depending on the working mode

(from Run/active down to standby) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 6. STM32L0xx peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 7. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 8. Internal voltage reference measured values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 9. Capacitive sensing GPIOs available on STM32L052x6/8 devices . . . . . . . . . . . . . . . . . . . 32

Table 10. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 11. Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 12. STM32L052x6/8 I

Table 13. USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 14. SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 15. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 16. STM32L052x6/8 pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 17. Alternate function port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 18. Alternate function port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 19. Alternate function port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 20. Alternate function port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 21. Alternate function port H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 22. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 23. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 24. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 25. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 26. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 27. Embedded internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 28. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 29. Current consumption in Run mode, code with data processing running from Flash. . . . . . 63

Table 30. Current consumption in Run mode vs code type,

code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 31. Current consumption in Run mode, code with data processing running from RAM . . . . . . 65

Table 32. Current consumption in Run mode vs code type,

code with data processing running from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 33. Current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 34. Current consumption in Low-power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 35. Current consumption in Low-power sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 36. Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 37. Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 70

Table 38. Average current consumption during Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 39. Peripheral current consumption in Run or Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 40. Peripheral current consumption in Stop and Standby mode . . . . . . . . . . . . . . . . . . . . . . . 73

Table 41. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 42. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 43. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 44. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 45. LSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

2

C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

DS10182 Rev 9 5/150

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List of tables STM32L052x6 STM32L052x8

Table 46. 16 MHz HSI16 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 47. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 48. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 49. MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 50. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 51. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 52. Flash memory and data EEPROM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 53. Flash memory and data EEPROM endurance and retention . . . . . . . . . . . . . . . . . . . . . . . 83

Table 54. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 55. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 56. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 57. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 58. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 59. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 60. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 61. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 62. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 63. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 64. R

max for f

AIN

= 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

ADC

Table 65. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 66. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 67. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 68. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 69. Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 70. Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 71. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 72. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 73. SPI characteristics in voltage Range 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 74. SPI characteristics in voltage Range 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 75. SPI characteristics in voltage Range 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 76. I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table 77. USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 78. USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 79. USB: full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 80. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Table 81. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball grid

array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Table 82. TFBGA64 recommended PCB design rules (0.5 mm pitch BGA). . . . . . . . . . . . . . . . . . . 120

Table 83. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data. . . . . . . . . . . 123

Table 84. UFQFPN48 - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Table 85. Standard WLCSP36 - 2.61 x 2.88 mm, 0.4 mm pitch wafer level chip scale

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Table 86. Standard WLCSP36 recommended PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 87. Thin WLCSP36 - 2.61 x 2.88 mm, 0.4 mm pitch wafer level chip scale

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Table 88. WLCSP36 recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Table 89. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical data. . . . . . . . . . . 135

Table 90. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Table 91. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

6/150 DS10182 Rev 9

STM32L052x6 STM32L052x8 List of tables

Table 92. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

DS10182 Rev 9 7/150

7

List of figures STM32L052x6 STM32L052x8

List of figures

Figure 1. STM32L052x6/8 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 3. STM32L052x6/8 LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 4. STM32L052x6/8 TFBGA64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 5. STM32L052x6/8 LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 6. STM32L052x6/8 UFQFPN48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 7. STM32L052x6/8 WLCSP36 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 8. STM32L052x6/8 LQFP32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 9. STM32L052x6/8 UFQFPN32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 10. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 11. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 12. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 13. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 14. IDD vs VDD, at TA= 25/55/85/105 °C, Run mode, code running from

Flash memory, Range 2, HSE, 1WS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 15. IDD vs VDD, at TA= 25/55/85/105 °C, Run mode, code running from

Flash memory, Range 2, HSI16, 1WS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 16. IDD vs VDD, at TA= 25/55/ 85/105/125 °C, Low-power run mode, code running

from RAM, Range 3, MSI (Range 0) at 64 KHz, 0 WS . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 17. IDD vs VDD, at TA= 25/55/ 85/105/125 °C, Stop mode with RTC enabled

and running on LSE Low drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 18. IDD vs VDD, at TA= 25/55/85/105/125 °C, Stop mode with RTC disabled,

all clocks OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 19. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 20. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 21. HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 22. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 23. HSI16 minimum and maximum value versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 24. VIH/VIL versus VDD (CMOS I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 25. VIH/VIL versus VDD (TTL I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 26. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 27. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 28. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 29. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 30. Power supply and reference decoupling (V
Figure 31. Power supply and reference decoupling (V

Figure 32. 12-bit buffered/non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Figure 33. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Figure 34. SPI timing diagram - slave mode and CPHA = 1
Figure 35. SPI timing diagram - master mode
Figure 36. I
Figure 37. I

2

S slave timing diagram (Philips protocol)

2

S master timing diagram (Philips protocol)

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Figure 38. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 39. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 115

Figure 40. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint . . . . . . . . . . 117

Figure 41. LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 42. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball

grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

not connected to V

REF+

connected to V

REF+

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

DDA

) . . . . . . . . . . . . . 97

DDA

). . . . . . . . . . . . . . . . . 98

8/150 DS10182 Rev 9

STM32L052x6 STM32L052x8 List of figures

Figure 43. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball

,grid array recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 44. TFBGA64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 45. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 122

Figure 46. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat recommended footprint . . . . . . . . . . . . 123

Figure 47. LQFP48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 48. UFQFPN48 - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Figure 49. UFQFPN48 - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat

package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Figure 50. UFQFPN48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Figure 51. Standard WLCSP36 - 2.61 x 2.88 mm, 0.4 mm pitch wafer level chip scale

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Figure 52. Standard WLCSP36 - 2.61 x 2.88 mm, 0.4 mm pitch wafer level chip scale

recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Figure 53. Standard WLCSP36 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . 130

Figure 54. Thin WLCSP36 - 2.61 x 2.88 mm, 0.4 mm pitch wafer level chip scale

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Figure 55. Thin WLCSP36 - 2.61 x 2.88 mm, 0.4 mm pitch wafer level chip scale

package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Figure 56. Standard WLCSP36 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . 133

Figure 57. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 134

Figure 58. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat recommended footprint . . . . . . . . . . . . 135

Figure 59. LQFP32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Figure 60. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Figure 61. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat

recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Figure 62. UFQFPN32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Figure 63. Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

DS10182 Rev 9 9/150

9

Introduction STM32L052x6 STM32L052x8

1 Introduction

The ultra-low-power STM32L052x6/8 are offered in 8 different package types: from 32 pins

to 64 pins. Depending on the device chosen, different sets of peripherals are included, the

description below gives an overview of the complete range of peripherals proposed in this

family.

These features make the ultra-low-power STM32L052x6/8 microcontrollers suitable for a

wide range of applications:

• Gas/water meters and industrial sensors

• Healthcare and fitness equipment

• Remote control and user interface

• PC peripherals, gaming, GPS equipment

• Alarm system, wired and wireless sensors, video intercom

This STM32L052x6/8 datasheet should be read in conjunction with the STM32L0x2xx

reference manual (RM0376).

For information on the Arm

Reference Manual, available from the www.arm.com website.

®(a)

Cortex®-M0+ core please refer to the Cortex®-M0+ Technical

Figure 1 shows the general block diagram of the device family.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

10/150 DS10182 Rev 9

STM32L052x6 STM32L052x8 Description

2 Description

The ultra-low-power STM32L052x6/8 microcontrollers incorporate the connectivity power of

the universal serial bus (USB 2.0 crystal-less) with the high-performance Arm Cortex-M0+

32-bit RISC core operating at a 32 MHz frequency, a memory protection unit (MPU), high-

speed embedded memories (

EEPROM and

The STM32L052x6/8 devices provide high power efficiency for a wide range of

performance. It is achieved with a large choice of internal and external clock sources, an

internal voltage adaptation and several low-power modes.

The STM32L052x6/8 devices offer several analog features, one 12-bit ADC with hardware

oversampling, one DAC, two ultra-low-power comparators, several timers, one low-power

timer (LPTIM), three general-purpose 16-bit timers and one basic timer, one RTC and one

SysTick which can be used as timebases. They also feature two watchdogs, one watchdog

with independent clock and window capability and one window watchdog based on bus

clock.

Moreover, the STM32L052x6/8 devices embed standard and advanced communication

interfaces: up to two I2C, two SPIs, one I2S, two USARTs, a low-power UART (LPUART),

and a crystal-less USB. The devices offer up to 24 capacitive sensing channels to simply

add touch sensing functionality to any application.

8

Kbytes of RAM) plus an extensive range of enhanced I/Os and peripherals.

64

Kbytes of Flash program memory, 2 Kbytes of data

The STM32L052x6/8 also include a real-time clock and a set of backup registers that

remain powered in Standby mode.

The ultra-low-power STM32L052x6/8 devices operate from a 1.8 to 3.6 V power supply

(down to 1.65 V at power down) with BOR and from a 1.65 to 3.6 V power supply without

BOR option. They are available in the -40 to +125 °C temperature range. A comprehensive

set of power-saving modes allows the design of low-power applications.

DS10182 Rev 9 11/150

37

Description STM32L052x6 STM32L052x8

2.1 Device overview

Table 2. Ultra-low-power STM32L052x6/x8 device features and peripheral counts

Peripheral

STM32L0

52T6

Flash (Kbytes) 32 64

Data EEPROM (Kbytes) 22

RAM (Kbytes) 88

STM32

L052K6

STM32

L052C6

STM32

L052R6

STM32L

052T8

STM32

L052K8

STM32

L052C8

STM32

L052R8

General­purpose

Timers

Basic 11

LPTIMER 11

RTC/SYSTICK/IWDG/

WWDG

(1)

SPI/I2S 3(2)

/0 3(2)

I2C 21 2 21 2

Communic
ation
interfaces

USART 22

LPUART 10 1 10 1

USB/
(VDD_USB)

1/(0) 1/(1) 1/(0) 1/(1)

GPIOs 29 27

Clocks:
HSE/LSE/HSI/MSI/LSI

12-bit synchronized
ADC
Number of channels

0/1/1/1/1 0/1/1/1/1 1/1/1/1/1 1/1/1/1/1 0/1/1/1/1 0/1/1/1/1 1/1/1/1/1 1/1/1/1/1

1

10

33

1/1/1/1 1/1/1/1

(1)

/0 4(2)

(2)

1

10

(1)

/1 3(2)

37 51

1

10

16

(1)

/0 3(2)

(3)

1

(3)

(1)

/0 4(2)

29 27

1

10

10

(1)

/1

(2)

1

37 51

1

10

16

(3)

1

(3)

12-bit DAC
Number of channels

1
1

Comparators 2

Capacitive sensing
channels

14 17 24

(3)

Max. CPU frequency 32 MHz

Operating voltage

1.8 V to 3.6 V (down to 1.65 V at power-down) with BOR option

1.65 V to 3.6 V without BOR option

12/150 DS10182 Rev 9

1
1

14 17 24

(3)

STM32L052x6 STM32L052x8 Description

Table 2. Ultra-low-power STM32L052x6/x8 device features and peripheral counts (continued)

Peripheral

STM32L0

52T6

STM32

L052K6

STM32

L052C6

STM32

L052R6

STM32L

052T8

STM32

L052K8

STM32

L052C8

STM32

L052R8

Operating temperatures

Packages

1. 2 SPI interfaces are USARTs operating in SPI master mode.

2. LQFP32 has two GPIOs, less than UFQFPN32 (27).

3. TFBGA64 has one GPIO, one ADC input and one capacitive sensing channel less than LQFP64.

WLCSP

36

LQFP32,
UFQFPN

32

Ambient temperature: –40 to +125 °C
Junction temperature: –40 to +130 °C

LQFP48

UFQFPN

48

LQFP64

TFBGA

64

WLCSP

36

LQFP32,

UFQFPN

32

LQFP48

UFQFPN

48

LQFP64

TFBGA

64

DS10182 Rev 9 13/150

37

Description STM32L052x6 STM32L052x8

CORTEX M0+ CPU

Fmax:32MHz

SWD

MPU

NVIC

GPIO PORT A

GPIO PORT B

GPIO PORT C

GPIO PORT D

GPIO PORT H

Temp

sensor

RESET & CLK

FLASH

EEPROM

BOOT

RAM

DMA1

AHB: Fmax 32MHz

TSC

CRC

RNG

BRIDGE

A
P
B
2

FIREWALL

DBG

EXTI

ADC1

SPI1

USART1

TIM21

COMP1

LSE

TIM22

BRIDGE

A
P
B
1

CRS

TIM6

RAM 1K

DAC1

I2C1

I2C2

USART2

USB 2.0 FS

LPUART1

SPI2/I2S

TIM2

IWDG

RTC

WWDG

LPTIM1

BCKP REG

HSE HSI 16M

PLL

MSI

LSI

HSI 48M

PMU

REGULATOR

VDD

VDDA

VREF_OUT

NRST

PVD_IN

OSC32_IN,

OSC32_OUT

OSC_IN,

OSC_OUT

WKUPx

PA[0:15]

PH[0:1]

PD[2]

PC[0:15]

PB[0:15]

AINx

MISO, MOSI,
SCK, NSS

RX, TX, RTS,
CTS, CK

2ch

2ch

INP, INM, OUT

IN1, IN2,
ETR, OUT

DP, DM, OE,
CRS_SYNC,
VDD_USB

OUT1

SCL, SDA,
SMBA

SCL, SDA,
SMBA

RX, TX, RTS,
CTS, CK

RX, TX, RTS,
CTS

MISO/MCK,
MOSI/SD,
SCK/CK, NSS/
WS

4ch

SWD

MS3388V1

COMP2

INP, INM, OUT

Figure 1. STM32L052x6/8 block diagram

14/150 DS10182 Rev 9

STM32L052x6 STM32L052x8 Description

2.2 Ultra-low-power device continuum

The ultra-low-power family offers a large choice of core and features, from 8-bit proprietary

core up to Arm

®

Cortex®-M4, including Arm® Cortex®-M3 and Arm® Cortex®-M0+. The
STM32Lx series are the best choice to answer your needs in terms of ultra-low-power
features. The STM32 ultra-low-power series are the best solution for applications such as
gaz/water meter, keyboard/mouse or fitness and healthcare application. Several built-in
features like LCD drivers, dual-bank memory, low-power run mode, operational amplifiers,
128-bit AES, DAC, crystal-less USB and many other definitely help you building a highly
cost optimized application by reducing BOM cost. STMicroelectronics, as a reliable and
long-term manufacturer, ensures as much as possible pin-to-pin compatibility between all
STM8Lx and STM32Lx on one hand, and between all STM32Lx and STM32Fx on the other
hand. Thanks to this unprecedented scalability, your legacy application can be upgraded to
respond to the latest market feature and efficiency requirements.

DS10182 Rev 9 15/150

37

Functional overview STM32L052x6 STM32L052x8

3 Functional overview

3.1 Low-power modes

The ultra-low-power STM32L052x6/8 support dynamic voltage scaling to optimize its power
consumption in Run mode. The voltage from the internal low-drop regulator that supplies
the logic can be adjusted according to the system’s maximum operating frequency and the
external voltage supply.

There are three power consumption ranges:

• Range 1 (V

• Range 2 (full V

• Range 3 (full V

Seven low-power modes are provided to achieve the best compromise between low-power
consumption, short startup time and available wakeup sources:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs. Sleep mode power consumption at
16 MHz is about 1 mA with all peripherals off.

• Low-power run mode

This mode is achieved with the multispeed internal (MSI) RC oscillator set to the low­speed clock (max 131 kHz), execution from SRAM or Flash memory, and internal
regulator in low-power mode to minimize the regulator's operating current. In Low­power run mode, the clock frequency and the number of enabled peripherals are both
limited.

• Low-power sleep mode

This mode is achieved by entering Sleep mode with the internal voltage regulator in
low-power mode to minimize the regulator’s operating current. In Low-power sleep
mode, both the clock frequency and the number of enabled peripherals are limited; a
typical example would be to have a timer running at 32 kHz.

When wakeup is triggered by an event or an interrupt, the system reverts to the Run
mode with the regulator on.

Stop mode with RTC

The Stop mode achieves the lowest power consumption while retaining the RAM and
register contents and real time clock. All clocks in the V
PLL, MSI RC, HSE crystal and HSI RC oscillators are disabled. The LSE or LSI is still
running. The voltage regulator is in the low-power mode.

Some peripherals featuring wakeup capability can enable the HSI RC during Stop
mode to detect their wakeup condition.

The device can be woken up from Stop mode by any of the EXTI line, in 3.5 µs, the
processor can serve the interrupt or resume the code. The EXTI line source can be any
GPIO. It can be the PVD output, the comparator 1 event or comparator 2 event
(if internal reference voltage is on), it can be the RTC alarm/tamper/timestamp/wakeup
events, the USB/USART/I2C/LPUART/LPTIMER wakeup events.

range limited to 1.71-3.6 V), with the CPU running at up to 32 MHz

DD

range), with a maximum CPU frequency of 16 MHz

DD

range), with a maximum CPU frequency limited to 4.2 MHz

DD

domain are stopped, the

CORE

16/150 DS10182 Rev 9

STM32L052x6 STM32L052x8 Functional overview

• Stop mode without RTC

The Stop mode achieves the lowest power consumption while retaining the RAM and
register contents. All clocks are stopped, the PLL, MSI RC, HSI and LSI RC, HSE and
LSE crystal oscillators are disabled.

Some peripherals featuring wakeup capability can enable the HSI RC during Stop
mode to detect their wakeup condition.

The voltage regulator is in the low-power mode. The device can be woken up from Stop
mode by any of the EXTI line, in 3.5 µs, the processor can serve the interrupt or
resume the code. The EXTI line source can be any GPIO. It can be the PVD output, the
comparator 1 event or comparator 2 event (if internal reference voltage is on). It can
also be wakened by the USB/USART/I2C/LPUART/LPTIMER wakeup events.

• Standby mode with RTC

The Standby mode is used to achieve the lowest power consumption and real time
clock. The internal voltage regulator is switched off so that the entire V

CORE

domain is
powered off. The PLL, MSI RC, HSE crystal and HSI RC oscillators are also switched
off. The LSE or LSI is still running. After entering Standby mode, the RAM and register
contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG,
RTC, LSI, LSE Crystal 32 KHz oscillator, RCC_CSR register).

The device exits Standby mode in 60 µs when an external reset (NRST pin), an IWDG
reset, a rising edge on one of the three WKUP pins, RTC alarm (Alarm A or Alarm B),
RTC tamper event, RTC timestamp event or RTC Wakeup event occurs.

• Standby mode without RTC

The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire V

domain is powered off. The

CORE

PLL, MSI RC, HSI and LSI RC, HSE and LSE crystal oscillators are also switched off.
After entering Standby mode, the RAM and register contents are lost except for
registers in the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32 KHz
oscillator, RCC_CSR register).

The device exits Standby mode in 60 µs when an external reset (NRST pin) or a rising
edge on one of the three WKUP pin occurs.

Note: The RTC, the IWDG, and the corresponding clock sources are not stopped automatically by

entering Stop or Standby mode.

DS10182 Rev 9 17/150

37

Functional overview STM32L052x6 STM32L052x8

Table 3. Functionalities depending on the operating power supply range

Functionalities depending on the operating power supply

range

Operating power supply

range

(1)

DAC and ADC

operation

Dynamic voltage

scaling range

USB

V

= 1.65 to 1.71 V

DD

= 1.71 to 1.8 V

V

DD

VDD = 1.8 to 2.0 V

(2)

(2)

VDD = 2.0 to 2.4 V

VDD = 2.4 to 3.6 V

1. GPIO speed depends on VDD voltage range. Refer to Table 61: I/O AC characteristics for more information
about I/O speed.

2. CPU frequency changes from initial to final must respect "fcpu initial <4*fcpu final". It must also respect 5
μs delay between two changes. For example to switch from 4.2 MHz to 32 MHz, you can switch from 4.2
MHz to 16 MHz, wait 5 μs, then switch from 16 MHz to 32 MHz.

3. To be USB compliant from the I/O voltage standpoint, the minimum V

Table 4. CPU frequency range depending on dynamic voltage scaling

ADC only, conversion

time up to 570 ksps

ADC only, conversion

time up to 1.14 Msps

Conversion time up to

1.14 Msps

Conversion time up to

1.14 Msps

Conversion time up to

1.14 Msps

Range 2 or

range 3

Range 1, range 2 or

range 3

Range1, range 2 or

range 3

Range 1, range 2 or

range 3

Range 1, range 2 or

range 3

is 3.0 V.

DD_USB

Not functional

Functional

Functional

Functional

Functional

(3)

(3)

(3)

(3)

CPU frequency range Dynamic voltage scaling range

16 MHz to 32 MHz (1ws)

32 kHz to 16 MHz (0ws)

8 MHz to 16 MHz (1ws)

32 kHz to 8 MHz (0ws)

Range 1

Range 2

32 kHz to 4.2 MHz (0ws) Range 3

18/150 DS10182 Rev 9

STM32L052x6 STM32L052x8 Functional overview

IPs Run/Active Sleep

Table 5. Functionalities depending on the working mode

(from Run/active down to standby)

Low-

power

run

power

Low-

sleep

(1)

Stop Standby

Wakeup

capability

CPU Y -- Y -- -- --

Flash memory O O O O -- --

RAM Y Y Y Y Y --

Backup registers Y Y Y Y Y Y

EEPROM O O O O -- --

Brown-out reset
(BOR)

OOOOOOOO

DMA O O O O -- --

Programmable
Voltage Detector

OOOOOO-

(PVD)

Power-on/down
reset (POR/PDR)

High Speed
Internal (HSI)

High Speed
External (HSE)

Low Speed Internal
(LSI)

YYYYYYYY

OO----

(2)

OOOO-- --

OOOOO O

Wakeup

capability

--

Low Speed
External (LSE)

Multi-Speed
Internal (MSI)

Inter-Connect
Controller

OOOOO O

OOYY-- --

YYYYY --

RTC O O O O O O O

RTC Tamper O O O O O O O O

Auto WakeUp
(AWU)

OOOOOOOO

USB O O -- -- -- O --

USART O O O O O

LPUART O O O O O

(3)

(3)

O--

O--

SPI O O O O -- --

I2C O O -- -- O

(4)

O--

ADC O O -- -- -- --

DAC O O O O O --

DS10182 Rev 9 19/150

37

Functional overview STM32L052x6 STM32L052x8

IPs Run/Active Sleep

Temperature
sensor

Table 5. Functionalities depending on the working mode

(from Run/active down to standby) (continued)

Low-

power

run

OOOOO --

Low-

power

sleep

(1)

Stop Standby

Wakeup

capability

Wakeup

capability

Comparators O O O O O O --

16-bit timers O O O O -- --

LPTIMER O O O O O O

IWDG O O O O O O O O

WWDG O O O O -- --

Touch sensing
controller (TSC)

O O -- -- -- --

SysTick Timer O O O O --

GPIOs O O O O O O 2 pins

Wakeup time to
Run mode

Consumption

=1.8 to 3.6 V

V

DD

(Typ)

1. Legend:
“Y” = Yes (enable).
“O” = Optional can be enabled/disabled by software)
“-” = Not available

2. Some peripherals with wakeup from Stop capability can request HSI to be enabled. In this case, HSI is woken up by the
peripheral, and only feeds the peripheral which requested it. HSI is automatically put off when the peripheral does not need
it anymore.

3. UART and LPUART reception is functional in Stop mode. It generates a wakeup interrupt on Start. To generate a wakeup
on address match or received frame event, the LPUART can run on LSE clock while the UART has to wake up or keep
running the HSI clock.

4. I2C address detection is functional in Stop mode. It generates a wakeup interrupt in case of address match. It will wake up
the HSI during reception.

0 µs 0.36 µs 3 µs 32 µs 3.5 µs 50 µs

0.4 µA (No

Down to

140 µA/MHz

(from Flash

memory)

Down to
37 µA/MHz
(from Flash

memory)

Down to

8 µA

Down to

4.5 µA

RTC) V

DD

0.8 µA (with

RTC) V

DD

0.4 µA (No

RTC) V

DD

=1.8 V

=1.8 V

=3.0 V

RTC) VDD=1.8 V

RTC) VDD=1.8 V

RTC) VDD=3.0 V

1 µA (with RTC)

V

DD

=3.0 V

RTC) VDD=3.0 V

0.28 µA (No

0.65 µA (with

0.29 µA (No

0.85 µA (with

20/150 DS10182 Rev 9

STM32L052x6 STM32L052x8 Functional overview

3.2 Interconnect matrix

Several peripherals are directly interconnected. This allows autonomous communication
between peripherals, thus saving CPU resources and power consumption. In addition,
these hardware connections allow fast and predictable latency.

Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power
run, Low-power sleep and Stop modes.

Table 6. STM32L0xx peripherals interconnect matrix

Interconnect

source

COMPx

TIMx TIMx

RTC

All clock

source

USB CRS/HSI48

Interconnect

destination

TIM2,TIM21,

TIM22

LPTIM

TIM21

LPTIM

TIMx

Interconnect action Run Sleep

Timer input channel,

trigger from analog

signals comparison

Timer input channel,

trigger from analog

signals comparison

Timer triggered by other

timer

Timer triggered by Auto

wake-up

Timer triggered by RTC

event

Clock source used as

input channel for RC

measurement and

trimming

the clock recovery

system trims the HSI48

based on USB SOF

YY Y Y -

YY Y Y Y

YY Y Y -

YY Y Y -

YY Y Y Y

YY Y Y -

YY - - -

Low-

power

run

Low-

power

sleep

Stop

GPIO

TIMx

LPTIM

ADC,DAC Conversion trigger Y Y Y Y -

Timer input channel and

trigger

Timer input channel and

trigger

DS10182 Rev 9 21/150

YY Y Y -

YY Y Y Y

37

Functional overview STM32L052x6 STM32L052x8

3.3 Arm® Cortex®-M0+ core with MPU

The Cortex-M0+ processor is an entry-level 32-bit Arm Cortex processor designed for a
broad range of embedded applications. It offers significant benefits to developers, including:

• a simple architecture that is easy to learn and program

• ultra-low power, energy-efficient operation

• excellent code density

• deterministic, high-performance interrupt handling

• upward compatibility with Cortex-M processor family

• platform security robustness, with integrated Memory Protection Unit (MPU).

The Cortex-M0+ processor is built on a highly area and power optimized 32-bit processor
core, with a 2-stage pipeline Von Neumann architecture. The processor delivers exceptional
energy efficiency through a small but powerful instruction set and extensively optimized
design, providing high-end processing hardware including a single-cycle multiplier.

The Cortex-M0+ processor provides the exceptional performance expected of a modern 32­bit architecture, with a higher code density than other 8-bit and 16-bit microcontrollers.

Owing to its embedded Arm core, the STM32L052x6/8 are compatible with all Arm tools and
software.

Nested vectored interrupt controller (NVIC)

The ultra-low-power STM32L052x6/8 embed a nested vectored interrupt controller able to
handle up to 32 maskable interrupt channels and 4 priority levels.

The Cortex-M0+ processor closely integrates a configurable Nested Vectored Interrupt
Controller (NVIC), to deliver industry-leading interrupt performance. The NVIC:

• includes a Non-Maskable Interrupt (NMI)

• provides zero jitter interrupt option

• provides four interrupt priority levels

The tight integration of the processor core and NVIC provides fast execution of Interrupt
Service Routines (ISRs), dramatically reducing the interrupt latency. This is achieved
through the hardware stacking of registers, and the ability to abandon and restart load­multiple and store-multiple operations. Interrupt handlers do not require any assembler
wrapper code, removing any code overhead from the ISRs. Tail-chaining optimization also
significantly reduces the overhead when switching from one ISR to another.

To optimize low-power designs, the NVIC integrates with the sleep modes, that include a
deep sleep function that enables the entire device to enter rapidly stop or standby mode.

This hardware block provides flexible interrupt management features with minimal interrupt
latency.

22/150 DS10182 Rev 9

STM32L052x6 STM32L052x8 Functional overview

3.4 Reset and supply management

3.4.1 Power supply schemes

• VDD = 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided
externally through V

• V

SSA

, V

= 1.65 to 3.6 V: external analog power supplies for ADC, DAC, reset

DDA

blocks, RCs and PLL (minimum voltage to be applied to V

• V

used). V

DD_USB

and V

DDA

= 1.65 to 3.6V: external power supply for USB transceiver, USB_DM (PA11)
and USB_DP (PA12). To guarantee a correct voltage level for USB communication
V

DD_USB

must be above 3.0V. If USB is not used this pin must be tied to VDD or VSS.
On packages without VDD_USB pin, V
voltage.

3.4.2 Power supply supervisor

The devices have an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR) that can be coupled with a brownout reset (BOR) circuitry.

Two versions are available:

• The version with BOR activated at power-on operates between 1.8 V and 3.6 V.

• The other version without BOR operates between 1.65 V and 3.6 V.

pins.

DD

is 1.8 V when the DAC is

must be connected to VDD and VSS, respectively.

SSA

DD_USB

voltage is internally connected to VDD

DDA

After the V

threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or

DD

not at power-on), the option byte loading process starts, either to confirm or modify default
thresholds, or to disable the BOR permanently: in this case, the VDD min value becomes

1.65 V (whatever the version, BOR active or not, at power-on).

When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever
the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the
power ramp-up should guarantee that 1.65 V is reached on V

at least 1 ms after it exits

DD

the POR area.

Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To
reduce the power consumption in Stop mode, it is possible to automatically switch off the
internal reference voltage (V
V

is below a specified threshold, V

DD

) in Stop mode. The device remains in reset mode when

REFINT

POR/PDR

or V

, without the need for any external

BOR

reset circuit.

Note: The start-up time at power-on is typically 3.3 ms when BOR is active at power-up, the start-

up time at power-on can be decreased down to 1 ms typically for devices with BOR inactive
at power-up.

The devices feature an embedded programmable voltage detector (PVD) that monitors the
V

DD/VDDA

power supply and compares it to the V

threshold. This PVD offers 7 different

PVD

levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An
interrupt can be generated when V
V

DD/VDDA

is higher than the V

PVD

DD/VDDA

threshold. The interrupt service routine can then generate

drops below the V

threshold and/or when

PVD

a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

DS10182 Rev 9 23/150

37

Functional overview STM32L052x6 STM32L052x8

3.4.3 Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR) and power down.

• MR is used in Run mode (nominal regulation)

• LPR is used in the Low-power run, Low-power sleep and Stop modes

• Power down is used in Standby mode. The regulator output is high impedance, the

kernel circuitry is powered down, inducing zero consumption but the contents of the
registers and RAM are lost except for the standby circuitry (wakeup logic, IWDG, RTC,
LSI, LSE crystal 32 KHz oscillator, RCC_CSR).

3.5 Clock management

The clock controller distributes the clocks coming from different oscillators to the core and
the peripherals. It also manages clock gating for low-power modes and ensures clock
robustness. It features:

• Clock prescaler

To get the best trade-off between speed and current consumption, the clock frequency
to the CPU and peripherals can be adjusted by a programmable prescaler.

• Safe clock switching

Clock sources can be changed safely on the fly in Run mode through a configuration
register.

• Clock management

To reduce power consumption, the clock controller can stop the clock to the core,
individual peripherals or memory.

• System clock source

Three different clock sources can be used to drive the master clock SYSCLK:

– 1-25 MHz high-speed external crystal (HSE), that can supply a PLL

– 16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can

supply a PLLMultispeed internal RC oscillator (MSI), trimmable by software, able
to generate 7 frequencies (65 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1
MHz, 4.2 MHz). When a 32.768 kHz clock source is available in the system (LSE),
the MSI frequency can be trimmed by software down to a ±0.5% accuracy.

• Auxiliary clock source

Two ultra-low-power clock sources that can be used to drive the real-time clock:

– 32.768 kHz low-speed external crystal (LSE)

– 37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.

The LSI clock can be measured using the high-speed internal RC oscillator for
greater precision.

• RTC clock source

The LSI, LSE or HSE sources can be chosen to clock the RTC, whatever the system
clock.

• USB clock source

A 48 MHz clock trimmed through the USB SOF supplies the USB interface.

24/150 DS10182 Rev 9

STM32L052x6 STM32L052x8 Functional overview

• Startup clock

After reset, the microcontroller restarts by default with an internal 2 MHz clock (MSI).
The prescaler ratio and clock source can be changed by the application program as
soon as the code execution starts.

• Clock security system (CSS)

This feature can be enabled by software. If an HSE clock failure occurs, the master
clock is automatically switched to HSI and a software interrupt is generated if enabled.

Another clock security system can be enabled, in case of failure of the LSE it provides
an interrupt or wakeup event which is generated if enabled.

• Clock-out capability (MCO: microcontroller clock output)

It outputs one of the internal clocks for external use by the application.

Several prescalers allow the configuration of the AHB frequency, each APB (APB1 and
APB2) domains. The maximum frequency of the AHB and the APB domains is 32 MHz. See

Figure 2 for details on the clock tree.

DS10182 Rev 9 25/150

37

Functional overview STM32L052x6 STM32L052x8

MS33392V1

Legend:
HSE = High-speed external clock signal
HSI = High-speed internal clock signal
LSI = Low-speed internal clock signal
LSE = Low-speed external clock signal
MSI = Multispeed internal clock signal

Watchdog LS

LSI RC

LSE OSC

RTC

LSI tempo

@V33

/ 1,2,4,8,16

HSI16 RC

Level shifters

HSE OSC

Level shifters

RC 48MHz

Level shifters

LSU

1 MHz Clock

Detector

LSD

Clock

Recovery

System

/ 8

LSE tempo

MSI RC

Level shifters

/ 2,4,8,16

/ 2,3,4

Level shifters

PLL

X

3,4,6,8,12,16,

24,32,48

AHB

PRESC

/ 1,2,…, 512

Clock
Source
Control

@V33

@V33

@V33

@V33

@V33

@V18

@V18

@V18

@V18

@V18

usb_en

rng_en

48MHz

USBCLK

48MHz RNG

I2C1CLK

LPUART/

UARTCLK

LPTIMCLK

LSE

HSI16

SYSCLK

PCLK

LSI

not (sleep or

deepsleep)

not (sleep or

deepsleep)

not deepsleep

not deepsleep

HCLK

CK_PWR

FCLK

PLLCLK

HSE

HSI16

MSI

LSE

LSI

Dedicated 48MHz PLL output

HSE present or not

@V33

@V

DDCORE

ck_rchs

/ 1,4

HSI16

HSI48

MSI

1 MHz

ck_pllin

Enable Watchdog

RTC2 enable

ADC enable

ADCCLK

LSU LSD LSD

MCO

MCOSEL

PLLSRC

RTCSEL

System

Clock

APB1

PRESC

/ 1,2,4,8,16

Peripheral

clock enable

PCLK1 to APB1

peripherals

32 MHz

max.

If (APB1 presc=1) x1

else x2)

to TIMx

Peripheral

clock enable

APB2

PRESC

/ 1,2,4,8,16

Peripheral

clock enable

PCLK2 to APB2

peripherals

32 MHz

max.

If (APB2 presc=1) x1

else x2)

to TIMx

Peripheral

clock enable

Peripheral

clock enable

Peripheral

clock enable

SysTick

Timer

HSI48MSEL

Figure 2. Clock tree

26/150 DS10182 Rev 9

STM32L052x6 STM32L052x8 Functional overview

3.6 Low-power real-time clock and backup registers

The real time clock (RTC) and the 5 backup registers are supplied in all modes including
standby mode. The backup registers are five 32-bit registers used to store 20 bytes of user
application data. They are not reset by a system reset, or when the device wakes up from
Standby mode.

The RTC is an independent BCD timer/counter. Its main features are the following:

• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format

• Automatically correction for 28, 29 (leap year), 30, and 31 day of the month

• Two programmable alarms with wake up from Stop and Standby mode capability

• Periodic wakeup from Stop and Standby with programmable resolution and period

• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to

synchronize it with a master clock.

• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.

• Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal
inaccuracy

• 2 anti-tamper detection pins with programmable filter. The MCU can be woken up from
Stop and Standby modes on tamper event detection.

• Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be
woken up from Stop and Standby modes on timestamp event detection.

The RTC clock sources can be:

• A 32.768 kHz external crystal

• A resonator or oscillator

• The internal low-power RC oscillator (typical frequency of 37 kHz)

• The high-speed external clock

3.7 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions, and can be individually
remapped using dedicated alternate function registers. All GPIOs are high current capable.
Each GPIO output, speed can be slowed (40 MHz, 10 MHz, 2 MHz, 400 kHz). The alternate
function configuration of I/Os can be locked if needed following a specific sequence in order
to avoid spurious writing to the I/O registers. The I/O controller is connected to a dedicated
IO bus with a toggling speed of up to 32 MHz.

Extended interrupt/event controller (EXTI)

The extended interrupt/event controller consists of 28 edge detector lines used to generate
interrupt/event requests. Each line can be individually configured to select the trigger event
(rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 51 GPIOs can be connected
to the 16 configurable interrupt/event lines. The 12 other lines are connected to PVD, RTC,
USB, USARTs, LPUART, LPTIMER or comparator events.

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Functional overview STM32L052x6 STM32L052x8

3.8 Memories

The STM32L052x6/8 devices have the following features:

• 8 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states. With the enhanced bus matrix, operating the RAM does not lead to any
performance penalty during accesses to the system bus (AHB and APB buses).

• The non-volatile memory is divided into three arrays:

– 32 or 64 Kbytes of embedded Flash program memory

– 2 Kbytes of data EEPROM

– Information block containing 32 user and factory options bytes plus 4 Kbytes of

system memory

The user options bytes are used to write-protect or read-out protect the memory (with
4 Kbyte granularity) and/or readout-protect the whole memory with the following options:

• Level 0: no protection

• Level 1: memory readout protected.

The Flash memory cannot be read from or written to if either debug features are
connected or boot in RAM is selected

• Level 2: chip readout protected, debug features (Cortex-M0+ serial wire) and boot in
RAM selection disabled (debugline fuse)

The firewall protects parts of code/data from access by the rest of the code that is executed
outside of the protected area. The granularity of the protected code segment or the non­volatile data segment is 256 bytes (Flash memory or EEPROM) against 64 bytes for the
volatile data segment (RAM).

The whole non-volatile memory embeds the error correction code (ECC) feature.

3.9 Boot modes

At startup, BOOT0 pin and nBOOT1 option bit are used to select one of three boot options:

• Boot from Flash memory

• Boot from System memory

• Boot from embedded RAM

The boot loader is located in System memory. It is used to reprogram the Flash memory by
using SPI1(PA4, PA5, PA6, PA7) or SPI2 (PB12, PB13, PB14, PB15), USART1(PA9,
PA10) or USART2(PA2, PA3). See STM32™ microcontroller system memory boot mode
AN2606 for details.

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STM32L052x6 STM32L052x8 Functional overview

3.10 Direct memory access (DMA)

The flexible 7-channel, general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management, avoiding the generation of interrupts when the controller
reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with software trigger
support for each channel. Configuration is done by software and transfer sizes between
source and destination are independent.

The DMA can be used with the main peripherals: SPI, I
general-purpose timers, DAC, and ADC.

2

C, USART, LPUART,

3.11 Analog-to-digital converter (ADC)

A native 12-bit, extended to 16-bit through hardware oversampling, analog-to-digital
converter is embedded into STM32L052x6/8 device. It has up to 16 external channels and 3
internal channels (temperature sensor, voltage reference). Three channels, PA0, PA4 and
PA5, are fast channels, while the others are standard channels.

The ADC performs conversions in single-shot or scan mode. In scan mode, automatic
conversion is performed on a selected group of analog inputs.

The ADC frequency is independent from the CPU frequency, allowing maximum sampling
rate of 1.14 MSPS even with a low CPU speed. The ADC consumption is low at all
frequencies (~25 µA at 10 kSPS, ~200 µA at 1MSPS). An auto-shutdown function
guarantees that the ADC is powered off except during the active conversion phase.

The ADC can be served by the DMA controller. It can operate from a supply voltage down to

1.65 V.

The ADC features a hardware oversampler up to 256 samples, this improves the resolution
to 16 bits (see AN2668).

An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all scanned channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.

The events generated by the general-purpose timers (TIMx) can be internally connected to
the ADC start triggers, to allow the application to synchronize A/D conversions and timers.

3.12 Temperature sensor

The temperature sensor (T
temperature.

The temperature sensor is internally connected to the ADC_IN18 input channel which is
used to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.

SENSE

) generates a voltage V

that varies linearly with

SENSE

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37

Functional overview STM32L052x6 STM32L052x8

To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.

Calibration value name Description Memory address

TSENSE_CAL1

TSENSE_CAL2

Table 7. Temperature sensor calibration values

TS ADC raw data acquired at
temperature of 30 °C,
V

= 3 V

DDA

TS ADC raw data acquired at
temperature of 130 °C
V

= 3 V

DDA

0x1FF8 007A - 0x1FF8 007B

0x1FF8 007E - 0x1FF8 007F

3.12.1 Internal voltage reference (V

The internal voltage reference (V
ADC and Comparators. V

REFINT

enables accurate monitoring of the V
for ADC). The precise voltage of V

REFINT

is internally connected to the ADC_IN17 input channel. It

REFINT

REFINT

DD

)

) provides a stable (bandgap) voltage output for the

value (when no external voltage, V

is individually measured for each part by ST during

production test and stored in the system memory area. It is accessible in read-only mode.

Calibration value name Description Memory address

VREFINT_CAL

Table 8. Internal voltage reference measured values

Raw data acquired at
temperature of 25 °C

= 3 V

V

DDA

3.13 Digital-to-analog converter (DAC)

One 12-bit buffered DAC can be used to convert digital signal into analog voltage signal
output. An optional amplifier can be used to reduce the output signal impedance.

This digital Interface supports the following features:

• One data holding register

• Left or right data alignment in 12-bit mode

• Synchronized update capability

• Noise-wave generation

• Triangular-wave generation

• DMA capability (including the underrun interrupt)

• External triggers for conversion

• Input reference voltage V

Four DAC trigger inputs are used in the STM32L052x6/8. The DAC channel is triggered
through the timer update outputs that are also connected to different DMA channels.

REF+

, is available

REF+

0x1FF8 0078 - 0x1FF8 0079

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