STMicroelectronics STM32H72x, STM32H73x, STM32H74x, STM32H75x User manual
AN4891
Application note
STM32H72x, STM32H73x, and single-core STM32H74x/75x
system architecture and performance
Introduction
The STM32H7 Series is the first series of STMicroelectronics microcontrollers in 40 nmprocess technology. This technology enables STM32H7 devices to integrate high-density
embedded Flash memory and SRAM that decrease the resource constraints typically
complicating high-end embedded development. It also unleashes the performance of the
core and enables ultra-fast data transfers through the system while realizing major power
savings.
t
In addition, the STM32H7 Series is
microcontrollers able to run at up to 550 MHz, reaching new performa
1177 DMIPS and 2777 CoreMark
he first series of Arm® Cortex®-M7-based 32-bit
®
.
nce records of
The STM32H7 Series is the continui
products with significant architecture improvement allowing a performance boost versus
STM32F7 Series devices.
The architecture and performance of STM32H7 Series devices make them ideally suited to
industria
as well as to high-performance motor control, domestic appliances, and use in small
devices with rich user interfaces such as smart watches.
This application note focuses on STM32H72x, STM32H73x, STM32H742x,
STM32H74
STM32H72x/73x/74x/75x (see Tabl e 1). Dual-core devices are not covered by this
document. Its objective is to present the global
memory interfaces and features, which provide a high degree of flexibility to achieve the
best performance and additional code and data size trade-off.
The application note also provides the results of a so
STM32H74x/75x Arm
memory partitioning configurations with different code and data locations.
This application note is delivered w
includes the H7_single_cpu_perf project aimed at demonstrating the performance of CPU
memory accesses in different configurations with code execution and data storage in
different memory locations using L1 cache. The project runs on the STM32H743I-EVAL
board.
l gateways, home automation, telecom equipment and smart consumer products,
3/753x and STM32H750x single-core microcontrollers, referred to herein as
®
Cortex®-M7 single-core architecture performance in various
ty of the STM32F7 Series in terms of high-performance
ar
chitecture of the devices as well as their
ftware demonstration of the
ith the X-CUBE-PERF-H7 Expansion Package, that
Reference documents
• Reference manual STM32H723/733, STM32H725/735 and STM32H730 Value line
advanced Arm®-
• Reference ma
advanced Arm®-based 32-bit MCUs (RM0433)
All documents are available from STMicroelectronics website: ww
September 2020 AN4891 Rev 4 1/55
based 32-bit MCUs (RM0468)
nual STM32H742, STM32H743/753 and STM32H750 Value line
.st.com.
w
www.st.com
1
Contents AN4891
Contents
1 General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 STM32H72x/73x/74x/75x
system architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Cortex®-M7 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Cortex
2.3 Cortex
2.3.1 AXI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3.2 TCM bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3.3 AHBS bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3.4 AHBP bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 STM32H72x/73x/74x/75x interconnect matrix . . . . . . . . . . . . . . . . . . . . . . 9
2.4.1 AXI bus matrix in the D1 domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
®
-M7 system caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
®
-M7 memory interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4.2 AHB bus matrices in the D2 and D3 domains . . . . . . . . . . . . . . . . . . . . 13
2.4.3 Inter-domain buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5 STM32H72x/73x/74x/75x memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.5.1 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.5.2 Embedded RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.5.3 External memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.6 Main architecture differences between STM32F7 Series and,
STM32H72x, STM32H73x, STM32H74x and STM32H75x devices . . . . 31
3 Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.1 FFT demonstration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.2 Configuring demonstration projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4 Benchmark results and analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.1 Benchmark results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.1.1 Effects of data and instructions locations on performance . . . . . . . . . . 39
4.1.2 Impact of basic parameters on performance . . . . . . . . . . . . . . . . . . . . . 44
4.2 Result analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5 Software memory partitioning and tips . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.1 Software memory partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2/55 AN4891 Rev 4
AN4891 Contents
5.2 Recommendations and tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
AN4891 Rev 4 3/55
3
List of tables AN4891
List of tables
Table 1. STM32H7 lines targeted by this application note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. STM32H72x/73x/74x/75x device cache sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Cortex
Table 4. Bus-master-to-bus-slave possible interconnections in
Table 5. Internal memory summary of the STM32H72x and STM32H73x . . . . . . . . . . . . . . . . . . . . 23
Table 6. Internal memory summary of the STM32H74x and STM32H75x . . . . . . . . . . . . . . . . . . . . 23
Table 7. Architecture differences between the STM32F7 Series and
Table 8. MDK-ARM results of data storage for different memory locations (execution location
Table 9. MDK-ARM results of execution in different memory locations (data location
Table 10. MDK-ARM results of data storage in different memory locations (execution location
Table 11. MDK-ARM results of execution in different memory locations (data location fixed in DTCM-
Table 12. MDK-ARM results of data storage in different memory locations (execution location fixed in
Table 13. MDK-ARM results of data storage in different memory locations (execution location fixed in
Table 14. MDK-ARM results of data storage in different memory locations (execution location fixed in
Table 15. MDK-ARM results of execution in different memory locations (data location fixed in DTCM-
Table 16. Number of Flash wait states vs performance (MDK-ARM)/CPU running at 480 MHz/
Table 17. Number of Flash wait states vs performance (MDK-ARM) /CPU running at 400 MHz/
Table 18. SDRAM data read/write access performance vs bus width and
Table 19. Execution performance from SDRAM versus bus width and clock
Table 20. SDRAM data read/write access performance in swapped and non-swapped
Table 21. Execution performance from SDRAM in swapped and non-swapped bank
Table 22. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
®
-M7 default memory attributes after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
STM32H72x/73x/74x/75x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
STM32H72x, STM32H73x, STM32H74x and STM32H75x devices. . . . . . . . . . . . . . . . . . 31
fixed in ITCM-RAM), CPU running at 480 MHz (AHB_FREQ_HALF_CORE_FREQ,
USE_VOS0_480MHZ = 1, Flash ws = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
fixed in DTCM-RAM), CPU running at 480 MHz (AHB_FREQ_HALF_CORE_FREQ,
USE_VOS0_480MHZ = 1, Flash ws = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
fixed in ITCM-RAM) CPU running at 240 MHz (AHB_FREQ_EQU_CORE_FREQ,
USE_VOS0_480MHZ = 1, Flash ws = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
RAM) CPU running at 240 MHz (AHB_FREQ_EQU_CORE_FREQ,
USE_VOS0_480MHZ = 1, Flash ws = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
ITCM-RAM) CPU running at 400 MHz (AHB_FREQ_HALF_CORE_FREQ,
USE_VOS0_480MHZ = 0, Flash ws = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
ITCM-RAM) CPU running at 400 MHz (AHB_FREQ_HALF_CORE_FREQ,
USE_VOS0_480MHZ = 0, Flash ws = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
ITCM-RAM) CPU running at 200 MHz (AHB_FREQ_EQU_CORE_FREQ,
USE_VOS0_480MHZ = 0, Flash ws = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
RAM) CPU running at 200 MHz ((AHB_FREQ_EQU_CORE_FREQ,
USE_VOS0_480MHZ = 0, Flash ws = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
AXI running at 240 MHz (VOS0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
AXI running at 200 MHz (VOS1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
clock frequency based on 6 - D1_ITCM - D1_SDRAM configuration . . . . . . . . . . . . . . . . . 46
frequency based on 10 - D1_SDRAM_Swapped - D1_DTCM configuration . . . . . . . . . . . 46
bank configurations based on 6 - D1_ITCM - D1_SDRAM configuration. . . . . . . . . . . . . . 46
configurations based on 10 - D1_SDRAM_Swapped - D1_DTCM configuration . . . . . . . . 47
4/55 AN4891 Rev 4
AN4891 List of figures
List of figures
Figure 1. STM32H72x and STM32H73x system architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 2. STM32H74x and STM32H75x system architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 3. Examples of D1/D2 master accesses to memories in D1, D2, and D3 domains
(STM32H74x and STM32H75x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 4. STM32H72x/73x/74x/75x Flash memory accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 5. STM32H72x and STM32H73x external memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 6. STM32H74x and STM32H75x external memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 7. Example of external memory interfaces for STM32H74x and STM32H75x . . . . . . . . . . . . 27
Figure 8. FFT example block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 9. Keil
Figure 10. MDK-ARM flags configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 11. MDK-ARM heap and stack configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 12. Virtual COM port number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 13. STM32H74x and STM32H75x FFT benchmark: data storage in different
Figure 14. STM32H74x and STM32H75x FFT benchmark: code execution from different
Figure 15. STM32H74x and STM32H75x FFT benchmark: data storage in different
Figure 16. STM32H74x and STM32H75x FFT benchmark: code execution from
®
(MDK-ARM) configuration selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
memory locations (code in ITCM-RAM) at 480 MHz with MDK-ARM toolchain . . . . . . . . . 42
memory locations (R/W data in DTCM-RAM) at 480 MHz with MDK-ARM toolchain. . . . . 43
memory locations (code in ITCM-RAM) at 400 MHz with MDK-ARM toolchain . . . . . . . . . 43
different memory locations (R/W data in DTCM-RAM) at 400 MHz
with MDK-ARM toolchain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
AN4891 Rev 4 5/55
5
General information AN4891
1 General information
This document applies to STM32 Arm®-based
2 STM32H72x/73x/74x/75x
system architecture overview
This section introduces the main architecture features of the STM32H72x/73x/74x/75x.
Tabl e 1 defines the product lines concerned.
Generic part numbers Products lines
STM32H72x, STM32H73x STM32H723/733, STM32H725/735, STM32H730 Value line
STM32H74x, STM32H75x STM32H742, STM32H743/753 lines, STM32H750 Value line
2.1 Cortex®-M7 core
The STM32H72x/73x/74x/75x devices are built on a high-performance Arm® Cortex®-M7
32-bit RISC core operating at up to 480 MHz frequency (STM32H74x/75x) and 550 MHz
TM32H72x/73x). The Cortex
(S
(FPU) as well as a double-precision floating point unit that supports all Arm
precision and double-precision data-processing instructions and data types. It also
implements a full set of DSP instructions and a memory protection unit (MPU) that
enhances the application security. The MPU embedded in STM32H72x/73x/74x/75x
devices enables defining up to 16 MPU regions. A forward compatibility from the Cortex
M4 to the Cortex
the Cortex
The Cortex
dual- issue instructions. The branch prediction feature enables the resolution of branches to
anticipate the next branch and therefore decrease the number of cycles consumed by loop.
The dual-instruction feature enables the core to execute two instructions simultaneously in
order to increase instruction throughput.
Table 1. STM32H7 lines targeted by this application note
®
-M7 core features a high-performance floating point unit
®
®
®
-M7 enables the binaries, compiled for the Cortex®-M4, to run directly on
-M7.
-M7 features a 6/7-stage superscalar pipeline with a branch prediction and
(a)
microcontrollers.
®
single-
®
-
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
6/55 AN4891 Rev 4
AN4891 STM32H72x/73x/74x/75x system architecture overview
2.2 Cortex®-M7 system caches
The devices embed the Cortex®-M7 with a level1 cache (L1-cache), which is split into two
separate caches: the data cache (DCACHE) and the instruction cache (ICACHE)
implementing a Harvard architecture bringing the best performance. These caches enable
the Cortex
cache size for both instruction and data caches are given in Tabl e 2.
®
-M7 to reach a performance of zero wait state even at high frequencies. The
By default, the instruction cache and th
The Arm
• SCB_EnableIC
®
CMSIS library provides two functions that enable data and instruction caches:
ache() to enable the instruction cache
e data cache are both disabled.
• SCB_EnableDCache() to enable and invalidate the data cache
Additional information about enabling and invalidating the cache are given in
®
Arm
Cortex®-M7 Processor - Technical Reference Manual available from the
www.arm.com website.
More details on L1-cache usage in STM32H72x/73x/74x/75x devices are available in the
a
pplication note Level 1 cache on STM32F7 and STM32H7 Series (AN4839).
STM32H72x/73x 32 Kbytes 32 Kbytes
STM32H74x/75x 16 Kbytes 16 Kbytes
Table 2. STM32H72x/73x/74x/75x
Devices Instruction cache size Data cache size
2.3 Cortex®-M7 memory interfaces
The Cortex®-M7 has five interfaces: AXIM, ITCM, DTCM, AHBS, and AHBP. This section
describes each of them.
device cache sizes
2.3.1 AXI bus interface
AXI stands for advanced extensible interface. The Cortex®-M7 implements the AXIM
®
AMBA
Any access that is not for the TCM or the AHBP inter
cache controller if the cache is enabled. The user must take into account that the memory
regions are not all cacheable. Cacheability depends on memory type:
• Sha
• Only Normal memory type is cacheable.
Additional information and general rules about memory attributes and behaviors are
av
(PM0253).
In order to modify the type and the attribute of a memory region, the MPU can be used to
con
B bits in the MPU_RASR register.
4, a 64-bit wide interface for more instruction fetch and data load bandwidth.
red memory, Device or Strongly-ordered memory regions are not cacheable.
ailable in STM32F7 and STM32H7 Series Cortex
figure it to be a cacheable region. This is done by configuring the TEX field and S, C and
face, is handled by the appropriate
®
-M7 processor programming manual
AN4891 Rev 4 7/55
54
STM32H72x/73x/74x/75x system architecture overview AN4891
Tabl e 3 summarizes the memory region attributes after Cortex®-M7 reset.
Table 3. Cortex
®
-M7 default memory attributes after reset
Address range Region name Type Attributes
0x0000 0000-0x1FFF FFFF Code Normal
0x2000 0000-0x3FFF FFFF SRAM Normal
0x4000 0000-0x5FFF FFFF Peripheral Device Non-shareable Yes
0x6000 0000-0x7FFF FFFF RAM Normal
0x8000 0000-0x9FFF FFFF RAM Normal
0xA000 0000-0xBFFF FFFF External device Device Shareable Yes
0xC000 0000-0xDFFF FFFF External device Device Non-shareable Yes
0xE000 0000-0xE000 FFFF
0xE001 0000-0xFFFF FFFF Vendor system Device Non-shareable Yes
Private peripheral
bus
Strongly
ordered
Cacheable, Write-Through,
Allocate on read miss
Cacheable, Write-Back, Allo-
cate on read and write miss
Cacheable, Write-Back, Allo-
cate on read and write miss
Cacheable, Write-Through,
Allocate on read miss
-Yes
Execute
never?
No
No
No
No
In STM32H72x/73x/74x/75x, the 64-bit AXI master bus connects the core to the 64-bit AXI
bus matrix (D1 domain).
2.3.2 TCM bus interface
The TCM (tightly-coupled memory) is provided to connect the Cortex®-M7 to an internal
RAM. The TCM interface has a Harvard architecture with ITCM (instruction TCM) and
DTCM (data TCM) interfaces. The ITCM has one 64-bit memory interface while the DTCM
is split into two 32-bit wide ports, D0TCM and D1TCM.
®
The Cortex
to access the data (literal pool) located in the ITCM-RAM. The ITCM is accessed by the
Cortex
-M7 CPU uses the 64-bit ITCM bus for fetching instructions from the ITCM and
®
-M7 at CPU clock speed with zero wait state. The DTCM interface can also fetch
instructions.
In the STM32H72x/73x/74x/75x architecture, o
to memories connected to the ITCM and DTCM interfaces.
2.3.3 AHBS bus interface
The Cortex®-M7 AHBS (AHB slave) is a 32-bit wide interface that provides system access
to the ITCM, D1TCM, and D0TCM. However, in the STM32H72x/73x/74x/75x architecture
and apart Cortex
using only MDMA. The AHBS interface can be used when the core is in Sleep state,
therefore, MDMA transfers from/to TCM-RAMs can be performed in low-power modes. This
connection is represented by the paths colored in light pink in Figure 3.
®
-M7, AHBS allows data transfer from/to DTCM-RAM and ITCM-RAM
nly the CPU and the MDMA can have access
8/55 AN4891 Rev 4
AN4891 STM32H72x/73x/74x/75x system architecture overview
2.3.4 AHBP bus interface
The AHBP interface (AHB peripheral) is a single 32-bit wide interface that is dedicated to
®
the connection of the Cortex
-M7 to the peripherals. It is only used for data access.
Instruction fetches are never performed on this interface.
In the STM32H72x/73x/74x/75x a
rchitecture, this interface connects the Cortex®-M7 core to
the AHB peripherals connected to a 32-bit AHB bus matrix that is located in the D2 domain
(see Section 2.4). The targets of this bus are the
peripherals located in the D2 domain. This connectio
AHB1, AHB2, APB1, and APB2
n is represented by the bus colored in
dark green in Figure 2. The peripherals located in the D1 and D3 domains (see Section 2.4)
®
are seen by the Cortex
domain are seen by the Cortex
-M7 through the AXI bus while the peripherals located in the D2
®
-M7 through the AHBP bus.
2.4 STM32H72x/73x/74x/75x interconnect matrix
The STM32H72x/73x/74x/75x devices are the first STM32 microcontrollers that embed
more than one bus matrix, thus giving the best compromise between performance and
power consumption. It also allows efficient simultaneous operation of high-speed
peripherals and removes bus congestion when several masters are simultaneously active
(different masters located in separated bus matrices).
The STM32H72x/73x/74x/75x feature three separ
associated to a domain:
• 64-bit
AXI bus matrix (in the D1 domain): It has a high-performance capability and is
dedicated to operations requiring high speed. The high bandwidth peripherals are
connected to the AXI bus matrix.
• 32-bit AHB bus matrix (in the D2 domain): communication peripherals and timers are
connected to this bus matrix.
• 32-bit AHB bus matrix (in the D3 domain): reset, clock control, power management and
GPIOs are located in this domain.
ate bus matrices. Each bus matrix is
The maximum bus matrix frequency is half the ma
ximum CPU frequency. Only the Cortex®-
M7, the ITCM-RAM and the DTCM-RAM can run at the CPU frequency.
All bus matrices are connected together by means of inter-domain buses to enable a master
lo
cated in a given domain to access to a slave located in another domain, except for BDMA
master whose access is limited to resources located in the D3 domain.
Figure 1 and Figure 2 show the overall system architecture of the STM32H72x/73x/74x/75x
as well as the connections of the interconnect matrix.
AN4891 Rev 4 9/55
54
10/55 AN4891 Rev 4
MSv66817V2
5
ITCM-RAM
DTCM-RAM
AHBS
DTCM
AHBP
ITCM
AXIM
APB3
Flash
OTFDEC1
FMC
AHB3
APB1
SRAM1
AHB1
SRAM2
AHB2
APB2
DMA1_MEM
DMA1_PERIPH
GPV
ASIB6
ASIB5
ASIB4
ASIB3
ASIB2
AXI
AXIAXI
AHB
AXI
AXI
AXI
AXI
AXI
AXIAHB
AHB
APB
APB
AHB
D1-to-D2
AHB bus
DMA2_MEM
DMA2_PERIPH
AMIB6AMIB5AMIB2 AMIB3
7
4
2
1
SDMMC2
Ethernet
MAC
USB
HS1
DMA2
DMA1
SDMMC1 MDMA
DMA2D
LTDC
(1)
L1-Cache
Cortex
®
-M7
APB4
AHB4
SRAM4
Bckp SRAM
D2-to-D1 AHB bus
D2-to-D3 AHB bus
BDMA
64-bit bus (AXI) 32-bit bus AHB
Bus multiplexer
Inter-domain bus (32-bit
AHB)
AXI bus matrix (D1 domain)
AHB bus matrix (D2
domain)
AHB bus matrix (D3
domain)
64-bit AXI bus matrix
D1 Domain
32-bit AHB bus matrix
D2 Domain
32-bit AHB bus matrix
D3 Domain
D2-to-D1 AHB bus
D1-to-D3 AHB bus
AHBx pripherals
Internal memory
External interface
Masters
APBx pripherals
ITCM bus
DTCM bus
AHBS bus
AHBP bus
6
3
AXI
DTCM
ITCM
AHB
AHBP
AHBS
APB
Master
interfaces
Slave
interfaces
APB bus
AMIB7
AXI
SRAM
AXI
Shared
SRAM
OCTOSPI2
OCTOSPI1
OTFDEC2
AMIB1
AMIB4
AMIB8
n
The domain number
ASIB1
Figure 1. STM32H72x and STM32H73x system architecture
STM32H72x/73x/74x/75x system architecture overview AN4891
Figure 2. STM32H74x and STM32H75x system architecture
MSv44011V13
ITCM-RAM
DTCM-RAM
AHBS
DTCM
AHBP
ITCM
AXIM
APB3
Flash 1
Flash 2
(2)
QUADSPI
FMC
AHB3
APB1
SRAM1
AHB1
SRAM2
SRAM3
(1)
AHB2
APB2
DMA1_MEM
DMA1_PERIPH
GPV
ASIB6
ASIB5
ASIB4
ASIB3
ASIB2
ASIB1
AXI
AXIAXI
AHB
AXI
AXI
AXI
AXI
AXI
AXIAHB
AHB
APB
APB
AHB
D1-to-D2 AHB bus
DMA2_MEM
DMA2_PERIPH
L1-Cache
(1)
AMIB6
d
AMIB5
AMIB4
AMIB1
AMIB2
AMIB3
7
4
5
2
1
SDMMC2
Ethernet
MAC
USB
HS1
USB
HS2
DMA2
DMA1
SDMMC1 MDMA
DMA2D
LTDC
(1)
L1-Cache
Cortex
®
-M7
APB4
AHB4
SRAM4
Bckp SRAM
D2-to-D1 AHB bus
D2-to-D3 AHB bus
BDMA
64-bit bus (AXI) 32-bit bus AHB
Bus multiplexer
Inter-domain bus (32-bit AHB)
AXI bus matrix (D1 domain)
AHB bus matrix (D2 domain)
AHB bus matrix (D3 domain)
64-bit AXI bus matrix
D1 Domain
32-bit AHB bus matrix
D2 Domain
32-bit AHB bus matrix
D3 Domain
D2-to-D1 AHB bus
D1-to-D3 AHB bus
AHBx pripherals
Internal memory
External interface
Masters
APBx pripherals
ITCM bus
DTCM bus
AHBS bus
AHBP bus
6
3
AXI
DTCM
ITCM
AHB
AHBP
AHBS
APB
Master
interfaces
Slave
interfaces
APB bus
AMIB7
AXI
SRAM
n
The domain number
Note 1: Not available in
STM32H742xx devices
Note 2: Not available in
STM32H750xx devices
AN4891 STM32H72x/73x/74x/75x system architecture overview
AN4891 Rev 4 11/55
STM32H72x/73x/74x/75x system architecture overview AN4891
2.4.1 AXI bus matrix in the D1 domain
The AXI interconnect is based on the Arm® CoreLink™ NIC-400 Network Interconnect. It
has six initiator ports called ASIBs (AMBA slave interface blocks) where masters are
connected, and up to eight target ports called AMIBs (AMBA master interface blocks) where
slaves are connected.
The AXI bus matrix is located in the D1 domain.
It can run at up to half the maximum CPU
frequency. It is a 64-bit bus matrix that connects ASIBs and AMIBs and enables a number of
parallel access paths between the core AXI bus, masters buses and the slaves buses, thus
making possible concurrent accesses and efficient operation even when several high-speed
peripherals are running simultaneously. An internal arbiter resolves the conflicts and the bus
concurrency of masters on the bus matrix using a round-robin algorithm with QoS capability
(quality of service). Each master has programmable read channel and write channel
priorities, from 0 to 15, configured respectively in AXI_INIx_READ_QOS and
AXI_INIx_WRITE_QOS registers so that the higher the value, the higher the priority. If two
masters attempt to access the same slave at the same time, the one having the higher
priority transaction accesses to the given slave before the other master. If the two
transactions have the same QoS value, then a least-recently-used (LRU) priority scheme is
adopted. The QoS is configurable in the Global Programmer View (GPV) that contains
registers for configuring some parameters, such as the QoS level at each ASIB.
The QoS is useful for tasks such as graphics p
and of the DMA2D versus the Cortex
®
-M7 CPU.
rocessing to boost the priority of the LTDC
The AXI bus matrix interconnects:
• six
bus masters:
–the Cortex
®
-M7 AXI bus
– the D2-to-D1 AHB inter-domain, a 32-bit AHB bus that connects the D2 domain to
the D1 domain
– the SDMMC1 32-bit AHB bus
– the MDMA 64-bit AXI bus
– the LCD-TFT Controller 64-bit AXI bus (not available in STM32H742x devices)
– the Chrom-Art Accelerator (DMA2D) 64-bit AXI bus
• Up to eight bus slaves:
– the embedded Flash memory bank 1 on AXI bus
– up to 512-Kbytes of AXI SRAM memory accessed through the AXI bus
– AHB3 peripherals including the AHB-to-APB bridge, APB3 peripherals and the
D1-to-D3 AHB inter-domain
– the FMC memory interface on AXI bus accessed by 64 bits
– the D1-to-D2 inter-domain 32-bit AHB bus that connects the D1 domain to the D2
domain
– the Quad-SPI memory interface on AXI bus with 64-bit access (available only in
STM32H74x/75x)
– the embedded Flash memory bank 2 on AXI bus (available only in
STM32H74x/75x except for STM32H750x)
– SRAM shared between ITCM and AXI (available only in STM32H72x/73x)
– OCTOSPI1 memory interface on AXI bus accessed by 64 bits (available only in
STM32H72x)
12/55 AN4891 Rev 4
AN4891 STM32H72x/73x/74x/75x system architecture overview
– OCTOSPI2 memory interface on AXI bus accessed by 64 bits (available only in
STM32H72x)
– OTFDEC1/OCTOSPI1 memory interface on AXI bus with 64-bit access (available
only in STM32H73x)
– OTFDEC1/OCTOSPI2 memory interface on AXI bus with 64-bit access (available
only in STM32H73x)
The Cortex®-M7 has access to every resource available in the system. The AHB1
peripherals are accessed by the CPU through the AHBP bus and not through the AXI bus
and D1-to-D2 AHB inter-domain bus (refer to Figure 2). The MDMA has access to all
resources available in the
system except to the AHB2 resources located in the D2 domain.
2.4.2 AHB bus matrices in the D2 and D3 domains
The AHB bus matrices are located in the D2 and D3 domains. Their maximum frequency is
half the maximum CPU frequency. They ensure and arbitrate concurrent accesses from
multiple masters to multiple slaves. This enables efficient simultaneous operation of highspeed peripherals and memories.
An internal arbiter resolves the conflicts an
d the bus concurrency of masters on the bus
matrix using a round-robin algorithm.
The AHB bus matrix in the D2 domain is dedicated to communication peripherals and
timers.
It interconnects the following buses:
• Up to
ten bus masters:
– the D1-to-D2 AHB inter-domain that connects the D1 domain to the D2 domain
–the Cortex
®
-M7 AHB peripherals bus that makes the CPU to access AHB1 and
AHB2 peripherals on D2 domain
– the DMA1 memory AHB bus
– the DMA1 peripheral AHB bus
– the DMA2 memory AHB bus
– the DMA2 peripheral AHB bus
– the Ethernet DMA AHB bus
– the SDMMC2 DMA AHB bus
– the USB OTG high-speed 1 DMA AHB bus
– the USB OTG high-speed 2 DMA AHB bus (available only in STM32H74x/75x)
• Up to nine bus slaves:
– internal SRAM1 up to 128 Kbytes with 32-bit AHB access
– internal SRAM2 up to 128 Kbytes with 32-bit AHB access
– internal SRAM3 of 32 Kbytes with 32-bit AHB access (available in
STM32H74x/75x except STM32H742x)
– the AHB1 peripherals bus including the AHB to APB bridge that makes
®
Cortex
-M7 to access APB1 and APB2 peripherals
– the AHB2 peripherals bus that connect speed peripherals
– the APB1 peripherals bus that enable DMA1 and DMA2 to access to APB1
peripherals
– the APB2 peripherals bus that enable DMA1 and DMA2 to access to APB2
peripherals
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STM32H72x/73x/74x/75x system architecture overview AN4891
– the D2-to-D3 AHB inter-domain that connects the D2 domain to the D3 domain
– the D2-to-D1 AHB inter-domain that connects the D2 domain to the D1 domain
The AHB bus matrix in the D3 domain is dedicated to reset, clock control, power
management and GPIOs. It interconnects:
• three initiators:
the D1-to-D3 AHB inter-domain that connects the D1 domain to the D3 domain
–
– the D2-to-D3 AHB inter-domain that connects the D2 domain to the D3 domain
– the BDMA memory AHB bus
• two bus slaves:
– the AHB4 peripherals including the AHB to APB bridge (connection 6 in Figure 2)
and APB4 peripherals
– internal SRAM4 up to 64 Kbytes and the Backup SRAM of 4 Kbytes that shares
the same AHB bus
2.4.3 Inter-domain buses
D1-to-D2 AHB inter-domain bus
This 32-bit AHB bus connects the AXI bus matrix located in the D1 domain to the AHB bus
matrix located in the D2 domain. It allows some masters in the D1 domain to access
resources (memories and peripherals) in the D2 domain.
®
Only the masters, Cortex
access to the following resources located in the D2 domain: SRAM1, SRAM2, SRAM3 (for
STM32H74x/75x), AHB1, APB1 and APB2 peripherals.
-M7, MDMA and DMA2D located in the D1 domain can have
The SDMMC1 and LTDC have no access to the re
So if, for example, SDMMC1 or LTDC needs some
MDMA or DMA2D to copy data from SRAM1 to AXI SRAM which is accessible by SDMMC1
and LTDC.
sources located in the D2 domain.
data from SRAM1, the user can use
D2-to-D1 AHB inter-domain bus
This 32-bit AHB bus connects the D2 domain to the AXI bus matrix located in the D1
domain. It enables bus masters in the D2 domain to access resources in the D1 domain and
indirectly, via the D1-to-D3 AHB inter-domain bus, the resources located in the D3 domain.
As a result, all the masters, DMA1, DMA2, Ethernet, SDMMC2 and a USB OTG_HS
troller located in the D2 domain can have access to the internal memories in the D1
con
domain (except TCM-RAMs), to external memories, and for STM32H74x/75x to the AHB3
and APB3 peripherals located in the D1 domain.
D1-to-D3 AHB inter-domain bus
This 32-bit AHB bus connects the D1 domain to the D3 domain AHB bus matrix. It enables
masters in the D1 domain and indirectly some masters in the D2 domain to access
resources located in the D3 domain.
®
Only the two masters, Cortex
resources located in the D3 domain, that is SRAM4, Backup SRAM, AHB4 and APB4
peripherals. SDMMC1, LTDC and DMA2D cannot access these resources.
-M7 and MDMA in the D1 domain, have access to the
14/55 AN4891 Rev 4
AN4891 STM32H72x/73x/74x/75x system architecture overview
If SDMMC1, LTDC and DMA2D need some data, for example, from SRAM4, MDMA can be
used to transfer them from SRAM4 to AXI SRAM.
For STM32H74x/75x, the D1-to-D3 AHB inter-domain bus also makes possible for some
masters located in the D2 domain to have access to the resources located in the D3
domain. Note that some masters in D2 domain, that is Ethernet and the USB OTG_HS, do
not have direct access to the resources located in D3 through the D2-to-D3 AHB interdomain bus. The access is performed first through the D2-to-D1 AHB and then through the
D1-to-D3 AHB inter-domain buses (refer to the USBHS2 access to SRAM4 path highlighted
in yellow in Figure 3).
D2-to-D3 AHB inter-domain bus
This 32-bit AHB bus connects the D2 domain to the D3 domain AHB bus matrix. It enables
masters located in the D2 domain to access resources in the D3 domain.
DMA1, DMA2 and SDMMC2 located in the D2 domain have direct access to the resources
lo
cated in the D3 domain through the D2-to-D3 AHB inter-domain bus. For
STM32H74x/75x, the access of the other masters is performed first through the D2-to-D1
AHB and then through the D1-to-D3 AHB inter-domain buses. For STM32H72x/73x,
Ethernet and USB OTG_HS peripherals do not have access to D3 resources.
Note that the basic-DMA controller
(BDMA) located in the D3 domain has only access to the
resources located in that domain including Backup SRAM.
Tabl e 4 summarizes the different possible interconne
combinations of the different masters to the dif
ferent slaves located in different domains.The
ctions and the different access path
numbering from 1 to 7 in Table 4 refers to the numbers indicated
refers to a given domain.
in Figure 2. Each number
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STM32H72x/73x/74x/75x system architecture overview AN4891
Table 4. Bus-master-to-bus-slave possible interconnections in
STM32H72x/73x/74x/75x
DMA1 - PERIPH
(1)
(5)
DMA2 - MEM
DMA2 - PERIPH
Eth. MAC - AHB
SDMMC2 - AHB
USBHS1 - AHB
USBHS2 - AHB
Bus master / type
-M7 - AHBP
®
Cortex
-M7 - ITCM
-M7 -DTCM
®
®
Cortex
Cortex
SDMMC1
MDMA - AXI
MDMA - AHBS
-M7 - AXIM
®
Cortex
(2)
DMA2D
LTD C
DMA1 - MEM
BDMA - AHB
Bus slave / type
(1)
Interconnect path and type
(3)
ITCM --D ---7-------------
DTCM ---
AHB3 peripherals
APB3 peripherals
Flash bank 1
Flash bank 2
(4)
AXI SRAM
QUADSPI
RAM shared between
ITCM and AXI
OCTOSPI
(5)
(6)
(6)
FMC
SRAM 1
SRAM 2
(7)
SRAM 3
AHB1 peripherals 12
APB1 peripherals 125
AHB2 peripherals -
APB2 peripherals 125
AHB4 peripherals
1----1---2121 - 21 21 - 21 21 21 21 -
14 - - - - 14 - - - 214 214 - 214 214 - 214 214 214 214 -
1 ---1 1 - 1 1 21 21 - 21 21 - 21 21 21 21 -
1 ---1 1 - 1 1 21 21 - 21 21 - 21 21 21 21 -
1 ---1 1 - 1 1 21 21 - 21 21 - 21 21 21 21 -
1 ---1 1 - 1 1 21 21 - 21 21 - 21 21 21 21 -
1 ---1 1 - 1 1 21 21 - 21 21 - 21 21 21 21 -
1 ---1 1 - 1 1 21 21 - 21 21 - 21 21 21 21 -
1 ---1 1 - 1 1 21 21 - 21 21 - 21 21 21 21 -
12----12 - 12 - 2 2-2 2-2 2 2 2-
12----12 - 12 - 2 2-2 2-2 2 2 2-
12----12 - 12 - 2 2-2 2-2 2 2 2-
2---12 - 12 - 2 2-22------
25 - - - 125 - 125 - 25 25 22525 2-----
2-------22-22------
25 - - - 125 - 125 - 25 25 22525 2-----
13----13---2323 - 23 23 -
D --7-------------
213
(8)23(8)
213
(8)
213 3
APB4 peripherals
SRAM4
Backup RAM
136 - - - - 136 - - - 236 236 - 236 236 -
13----13 - - - 23 23 - 23 23 -
13----13 - - - 23 23 - 23 23 -
1. Bold font type denotes 64-bit bus, plain type denotes 32-bit bus.
2. LTDC is not available on STM32H742x devices.
16/55 AN4891 Rev 4
213
(8)23(8)
213
(8)23(8)
213
(8)23(8)
213
(8)
213
(8)
213
(8)
213 36
213 3
213 3
AN4891 STM32H72x/73x/74x/75x system architecture overview
3. Cells in the table body indicate access possibility, utility, path and type:
Access possibility and utility:
Any figure = access possible, “-” = access not possible, gray shading = access useful/usable
Access path
D = direct, 1 = via AXI bus matrix, 2 = via AHB bus matrix in D2, 3 = via AHB bus matrix in D3, 4 = via AHB/APB bridge in
D1, 5 = via AHB/APB bridge in D2, 6 = via AHB/APB bridge in D3, 7 = via AHBS bus of Cortex
Multi-digit numbers = interconnect path goes through more than one matrix or/and bridge, in the order of the digits.
Access type:
Plain = 32-bit, Italic=32-bit on bus master end / 64-bit on bus slave end, Bold=64-bit
4. Flash bank 2 is available only in STM32H74x/75x except for STM32H750x devices.
5. QUADSPI and USBHS2 are available only in STM32H74x/75x devices.
6. Available only in STM32H72x/73x.
7. SRAM3 is available only in STM32H74x/75x except STM32H742x.
8. Connection available only in STM32H74x/75x.
:
®
-M7,
Figure 3 shows some paths (ten examples of master access paths) used by some masters
located in the D1 and D2 domains to access to resources located in the D1, D2, and D3
omains. This example is based on STM32H74x/75x. However, the paths are the same for
d
STM32H72x/73x except for the USBHS2 access to SRAM4 path.
AN4891 Rev 4 17/55
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