STM32H742xI/G STM32H743xI/G Errata sheet
STM32H742xI/G and STM32H743xI/G device limitations
Applicability
This document applies to the part numbers of STM32H742/743xI/G devices listed in Table 1 and their variants shown in Table 2.
Section 1 gives a summary and Section 2 a description of workarounds for device limitations, with respect to the device datasheet and reference manual RM0433.
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Table 1. Device summary |
Reference |
Part numbers |
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STM32H742VI, STM32H742ZI, STM32H742II, STM32H742BI, |
STM32H742xI/G |
STM32H742XI, STM32H742AI, STM32H742VG, STM32H742ZG, |
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STM32H742IG, STM32H742BG, STM32H742XG, STM32H742AG |
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STM32H743VI, STM32H743ZI, STM32H743II, STM32H743BI, |
STM32H743xI/G |
STM32H743XI, STM32H743AI, STM32H743VG, STM32H743ZG, |
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STM32H743IG, STM32H743BG, STM32H743XG, STM32H743AG |
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Reference |
Silicon revision codes |
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Device marking(1) |
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REV_ID(2) |
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STM32H742xI/G |
V |
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0x2003 |
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STM32H743xI/G |
Y |
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0x1003 |
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STM32H743xI/G |
X |
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0x2001 |
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STM32H743xI/G |
V |
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0x2003 |
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1.Refer to the device datasheet for how to identify this code on different types of package.
2.REV_ID[15:0] bit field of DBGMCU_IDC register. Refer to the reference manual.
February 2021 |
ES0392 Rev 8 |
1/44 |
www.st.com
Contents |
STM32H742/743xI/G |
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Contents
1 |
Summary of device limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 6 |
2 |
Description of device limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
10 |
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2.1 Arm® 32-bit Cortex®-M7 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
10 |
2.1.1Cortex®-M7 data corruption when using Data cache configured in
write-through . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1.2 Cortex®-M7 FPU interrupt not present on NVIC line 81 . . . . . . . . . . . . 11
2.2 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.2.1 Timer system breaks do not work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.2Clock recovery system synchronization with USB SOF does not work . 11
2.2.3 SysTick external clock is not HCLK/8 . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.4Option byte loading can be done with the user wait-state configuration 12
2.2.5Flash BusFault address register may not be valid when
an ECC double error occurs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.6 Flash ECC address register may not be updated . . . . . . . . . . . . . . . . . 12 2.2.7 PCROP-protected areas in Flash memory may be unprotected . . . . . . 13
2.2.8Flash memory bank swapping might impact embedded
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Flash memory interface behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
13 |
2.2.9 |
Reading from AXI SRAM may lead to data read corruption . . . . . . . . . |
13 |
2.2.10 |
Clock switching does not work when LSE failure is detected by CSS . . |
13 |
2.2.11RTC stopped when a system reset occurs while the LSI is used
as a clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
14 |
2.2.12 USB OTG_FS PHY drive limit on DP/DM pins . . . . . . . . . . . . . . . . . . . |
14 |
2.2.13Unexpected leakage current on I/Os when VIN higher that VDD . . . . . 14
2.2.14 LSE oscillator driving capability selection bits are swapped . . . . . . . . . 14 2.2.15 HRTIM internal synchronization does not work . . . . . . . . . . . . . . . . . . . 15
2.2.16Device stalled when two consecutive level regressions occur
without accessing from/to backup SRAM . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.17 Invalid Flash memory CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.18GPIO assigned to DAC cannot be used in output mode when
the DAC output is connected to on-chip peripheral . . . . . . . . . . . . . . . . 15 2.2.19 Unstable LSI when it clocks RTC or CSS on LSE . . . . . . . . . . . . . . . . . 16
2.2.20480 MHz maximum CPU frequency not available on silicon revision Y . 16
2.2.21VDDLDO is not available on TFBGA100 package
on devices revision Y and V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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STM32H742/743xI/G |
Contents |
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2.2.22WWDG not functional when VDD is lower than 2.7 V and VOS0
or VOS1 voltage level is selected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2.23A tamper event does not erase the backup RAM when the
backup RAM clock is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.24 LSE CSS parasitic detection even when disabled . . . . . . . . . . . . . . . . . 17
2.3 FMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.1 Dummy read cycles inserted when reading synchronous memories . . . 18 2.3.2 Wrong data read from a busy NAND Flash memory . . . . . . . . . . . . . . . 18 2.3.3 Missed clocks with continuous clock feature enabled . . . . . . . . . . . . . . 18
2.4 QUADSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.4.1 First nibble of data is not written after a dummy phase . . . . . . . . . . . . . 19 2.4.2 QUADSPI hangs when QUADSPI_CCR is cleared . . . . . . . . . . . . . . . . 19
2.4.3QUADSPI cannot be used in Indirect read mode when only
data phase is activated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.4.4 Memory-mapped read of last memory byte fails . . . . . . . . . . . . . . . . . . 20
2.5 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.5.1 Conversion overlap may impact the ADC accuracy . . . . . . . . . . . . . . . . 20 2.5.2 ADC resolution limited by LSE activity . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.5.3 ADC maximum sampling rate when VDDA is lower than 2 V . . . . . . . . 21 2.5.4 ADC maximum resolution when VDDA is higher than 3.3 V . . . . . . . . . 21 2.5.5 First ADC injected conversion in a sequence may be corrupted . . . . . . 21
2.5.6Writing the ADC_JSQR register when JADCSTART = 1 and JQDIS = 1
may lead to incorrect behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.5.7 Conversion may be triggered by context queue register update . . . . . . 22
2.5.8Updated conversion sequence may be trigged by
context queue update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.6 VREFBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.6.1 |
Overshoot on VREFBUF output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
23 |
2.6.2 |
VREFBUF Hold mode cannot be used . . . . . . . . . . . . . . . . . . . . . . . . . |
23 |
2.7 OPAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.7.1 OPAMP high-speed mode must not be used . . . . . . . . . . . . . . . . . . . . . 23
2.8 LCD-TFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.8.1Device stalled when accessing LTDC registers while pixel clock
is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.9 TIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.9.1One-pulse mode trigger not detected in master-slave reset +
trigger configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.9.2 Consecutive compare event missed in specific conditions . . . . . . . . . . 24
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STM32H742/743xI/G |
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2.9.3 |
Output compare clear not working with external counter reset . . . . . . |
. 25 |
2.10 |
LPTIM . |
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26 |
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2.10.1 |
MCU may remain stuck in LPTIM interrupt when entering Stop mode |
. 26 |
2.11 |
RTC . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
26 |
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2.11.1 |
RTC calendar registers are not locked properly . . . . . . . . . . . . . . . . . |
. 26 |
2.12 |
I2C . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
27 |
2.12.110-bit master mode: new transfer cannot be launched if first part
of the address is not acknowledged by the slave . . . . . . . . . . . . . . . . . |
27 |
2.12.2Wrong behavior in Stop mode when wakeup from Stop
mode is disabled in I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.12.3 Wrong data sampling when data setup time (tSU;DAT) is shorter than |
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one I2C kernel clock period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
28 |
2.12.4 Spurious bus error detection in Master mode . . . . . . . . . . . . . . . . . . . . |
28 |
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2.12.5 |
Last-received byte loss in Reload mode . . . . . . . . . . . . . . . . . . . . . . . . |
29 |
2.12.6 |
Spurious master transfer upon own slave address match . . . . . . . . . . . |
30 |
2.12.7START bit is cleared upon setting ADDRCF, not upon address match . 31
2.13 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.13.1Underrun flag is set when the USART is used in SPI Slave
receive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.13.2 DMA stream locked when transferring data to/from USART/UART . . . . 31
2.14 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.14.1 Spurious DMA Rx transaction after simplex Tx traffic . . . . . . . . . . . . . . 32
2.14.2Master data transfer stall at system clock much faster than SCK . . . . . 32
2.14.3 Corrupted CRC return at non-zero UDRDET setting . . . . . . . . . . . . . . . 32 2.14.4 TXP interrupt occurring while SPI/I2Sdisabled . . . . . . . . . . . . . . . . . . . 32
2.15 SDMMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.15.1Busy not detected when a write operation suspended
during busy phase resumes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.15.2Wrong data line 2 generation between two blocks
during DDR transfer with Read wait mode enabled . . . . . . . . . . . . . . . . 33
2.15.3Unwanted overrun detection when an AHB error is reported
whereas all bytes have been received . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.15.4Consecutive multiple block transfers can induce incorrect data length . 34
2.15.5 Clock stop reported during Read wait mode sequence . . . . . . . . . . . . . 34
2.16 FDCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.16.1 Writing FDCAN_TTTS during initialization corrupts FDCAN_TTTMC . . 34
2.16.2Wrong data may be read from Message RAM by the CPU
when using two FDCANs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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2.16.3Mis-synchronization in Edge filtering mode when the falling edge at FDCAN_Rx input pin coincides with the end of the
integration phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.16.4Tx FIFO messages inverted when both Tx buffer and FIFO are used and the messages in the Tx buffer have higher priority than
in the Tx FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.17 USB OTG_HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.17.1 Possible drift of USB PHY pull-up resistor . . . . . . . . . . . . . . . . . . . . . . . 36
2.18 ETH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.18.1 Incorrect L4 inverse filtering results for corrupted packets . . . . . . . . . . |
37 |
2.18.2Rx DMA may fail to recover upon DMA restart following a bus error,
with Rx timestamping enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.18.3Tx DMA may halt while fetching TSO header under specific conditions 37
2.18.4 Spurious receive watchdog timeout interrupt . . . . . . . . . . . . . . . . . . . . . |
38 |
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2.18.5 |
Incorrect flexible PPS output interval under specific conditions . . . . . . |
38 |
2.18.6 Packets dropped in RMII 10Mbps mode due to fake dribble |
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and CRC error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
38 |
2.18.7 |
ARP offload function not effective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
39 |
2.19 HDMI-CEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.19.1Unexpected switch to Receive mode without automatic transmission
retry and notification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.19.2 CEC header not received due to unjustified Rx-Overrun detection . . . . 40
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Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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Summary of device limitations |
STM32H742/743xI/G |
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The following table gives a quick references to all documented device limitations of STM32H742/743xI/G and their status:
A = limitation present, workaround available
N = limitation present, no workaround available
P = limitation present, partial workaround available “-” = limitation absent
Applicability of a workaround may depend on specific conditions of target application. Adoption of a workaround may cause restrictions to target application. Workaround for a limitation is deemed partial if it only reduces the rate of occurrence and/or consequences of the limitation, or if it is fully effective for only a subset of instances on the device or in only a subset of operating modes, of the function concerned.
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Status |
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Function |
Section |
Limitation |
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Rev. |
Rev. |
Rev. |
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Y |
X(1) |
V |
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Arm® 32- |
2.1.1 |
Cortex®-M7 data corruption when using Data cache configured in |
A |
A |
A |
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bit |
write-through |
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Cortex®- |
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2.1.2 |
Cortex®-M7 FPU interrupt not present on NVIC line 81 |
A |
A |
A |
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M7 core |
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2.2.1 |
Timer system breaks do not work |
N |
- |
- |
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2.2.2 |
Clock recovery system synchronization with USB SOF does not work |
A |
- |
- |
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2.2.3 |
SysTick external clock is not HCLK/8 |
A |
- |
- |
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2.2.4 |
Option byte loading can be done with the user wait-state configuration |
A |
- |
- |
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2.2.5 |
Flash BusFault address register may not be valid when an ECC double |
A |
- |
- |
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error occurs |
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2.2.6 |
Flash ECC address register may not be updated |
N |
- |
- |
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2.2.7 |
PCROP-protected areas in Flash memory may be unprotected |
A |
- |
- |
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System |
2.2.8 |
Flash memory bank swapping might impact embedded Flash memory |
N |
- |
- |
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interface behavior |
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2.2.9 |
Reading from AXI SRAM may lead to data read corruption |
A |
- |
- |
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2.2.10 |
Clock switching does not work when LSE failure is detected by CSS |
A |
- |
- |
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2.2.11 |
RTC stopped when a system reset occurs while the LSI is used as a |
A |
- |
- |
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clock source |
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2.2.12 |
USB OTG_FS PHY drive limit on DP/DM pins |
N |
- |
- |
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2.2.13 |
Unexpected leakage current on I/Os when VIN higher that VDD |
A |
- |
- |
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2.2.14 |
LSE oscillator driving capability selection bits are swapped |
A |
- |
- |
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2.2.15 |
HRTIM internal synchronization does not work |
N |
- |
- |
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Summary of device limitations |
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Table 3. Summary of device limitations (continued) |
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Status |
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Function |
Section |
Limitation |
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Rev. |
Rev. |
Rev. |
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Y |
X(1) |
V |
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2.2.16 |
Device stalled when two consecutive level regressions occur without |
- |
A |
A |
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accessing from/to backup SRAM |
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2.2.17 |
Invalid Flash memory CRC |
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P |
- |
- |
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2.2.18 |
GPIO assigned to DAC cannot be used in output mode when the DAC |
N |
N |
N |
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output is connected to on-chip peripheral |
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2.2.19 |
Unstable LSI when it clocks RTC or CSS on LSE |
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A |
A |
A |
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System |
2.2.20 |
480 MHz maximum CPU frequency not available on silicon revision Y |
P |
P |
P |
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(continued) |
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2.2.21 |
VDDLDO is not available on TFBGA100 package on devices revision Y |
N |
N |
N |
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and V |
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2.2.22 |
WWDG not functional when VDD is lower than 2.7 V and VOS0 or |
N |
N |
N |
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VOS1 voltage level is selected |
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2.2.23 |
A tamper event does not erase the backup RAM when the backup RAM |
N |
N |
N |
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clock is disabled |
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2.2.24 |
LSE CSS parasitic detection even when disabled |
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N |
N |
N |
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2.3.1 |
Dummy read cycles inserted when reading synchronous memories |
N |
N |
N |
||
|
|
|
|
|
|
|
|
FMC |
2.3.2 |
Wrong data read from a busy NAND Flash memory |
|
A |
A |
A |
|
|
|
|
|
|
|
|
|
|
2.3.3 |
Missed clocks with continuous clock feature enabled |
|
A |
- |
- |
|
|
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|
|
|
|
|
|
2.4.1 |
First nibble of data is not written after a dummy phase |
|
A |
- |
- |
|
|
|
|
|
|
|
|
|
QUADSPI |
2.4.2 |
QUADSPI hangs when QUADSPI_CCR is cleared |
|
A |
A |
A |
|
|
|
|
|
|
|
||
|
2.4.3 |
QUADSPI cannot be used in Indirect read mode when only data |
A |
A |
A |
||
|
phase is activated |
|
|||||
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||
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2.5.1 |
Conversion overlap may impact the ADC accuracy |
|
A |
- |
- |
|
|
|
|
|
|
|
|
|
|
2.5.2 |
ADC resolution limited by LSE activity |
|
A |
- |
- |
|
|
|
|
|
|
|
||
|
2.5.3 |
ADC maximum sampling rate when VDDA is lower than 2 V |
A |
- |
- |
||
|
|
|
|
|
|
||
|
2.5.4 |
ADC maximum resolution when VDDA is higher than 3.3 V |
A |
- |
- |
||
ADC |
|
|
|
|
|
|
|
2.5.5 |
First ADC injected conversion in a sequence may be corrupted |
A |
- |
- |
|||
|
|||||||
|
|
|
|
|
|
||
|
2.5.6 |
Writing the ADC_JSQR register when JADCSTART = 1 and JQDIS = 1 |
A |
- |
- |
||
|
may lead to incorrect behavior |
|
|||||
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|
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||
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||
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2.5.7 |
Conversion may be triggered by context queue register update |
A |
A |
A |
||
|
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||
|
2.5.8 |
Updated conversion sequence may be trigged by context queue update |
A |
A |
A |
||
|
|
|
|
|
|
|
|
VREFBUF |
2.6.1 |
Overshoot on VREFBUF output |
|
A |
A |
A |
|
|
|
|
|
|
|
||
2.6.2 |
VREFBUF Hold mode cannot be used |
|
N |
N |
N |
||
|
|
||||||
|
|
|
|
|
|
|
|
OPAMP |
2.7.1 |
OPAMP high-speed mode must not be used |
|
N |
- |
- |
|
|
|
|
|
|
|
||
LCD- |
2.8.1 |
Device stalled when accessing LTDC registers while pixel clock is |
A |
A |
A |
||
TFT(2) |
disabled |
|
|||||
|
|
|
|
|
ES0392 Rev 8 |
7/44 |
Summary of device limitations |
STM32H742/743xI/G |
||||||
|
|
|
|
|
|
||
|
|
Table 3. Summary of device limitations (continued) |
|
|
|
||
|
|
|
|
|
Status |
|
|
Function |
Section |
Limitation |
|
|
|
|
|
|
Rev. |
Rev. |
Rev. |
||||
|
|
|
|
||||
|
|
|
|
Y |
X(1) |
V |
|
|
2.9.1 |
One-pulse mode trigger not detected in master-slave reset + |
trigger |
P |
P |
P |
|
|
configuration |
|
|||||
TIM |
|
|
|
|
|
||
|
|
|
|
|
|
||
2.9.2 |
Consecutive compare event missed in specific conditions |
|
N |
N |
N |
||
|
|
||||||
|
|
|
|
|
|
|
|
|
2.9.2 |
Output compare clear not working with external counter reset |
|
P |
P |
P |
|
|
|
|
|
|
|
||
LPTIM |
2.10.1 |
MCU may remain stuck in LPTIM interrupt when entering Stop mode |
A |
- |
- |
||
|
|
|
|
|
|
|
|
RTC |
2.11.1 |
RTC calendar registers are not locked properly |
|
A |
- |
- |
|
|
|
|
|
|
|
||
|
2.12.1 |
10-bit master mode: new transfer cannot be launched if first part of the |
A |
A |
A |
||
|
address is not acknowledged by the slave |
|
|||||
|
|
|
|
|
|
||
|
|
|
|
|
|
||
|
2.12.2 |
Wrong behavior in Stop mode when wakeup from Stop mode is |
A |
A |
A |
||
|
disabled in I2C |
|
|||||
|
|
|
|
|
|
||
|
|
|
|
|
|
||
I2C |
2.12.3 |
Wrong data sampling when data setup time (tSU;DAT) is shorter than |
P |
- |
- |
||
|
one I2C kernel clock period |
|
|
|
|
||
|
2.12.4 |
Spurious bus error detection in Master mode |
|
A |
A |
A |
|
|
|
|
|
|
|
|
|
|
2.12.5 |
Last-received byte loss in Reload mode |
|
P |
- |
- |
|
|
|
|
|
|
|
|
|
|
2.12.6 |
Spurious master transfer upon own slave address match |
|
P |
P |
P |
|
|
|
|
|
|
|
||
|
2.12.7 |
START bit is cleared upon setting ADDRCF, not upon address match |
P |
P |
P |
||
|
|
|
|
|
|
||
|
2.13.1 |
Underrun flag is set when the USART is used in SPI Slave receive |
A |
A |
A |
||
USART |
mode |
|
|||||
|
|
|
|
|
|||
|
|
|
|
|
|
||
|
2.13.2 |
DMA stream locked when transferring data to/from USART/UART |
- |
A |
A |
||
|
|
|
|
|
|
|
|
|
2.14.1 |
Spurious DMA Rx transaction after simplex Tx traffic |
|
A |
- |
- |
|
|
|
|
|
|
|
||
SPI |
2.14.2 |
Master data transfer stall at system clock much faster than SCK |
A |
A |
A |
||
|
|
|
|
|
|
||
2.14.3 |
Corrupted CRC return at non-zero UDRDET setting |
|
P |
P |
P |
||
|
|
||||||
|
|
|
|
|
|
|
|
|
2.14.4 |
TXP interrupt occurring while SPI/I2Sdisabled |
|
A |
A |
A |
|
|
|
|
|
|
|
||
|
2.15.1 |
Busy not detected when a write operation suspended during busy |
A |
- |
- |
||
|
phase resumes |
|
|||||
|
|
|
|
|
|
||
|
|
|
|
|
|
||
|
2.15.2 |
Wrong data line 2 generation between two blocks during DDR transfer |
A |
- |
- |
||
|
with Read wait mode enabled |
|
|||||
SDMMC |
|
|
|
|
|
||
|
|
|
|
|
|
||
2.15.3 |
Unwanted overrun detection when an AHB error is reported whereas all |
A |
- |
- |
|||
|
|||||||
|
bytes have been received |
|
|||||
|
|
|
|
|
|
||
|
|
|
|
|
|
||
|
2.15.4 |
Consecutive multiple block transfers can induce incorrect data length |
A |
- |
- |
||
|
|
|
|
|
|
|
|
|
2.15.5 |
Clock stop reported during Read wait mode sequence |
|
A |
- |
- |
|
|
|
|
|
|
|
|
8/44 |
ES0392 Rev 8 |
STM32H742/743xI/G |
Summary of device limitations |
|||||
|
|
|
|
|
|
|
|
|
Table 3. Summary of device limitations (continued) |
|
|
|
|
|
|
|
|
|
Status |
|
Function |
Section |
Limitation |
|
|
|
|
|
Rev. |
Rev. |
Rev. |
|||
|
|
|
|
|||
|
|
|
|
Y |
X(1) |
V |
|
2.16.1 |
Writing FDCAN_TTTS during initialization corrupts FDCAN_TTTMC |
A |
A |
A |
|
|
|
|
|
|
|
|
|
2.16.2 |
Wrong data may be read from Message RAM by the CPU when using |
A |
- |
- |
|
|
two FDCANs |
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
FDCAN |
2.16.3 |
Mis-synchronization in Edge filtering mode when the falling edge at |
A |
A |
A |
|
|
FDCAN_Rx input pin coincides with the end of the integration phase |
|||||
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
Tx FIFO messages inverted when both Tx buffer and FIFO are used |
|
|
|
|
|
2.16.4 |
and the messages in the Tx buffer have higher priority than in the Tx |
A |
A |
A |
|
|
|
FIFO |
|
|
|
|
|
|
|
|
|
|
|
USB |
2.17.1 |
Possible drift of USB PHY pull-up resistor |
|
P |
- |
- |
OTG_HS |
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2.18.1 |
Incorrect L4 inverse filtering results for corrupted packets |
N |
N |
N |
|
|
|
|
|
|
|
|
|
2.18.2 |
Rx DMA may fail to recover upon DMA restart following a bus error, |
P |
P |
P |
|
|
with Rx timestamping enabled |
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2.18.3 |
Tx DMA may halt while fetching TSO header under specific conditions |
A |
A |
A |
|
|
|
|
|
|
|
|
ETH |
2.18.4 |
Spurious receive watchdog timeout interrupt |
|
A |
A |
A |
|
|
|
|
|
|
|
|
2.18.5 |
Incorrect flexible PPS output interval under specific conditions |
A |
A |
A |
|
|
|
|
|
|
|
|
|
2.18.6 |
Packets dropped in RMII 10Mbps mode due to fake dribble and CRC |
A |
A |
A |
|
|
error |
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2.18.7 |
ARP offload function not effective |
|
A |
A |
A |
|
|
|
|
|
|
|
|
2.19.1 |
Unexpected switch to Receive mode without automatic transmission |
A |
A |
A |
|
HDMI-CEC |
retry and notification |
|
||||
|
|
|
|
|
||
|
|
|
|
|
|
|
|
2.19.2 |
CEC header not received due to unjustified Rx-Overrun detection |
A |
A |
A |
|
|
|
|
|
|
|
|
1.Engineering samples only.
2.This limitation applies only to STM32H743xI/G microcontrollers.
ES0392 Rev 8 |
9/44 |
Description of device limitations |
STM32H742/743xI/G |
|
|
The following sections describe device limitations of the applicable Arm(a) core devices and provide workarounds if available. They are grouped by device functions.
2.1Arm® 32-bit Cortex®-M7 core
Errata notice for the Arm® processor Cortex®-M7 core revision r1p1 is available from http://infocenter.arm.com.
2.1.1Cortex®-M7 data corruption when using Data cache configured in write-through
Description
This limitation is registered under Arm® ID number 1259864 and classified into “Category A”.
If a particular sequence of stores and loads is performed to write-through memory, and some timing-based internal conditions are met, then a load might not get the last data stored to that address.
This erratum can only occur if the loads and stores are to write-through memory. This could be due to any of the following:
•The MPU has been programmed to set this address as write-through.
•The default memory map is being used and this address is write-through in that map.
•The memory is cacheable, and the CM7_CACR.FORCEWT bit is set.
•The memory is cacheable, shared, and the CM7_CACR.SIWT bit is set.
The following sequence is required for this erratum to occur:
1.The address of interest must be in the cache.
2.A write-through store to the same doubleword as the address of interest.
3.One of the following:
–A linefill is started (to a different cacheline to the address of interest) that allocates to the same set as the address of interest.
–An ECC error.
–A cache maintenance operation without a following DSB.
4.A store to the address of interest.
5.A load from the address of interest.
If certain specific timing conditions are met, the load will get the data from the first store, or from what was in the cache at the start of the sequence instead of the data from the second store.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
10/44 |
ES0392 Rev 8 |
STM32H742/743xI/G |
Description of device limitations |
|
|
The effect of this erratum is that load operations can return incorrect data.
Workaround
There is no direct workaround for this erratum.
Where possible, Arm® recommends that you use the MPU to change the attributes on any write-through memory to write-back memory. If this is not possible, it might be necessary to disable the cache for sections of code that access write-through memory.
2.1.2Cortex®-M7 FPU interrupt not present on NVIC line 81
|
Description |
|
Arm® Cortex®-M7 FPU interrupt is not mapped on NVIC line 81. |
Note: |
This limitation is due to an error of implementation of the Arm core on the die, as opposed to |
|
a limitation of the core itself. |
|
Workaround |
|
None. |
Description
System break sources (processor LOCKUP output, PVD detection, RAM ECC error, Flash ECC error or clock security system detection) do not generate a break event on TIM1, TIM8 and HRTIM.
Workaround
None
Description
The clock recovery system (CRS) synchronization by USB start-of-frame signal (SOF) does not work.
Workaround
When available, use the LSE oscillator as synchronization source.
ES0392 Rev 8 |
11/44 |
Description of device limitations |
STM32H742/743xI/G |
|
|
Description
The SysTick external clock is the system clock, instead of the system clock divided by 8 (HCLK/8).
Workaround
Use the system clock (HCLK) as external clock and multiply the reload value by 8 in STK_LOAD register (take care that the maximum value is 224-1).
2.2.4Option byte loading can be done with the user wait-state configuration
Description
After an option byte change, the option byte loading is performed with the user wait-state configuration instead of the default configuration.
Workaround
When performing option byte loading (modification), configure the correct number of waitstates or use the default value (7 wait states).
Description
When a first read operation is performed without ECC error and a master accesses data with wait states, if a new access is done and contains an ECC double detection error, then the error message returns the address of the first data which has not generated the error.
Workaround
When a double ECC error flag is raised, check the failing address in the Flash interface (FAIL_ECC_ADDR1/2 in FLASH_ECC_FA1R/FA2R) and disregard the content of the BusFault address register.
Description
When two consecutive ECC errors occur, the content of the FLASH_ECC_FA1/2 register cannot be updated if the error correction flag (SNECCERR1/2 or DBECCERR1/2 in FLASH_SR1/2 register) is cleared at the same time as a new ECC error occurs.
Workaround
None.
12/44 |
ES0392 Rev 8 |
STM32H742/743xI/G |
Description of device limitations |
|
|
2.2.7PCROP-protected areas in Flash memory may be unprotected
Description
In case of readout protection level regression from level 1 to level 0, the PCROP protected areas in Flash memory may become unprotected.
Workaround
The user application must set the readout protection level to level 2 to avoid PCROPprotected areas from being unprotected.
Description
When Flash memory bank swapping feature is enabled, the embedded Flash memory interface behavior might become unpredictable.
Workaround
Do not enable the Flash memory bank swapping feature on devices revision Y.
Description
Read data may be corrupted when the following conditions are met:
•Several read transactions are performed to the AXI SRAM,
•and a master delays its data acceptance while a new transfer is requested.
Workaround
Set the READ_ISS_OVERRIDE bit in the AXI_TARG7_FN_MOD register. This will reduce the read issuing capability to 1 at AXI interconnect level and avoid data corruption.
Description
When a failure on the LSE oscillator is detected by a clock security system (CSS), the backup domain clock source cannot be changed.
Workaround
When a clock security system detects a LSE failure, reset the backup domain and select a functional clock source.
ES0392 Rev 8 |
13/44 |
Description of device limitations |
STM32H742/743xI/G |
|
|
Description
When the LSI clock is used as RTC clock source, the RTC is stopped (it does not received the clock anymore) when a system reset occurs.
Workaround
1.Check the RTC clock source after each system reset.
2.If the LSI clock is selected, enable it again.
Description
To avoid damaging parts, the user application must avoid to load more than 5 mA on OTG_FS_DP/DM pins.
Workaround
None
2.2.13Unexpected leakage current on I/Os when VIN higher that VDD
Description
|
When VIN is higher than VDD and depending on the waveform applied to I/Os, an |
|
unexpected leakage current might be observed when VIN decreases. |
Note: |
This leakage does not impact the product reliability. |
Workaround
The application must maintain VIN lower that VDD to avoid current leakage on I/Os.
Description
The LSEDRV[1:0] bits in the RCC_BDCR register, which are used to select LSE oscillator driving capability, are swapped (see Table 4).
LSEDRV[1:0] |
LSE driving mode |
||
|
|
||
Expected mode |
Effective mode |
||
|
|||
|
|
|
|
01 |
Medium-low drive |
Medium-high drive |
|
|
|
|
|
10 |
Medium-high drive |
Medium-low drive |
|
|
|
|
14/44 |
ES0392 Rev 8 |