STMicroelectronics STM32H725ZE, STM32H725VE, STM32H725RE, STM32H725IE, STM32H725AE Datasheet

...

STM32H725xE/G

VFQFPN 68

(8x8 mm)

FBGA

TFBGA100

(8x8 mm)

LQFP100 (14 x 14 mm) LQFP144 (20 x 20 mm) LQFP176 (24 x 24 mm)

FBGA

UFBGA 169 (7 x 7 mm)

UFBGA 176+25 (10 x 10 mm)

32-bit Arm® Cortex®-M7 550 MHz MCU, up to 1 MB Flash memory,

564 KB RAM, 35 comms peripherals and analog interfaces

Datasheet - production data

Features

Core

• 32-bit Arm® Cortex®-M7 CPU with DP-FPU, L1 cache: 32-Kbyte data cache and 32-Kbyte instruction cache allowing 0-wait state execution from embedded Flash memory and external memories, frequency up to 550 MHz, MPU, 1177 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions

Memories

• Up to 1 Mbyte of embedded Flash memory with ECC

• SRAM: total 564 Kbytes all with ECC, including 128 Kbytes of data TCM RAM for critical realtime data + 432 Kbytes of system RAM (up to 256 Kbytes can remap on instruction TCM RAM for critical real time instructions) + 4 Kbytes of backup SRAM (available in the lowest-power modes)

• Flexible external memory controller with up to 24-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories

• 2 x Octo-SPI interface with XiP

• 2 x SD/SDIO/MMC interface

• Bootloader

Graphics

Clock, reset and supply management

• 1.62 V to 3.6 V application supply and I/O

• POR, PDR, PVD and BOR

• Dedicated USB power

• Embedded DCDC and LDO regulator

(*)VFQFPN68 variant is DCDC only

• Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI

• External oscillators: 4-50 MHz HSE,

32.768 kHz LSE

• Chrom-ART Accelerator graphical hardware

• LCD-TFT controller supporting up to XGA

September 2020 DS13311 Rev 2 1/276

accelerator enabling enhanced graphical user interface to reduce CPU load

resolution

Low power

• Sleep, Stop and Standby modes

• V

supply for RTC, 32×32-bit backup

BAT

registers

Analog

• 2×16-bit ADC, up to 3.6 MSPS in 16-bit: up to 22 channels and 7.2 MSPS in doubleinterleaved mode

www.st.com

STM32H725xE/G

• 1 x 12-bit ADC, up to 5 MSPS in 12-bit, up to 12 channels

• 2 x comparators

• 2 x operational amplifier GBW = 8 MHz

• 2× 12-bit D/A converters

Digital filters for sigma delta modulator (DFSDM)

• 8 channels/4 filters

4 DMA controllers to offload the CPU

• 1 × MDMA with linked list support

• 2 × dual-port DMAs with FIFO

• 1 × basic DMA with request router capabilities

24 timers

• Seventeen 16-bit (including 5 x low power 16-bit timer available in stop mode) and four 32-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input

• 2x watchdogs, 1x SysTick timer

external clock and up to 5 x SPI (from 5 x USART when configured in synchronous mode)

• 2x SAI (serial audio interface)

• 1× FD/TT-CAN and 2xFD-CAN

• 8- to 14-bit camera interface

• 16-bit parallel slave synchronous interface

• SPDIF-IN interface

• HDMI-CEC

• Ethernet MAC interface with DMA controller

• USB 2.0 high-speed/full-speed

device/host/OTG controller with dedicated DMA, on-chip FS PHY and ULPI for external HS PHY

• SWPMI single-wire protocol master I/F

• MDIO slave interface

Mathematical acceleration

• CORDIC for trigonometric functions acceleration

• FMAC: Filter mathematical accelerator

Debug mode

• SWD and JTAG interfaces

• 2-Kbyte embedded trace buffer

Up to 128 I/O ports with interrupt capability

Up to 35 communication interfaces

• Up to 5 × I2C FM+ interfaces (SMBus/PMBus™)

• Up to 5 USARTs/5 UARTs (ISO7816 interface, LIN, IrDA, modem control) and 1 x LPUART

• Up to 6 SPIs with 4 with muxed duplex I2S for audio class accuracy via internal audio PLL or

Table 1. Device summary

Reference Part number

STM32H725xE

STM32H725xG

STM32H725ZE, STM32H725VE, STM32H725RE, STM32H725IE, STM32H725AE

STM32H725ZG, STM32H725VG, STM32H725RG, STM32H725IG, STM32H725AG

Digital temperature sensor

True random number generator

CRC calculation unit

RTC with sub-second accuracy and hardware calendar

ROP, PC-ROP, tamper detection

96-bit unique ID

All packages are ECOPACK2 compliant

2/276 DS13311 Rev 2

STM32H725xE/G Contents

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.1 Arm® Cortex®-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.2 Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.3 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.3.1 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.3.2 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Error code correction (ECC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

3.4 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.5 CORDIC co-processor (CORDIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

CORDIC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

3.6 Filter mathematical accelerator (FMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . 27

FMAC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

3.7 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.7.1 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.7.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.7.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.8 Low-power strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.9 Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.9.1 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.9.2 System reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.10 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.11 Bus-interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.12 DMA controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.13 Chrom-ART Accelerator (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.14 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 35

3.15 Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . . . . 35

3.16 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 35

3.17 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.18 Octo-SPI memory interface (OCTOSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 36

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Contents STM32H725xE/G

3.19 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.20 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.21 Digital temperature sensor (DTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.22 V

operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

BAT

3.23 Digital-to-analog converters (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.24 Ultra-low-power comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.25 Operational amplifiers (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.26 Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 40

3.27 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.28 PSSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.29 LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.30 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.31 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.31.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.31.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.31.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.31.4 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5) . . . . 47

3.31.5 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.31.6 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.31.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.32 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 48

3.33 Inter-integrated circuit interface (I

3.34 Universal synchronous/asynchronous receiver transmitter (USART) . . . 49

3.35 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 50

3.36 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) . 51

3.37 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.38 SPDIFRX Receiver Interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.39 Single wire protocol master interface (SWPMI) . . . . . . . . . . . . . . . . . . . . 52

3.40 Management data input/output (MDIO) slaves . . . . . . . . . . . . . . . . . . . . . 53

3.41 SD/SDIO/MMC card host interfaces (SDMMC) . . . . . . . . . . . . . . . . . . . . 53

3.42 Controller area network (FDCAN1, FDCAN2, FDCAN3) . . . . . . . . . . . . . 53

3.43 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 54

3.44 Ethernet MAC interface with dedicated DMA controller (ETH) . . . . . . . . . 54

4/276 DS13311 Rev 2

C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

STM32H725xE/G Contents

3.45 High-definition multimedia interface (HDMI)

- consumer electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.46 Debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

5 Pinouts, pin descriptions and alternate functions . . . . . . . . . . . . . . . . 57

6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 116

6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116

6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118

6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

6.3.2 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

6.3.3 SMPS step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

6.3.4 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 125

6.3.5 Embedded reset and power control block characteristics . . . . . . . . . . 126

6.3.6 Embedded reference voltage characteristics . . . . . . . . . . . . . . . . . . . . 127

6.3.7 Embedded USB regulator characteristics . . . . . . . . . . . . . . . . . . . . . . 128

6.3.8 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Typical and maximum current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Typical SMPS efficiency versus load current and temperature . . . . . . . . . . . . . 135

I/O system current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

6.3.9 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 139

6.3.10 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 140

High-speed external user clock generated from an external source . . . . . . . . .140

Low-speed external user clock generated from an external source . . . . . . . . . .141

High-speed external clock generated from a crystal/ceramic resonator. . . . . . .142

Low-speed external clock generated from a crystal/ceramic resonator . . . . . . . 143

6.3.11 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 144

48 MHz high-speed internal RC oscillator (HSI48) . . . . . . . . . . . . . . . . . . . . . . .144

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Contents STM32H725xE/G

64 MHz high-speed internal RC oscillator (HSI) . . . . . . . . . . . . . . . . . . . . . . . . .145

4 MHz low-power internal RC oscillator (CSI) . . . . . . . . . . . . . . . . . . . . . . . . . .146

Low-speed internal (LSI) RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146

6.3.12 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

6.3.13 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Flash memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

6.3.14 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . . . . . . . .152

Designing hardened software to avoid noise problems . . . . . . . . . . . . . . . . . . .152

Electromagnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153

6.3.15 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 153

Electrostatic discharge (ESD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153

Static latchup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154

6.3.16 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Functional susceptibility to I/O current injection . . . . . . . . . . . . . . . . . . . . . . . . .154

6.3.17 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

General input/output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155

Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157

Output voltage levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158

Output buffer timing characteristics (HSLV option disabled) . . . . . . . . . . . . . . .160

Output buffer timing characteristics (HSLV option enabled). . . . . . . . . . . . . . . .162

Analog switch between ports Pxy_C and Pxy . . . . . . . . . . . . . . . . . . . . . . . . . .163

6.3.18 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

6.3.19 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Asynchronous waveforms and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Synchronous waveforms and timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172

NAND controller waveforms and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180

SDRAM waveforms and timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183

6.3.20 Octo-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

6.3.21 Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

6.3.22 16-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

General PCB design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199

6.3.23 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

6.3.24 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

6.3.25 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 211

6.3.26 Analog temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . 212

6.3.27 Digital temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . 213

6.3.28 Temperature and V

monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

BAT

6.3.29 Voltage booster for analog switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

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STM32H725xE/G Contents

6.3.30 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

6.3.31 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 215

6.3.32 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics . . . 218

6.3.33 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 221

6.3.34 Parallel synchronous slave interface (PSSI) characteristics . . . . . . . . 222

6.3.35 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 223

6.3.36 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

6.3.37 Low-power timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

6.3.38 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226

USART interface characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227

SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229

I2S Interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232

SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234

MDIO characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236

SD/SDIO MMC card host interface (SDMMC) characteristics . . . . . . . . . . . . . .237

USB OTG_FS characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240

USB OTG_HS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

Ethernet interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242

JTAG/SWD interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244

7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

7.1 VFQFPN68 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Device marking for VFQFPN68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248

7.2 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

Device marking for LQFP100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251

7.3 TFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

Device marking for TFBGA100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254

7.4 WLCSP115 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Device marking for WLSCP115 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257

7.5 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

Device marking for LQFP144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261

7.6 UFBGA169 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

Device marking for UFBGA169 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264

7.7 LQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

Device marking for LQFP176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268

7.8 UFBGA176+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

Device marking for UFBGA176+25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

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Contents STM32H725xE/G

7.9 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

7.9.1 Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

8/276 DS13311 Rev 2

STM32H725xE/G List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2. STM32H725xE/G features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 3. System versus domain low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 4. DFSDM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 5. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 6. USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 7. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 8. STM32H725 pin and ball descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 9. STM32H725 pin alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 10. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Table 11. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 12. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 13. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Table 14. Supply voltage and maximum temperature configuration. . . . . . . . . . . . . . . . . . . . . . . . . 120

Table 15. VCAP operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Table 16. Characteristics of SMPS step-down converter external components. . . . . . . . . . . . . . . . 122

Table 17. SMPS step-down converter characteristics for external usage . . . . . . . . . . . . . . . . . . . . 122

Table 18. Inrush current and inrush electric charge characteristics for LDO and SMPS . . . . . . . . . 123

Table 19. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . 125

Table 20. Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Table 21. Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Table 22. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Table 23. USB regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Table 24. Typical and maximum current consumption in Run mode,

code with data processing running from ITCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Table 25. Typical and maximum current consumption in Run mode, code with data processing

running from Flash memory, cache ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Table 26. Typical and maximum current consumption in Run mode,

code with data processing running from Flash memory, cache OFF. . . . . . . . . . . . . . . . 132

Table 27. Typical consumption in Run mode and corresponding performance

versus code position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Table 28. Typical current consumption in Autonomous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Table 29. Typical current consumption in Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Table 30. Typical current consumption in System Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Table 31. Typical current consumption in Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Table 32. Typical and maximum current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . 135

Table 33. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Table 34. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Table 35. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Table 36. 4-50 MHz HSE oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Table 37. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Table 38. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Table 39. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Table 40. CSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Table 41. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Table 42. PLL1 characteristics (wide VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Table 43. PLL1 characteristics (medium VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Table 44. PLL2 and PLL3 characteristics (wide VCO frequency range) . . . . . . . . . . . . . . . . . . . . . 149

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List of tables STM32H725xE/G

Table 45. PLL2 and PLL3 characteristics (medium VCO frequency range) . . . . . . . . . . . . . . . . . . . 150

Table 46. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Table 47. Flash memory programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Table 48. Flash memory endurance and data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Table 49. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Table 50. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 51. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 52. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Table 53. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Table 54. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Table 55. Output voltage characteristics for all I/Os except PC13, PC14 and PC15 . . . . . . . . . . . . 158

Table 56. Output voltage characteristics for PC13, PC14 and PC15 . . . . . . . . . . . . . . . . . . . . . . . . 159

Table 57. Output timing characteristics (HSLV OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Table 58. Output timing characteristics (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Table 59. Pxy_C and Pxy analog switch characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Table 60. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Table 61. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 166

Table 62. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 166

Table 63. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 168

Table 64. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 168

Table 65. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Table 66. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 170

Table 67. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Table 68. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 171

Table 69. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Table 70. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Table 71. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 177

Table 72. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Table 73. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Table 74. Switching characteristics for NAND Flash write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Table 75. SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Table 76. LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Table 77. SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Table 78. LPSDR SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Table 79. OCTOSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Table 80. OCTOSPI characteristics in DTR mode (no DQS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Table 81. OCTOSPI characteristics in DTR mode (with DQS)/Octal and Hyperbus . . . . . . . . . . . . 189

Table 82. Delay Block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Table 83. 16-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Table 84. Minimum sampling time vs RAIN (16-bit ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Table 85. 16-bit ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Table 86. 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Table 87. Minimum sampling time vs RAIN (12-bit ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Table 88. 12-bit ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Table 89. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Table 90. DAC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Table 91. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Table 92. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Table 93. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Table 94. Digital temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Table 95. V Table 96. V

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

BAT

charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

BAT

10/276 DS13311 Rev 2

STM32H725xE/G List of tables

Table 97. Temperature monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Table 98. Voltage booster for analog switch characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Table 99. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Table 100. Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

Table 101. DFSDM measured timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Table 102. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Table 103. PSSI transmit characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

Table 104. PSSI receive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

Table 105. LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

Table 106. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Table 107. LPTIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Table 108. Minimum i2c_ker_ck frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

Table 109. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

Table 110. USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

Table 111. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

Table 112. I

S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

Table 113. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

Table 114. MDIO Slave timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Table 115. Dynamics characteristics: SD / MMC characteristics, VDD=2.7 to 3.6 V . . . . . . . . . . . . . 237

Table 116. Dynamics characteristics: eMMC characteristics VDD=1.71V to 1.9V . . . . . . . . . . . . . . . 238

Table 117. USB OTG_FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

Table 118. Dynamics characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

Table 119. Dynamics characteristics: Ethernet MAC signals for SMI . . . . . . . . . . . . . . . . . . . . . . . . 242

Table 120. Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 243

Table 121. Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 243

Table 122. Dynamics JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

Table 123. Dynamics SWD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Table 124. VFQFPN68 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

Table 125. LQPF100 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

Table 126. TFBGA100 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

Table 127. TFBGA100 recommended PCB design rules (0.8 mm pitch BGA). . . . . . . . . . . . . . . . . . 254

Table 128. WLCSP115 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

Table 129. WLCSP115 recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

Table 130. LQFP144 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

Table 131. UFBGA169 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

Table 132. UFBGA169 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 263

Table 133. LQFP176 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

Table 134. UFBGA176+25 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

Table 135. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 270

Table 136. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

Table 137. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

DS13311 Rev 2 11/276

List of figures STM32H725xE/G

List of figures

Figure 1. STM32H725xE/G block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 2. Power-up/power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 3. STM32H725xE/G bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 4. VFQFPN68 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 5. TFBGA100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 6. LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 7. WLCSP115 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 8. LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 9. LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 10. UFBGA169 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 11. UFBGA176+25 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 12. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figure 13. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figure 14. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 15. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 16. External capacitor C

Figure 17. External components for SMPS step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Figure 18. Typical SMPS efficiency (%) vs load current (A) in Run mode at TJ = 30 °C. . . . . . . . . . 135

Figure 19. Typical SMPS efficiency (%) vs load current (A) in Run mode at TJ = TJmax . . . . . . . . . 136

Figure 20. Typical SMPS efficiency (%) vs load current (A) in Stop and

DStop modes at TJ = 30 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Figure 21. Typical SMPS efficiency (%) vs load current (A) in low-power mode at TJ = TJmax . . . 137

Figure 22. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Figure 23. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Figure 24. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Figure 25. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Figure 26. VIL/VIH for all I/Os except BOOT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Figure 27. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Figure 28. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 165

Figure 29. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 167

Figure 30. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 169

Figure 31. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Figure 32. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Figure 33. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 176

Figure 34. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Figure 35. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Figure 36. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Figure 37. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 181

Figure 38. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 182

Figure 39. SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Figure 40. SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Figure 41. OCTOSPI SDR read/write timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Figure 42. OCTOSPI DTR mode timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Figure 43. OCTOSPI Hyperbus clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Figure 44. OCTOSPI Hyperbus read timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Figure 45. OCTOSPI Hyperbus write timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Figure 46. ADC accuracy characteristics (12-bit resolution) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Figure 47. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

EXT

12/276 DS13311 Rev 2

STM32H725xE/G List of figures

Figure 48. Power supply and reference decoupling (V Figure 49. Power supply and reference decoupling (V

not connected to V

REF+

connected to V

REF+

). . . . . . . . . . . . . 199

DDA

). . . . . . . . . . . . . . . . 199

DDA

Figure 50. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Figure 51. Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

Figure 52. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Figure 53. LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Figure 54. LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Figure 55. USART timing diagram in Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

Figure 56. USART timing diagram in Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

Figure 57. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

Figure 58. SPI timing diagram - slave mode and CPHA = 1 Figure 59. SPI timing diagram - master mode Figure 60. I Figure 61. I

S slave timing diagram (Philips protocol)

S master timing diagram (Philips protocol)

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

Figure 62. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Figure 63. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Figure 64. MDIO Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

Figure 65. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

Figure 66. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

Figure 67. DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

Figure 68. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

Figure 69. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

Figure 70. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

Figure 71. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

Figure 72. JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Figure 73. SWD timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Figure 74. VFQFPN68 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Figure 75. VFQFPN68 package recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

Figure 76. VFQFPN68 marking example (package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

Figure 77. LQFP100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

Figure 78. LQFP100 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

Figure 79. LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

Figure 80. TFBGA100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

Figure 81. TFBGA100 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

Figure 82. TFBGA100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

Figure 83. WLCSP115 package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Figure 84. WLCSP115 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

Figure 85. WLCSP115 marking example (package top view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

Figure 86. LQFP144 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

Figure 87. LQFP144 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

Figure 88. LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

Figure 89. UFBGA169 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

Figure 90. UFBGA169 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

Figure 91. UFBGA169 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

Figure 92. LQFP176 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

Figure 93. LQFP176 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

Figure 94. LQFP176 marking example (package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

Figure 95. UFBGA176+25 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

Figure 96. UFBGA176+25 package recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

Figure 97. UFBGA176+25 marking example (package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

DS13311 Rev 2 13/276

Introduction STM32H725xE/G

1 Introduction

This document provides information on STM32H725xE/G microcontrollers, such as description, functional overview, pin assignment and definition, packaging, and ordering information.

This document should be read in conjunction with the STM32H725xE/G reference manual (RM0468), available from the STMicroelectronics website www.st.com.

For information on the Arm Reference Manual, available from the http://www.arm.com website.

®(a)

Cortex®-M7 core, refer to the Cortex®-M7 Technical

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

14/276 DS13311 Rev 2

STM32H725xE/G Description

2 Description

STM32H725xE/G devices are based on the high-performance Arm® Cortex®-M7 32-bit RISC core operating at up to 550 MHz. The Cortex® -M7 core features a floating point unit (FPU) which supports Arm data-processing instructions and data types. The Cortex -M7 core includes 32 Kbytes of instruction cache and 32 Kbytes of data cache. STM32H725xE/G devices support a full set of DSP instructions and a memory protection unit (MPU) to enhance application security.

STM32H725xE/G devices incorporate high-speed embedded memories with up to 1 Mbyte of Flash memory, up to 564 Kbytes of RAM (including 192 Kbytes that can be shared between ITCM and AXI, plus 64 Kbytes exclusively ITCM, plus 128 Kbytes exclusively AXI, 128 Kbyte DTCM, 48 Kbytes AHB and 4 Kbytes of backup RAM), as well as an extensive range of enhanced I/Os and peripherals connected to APB buses, AHB buses, 2x32-bit multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external memory access. To improve application robustness, all memories feature error code correction (one error correction, two error detections).

The devices embed peripherals allowing mathematical/arithmetic function acceleration (CORDIC co-processor for trigonometric functions and FMAC unit for filter functions). All the devices offer three ADCs, two DACs, two operational amplifiers, two ultra-low power comparators, a low-power RTC, 4 general-purpose 32-bit timers, 12 general-purpose 16-bit timers including two PWM timers for motor control, five low-power timers, a true random number generator (RNG). The devices support four digital filters for external sigma-delta modulators (DFSDM). They also feature standard and advanced communication interfaces.

• Standard peripherals

–Five I

– Five USARTs, five UARTs and one LPUART

– Six SPIs, four I

peripherals can be clocked by a dedicated internal audio PLL or by an external clock to allow synchronization. (Note that the five USARTs also provide SPI slave capability.)

– Two SAI serial audio interfaces

– One SPDIFRX interface with four inputs

– One SWPMI (Single Wire Protocol Master Interface)

– Management Data Input/Output (MDIO) slaves

– Two SDMMC interfaces

– A USB OTG high-speed interface with full-speed capability (with the ULPI)

– Two FDCANs plus one TT-FDCAN interface

– An Ethernet interface

– Chrom-ART Accelerator

– HDMI-CEC

double-precision (IEEE 754 compliant) and single-precision

Ss in Half-duplex mode. To achieve audio class accuracy, the I2S

DS13311 Rev 2 15/276

Description STM32H725xE/G

• Advanced peripherals including

– A flexible memory control (FMC) interface

– Two Octo-SPI memory interfaces

– A camera interface for CMOS sensors

– An LCD-TFT display controller

Refer to Table 2: STM32H725xE/G features and peripheral counts for the list of peripherals available on each part number.

To reduce the power consumption the STM32H725xE/G include an optional step-down converter that can be used either for internal or external supply, or both.

STM32H725xE/G devices operate in the –40 to +125 °C ambient temperature range from a

1.62 to 3.6 V power supply. The supply voltage can drop down to 1.62 V by using an external power supervisor (see Section 3.7.2: Power supply supervisor) and connecting the PDR_ON pin to V

. Otherwise the supply voltage must stay above 1.71 V with the

embedded power voltage detector enabled.

Dedicated supply inputs for USB are available to allow a greater power supply choice.

A comprehensive set of power-saving modes allows the design of low-power applications.

STM32H725xE/G devices are offered in several packages ranging from 68 to 176 pins/balls. The set of included peripherals changes with the device chosen.

These features make STM32H725xE/G microcontrollers suitable for a wide range of applications:

• Motor drive and application control

• Medical equipment

• Industrial applications: PLC, inverters, circuit breakers

• Printers, and scanners

• Alarm systems, video intercom, and HVAC

• Home audio appliances

• Mobile applications, Internet of Things

• Wearable devices: smart watches.

Figure 1 shows the device block diagram.

16/276 DS13311 Rev 2

MSv52562V4

TT-FDCAN1

FDCAN2

I2C1/SMBUS

I2C2/SMBUS

I2C3/SMBUS

AXI/AHB12 (275MHz)

CH[1:4]N, CH[1:4], ETR, BKIN, BKIN2

as AF

APB1 30MHz

SCL, SDA, SMBA as AF

APB1 138 MHz (max)

MDMA

PJ,PK[11:0]

SCL, SDA, SMBA as AF

MOSI, MISO, SCK, NSS / SDO, SDI, CK, WS, MCK, as AF

TX, RX, RXFD_MODE, TXFD_MODE as AF

CH[4;1], ETR as AF

FIFO

LCD-TFT

FIFO

CHROM-ART

(DMA2D)

LCD_R[7:0], LCD_G[7:0],

LCD_B[7:0], LCD_HSYNC,

LCD_VSYNC, LCD_DE, LCD_CLK

64-bit AXI BUS-MATRIX

CEC as AF

IN[1:4] as AF

MDC, MDIO as AF

AXIM

Arm CPU

Cortex-M7

550 MHz

AHBP

AHBS

TRACECLK

TRACED[3:0]

NJTRST, JTDI,

JTCK/SWCLK

JTDO/SWDIO, JTDO

JTAG/SW

ETM

I-Cache

32KB

D-Cache

32KB

I-TCM 64KB

D-TCM

64KB

16 Streams

FIFO

SDMMC1

D[7:0], D123DIR, D0DIR,

CMD, CKas AF

FIFO

DMA1

FIFOs

8 Stream

DMA2

FIFOs

ETHER

MAC

FIFO

SDMMC2

FIFO

OTG_HS

FIFO

SRAM1

16 KB

8 Stream

FMC_signals

DMA/ DMA/

PHY

MII / RMII

MDIO as AF

DP, DM, STP, NXT,ULPI:CK

, D[7:0], DIR,

ID, VBUS

AHB1 (275MHz)

ADC1

OUT1, OUT2 as AF

16b

AXI/AHB34 (275MHz)

WWDG

AHB2 (275MHz)

PA..H[15:0]

HSYNC, VSYNC, PIXCLK, D[13:0]

PDCK, DE, RDY, D[15:0]

UART9

MOSI, MISO, SCK, NSS as AF

32-bit AHB BUS-MATRIX

BDMA

DMA

Mux2

Up to 20 analog inputs Most are common to ADC1 & 2

HSEM

AHB4 (275MHz)

AHB4

AHB4_MEMD3 (275MHz)

AHB4

VDDA, VSSA

NRESET

WKUP[1;2;4;6]

@VDD

RCC

Reset &

control

OSC32_IN OSC32_OUT

AWU

VCORE

BBgen + POWER MNGT

OSC_IN OSC_OUT

TS, TAMP1, TAMP3, OUT, REFIN

VDD VSS VCAP, VDDLDO VDDSMPS, VSSSMPS, VLXSMPS, VFBSMPS

@VDD

@VSW

PWRCTRL

AHB4 (275MHz)

SUPPLY SUPERVISION

Int

POR reset

@VDD

VINM, VINP, VOUT as AF

CKOUT, DATIN[7:0], CKIN[7:0]

2 compl. chan.(TIM15_CH1[1:2]N),

2 chan. (TIM_CH15[1:2], BKIN as AF

1 compl. chan.(TIM16_CH1N),

1 chan. (TIM16_CH1, BKIN as AF

1 compl. chan.(TIM17_CH1N),

1 chan. (TIM17_CH1, BKIN as AF

D[7:0],

D123DIR,

D0DIR,

CMD, CKas AF

Up to 17 analog inputs

Some common to ADC1 and 2

SD_[A;B], SCK_[A;B], FS_[A;B],

MCLK_[A;B], D[3:1], CK[2:1] as AF

SCL, SDA, SMBA as AF

COMPx_INP, COMPx_INM,

COMPx_OUT as AF

OUT as AF

D-TCM

64KB

AHB/APB

OCTOSPI1

Up to 1 MB

FLASH

128 KB AXI

SRAM

FMC

AHB/APB

DFSDM

USART10

SD_[A;B], SCK_[A;B], FS_[A;B],

MCLK_[A;B], D[3:1], CK[2:1] as AF

FIFO

SAI1

SPI5

TIM17

TIM16

TIM15

SPI4

MOSI, MISO, SCK, NSS /

SDO, SDI, CK, WS, MCK, as AF

SPI1/I2S1

USART6

USART1

TIM1/PWM

16b

TIM8/PWM

16b

APB2 138 MHz (max)

ADC3

GPIO PORTA.. H

GPIO PORTJ,K

SAI4

COMP1&2

LPTIM5

OUT as AF

LPTIM4

OUT as AF

LPTIM3

I2C4

MOSI, MISO, SCK, NSS /

SDO, SDI, CK, WS, MCK, as AF

SPI6/I2S6

RX, TX, CK, CTS, RTS as AF

LPUART1

LPTIM2

VREF

SYSCFG

EXTI WKUP

CRC

DAP

RNG

DMA

Mux1

To APB1-2 peripherals

SRAM2

16 KB

ADC2

AHB/APB

TIM6

16b

TIM7

16b

SWPMI

TIM2

32b

TIM3

16b

TIM4

16b

TIM5

32b

TIM12

16b

TIM13

16b

TIM14

16b

USART2

USART3

UART4

UART5

UART7

UART8

SPI2/I2S2

MOSI, MISO, SCK, NSS / SDO, SDI, CK, WS, MCK, as AF

SPI3/I2S3

MDIOS

10 KB SRAM

RAM

I/F

USBCR

SPDIFRX1

HDMI-CEC

DAC

LPTIM1

OPAMP2

AHB/APB

XTAL 32 kHz

RTC

Backup registers

XTAL OSC 4- 48 MHz

CSI RC

LSI RC

PLL1+PLL2+PLL3

POR/PDR/BOR

PVD

Voltage

regulator

3.3 to 1.2V

LSI

HSI

CSI

HSI48

IN1, IN2, ETR, OUT as AF

AHB1 (275MHz)

16 KB SRAM

4 KB BKP

RAM

AHB4

32-bit AHB BUS-MATRIX

APB4 138MHz (max)

APB4 138 MHz (max)

IWDG

Temperature

sensor

Shared AXI

I-TCM 192KB

OCTOSPI2

OCTOSPIM

AHB4

OCTOSPI2 signals

OCTOSPI1 signals

DLYBSD1

APB3 (138MHz)

DLYBOS1-2

AHB3

FDCAN3

FIFO

DCMI

PSSI

RX, TX, CK, CTS, RTS, DE as AF

RX, TX, CTS, RTS, DE as AF

CORDIC

FMAC

TIM23

TIM24

32b

I2C5/SMBUS

SCL, SDA, SMBA as AF

Digital filter

RX, TX, CK, CTS, RTS, DE as AF

RX, TX, CTS, RTS, DE as AF

CH[1:4]N, CH[1:4], ETR, BKIN, BKIN2

as AF

16b

CH[4;1], ETR as AF

CH[2;1] as AF

CH1 as AF

TX, RX, RXFD_MODE, TXFD_MODE as AF

OPAMP1

VINM, VINP, VOUT as AF

HSI48 RC

HSI RC

VBAT

DLYBSD2

IN1, IN2, ETR, OUT as AF

STM32H725xE/G Description

Figure 1. STM32H725xE/G block diagram

DS13311 Rev 2 17/276

Description STM32H725xE/G

Table 2. STM32H725xE/G features and peripheral counts

Peripherals

Flash memory (Kbytes)

STM32H 725REV/

RGV

512/

1024

STM32H 725VET/

VGT

512/

1024

STM32H 725VEH/

VGH

512/

1024

STM32H

725ZET/

ZGT

512/

1024

SRAM mapped onto

128

AXI bus

SRAM1

SRAM

(D2 domain)

(Kbytes)

SRAM2 (D2 domain)

SRAM4 (D3 domain)

RAM shared between ITCM and AXI (Kbytes)

192

ITCM RAM

TCM RAM in Kbytes

(instruction)

DTCM RAM (data)

128

Backup SRAM (Kbytes) 4

Interface 1

STM3

2H725

VGY

1024

STM32H

725AEI/

AGI

512/

1024

STM32H

725IEK/

IGK

512/

1024

STM32H

725IET/

IGT

512/

1024

NOR Flash memory/

RAM

- - - - - yes yes yes

controller

Multiplexed

FMC

I/O NOR Flash

- yes yes yes - yes yes yes

memory

16-bit NAND Flash memory

16-bit SDRAM controller

24-bit SDRAM controller

(1)

- yes yes yes yes yes yes yes

- - - - - yes yes yes

------yes-

GPIO 46 67 74 97 67 121 128 119

Quad-

SPI

222

OctoSPI interface

1 Quad-

SPI

2 Quad-

SPI

(2)

OTFDEC no

Cordic yes

18/276 DS13311 Rev 2

STM32H725xE/G Description

Table 2. STM32H725xE/G features and peripheral counts (continued)

Peripherals

STM32H 725REV/

RGV

STM32H 725VET/

VGT

STM32H 725VEH/

VGH

STM32H

725ZET/

ZGT

STM3

2H725

VGY

STM32H

725AEI/

AGI

STM32H

725IEK/

IGK

STM32H

725IET/

IGT

FMAC yes

General purpose 32

222222 2 2

bits

General purpose 16

10 10 10 10 10 10 10 10

bits

Advanced

Timers

control (PWM)

(3)

222 2 2

Basic 222222 2 2

Low-power 5 5 5 5 5 5 5 5

RTC 111111 1 1

Window watchdog /

independent

222222 2 2

watchdog

Wakeup pins 3 4 4 4 4 4 4 4

Tamper pins 1 2 2 2 2 2 2 2

Random number generator yes

Cryptographic accelerator no

DS13311 Rev 2 19/276

Description STM32H725xE/G

Table 2. STM32H725xE/G features and peripheral counts (continued)

STM32H

Peripherals

725REV/

SPI / I2S 4/4 5/4

RGV

STM32H 725VET/

VGT

(3)

STM32H 725VEH/

VGH

STM32H

725ZET/

ZGT

5/4 6/4 6/4 4/4 6/4 6/4

I2C 455555 55

USART/ UART/

3/4/1 4/4/1 4/6/1 5/5/1 4/4/1 5/5/1 5/5/1 5/5/1

LPUART

SAI/PDM 1/0

(3)

2/1

(3)

2/1

(3)

2/1 1/1

SPDIFRX 1

HDMI-CEC 1

Communication interfaces

SWPMI 1

MDIO 1

SDMMC 2

FDCAN/ TT-FDCAN

1/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1

USB [OTG_HS(UL PI)/

1 [0/1] 1 [1/1] 1 [1/1] 1 [1/1] 1 [0/1] 1 [1/1] 1 [1/1] 1 [1/1]

FS(PHY)]

Ethernet [MII/RMII]

- 1 [1/1] 1 [1/1] 1 [1/1] 1 [0/1] 1 [1/1] 1 [1/1] 1 [1/1]

Camera interface/PSSI yes

LCD-TFT yes

(3)

yes

(3)

yes

(3)

yes yes yes yes yes

STM3

2H725

VGY

(3)

STM32H

725AEI/

AGI

STM32H

725IEK/

IGK

2/1 2/1 2/1

STM32H

725IET/

IGT

Chrom-ART Accelerator (DMA2D)

Number of ADCs

Number of Direct channels

0 0 2/2 0 2/2 2/2 2/2 0

ADC1/ADC2

16-bit ADCs

Number of Fast channels

3/2 3/2 3/2 4/2 3/2 6/5 6/5 4/3

ADC1/ADC2

Number of Slow channels

11/10 11/10 9/8 11/11 9/8 12/11 12/11 12/11

ADC1/ADC2

20/276 DS13311 Rev 2

yes

STM32H725xE/G Description

Table 2. STM32H725xE/G features and peripheral counts (continued)

Peripherals

Number of ADCs

STM32H 725REV/

RGV

STM32H 725VET/

VGT

STM32H 725VEH/

VGH

STM32H

725ZET/

ZGT

STM3

2H725

VGY

STM32H

725AEI/

AGI

STM32H

725IEK/

IGK

STM32H

725IET/

IGT

Number of

12-bit ADCs

Direct channels

Number of Fast channels

Number of Slow channels

022222 2 2

026466 6 6

209399 9 4

Present in IC yes

12-bit DAC

Number of channels

Comparators 2

Operational amplifiers 2

DFSDM Present in IC yes

Maximum CPU frequency 550 MHz

USB separate supply pad - yes yes yes yes yes yes yes

USB internal regulator - - - yes yes yes yes yes

LDO - yes yes yes

SMPS step-down converter yes

DS13311 Rev 2 21/276

Description STM32H725xE/G

Table 2. STM32H725xE/G features and peripheral counts (continued)

STM32H

Peripherals

725REV/

RGV

Operating voltage 1.71 to 3.6 V

Ambient

Operating temperatures

temperature

Junction

temperature

Extended operating temperatures

(4)

Package

1. The 24-bit SDRAM controller is a 32-bit controller with only a 24-bit data bus and without NBL2-3. It can be used for graphical purposes to access aligned 32-bit words ignoring upper 8 bits.

2. The two Octo-SPI/Quad-SPI interfaces are available only in Muxed mode.

3. For limitations on peripheral features depending on packages, check the available pins/balls in Table 8: STM32H725 pin and

ball descriptions.

4. The extended temperature range is not available on WLCSP115 package.

Ambient

temperature

Junction

temperature

VFQFPN68LQFP

STM32H 725VET/

VGT

100

STM32H 725VEH/

VGH

TFBGA

100

STM32H

725ZET/

ZGT

STM3

2H725

VGY

-40°C to +85°C

-40°C to +125°C

-40°C to +140°C

LQFP

144

WLCS

115

STM32H

725AEI/

AGI

1.62 to 3.6 V

UFBGA

169

STM32H

725IEK/

IGK

UFBGA 176+25

STM32H

725IET/

IGT

LQFP17

22/276 DS13311 Rev 2

STM32H725xE/G Functional overview

3 Functional overview

3.1 Arm® Cortex®-M7 with FPU

The Arm® Cortex®-M7 with double-precision FPU processor is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and optimized power consumption, while delivering outstanding computational performance and low interrupt latency.

The Cortex

• Six-stage dual-issue pipeline

• Dynamic branch prediction

• Harvard architecture with L1 caches (32 Kbytes of I-cache and 32 Kbytes of D-cache)

• 64-bit AXI interface

• 64-bit ITCM interface

• 2x32-bit DTCM interfaces

The following memory interfaces are supported:

• Separate Instruction and Data buses (Harvard Architecture) to optimize CPU latency

• Tightly Coupled Memory (TCM) interface designed for fast and deterministic SRAM

• AXI Bus interface to optimize Burst transfers

• Dedicated low-latency AHB-Lite peripheral bus (AHBP) to connect to peripherals.

accesses

-M7 processor is a highly efficient high-performance featuring:

The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution.

It also supports single and double precision FPU (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation.

Figure 1 shows the general block diagram of the STM32H725xE/G family.

3.2 Memory protection unit (MPU)

The memory protection unit (MPU) manages the CPU access rights and the attributes of the system resources. It has to be programmed and enabled before use. Its main purposes are to prevent an untrusted user program to accidentally corrupt data used by the OS and/or by a privileged task, but also to protect data processes or read-protect memory regions.

The MPU defines access rules for privileged accesses and user program accesses. It allows defining up to 16 protected regions that can in turn be divided into up to 8 independent subregions, where region address, size, and attributes can be configured. The protection area ranges from 32 bytes to 4 Gbytes of addressable memory. When an unauthorized access is performed, a memory management exception is generated.

DS13311 Rev 2 23/276

Functional overview STM32H725xE/G

3.3 Memories

3.3.1 Embedded Flash memory

The STM32H725xE/G devices embed up to 1 Mbyte of Flash memory that can be used for storing programs and data.

The Flash memory is organized as 266-bit Flash words memory that can be used for storing both code and data constants. Each word consists of:

• one Flash word (8 words, 32 bytes or 256 bits)

• 10 ECC bits (single-error correction and double-error detection).

The Flash memory is organized as follows:

• up to 1 Mbyte of user Flash memory block containing eight user sectors of 128 Kbytes

(4 K Flash memory words)

• 128 Kbytes of system Flash memory from which the device can boot

• 2 Kbytes (64 Flash words) of user option bytes for user configuration

3.3.2 Embedded SRAM

All devices feature:

• from 128 to 320 Kbytes of AXI-SRAM mapped onto the AXI bus on D1 domain

• SRAM1 mapped on D2 domain: 16 Kbytes

• SRAM2 mapped on D2 domain: 16 Kbytes

• SRAM4 mapped on D3 domain: 16 Kbytes

• 4 Kbytes of backup SRAM

The content of this area is protected against possible unwanted write accesses, and can be retained in Standby or V

• RAM mapped to TCM interface (ITCM and DTCM):

Both ITCM and DTCM RAMs are 0 wait state memories. They can be accessed either from the CPU or the MDMA (even in Sleep mode) through a specific AHB slave of the Cortex®-M7CPU(AHBSAHBP):

– 64 to 256 Kbytes of ITCM-RAM (instruction RAM)

This RAM is connected to ITCM 64-bit interface designed for execution of critical real-times routines by the CPU.

– 128 Kbytes of DTCM-RAM (2x 64-Kbyte DTCM-RAMs on 2x32-bit DTCM ports)

The DTCM-RAM could be used for critical real-time data, such as interrupt service routines or stack/heap memory. Both DTCM-RAMs can be used in parallel (for load/store operations) thanks to the Cortex®-M7 dual issue capability.

The MDMA can be used to load code or data in ITCM or DTCM RAMs. As reflected above, 192 Kbyte of RAM can be used either for AXI SRAM or ITCM, with a 64Kbyte granularity.

BAT

mode.

24/276 DS13311 Rev 2

STM32H725xE/G Functional overview

Error code correction (ECC)

Over the product lifetime, and/or due to external events such as radiations, invalid bits in memories may occur. They can be detected and corrected by ECC. This is an expected behavior that has to be managed at final-application software level in order to ensure data integrity through ECC algorithms implementation.

SRAM data are protected by ECC:

• 7 ECC bits are added per 32-bit word.

• 8 ECC bits are added per 64-bit word for AXI-SRAM and ITCM-RAM.

The ECC mechanism is based on the SECDED algorithm. It supports single-error correction and double-error detection.

DS13311 Rev 2 25/276

Functional overview STM32H725xE/G

3.4 Boot modes

At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF which includes:

• All Flash address space

• All RAM address space: ITCM, DTCM RAMs and SRAMs

• The System memory bootloader

The boot loader is located in non-user System memory. It is used to reprogram the Flash memory through a serial interface (USART, I2C, SPI, FDCAN, USB-DFU). Refer to application note AN2606 “STM32 microcontroller System memory Boot mode” for details.

3.5 CORDIC co-processor (CORDIC)

The CORDIC co-processor provides hardware acceleration of certain mathematical functions, notably trigonometric, commonly used in motor control, metering, signal processing and many other applications.

It speeds up the calculation of these functions compared to a software implementation, allowing a lower operating frequency, or freeing up processor cycles in order to perform other tasks.

The filter mathematical accelerator unit performs arithmetic operations on vectors. It comprises a multiplier/accumulator (MAC) unit, together with address generation logic, which allows it to index vector elements held in local memory.

The unit includes support for circular buffers on input and output, which allows digital filters to be implemented. Both finite and infinite impulse response filters can be realized.

The unit allows frequent or lengthy filtering operations to be offloaded from the CPU, freeing up the processor for other tasks. In many cases it can accelerate such calculations compared to a software implementation, resulting in a speed-up of time critical tasks.

CORDIC features

• 24-bit CORDIC rotation engine

• Circular and Hyperbolic modes

• Rotation and Vectoring modes

• Functions: Sine, Cosine, Sinh, Cosh, Atan, Atan2, Atanh, Modulus, Square root,

Natural logarithm

• Programmable precision up to 20-bit

• Fast convergence: 4 bits per clock cycle

• Supports 16-bit and 32-bit fixed point input and output formats

• Low latency AHB slave interface

• Results can be read as soon as ready without polling or interrupt

• DMA read and write channels

26/276 DS13311 Rev 2

STM32H725xE/G Functional overview

3.6 Filter mathematical accelerator (FMAC)

The unit includes support for circular buffers on input and output, which allows digital filters to be implemented. Both finite and infinite impulse response filters can be realized.

FMAC features

• 16 x 16-bit multiplier

• 24+2-bit accumulator with addition and subtraction

• 16-bit input and output data

• 256 x 16-bit local memory

• Up to three areas can be defined in memory for data buffers (two input, one output),

defined by programmable base address pointers and associated size registers

• Input and output sample buffers can be circular

• Buffer “watermark” feature reduces overhead in interrupt mode

• Filter functions: FIR, IIR (direct form 1)

• AHB slave interface

• DMA read and write data channels

3.7 Power supply management

3.7.1 Power supply scheme

STM32H725xE/G power supply voltages are the following:

• V

= 1.62 to 3.6 V: external power supply for I/Os, provided externally through V

pins.

= 1.62 to 3.6 V: supply voltage for the internal regulator supplying V

DDLDO

= 1.62 to 3.6 V: external analog power supplies for ADC, DAC, COMP and

DDA

OPAMP.

DD33USB

USB transceiver with 3.3V on V

DD50USB

: allows the support of a VDD supply different from 3.3 V while powering the

DD33USB

can be supplied through the USB cable to generate the V

USB internal regulator. This allows support of a V

The USB regulator can be bypassed to supply directly V

= 1.2 to 3.6 V: power supply for the VSW domain when VDD is not present.

BAT

CAP

: V

supply voltage, which values depend on voltage scaling (1.0 V, 1.1 V,

CORE

1.2 V or 1.35 V). They are configured through VOS bits in PWR_D3CR register. The

CORE

supply different to 3.3 V.

DD33USB

if VDD = 3.3 V.

via the

DS13311 Rev 2 27/276

Functional overview STM32H725xE/G

MSv47490V1

0.3

BOR0

3.6

Operating modePower-on Power-down time

DDX

(1)

Invalid supply area V

DDX

< V

+ 300 mV

DDX

independent from V

domain is split into the following power domains that can be independently

CORE

switch off.

– D1 domain containing some peripherals and the Cortex

-M7 core

– D2 domain containing a large part of the peripherals

– D3 domain containing some peripherals and the system control

• VDDSMPS= 1.62 V to 3.6 V: SMPS step-down converter power supply VDDSMPS must be kept at the same voltage level as VDD

• VLXSMPS = SMPS step-down converter output coupled to an inductor

• VFBSMPS = VCORE or 1.8 V or 2.5 V external SMPS step-down converter feedback

voltage sense input.

During power-up and power-down phases, the following power sequence requirements must be respected (see Figure 2):

• When V remain below V

• When V

During the power-down phase, V

is below 1 V, other power supplies (V

is above 1 V, all power supplies are independent.

+ 300 mV.

can temporarily become lower than other supplies only

DDA

, V

DD33USB

, V

DD50USB

) must

if the energy provided to the microcontroller remains below 1 mJ. This allows external decoupling capacitors to be discharged with different time constants during the power-down transient phase.

Figure 2. Power-up/power-down sequence

1. V

refers to any power supply among V

DDx

DDA

, V

DD33USB

, V

DD50USB

28/276 DS13311 Rev 2

STM32H725xE/G Functional overview

3.7.2 Power supply supervisor

The devices have an integrated power-on reset (POR)/ power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry:

• Power-on reset (POR)

The POR supervisor monitors V The devices remain in Reset mode when V

• Power-down reset (PDR)

The PDR supervisor monitors V below a fixed threshold.

The PDR supervisor can be enabled/disabled through PDR_ON pin.

• Brownout reset (BOR)

The BOR supervisor monitors V

2.7 V) can be configured through option bytes. A reset is generated when V below this threshold.

power supply and compares it to a fixed threshold.

power supply. A reset is generated when V

power supply. Three BOR thresholds (from 2.1 to

is below this threshold,

drops

DS13311 Rev 2 29/276

Functional overview STM32H725xE/G

3.7.3 Voltage regulator

The same voltage regulator supplies the 3 power domains (D1, D2 and D3). D1 and D2 can be independently switched off.

Voltage regulator output can be adjusted according to application needs through 6 power supply levels:

• Run mode (VOS0 to VOS3)

– Scale 0: boosted performance

– Scale 1: high performance

– Scale 2: medium performance and consumption

– Scale 3: optimized performance and low-power consumption

• Stop mode (SVOS3 to SVOS5)

– Scale 3: peripheral with wakeup from Stop mode capabilities (UART, SPI, I2C,

LPTIM) are operational

– Scale 4 and 5 where the peripheral with wakeup from Stop mode is disabled. The

peripheral functionality is disabled but wakeup from Stop mode is possible through GPIO or asynchronous interrupt.

3.8 Low-power strategy

There are several ways to reduce power consumption on STM32H725xE/G:

• Decrease the dynamic power consumption by slowing down the system clocks even in Run mode and by individually clock gating the peripherals that are not used.

• Save power when the CPU is idle, by selecting among the available low-power modes according to the user application needs. This allows the best compromise between short startup time and low power consumption to be achieved, according to the available wakeup sources.

The devices feature several low-power modes:

• CSleep (CPU clock stopped)

• CStop (CPU sub-system clock stopped)

• DStop (Domain bus matrix clock stopped)

• Stop (System clock stopped)

• DStandby (Domain powered down)

• Standby (System powered down)

CSleep and CStop low-power modes are entered by the MCU when executing the WFI (Wait for Interrupt) or WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit of the Cortex

A domain can enter low-power mode (DStop or DStandby) when the processor, its subsystem and the peripherals allocated in the domain enter low-power mode.

If part of the domain is not in low-power mode, the domain remains in the current mode.

-Mx core is set after returning from an interrupt service routine.

Finally the system can enter Stop or Standby when all EXTI wakeup sources are cleared and the power domains are in DStop or DStandby mode.

30/276 DS13311 Rev 2

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