ST MICROELECTRONICS STM32G441RBT6 Datasheet

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Arm® Cortex®-M4 32b MCU+FPU, 170 MHz / 213DMIPS, 128 KB Flash,

LQFP48 (7 x 7 mm) LQFP64 (10 x 10 mm) LQFP80 (12 x 12 mm)

LQFP32 (7 x 7 mm)

UFBGA64

(5 x 5 mm)

UFQFPN32 (5 x 5 mm) UFQFPN48 (7 x 7 mm)

WLCSP49 (Pitch 0.4)

FBGA

LQFP100 (14 x 14 mm)

32 KB SRAM, rich analog, math accelerator, AES

Features

• Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait-state execution from Flash memory, frequency up to 170 MHz with 213 DMIPS, MPU, DSP instructions

• Operating conditions: – VDD, VDDA voltage range:

1.71 V to 3.6 V

• Mathematical hardware accelerators – CORDIC for trigonometric functions

acceleration

– FMAC: Filter mathematical accelerator

• Memories – 128 Kbytes of Flash memory with ECC

support, proprietary code readout protection (PCROP), securable memory area, 1 Kbyte OTP

– 22 Kbytes of SRAM, with hardware parity

check implemented on the first 16 Kbytes

– Routine booster: 10 Kbytes of SRAM on

instruction and data bus, with hardware parity check (CCM SRAM)

• Reset and supply management – Power-on/power-down reset

(POR/PDR/BOR) – Programmable voltage detector (PVD) – Low-power modes: sleep, stop, standby

and shutdown

• Clock management –4

to 48 MHz crystal oscillator

– Internal 16 MHz RC with PLL option (± 1%)

• Up to 86 fast I/Os – All mappable on external interrupt vectors – Several I/Os with 5 V tolerant capability

• Interconnect matrix

• 12-channel DMA controller

STM32G441xB

Datasheet - production data

• 2 x ADCs 0.25 µs(up to 23 channels). Resolution up to 16-bit with hardware oversampling, 0 to 3.6 V conversion range

• 4 x 12-bit DAC channels – 2 x buffered external channels 1 MSPS – 2 x unbuffered internal channels 15 MSPS

• 4 x ultra-fast rail-to-rail analog comparators

• 3 x operational amplifiers that can be used in

PGA mode, all terminals accessible

• Internal voltage reference buffer (VREFBUF) supporting three output voltages (2.048 V,

2.5 V, 2.95 V)

• 14 timers: – 1 x 32-bit timer and 2 x 16-bit timers with up

to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input

– 2 x 16-bit 8-channel advanced motor

control timers, with up to 8 x PWM channels, dead time generation and emergency stop

– 1 x 16-bit timer with 2 x IC/OCs, one

OCN/PWM, dead time generation and emergency stop

– 2 x 16-bit timers with IC/OC/OCN/PWM,

dead time generation and emergency stop – 2 x watchdog timers (independent, window) – 1 x SysTick timer: 24-bit downcounter – 2 x 16-bit basic timers – 1 x low-power timer

• Calendar RTC with alarm, periodic wakeup from stop/standby

May 2019 DS12960 Rev 1 1/192

This is information on a product in full production.

www.st.com

STM32G441xB

• Communication interfaces – 1 x FDCAN controller supporting flexible

data rate

– 3 x I

C Fast mode plus (1 Mbit/s) with 20 mA current sink, SMBus/PMBus, wakeup from stop

– 4 x USART/UARTs (ISO 7816 interface,

LIN, IrDA, modem control)

–1 x LPUART – 3 x SPIs, 4 to 16 programmable bit frames,

2 x with multiplexed half duplex I

interface

– 1 x SAI (serial audio interface)

– USB 2.0 full-speed interface with LPM and

BCD support – IRTIM (infrared interface) – USB Type-C™ /USB power delivery

controller (UCPD)

• True random number generator (RNG)

• CRC calculation unit, 96-bit unique ID

• AES: 128/256-bit key encryption hardware

accelerator

• Development support: serial wire debug (SWD), JTAG, Embedded trace macrocell™

Table 1. Device summary

Reference Part number

STM32G441xB STM32G441CB, STM32G441KB, STM32G441RB, STM32G441MB, STM32G441VB

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STM32G441xB Contents

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1 Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.2 Adaptive real-time memory accelerator (ART accelerator) . . . . . . . . . . . 17

3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.6 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.7 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.8 CORDIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.9 Filter mathematical accelerator (FMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.10 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 21

3.11 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.11.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.11.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.11.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.11.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.11.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.11.6 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.12 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.13 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.14 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.15 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.16 DMA request router (DMAMux) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.17 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.17.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 28

3.17.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 28

3.18 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.18.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

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Contents STM32G441xB

3.18.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.18.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.19 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.20 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.21 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.22 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.23 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.24 Advanced encryption standard hardware accelerator (AES) . . . . . . . . . . 32

3.25 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.25.1 Advanced motor control timer (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . 34

3.25.2 General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16,

TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.25.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.25.4 Low-power timer (LPTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.25.5 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.25.6 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.25.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.26 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 37

3.27 Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.28 Infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.29 Inter-integrated circuit interface (I

C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.30 Universal synchronous/asynchronous receiver transmitter (USART) . . . 40

3.31 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 41

3.32 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.33 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.33.1 SAI peripheral supports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.34 Controller area network (FDCAN1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.35 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.36 USB Type-C™ / USB Power Delivery controller (UCPD) . . . . . . . . . . . . . 43

3.37 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.38 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.38.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.38.2 Embedded trace macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4/192 DS12960 Rev 1

STM32G441xB Contents

4.1 UFQFPN32 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4.2 LQFP32 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4.3 UFQFPN48 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.4 LQFP48 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.5 WLCSP49 ballout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4.6 LQFP80 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4.7 UFBGA64 ballout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.8 Pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

4.9 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 72

5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 72

5.3.4 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

5.3.6 Wakeup time from low-power modes and voltage scaling

transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

5.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 102

5.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 107

5.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

5.3.10 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

5.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

5.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

5.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

5.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

DS12960 Rev 1 5/192

Contents STM32G441xB

5.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

5.3.16 Extended interrupt and event controller input (EXTI) characteristics . . 121

5.3.17 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

5.3.18 Analog-to-digital converter characteristics . . . . . . . . . . . . . . . . . . . . . . 122

5.3.19 Digital-to-Analog converter characteristics . . . . . . . . . . . . . . . . . . . . . 133

5.3.20 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 140

5.3.21 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

5.3.22 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 144

5.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

5.3.24 V

5.3.25 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

5.3.26 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 150

5.3.27 UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

BAT

6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

6.1 UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

6.2 LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

6.3 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

6.4 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

6.5 WLCSP49 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

6.6 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

6.7 LQFP80 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

6.8 UFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

6.9 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

6.10 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

6.10.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

6.10.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 188

7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

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STM32G441xB List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2. STM32G441xB features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 3. STM32G441xB peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 4. DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 5. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 6. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 7. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 8. I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 9. USART/UART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 10. SAI implementation for the features implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 11. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 12. STM32G441xB pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 13. Alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 14. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 15. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 16. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 17. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 18. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 19. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 20. Embedded internal voltage reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 21. Current consumption in Run and Low-power run modes, code with data

processing running from Flash in single Bank, ART enable (Cache ON Prefetch OFF) . . 76

Table 22. Current consumption in Run and Low-power run modes,

code with data processing running from Flash in single Bank, ART disable . . . . . . . . . . . 78

Table 23. Current consumption in Run and Low-power run modes,

code with data processing running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 24. Typical current consumption in Run and Low-power run modes, with different codes

running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . . 82

Table 25. Typical current consumption in Run and Low-power run modes,

with different codes running from Flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 26. Typical current consumption in Run and Low-power run modes, with different codes

running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 27. Typical current consumption in Run and Low-power run modes, with different codes

running from SRAM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 28. Typical current consumption in Run and Low-power run modes, with different codes

running from CCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 29. Current consumption in Sleep and Low-power sleep mode Flash ON . . . . . . . . . . . . . . . . 87

Table 30. Current consumption in low-power sleep modes, Flash in power-down . . . . . . . . . . . . . . . 88

Table 31. Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 32. Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 33. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 34. Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 35. Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 36. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 37. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Table 38. Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 39. Wakeup time using USART/LPUART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 40. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

DS12960 Rev 1 7/192

List of tables STM32G441xB

Table 41. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 42. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 43. LSE oscillator characteristics (f

= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

LSE

Table 44. HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 45. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 46. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 47. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Table 48. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table 49. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table 50. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Table 51. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 52. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 53. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 54. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 55. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Table 56. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 57. I/O (except FT_c) AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Table 58. I/O FT_c AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Table 59. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Table 60. EXTI input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Table 61. Analog switches booster characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Table 62. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 63. Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Table 64. ADC accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Table 65. ADC accuracy - limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Table 66. ADC accuracy - limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Table 67. DAC 1MSPS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Table 68. DAC 1MSPS accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Table 69. DAC 15MSPS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Table 70. DAC 15MSPS accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Table 71. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Table 72. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Table 73. OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Table 74. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Table 75. V Table 76. V

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

BAT

charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

BAT

Table 77. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Table 78. IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Table 79. WWDG min/max timeout value at 170 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Table 80. Minimum I2CCLK frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Table 81. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Table 82. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Table 83. I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Table 84. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Table 85. USB electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Table 86. USART electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Table 87. UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Table 88. UFQFPN - 32 pins, 5 x 5 mm, 0.5 mm pitch ultra thin fine pitch quad flat

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Table 89. LQFP - 32-pin, 7 x 7 mm low-profile quad flat package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Table 90. UFQFPN - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat

8/192 DS12960 Rev 1

STM32G441xB List of tables

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Table 91. LQFP - 48 pins, 7 x 7 mm low-profile quad flat package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Table 92. WLCSP - 49 balls, 3.15 x 3.13 mm, 0.4 mm pitch, wafer level chip scale

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Table 93. WLCSP49 recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Table 94. LQFP - 64 pins, 10 x 10 mm low-profile quad flat

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Table 95. LQFP - 80 pins, 12 x 12 mm low-profile quad flat package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Table 96. UFBGA – 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid

array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Table 97. UFBGA64 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . 182

Table 98. LQPF - 100 pins, 14 x 14 mm low-profile quad flat package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Table 99. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Table 100. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Table 101. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

DS12960 Rev 1 9/192

List of figures STM32G441xB

List of figures

Figure 1. STM32G441xB block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 2. Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 3. Voltage reference buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 4. Infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 5. STM32G441xB UFQFPN32 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 6. STM32G441xB LQFP32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 7. STM32G441xB UFQFPN48 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 8. STM32G441xB LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 9. STM32G441xB WLCSP49 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 10. STM32G441xB LQFP80 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 11. STM32G441xB UFBGA64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 12. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 13. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 14. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 15. Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 16. VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 17. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Figure 18. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Figure 19. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Figure 20. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 21. HSI16 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 22. HSI48 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Figure 23. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 24. I/O AC characteristics definition

Figure 25. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 26. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Figure 27. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Figure 28. 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Figure 29. VREFOUT_TEMP in case VRS = 00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Figure 30. VREFOUT_TEMP in case VRS = 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Figure 31. VREFOUT_TEMP in case VRS = 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Figure 32. OPAMP noise density @ 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Figure 33. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Figure 34. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Figure 35. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Figure 36. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Figure 37. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Figure 38. UFQFPN - 32 pins, 5 x 5 mm, 0.5 mm pitch ultra thin fine pitch quad flat

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Figure 39. UFQFPN - 32 pins, 5 x 5 mm, 0.5 mm pitch ultra thin fine pitch quad flat

package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Figure 40. LQFP - 32-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . 163

Figure 41. LQFP - 32-pin, 7 x 7 mm low-profile quad flat package

recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Figure 42. LQFP32, 7 x 7 mm, low-profile quad flat package top view example . . . . . . . . . . . . . . . 166

Figure 43. UFQFPN - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Figure 44. UFQFPN - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

10/192 DS12960 Rev 1

STM32G441xB List of figures

package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Figure 45. LQFP - 48 pins, 7 x 7 mm low-profile quad flat package outline. . . . . . . . . . . . . . . . . . . . 169

Figure 46. LQFP - 48 pins, 7 x 7 mm low-profile quad flat package

recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Figure 47. LQFP48, 7 x 7 mm, low-profile quad flat package top view example . . . . . . . . . . . . . . . . 172

Figure 48. WLCSP - 49 balls, 3.15 x 3.13 mm, 0.4 mm pitch, wafer level chip scale

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Figure 49. WLCSP - 49 balls, 3.14x 3.15 mm, 0.4 mm pitch, wafer level chip scale

recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Figure 50. LQFP - 64 pins, 10 x 10 mm low-profile quad flat package outline. . . . . . . . . . . . . . . . . . 176

Figure 51. LQFP - 64 pins, 10 x 10 mm low-profile quad flat package

recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Figure 52. LQFP64, 10 x 10 mm, low-profile quad flat package top view example . . . . . . . . . . . . 178

Figure 53. LQFP - 80 pins, 12 x 12 mm low-profile quad flat package outline. . . . . . . . . . . . . . . . . . 179

Figure 54. LQFP - 80 pins, 12 x 12 mm low-profile quad flat package

recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Figure 55. UFBGA – 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid

array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Figure 56. UFBGA – 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid

array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Figure 57. LQFP - 100 pins, 14 x 14 mm low-profile quad flat package outline. . . . . . . . . . . . . . . . . 183

Figure 58. LQFP - 100 pins, 14 x 14 mm low-profile quad flat

recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Figure 59. LQFP100 - 14 x 14 mm, low-profile quad flat package top view example . . . . . . . . . . . . 185

DS12960 Rev 1 11/192

Introduction STM32G441xB

1 Introduction

This datasheet provides the ordering information and mechanical device characteristics of

the STM32G441xB microcontrollers.

This document should be read in conjunction with the reference manual RM0440

“STM32G4 Series advanced Arm

32-bit MCUs”. The reference manual is available from

the STMicroelectronics website www.st.com.

For information on the Arm

®(a)

Cortex®-M4 core, refer to the Cortex®-M4 technical

reference manual, available from the www.arm.com website.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

12/192 DS12960 Rev 1

STM32G441xB Description

2 Description

The STM32G441xB devices are based on the high-performance Arm® Cortex®-M4 32-bit

RISC core. They operate at a frequency of up to 170 MHz.

The Cortex-M4 core features a single-precision floating-point unit (FPU), which supports all

the Arm single-precision data-processing instructions and all the data types. It also

implements a full set of DSP (digital signal processing) instructions and a memory protection

unit (MPU) which enhances the application’s security.

These devices embed high-speed memories (128 Kbytes of Flash memory, and 32 Kbytes

of SRAM), an extensive range of enhanced I/Os and peripherals connected to two APB

buses, two AHB buses and a 32-bit multi-AHB bus matrix.

The devices also embed several protection mechanisms for embedded Flash memory and

SRAM: readout protection, write protection, securable memory area and proprietary code

readout protection.

The devices embed peripherals allowing mathematical/arithmetic function acceleration

(CORDIC for trigonometric functions and FMAC unit for filter functions).

They offer two fast 12-bit ADCs (5 Msps), four comparators, three operational amplifiers,

four DAC channels (2 external and 2 internal), an internal voltage reference buffer, a low-

power RTC, one general-purpose 32-bit timers, two 16-bit PWM timers dedicated to motor

control, seven general-purpose 16-bit timers, and one 16-bit low-power timer.

They also feature standard and advanced communication interfaces such as:

• Three I2Cs

• Three SPIs multiplexed with two half duplex I2Ss

• Three USARTs, one UART and one low-power UART.

• One FDCAN

• One SAI

• USB device

• UCPD

The STM32G441xB devices embed an AES.

The devices operate in the -40 to +85 °C (+105 °C junction), -40 to +105 °C (+125 °C

junction) and -40 to +125 °C (+130 °C junction) temperature ranges from a 1.71 to 3.6 V

power supply. A comprehensive set of power-saving modes allows the design of low-power

applications.

Some independent power supplies are supported including an analog independent supply

input for ADC, DAC, OPAMPs and comparators. A VBAT input allows backup of the RTC

and the registers.

The STM32G441xB family offers 9 packages from 32-pin to 100-pin.

DS12960 Rev 1 13/192

Description STM32G441xB

Table 2. STM32G441xB features and peripheral counts

Peripheral STM32G441KB STM32G441CB STM32G441RB STM32G441MB STM32G441VB

Flash memory 128 Kbytes 128 Kbytes 128 Kbytes 128 Kbytes 128 Kbytes

SRAM 32 (16 + 6 + 10) Kbytes

Advanced motor

2 (16-bit)

control

General purpose

5 (16-bit) 1 (32-bit)

Basic 2 (16-bit)

Timers

Low power 1 (16-bit)

SysTick timer

Watchdog timers (independe

nt, window)

SPI(I2S)

(1)

C2 3

3 (2)

USART 2 3

UART 0 1 Comm. interfaces

LPUART 1

FDCANs 1

USB device Yes

UCPD Yes

SAI Yes

RTC Yes

Tamper pins 1 2 3

Random number generator

Yes

AES Yes

CORDIC Yes

FMAC Yes

GPIOs

Wakeup pins

38 in LQFP48

42 in

UFQFPN48

14/192 DS12960 Rev 1

STM32G441xB Description

Table 2. STM32G441xB features and peripheral counts (continued)

Peripheral STM32G441KB STM32G441CB STM32G441RB STM32G441MB STM32G441VB

12-bit ADCs Number of channels

17 in LQFP48

18 in

UFQFPN48

23 23 23

18 in WLCSP49

12-bit DAC Number of channels

Internal voltage reference buffer

4 (2 external + 2 internal)

Yes

Analog comparator 4

Operational amplifiers 3

Max. CPU frequency 150 MHz

Operating voltage 1.71 V to 3.6 V

Operating temperature Ambient operating temperature: -40 to 85 °C / -40 to 105 °C / -40 to 125 °C

Packages

1. The SPI2/3 interfaces can work in an exclusive way in either the SPI mode or the I2S audio mode.

LQFP32/

UFQFPN32

LQFP48/

UFQFPN48

LQFP64/

TFBGA64

LQFP80 LQFP100

DS12960 Rev 1 15/192

GPIO PORT A

AHB/APB2

USART 2MBps

EXT IT. WKUP

140 AFP

USART 2MBps

GPIO PORT B

PB(15:0)

USART 2MBps

GPIO PORT C

PC(15:0)

USART 2MBps

RX, TX, SCK,CTS,

RTS as AF

USART 2MBps

GPIO PORT D

PD(15:0)

USART 2MBps

GPIO PORT E

PE(15:0)

USART 2MBps

SPI 1

MOSI, MISO

SCK, NSS as AF

APB2 60MHzAPB1

4 CH, ETR as AF

TIMER2

4 CH, ETR as AF

TIMER3&4

RX, TX, SCK, CTS, RTS as AF

USART2&3

UART4

MOSI, MISO, SCK

SPI2&3

NSS, as AF

OUT1/OUT2

DAC1

TIMER6

RTC_OUT RTC_TS RTC_TAMPx

OSC_IN

OSC_OUT

VDD, VSS, VDDA, VSSA, RESET

VBAT = 1.55 to 3.6V

AHB/APB1

JTAG & SW

Arm

Cortex-M4

150MHz

S-BUS

ETM

MPU

TRACECK

TRACED(3:0)

JTRST, JTDI,

JTCK/SWCLK

JTDO/SWD, JTDO

GP-DMA2

GP-DMA1

6 Chan

FLASH 128 KB

ACCEL/

CACHE

AHB1

@VDDA

POR / BOR

SUPPLY

@VDD

SUPERVISION

Reset

Int

POR

XTAL OSC

4-48MHz

XTAL 32kHz

RTC

AWU

BKPREG

LSI

Standby Interface

IWDG

@VBAT

@VDD

RESET&

CLOCKCTRL

PLL

VDD = 1.71 to 3.6V VSS

VOLT. REG.

3.3V TO 1.2V

VDD12

POWER MNGT

AHB BUS-MATRIX 5M / 7S

APB2

peripheralclocks

TinyAES

RTC Interface

FPU

WinWATCHDOG

and system

LP timer1

AHB2

SAR ADC2

Ain ADC

SysCfg

CRC

LP_UART1

I2C1&2&3

SCL, SDA, SMBAL as AF

RNG

RNB1

analog

COMP 1,2,3,4

SRAM2 6 KB

PWRCTRL

CAN1

FIFO

RX,TX as AF

Vref_Buf

CRS

6 Chan

SRAM1 16 KB

CCM SRAM 10 KB

DMAMUX

HSI

SAR ADC1

@VDDA

16b trigg

TIMER7

16b trigg

USBPD

PHY

CC1 CC2

HSI48

CH2

USB

Device

PHY

D+ D-

FIFO

I2S half

duplex

CH1

OPAMP

1,2,3

USART 2MBps

GPIO PORT F

PF(10:9,2:0)

DAC3

CH2

CH1

USART 2MBps

GPIO PORT G

PG(10:10)

CORDIC

FMAC

SAI1

FS, SCK, SD,

MCLK as AF

MSv47173V1

irDA

Smcard

irDA

RX, TX, CTS, RTS as AF

RX, TX as AF

OSC32_IN

OSC_OUT

@VDDA

NVIC

I-BUS

D-BUS

PVD, PWM

PA(15:0)

TIMER1

16b PWM

TIMER8

16b PWM

USART 2MBps

CH as AF

TIMER15

16b

USART 2MBps

CH as AF

TIMER16

16b

USART 2MBps

TIMER17

CH as AF16b

16b

4 PWM,4PWM, ETR,BKIN as F

USART1

Smcard

irDA

Description STM32G441xB

Figure 1. STM32G441xB block diagram

Note: AF: alternate function on I/O pins.

16/192 DS12960 Rev 1

STM32G441xB Functional overview

3 Functional overview

3.1 Arm® Cortex®-M4 core with FPU

The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of the MCU implementation, with a reduced pin count and with low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.

The Arm efficiency, delivering the expected high-performance from an Arm core in a memory size usually associated with 8-bit and 16-bit devices.

The processor supports a set of DSP instructions which allows an efficient signal processing and a complex algorithm execution. Its single precision FPU speeds up the software development by using metalanguage development tools to avoid saturation.

With its embedded Arm core, the STM32G441xB family is compatible with all Arm tools and software.

Figure 1 shows the general block diagram of the STM32G441xB devices.

Cortex®-M4 with FPU 32-bit RISC processor features an exceptional code-

3.2 Adaptive real-time memory accelerator (ART accelerator)

The ART accelerator is a memory accelerator that is optimized for the STM32 industrystandard Arm the Arm processor to wait for the Flash memory at higher frequencies.

Cortex®-M4 processors. It balances the inherent performance advantage of

Cortex®-M4 over Flash memory technologies, which normally requires the

3.3 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to the memory and to prevent one task to accidentally corrupt the memory or the resources used by any other active task. This memory area is organized into up to 8 protected areas, which can be divided in up into 8 subareas each. The protection area sizes range between 32 bytes and the whole 4 gigabytes of addressable memory.

The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

3.4 Embedded Flash memory

The STM32G441xB devices feature 128 kbytes of embedded Flash memory which is available for storing programs and data.

Flexible protections can be configured thanks to the option bytes:

DS12960 Rev 1 17/192

Functional overview STM32G441xB

• Readout protection (RDP) to protect the whole memory. Three levels of protection are available:

– Level 0: no readout protection – Level 1: memory readout protection; the Flash memory cannot be read from or written

to if either the debug features are connected or the boot in RAM or bootloader are selected

– Level 2: chip readout protection; the debug features (Cortex-M4 JTAG and serial

wire), the boot in RAM and the bootloader selection are disabled (JTAG fuse). This selection is irreversible.

• Write protection (WRP): the protected area is protected against erasing and

programming.

• Proprietary code readout protection (PCROP): a part of the Flash memory can be

protected against read and write from third parties. The protected area is execute-only and it can only be reached by the STM32 CPU as an instruction code, while all other accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited. An additional option bit (PCROP_RDP) allows to select if the PCROP area is erased or not when the RDP protection is changed from Level 1 to Level 0.

• Securable memory area: a part of Flash memory can be configured by option bytes to

be securable. After reset this securable memory area is not secured and it behaves like the remainder of main Flash memory (execute, read, write access). When secured, any access to this securable memory area generates corresponding read/write error. Purpose of the Securable memory area is to protect sensitive code and data (secure keys storage) which can be executed only once at boot, and never again unless a new reset occurs.

The Flash memory embeds the error correction code (ECC) feature supporting:

• Single error detection and correction

• Double error detection

• The address of the ECC fail can be read in the ECC register

3.5 Embedded SRAM

STM32G441xB devices feature 32 Kbytes of embedded SRAM. This SRAM is split into three blocks:

• 16 Kbytes mapped at address 0x2000 0000 (SRAM1). The CM4 can access the

SRAM1 through the System Bus or through the I-Code/D-Code bus.

• 6 Kbytes mapped at address 0x2000 4000 (SRAM2). The CM4 can access the SRAM2

through the System Bus or through the I-Code/D-Code bus. SRAM2 can be kept in stop andstandby modes.

• 10 Kbytes mapped at address 0x1000 0000 (CCM SRAM). It is accessed by the CPU

through I-Code/D-Code bus for maximum performance. It is also aliased at 0x2000 5800 address to be accessed by all masters (CPU, DMA1, DMA2) through SBUS contiguously to SRAM1 and SRAM2.

18/192 DS12960 Rev 1

STM32G441xB Functional overview

MS47544V1

Cortex®-M4

with FPU

DMA1 DMA2

CCM

SRAM

AHB1

peripherals

AHB2

peripherals

SRAM1

FLASH 128 KB

ACCEL

S-bus

D-bus

ICode

DCode

I-bus

BusMatrix-S

SRAM2

3.6 Multi-AHB bus matrix

The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs) and the slaves (Flash memory, RAM, AHB and APB peripherals). It also ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously.

Figure 2. Multi-AHB bus matrix

3.7 Boot modes

At startup, a BOOT0 pin (or nBOOT0 option bit)and an nBOOT1 option bit are used to select one of three boot options:

• Boot from user Flash

• Boot from system memory

• Boot from embedded SRAM

The BOOT0 value may come from the PB8-BOOT0 pin or from an nBOOT0 option bit depending on the value of a user nBOOT_SEL option bit to free the GPIO pad if needed.

The boot loader is located in the system memory. It is used to reprogram the Flash memory by using USART, I2C, SPI, and USB through the DFU (device firmware upgrade).

DS12960 Rev 1 19/192

Functional overview STM32G441xB

3.8 CORDIC

The CORDIC provides hardware acceleration of certain mathematical functions, notably trigonometric, commonly used in motor control, metering, signal processing and many other applications.

It speeds up the calculation of these functions compared to a software implementation, allowing a lower operating frequency, or freeing up processor cycles in order to perform other tasks.

Cordic features

• 24-bit CORDIC rotation engine

• Circular and Hyperbolic modes

• Rotation and Vectoring modes

• Functions: Sine, Cosine, Sinh, Cosh, Atan, Atan2, Atanh, Modulus, Square root,

Natural logarithm

• Programmable precision up to 20-bit

• Fast convergence: 4 bits per clock cycle

• Supports 16-bit and 32-bit fixed point input and output formats

• Low latency AHB slave interface

• Results can be read as soon as ready without polling or interrupt

• DMA read and write channels

3.9 Filter mathematical accelerator (FMAC)

The filter mathematical accelerator unit performs arithmetic operations on vectors. It comprises a multiplier/accumulator (MAC) unit, together with address generation logic, which allows it to index vector elements held in local memory.

The unit includes support for circular buffers on input and output, which allows digital filters to be implemented. Both finite and infinite impulse response filters can be realized.

The unit allows frequent or lengthy filtering operations to be offloaded from the CPU, freeing up the processor for other tasks. In many cases it can accelerate such calculations compared to a software implementation, resulting in a speed-up of time critical tasks.

20/192 DS12960 Rev 1

STM32G441xB Functional overview

FMAC features

• 16 x 16-bit multiplier

• 24+2-bit accumulator with addition and subtraction

• 16-bit input and output data

• 256 x 16-bit local memory

• Up to three areas can be defined in memory for data buffers (two input, one output),

defined by programmable base address pointers and associated size registers

• Input and output sample buffers can be circular

• Buffer “watermark” feature reduces overhead in interrupt mode

• Filter functions: FIR, IIR (direct form 1)

• AHB slave interface

• DMA read and write data channels

3.10 Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator with polynomial value and size.

Among other applications, the CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a mean to verify the Flash memory integrity.

The CRC calculation unit helps to compute a signature of the software during runtime, which can be ulteriorly compared with a reference signature generated at link-time and which can be stored at a given memory location.

3.11 Power supply management

3.11.1 Power supply schemes

The STM32G441xB devices require a 1.71 V to 3.6 V V independent supplies, can be provided for specific peripherals:

• V

= 1.71 V to 3.6 V

is the external power supply for the I/Os, the internal regulator and the system

analog such as reset, power management and internal clocks. It is provided externally through the VDD pins.

= 1.62 V to 3.6 V (see Section 5: Electrical characteristics for the minimum VDDA

DDA

voltage required for ADC, DAC, COMP, OPAMP, VREFBUF operation). V

is the external analog power supply for A/D converters, D/A converters, voltage

DDA

reference buffer, operational amplifiers and comparators. The V

operating voltage supply. Several

voltage level is

DDA

DS12960 Rev 1 21/192

Functional overview STM32G441xB

independent from the V

these peripherals are not used.

• V

= 1.55 V to 3.6 V

BAT

is the power supply for RTC, external clock 32 kHz oscillator and backup registers

BAT

(through power switch) when V

• V

REF-, VREF+

is the input reference voltage for ADCs and DACs. It is also the output of the

REF+

internal voltage reference buffer when enabled.

When V

DDA

< 2 V V  2 V V

must be equal to V

REF+

must be between 2 V and V

REF+

The internal voltage reference buffer supports three output voltages, which are configured with VRS bits in the VREFBUF_CSR register:

–V

REF-

= 2.048 V

REF+

= 2.5 V

REF+

= 2.95 V

REF+

is double bonded with V

3.11.2 Power supply supervisor

The device has an integrated ultra-low-power brown-out reset (BOR) active in all modes (except for Shutdown mode). The BOR ensures proper operation of the device after poweron and during power down. The device remains in reset mode when the monitored supply voltage V

The lowest BOR level is 1.71 V at power on, and other higher thresholds can be selected through option bytes.The device features an embedded programmable voltage detector (PVD) that monitors the V interrupt can be generated when V higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

is below a specified threshold, without the need for an external reset circuit.

power supply and compares it to the VPVD threshold. An

voltage and should preferably be connected to VDD when

is not present.

DDA

SSA

drops below the VPVD threshold and/or when VDD is

In addition, the device embeds a peripheral voltage monitor which compares the independent supply voltages V

, with a fixed threshold in order to ensure that the

DDA

peripheral is in its functional supply range.

3.11.3 Voltage regulator

Two embedded linear voltage regulators, main regulator (MR) and low-power regulator (LPR), supply most of digital circuitry in the device. The MR is used in Run and Sleep modes. The LPR is used in Low-power run, Low-power sleep and Stop modes. In Standby and Shutdown modes, both regulators are powered down and their outputs set in highimpedance state, such as to bring their current consumption close to zero.

The device supports dynamic voltage scaling to optimize its power consumption in Run mode. the voltage from the main regulator that supplies the logic (VCORE) can be adjusted according to the system’s maximum operating frequency.

The main regulator (MR) operates in the following ranges:

• Range 1 boost mode with the CPU running at up to 170 MHz.

• Range 1 normal mode with CPU running at up to 150 MHz.

• Range 2 with a maximum CPU frequency of 26 MHz.

22/192 DS12960 Rev 1

STM32G441xB Functional overview

3.11.4 Low-power modes

By default, the microcontroller is in Run mode after system or power Reset. It is up to the user to select one of the low-power modes described below:

• Sleep mode: In Sleep mode, only the CPU is stopped. All peripherals continue to

operate and can wake up the CPU when an interrupt/event occurs.

• Low-power run mode: This mode is achieved with VCORE supplied by the low-power

regulator to minimize the regulator's operating current. The code can be executed from SRAM or from Flash, and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can be clocked by HSI16.

• Stop mode: In Stop mode, the device achieves the lowest power consumption while

retaining the SRAM and register contents. All clocks in the VCORE domain are stopped. The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are disabled. The LSE or LSI keep running. The RTC can remain active (Stop mode with RTC, Stop mode without RTC). Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode, so as to get clock for processing the wakeup event.

• Standby mode: The Standby mode is used to achieve the lowest power consumption

with brown-out reset, BOR. The internal regulator is switched off to power down the VCORE domain. The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are also powered down. The RTC can remain active (Standby mode with RTC, Standby mode without RTC). The BOR always remains active in Standby mode. For each I/O, the software can determine whether a pull-up, a pull-down or no resistor shall be applied to that I/O during Standby mode. Upon entering Standby mode, SRAM and register contents are lost except for registers in the RTC domain and standby circuitry. The device exits Standby mode upon external reset event (NRST pin), IWDG reset event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event (alarm, periodic wakeup, timestamp, tamper), or when a failure is detected on LSE (CSS on LSE).

• Shutdown mode: The Shutdown mode allows to achieve the lowest power

consumption. The internal regulator is switched off to power down the VCORE domain. The PLL, as well as the HSI16 and LSI RC-oscillators and HSE crystal oscillator are also powered down. The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC). The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode. Therefore, switching to RTC domain is not supported. SRAM and register contents are lost except for registers in the RTC domain. The device exits Shutdown mode upon external reset event (NRST pin), IWDG reset event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event (alarm, periodic wakeup, timestamp, tamper).

3.11.5 Reset mode

In order to improve the consumption under reset, the I/Os state under and after reset is “analog state” (the I/O schmitt trigger is disabled). In addition, the internal reset pull-up is deactivated when the reset source is internal.

3.11.6 VBAT operation

The VBAT pin allows to power the device VBAT domain from an external battery, an external supercapacitor, or from V supercapacitor is present. The VBAT pin supplies the RTC with LSE and the backup registers. Three anti-tamper detection pins are available in VBAT mode.

when there is no external battery and when an external

DS12960 Rev 1 23/192

Functional overview STM32G441xB

The VBAT operation is automatically activated when VDD is not present. An internal VBAT battery charging circuit is embedded and can be activated when V

is present.

Note: When the microcontroller is supplied from VBAT, neither external interrupts nor RTC

alarm/events exit the microcontroller from the VBAT operation.

24/192 DS12960 Rev 1

STM32G441xB Functional overview

3.12 Interconnect matrix

Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections allow fast and predictable latency.

Depending on peripherals, these interconnections can operate in Run, Sleep and Stop modes.

Table 3. STM32G441xB peripherals interconnect matrix

Interconnect source

TIMx

TIM16/TIM17 IRTIM Infrared interface output generation Y Y Y -

COMPx

ADCx TIM1, 8 Timer triggered by analog watchdog Y Y Y -

RTC

All clocks sources (internal and external)

USB TIM2 Timer triggered by USB SOF Y Y - -

CSS CPU (hard fault) RAM (parity error) Flash memory (ECC error) COMPx PVD

Interconnect

destination

TIMx Timers synchronization or chaining Y Y Y -

ADCx DACx

DMA Memory to memory transfer trigger Y Y Y -

COMPx Comparator output blanking Y Y Y -

TIM1, 8 TIM2, 3, 4

LPTIMER1

TIM16

LPTIMER1

TIM15, 16, 17

TIM1,8 TIM15,16,17

TIMx External trigger Y Y Y -

Conversion triggers Y Y Y -

Timer input channel, trigger, break from analog signals comparison

Low-power timer triggered by analog signals comparison

Timer input channel from RTC events

Low-power timer triggered by RTC alarms or tampers

Clock source used as input channel for RC measurement and trimming

Timer break Y Y Y -

Interconnect action

Run

Sleep

Low-power run

YYY -

YYYY

YYY -

YYYY

YYY -

Stop

GPIO

LPTIMER1 External trigger Y Y Y -

ADCx DACx

DS12960 Rev 1 25/192

Conversion external trigger Y Y Y -

Functional overview STM32G441xB

3.13 Clocks and startup

The clock controller distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. It features:

• Clock prescaler: to get the best trade-off between speed and current consumption,

the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler

• Safe clock switching: clock sources can be changed safely on the fly in run mode

through a configuration register.

• Clock management: to reduce power consumption, the clock controller can stop the

clock to the core, individual peripherals or memory.

• System clock source: three different sources can deliver SYSCLK system clock:

– 4 - 48 MHz high-speed oscillator with external crystal or ceramic resonator (HSE).

It can supply clock to system PLL. The HSE can also be configured in bypass mode for an external clock.

– 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software. It can

supply clock to system PLL.

– System PLL with maximum output frequency of 170 MHz. It can be fed with HSE

or HSI16 clocks.

• RC48 with clock recovery system (HSI48): internal HSIRC48 MHz clock source can

be used to drive the USB or the RNG peripherals.

• Auxiliary clock source: two ultra-low-power clock sources for the real-time clock

(RTC):

– 32.768 kHz low-speed oscillator with external crystal (LSE), supporting four drive

capability modes. The LSE can also be configured in bypass mode for using an external clock.

– 32 kHz low-speed internal RC oscillator (LSI) with ±5% accuracy, also used to

clock an independent watchdog.

• Peripheral clock sources: several peripherals (I2S, USART, I2C, LPTimer, ADC, SAI,

RNG) have their own clock independent of the system clock.

• Clock security system (CSS): in the event of HSE clock failure, the system clock is

automatically switched to HSI16 and, if enabled, a software interrupt is generated. LSE clock failure can also be detected and generate an interrupt.

• Clock-out capability:

– MCO: microcontroller clock output: it outputs one of the internal clocks for external

use by the application

– LSCO: low speed clock output: it outputs LSI or LSE in all low-power modes.

Several prescalers allow to configure the AHB frequency, the High-speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 170 MHz.

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3.14 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be achieved thanks to their mapping on the AHB2 bus.

The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.

3.15 Direct memory access controller (DMA)

The device embeds 2 DMAs. Refer to Table 4: DMA implementation for the features implementation.

Direct memory access (DMA) is used in order to provide a high-speed data transfer between peripherals and memory as well as from memory to memory. Data can be quickly moved by DMA without any CPU actions. This keeps the CPU resources free for other operations.

The two DMA controllers have 12 channels in total, each one dedicated to manage memory access requests from one or more peripherals. Each controller has an arbiter for handling the priority between DMA requests.

The DMA supports:

• 12 independently configurable channels (requests)

– Each channel is connected to a dedicated hardware DMA request, a software

trigger is also supported on each channel. This configuration is done by software.

• Priorities between requests from channels of one DMA are both software

programmable (4 levels: very high, high, medium, low) or hardware programmable in case of equality (request 1 has priority over request 2, etc.)

• Independent source and destination transfer size (byte, half word, word), emulating

packing and unpacking. Source/destination addresses must be aligned on the data size.

• Support for circular buffer management

• 3 event flags (DMA half transfer, DMA transfer complete and DMA transfer error)

logically ORed together in a single interrupt request for each channel

• Memory-to-memory transfer

• Peripheral-to-memory, memory-to-peripheral, and peripheral-to-peripheral transfers

• Access to Flash, SRAM, APB and AHB peripherals as source and destination

• Programmable number of data to be transferred: up to 65536.

DMA features DMA1 DMA2

Number of regular channels 6 6

Table 4. DMA implementation

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Functional overview STM32G441xB

3.16 DMA request router (DMAMux)

When a peripheral indicates a request for DMA transfer by setting its DMA request line, the DMA request is pending until it is served and the corresponding DMA request line is reset. The DMA request router allows to route the DMA control lines between the peripherals and the DMA controllers of the product.

An embedded multi-channel DMA request generator can be considered as one of such peripherals. The routing function is ensured by a multi-channel DMA request line multiplexer. Each channel selects a unique set of DMA control lines, unconditionally or synchronously with events on synchronization inputs.

For simplicity, the functional description is limited to DMA request lines. The other DMA control lines are not shown in figures or described in the text. The DMA request generator produces DMA requests following events on DMA request trigger inputs.

3.17 Interrupts and events

3.17.1 Nested vectored interrupt controller (NVIC)

The STM32G441xB devices embed a nested vectored interrupt controller which is able to manage 16 priority levels, and to handle up to maskable interrupt channels plus the 16 interrupt lines of the Cortex

-M4.

The NVIC benefits are the following:

• Closely coupled NVIC gives low latency interrupt processing

• Interrupt entry vector table address passed directly to the core

• Allows early processing of interrupts

• Processing of late arriving higher priority interrupts

• Support for tail chaining

• Processor state automatically saved

• Interrupt entry restored on interrupt exit with no instruction overhead

The NVIC hardware block provides flexible interrupt management features with minimal interrupt latency.

3.17.2 Extended interrupt/event controller (EXTI)

The extended interrupt/event controller consists of 39 edge detector lines used to generate interrupt/event requests and to wake-up the system from the Stop mode. Each external line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently.

A pending register maintains the status of the interrupt requests. The internal lines are connected to peripherals with wakeup from Stop mode capability. The EXTI can detect an external line with a pulse width shorter than the internal clock period. Up to 86 GPIOs can be connected to the 16 external interrupt lines.

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3.18 Analog-to-digital converter (ADC)

The device embeds two successive approximation analog-to-digital converters with the following features:

• 12-bit native resolution, with built-in calibration

• 4 Msps maximum conversion rate with full resolution

– Down to 25 ns sampling time

– Increased conversion rate for lower resolution (up to 6.66 Msps for 6-bit

resolution)

• One external reference pin is available on all packages, allowing the input voltage

range to be independent from the power supply

• Single-ended and differential mode inputs

• Low-power design

– Capable of low-current operation at low conversion rate (consumption decreases

linearly with speed)

– Dual clock domain architecture: ADC speed independent from CPU frequency

• Highly versatile digital interface

– Single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups

of analog signals conversions can be programmed to differentiate background and high-priority real-time conversions

– Each ADC support multiple trigger inputs for synchronization with on-chip timers

and external signals

– Results stored into a data register or in RAM with DMA controller support

– Data pre-processing: left/right alignment and per channel offset compensation

– Built-in oversampling unit for enhanced SNR

– Channel-wise programmable sampling time

– Analog watchdog for automatic voltage monitoring, generating interrupts and

trigger for selected timers

– Hardware assistant to prepare the context of the injected channels to allow fast

context switching

– Flexible sample time control

– Hardware gain and offset compensation

3.18.1 Temperature sensor

The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature. The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only.

To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode.

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Functional overview STM32G441xB

Calibration value name Description Memory address

TS_CAL1

TS_CAL2

Table 5. Temperature sensor calibration values

TS ADC raw data acquired at a temperature of 30 °C (± 5 °C), V

DDA

TS ADC raw data acquired at a temperature of 110 °C (± 5 °C), V

DDA

3.18.2 Internal voltage reference (V

The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC and the comparators. The VREFINT is internally connected to the ADC1_IN18 input channel. The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode.

Calibration value name Description Memory address

Table 6. Internal voltage reference calibration values

Raw data acquired at a

VREFINT

temperature of 30 °C (± 5 °C), V

DDA

= V

REF+

= V

REF+

REFINT

= V

REF+

0x1FFF 75A8 - 0x1FFF 75A9

= 3.0 V (± 10 mV)

0x1FFF 75CA - 0x1FFF 75CB

= 3.0 V (± 10 mV)

)

0x1FFF 75AA - 0x1FFF 75AB

= 3.0 V (± 10 mV)

3.18.3 V

battery voltage monitoring

BAT

This embedded hardware enables the application to measure the V the internal ADC1_IN17 channel. As the V

voltage may be higher than the VDDA, and

BAT

thus outside the ADC input range, the VBAT pin is internally connected to a bridge divider by

3. As a consequence, the converted digital value is one third of the V

3.19 Digital to analog converter (DAC)

Four 12 bit DAC channels (2 external buffered and 2 internal unbuffered) can be used to convert digital signals into analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration.

battery voltage using

BAT

voltage.

BAT

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MSv40197V1

VREFBUF

Low frequency cut-off capacitor

DAC, ADC

Bandgap +

DDA

100 nF

VREF+

This digital interface supports the following features:

• Up to two DAC output channels

• 8-bit or 12-bit output mode

• Buffer offset calibration (factory and user trimming)

• Left or right data alignment in 12-bit mode

• Synchronized update capability

• Noise-wave generation

• Triangular-wave generation

• Saw tooth wave generation

• Dual DAC channel independent or simultaneous conversions

• DMA capability for each channel

• External triggers for conversion

• Sample and hold low-power mode, with internal or external capacitor

• Up to 1 Msps for external output and 15 Msps for internal output

The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels.

3.20 Voltage reference buffer (V

The STM32G441xB devices embed a voltage reference buffer which can be used as voltage reference for ADC, DACs and also as voltage reference for external components through the VREF+ pin.

The internal voltage reference buffer supports three voltages:

• 2.048 V

• 2.5 V

• 2.95 V

An external voltage reference can be provided through the VREF+ pin when the internal voltage reference buffer is off.

Figure 3. Voltage reference buffer

REFBUF

)

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Functional overview STM32G441xB

3.21 Comparators (COMP)

The STM32G441xB devices embed four rail-to-rail comparators with programmable reference voltage (internal or external), hysteresis.

The reference voltage can be one of the following:

• External I/O

• DAC output channels

• Internal reference voltage or submultiple (1/4, 1/2, 3/4).

All comparators can wake up from Stop mode, generate interrupts and breaks for the timers.

3.22 Operational amplifier (OPAMP)

The STM32G441xB devices embed three operational amplifiers with external or internal follower routing and PGA capability.

The operational amplifier features:

• 15 MHz bandwidth

• Rail-to-rail input/output

• PGA with a non-inverting gain ranging of 2, 4, 8, 16, 32 or 64 or inverting gain ranging

of -1, -3, -7, -15, -31 or -63

3.23 Random number generator (RNG)

All devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit.

3.24 Advanced encryption standard hardware accelerator (AES)

The STM32G441xB devices embed an AES hardware accelerator that can be used both to encipher and to decipher data using an AES algorithm.

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The AES peripheral supports:

• Encryption/decryption using AES Rijndael block cipher algorithm

• NIST FIPS 197 compliant implementation of AES encryption/decryption algorithm

• 128-bit and 256-bit register for storing the encryption, decryption or derivation key (4x

32-bit registers)

• Electronic codebook (ECB), cipher block chaining (CBC), Counter mode (CTR), Galois

Counter Mode (GCM), Galois Message Authentication Code mode (GMAC) and Cipher Message Authentication Code mode (CMAC) supported

• Key scheduler

• Key derivation for decryption

• 128-bit data block processing

• 128-bit, 256-bit key length

• 1x32-bit INPUT buffer and 1x32-bit OUTPUT buffer

• Register access supporting 32-bit data width only

• One 128-bit Register for the initialization vector when AES is configured in CBC mode

or for the 32-bit counter initialization when CTR mode is selected, GCM mode or CMAC mode

• Automatic data flow control with support of direct memory access (DMA) using 2

channels, one for incoming data, and one for outcoming data

• Suspend a message if another message with a higher priority needs to be processed.

3.25 Timers and watchdogs

The STM32G441xB devices include two advanced motor control timers, up to six generalpurpose timers, two basic timers, one low-power timer, two watchdog timers and a SysTick timer. The table below compares the features of the advanced motor control, general purpose and basic timers.

Timer type Timer

Advanced

motor

control

General-

purpose

General-

purpose

General-

purpose

TIM1, TIM8 16-bit

TIM2 32-bit

TIM3, TIM4 16-bit

TIM15 16-bit Up

Table 7. Timer feature comparison

Counter

resolution

Counter

type

Up,

down,

Up/down

Up,

down,

Up/down

Up,

down,

Up/down

Prescaler

factor

Any integer

between 1 and

65536

Any integer

between 1 and

65536

Any integer

between 1 and

65536

Any integer

between 1 and

65536

DMA

request

generation

Yes 4 4

Yes 4 No

Yes 2 1

Capture/ compare

channels

Complementary

outputs

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Table 7. Timer feature comparison (continued)

Timer type Timer

General-

purpose

Basic TIM6, TIM7 16-bit Up

TIM16, TIM17 16-bit Up

Counter

resolution

Counter

type

Prescaler

factor

Any integer

between 1 and

65536

Any integer

between 1 and

65536

generation

3.25.1 Advanced motor control timer (TIM1, TIM8)

The advanced motor control timers can each be seen as a four-phase PWM multiplexed on 8 channels. They have complementary PWM outputs with programmable inserted dead-times. They can also be seen as complete general-purpose timers.

The 4 independent channels can be used for:

• Input capture

• Output compare

• PWM generation (edge or center-aligned modes) with full modulation capability

(0-100%)

• One-pulse mode output

DMA

request

Yes 1 1

Yes 0 No

Capture/ compare

channels

Complementary

outputs

In debug mode, the advanced motor control timer counter can be frozen and the PWM outputs disabled in order to turn off any power switches driven by these outputs.

Many features are shared with the general-purpose TIMx timers (described in

Section 3.25.2) using the same architecture, so the advanced motor control timers can work

together with the TIMx timers via the Timer Link feature for synchronization or event chaining.

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3.25.2 General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16, TIM17)

There are up to six synchronizable general-purpose timers embedded in the STM32G441xB devices (see Table 7 for differences). Each general-purpose timer can be used to generate PWM outputs, or act as a simple time base.

• TIM2, TIM3, and TIM4

They are full-featured general-purpose timers:

– TIM2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler

– TIM3 and TIM4 have 16-bit auto-reload up/downcounter and 16-bit prescaler.

These timers feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. They can work together, or with the other general-purpose timers via the Timer Link feature for synchronization or event chaining.

The counters can be frozen in debug mode.

All have independent DMA request generation and support quadrature encoders.

• TIM15, 16 and 17

They are general-purpose timers with mid-range features:

They have 16-bit auto-reload upcounters and 16-bit prescalers.

– TIM15 has 2 channels and 1 complementary channel

– TIM16 and TIM17 have 1 channel and 1 complementary channel

All channels can be used for input capture/output compare, PWM or one-pulse mode output.

The timers can work together via the Timer Link feature for synchronization or event chaining. The timers have independent DMA request generation.

The counters can be frozen in debug mode.

3.25.3 Basic timers (TIM6 and TIM7)

The basic timers are mainly used for DAC trigger generation. They can also be used as generic 16-bit timebases.

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Functional overview STM32G441xB

3.25.4 Low-power timer (LPTIM1)

The devices embed a low-power timer. This timer has an independent clock and are running in Stop mode if it is clocked by LSE, LSI or an external clock. It is able to wakeup the system from Stop mode.

LPTIM1 is active in Stop mode.

This low-power timer supports the following features:

• 16-bit up counter with 16-bit autoreload register

• 16-bit compare register

• Configurable output: pulse, PWM

• Continuous/ one shot mode

• Selectable software/hardware input trigger

• Selectable clock source

– Internal clock sources: LSE, LSI, HSI16 or APB clock

– External clock source over LPTIM input (working even with no internal clock

source running, used by pulse counter application).

• Programmable digital glitch filter

• Encoder mode

3.25.5 Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and an 8-bit prescaler. It is clocked from an independent 32 kHz internal RC (LSI) and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.

3.25.6 System window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

3.25.7 SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features:

• A 24-bit down counter

• Autoreload capability

• Maskable system interrupt generation when the counter reaches 0.

• Programmable clock source

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3.26 Real-time clock (RTC) and backup registers

The RTC supports the following features:

• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,

month, year, in BCD (binary-coded decimal) format.

• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.

• Two programmable alarms.

• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to

synchronize it with a master clock.

• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be

used to enhance the calendar precision.

• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal

inaccuracy.

• Timestamp feature which can be used to save the calendar content. This function can

be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to VBAT mode.

• 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable

resolution and period.

The RTC is supplied through a switch that takes power either from the V present or from the VBAT pin.

The RTC clock sources can be:

• A 32.768 kHz external crystal (LSE)

• An external resonator or oscillator (LSE)

• The internal low power RC oscillator (LSI, with typical frequency of 32 kHz)

• The high-speed external clock (HSE) divided by 32.

The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in all low-power modes except Shutdown mode.

All RTC events (Alarm, WakeUp Timer, Timestamp) can generate an interrupt and wakeup the device from the low-power modes.

3.27 Tamper and backup registers (TAMP)

• 16 32-bit backup registers, retained in all low-power modes and also in VBAT mode.

They can be used to store sensitive data as their content is protected by an tamper detection circuit. They are not reset by a system or power reset, or when the device wakes up from Standby or Shutdown mode.

• Up to three tamper pins for external tamper detection events. The external tamper pins

can be configured for edge detection, edge and level, level detection with filtering.

• Five internal tampers events.

• Any tamper detection can generate a RTC timestamp event.

• Any tamper detection erases the backup registers.

• Any tamper detection can generate an interrupt and wake-up the device from all low-

power modes.

supply when

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Functional overview STM32G441xB

3.28 Infrared transmitter

The STM32G441xB devices provide an infrared transmitter solution. The solution is based on internal connections between TIM16 and TIM17 as shown in the figure below.

TIM17 is used to provide the carrier frequency and TIM16 provides the main signal to be sent. The infrared output signal is available on PB9 or PA13.

To generate the infrared remote control signals, TIM16 channel 1 and TIM17 channel 1 must be properly configured to generate correct waveforms. All standard IR pulse modulation modes can be obtained by programming the two timers output compare channels.

Figure 4. Infrared transmitter

TIM17_CH1

TIM16_CH1

IRTIM

IR_OUT

MS30474V2

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3.29 Inter-integrated circuit interface (I2C)

The device embeds three I2Cs. Refer to Table 8: I2C implementation for the features implementation.

The I

C bus interface handles communications between the microcontroller and the serial

C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.

The I2C peripheral supports:

• I

C-bus specification and user manual rev. 5 compatibility:

– Slave and master modes, multimaster capability

– Standard-mode (Sm), with a bitrate up to 100 kbit/s

– Fast-mode (Fm), with a bitrate up to 400 kbit/s

– Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os

– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses

– Programmable setup and hold times

– Optional clock stretching

• System management bus (SMBus) specification rev 2.0 compatibility:

– Hardware PEC (packet error checking) generation and verification with ACK

control

– Address resolution protocol (ARP) support

– SMBus alert

• Power system management protocol (PMBus

• Independent clock: a choice of independent clock sources allowing the I2C

communication speed to be independent from the PCLK reprogramming.

• Wakeup from Stop mode on address match

• Programmable analog and digital noise filters

• 1-byte buffer with DMA capability

Table 8. I2C implementation

I2C features

(1)

) specification rev 1.1 compatibility

I2C1 I2C2 I2C3

Standard-mode (up to 100 kbit/s) X X X

Fast-mode (up to 400 kbit/s) X X X

Fast-mode Plus with 20mA output drive I/Os (up to 1 Mbit/s) X X X

Programmable analog and digital noise filters X X X

SMBus/PMBus hardware support X X X

Independent clock X X X

Wakeup from Stop mode on address match X X X

1. X: supported

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Functional overview STM32G441xB

3.30 Universal synchronous/asynchronous receiver transmitter (USART)

The STM32G441xB devices have three embedded universal synchronous receiver transmitters (USART1, USART2 and USART3) and one universal asynchronous receiver transmitters (UART4).

These interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN master/slave capability. They provide hardware management of the CTS and RTS signals, and RS485 driver enable.

The USART1, USART2 and USART3 also provide a Smartcard mode (ISO 7816 compliant) and an SPI-like communication capability.

The USART comes with a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO mode is enabled by software and is disabled by default.

All USART have a clock domain independent from the CPU clock, allowing the USARTx (x=1,2,3,4) to wake up the MCU from Stop mode. The wakeup from Stop mode can be done on:

• Start bit detection

• Any received data frame

• A specific programmed data frame

• Some specific TXFIFO/RXFIFO status interrupts when FIFO mode is enabled

All USART interfaces can be served by the DMA controller.

USART modes/features

Hardware flow control for modem X X X X X

Continuous communication using DMA X X X X X

Multiprocessor communication X X X X X

Synchronous mode X X X - -

Smartcard mode X X X - -

Single-wire half-duplex communication X X X X X

IrDA SIR ENDEC block X X X X -

LIN mode X X X X -

Dual clock domain X X X X X

Wakeup from Stop mode X X X X X

Receiver timeout interrupt X X X X -

Modbus communication X X X X -

Auto baud rate detection X (4 modes) -

Driver Enable X X X X X

LPUART/USART data length 7, 8 and 9 bits

Table 9. USART/UART/LPUART features

(1)

USART1 USART2 USART3 UART4 LPUART1

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Table 9. USART/UART/LPUART features (continued)

USART modes/features

Tx/Rx FIFO X

Tx/Rx FIFO size 8

1. X = supported.

(1)

USART1 USART2 USART3 UART4 LPUART1

3.31 Low-power universal asynchronous receiver transmitter (LPUART)

The STM32G441xB devices embed one Low-Power UART. The LPUART supports asynchronous serial communication with minimum power consumption. It supports halfduplex single-wire communication and modem operations (CTS/RTS). It allows multiprocessor communication.

The LPUART comes with a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO mode is enabled by software and is disabled by default. It has a clock domain independent from the CPU clock, and can wakeup the system from Stop mode. The wake up from Stop mode can be done on:

• Start bit detection

• Any received data frame

• A specific programmed data frame

• Some specific TXFIFO/RXFIFO status interrupts when FIFO mode is enabled

Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while having an extremely low energy consumption. Higher speed clock can be used to reach higher baudrates.

The LPUART interface can be served by the DMA controller.

3.32 Serial peripheral interface (SPI)

Three SPI interfaces allow communication up to 75 Mbits/s in master and up to 41 Mbits/s in slave, half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI interfaces support NSS pulse mode, TI mode and hardware CRC calculation.

Two standard I standards can operate as master or slave at half-duplex communication modes. They can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data resolution and synchronized by a specific signal. Audio sampling frequency from 8 kHz up to 192 kHz can be set by 8-bit programmable linear prescaler. When operating in master mode it can output a clock for an external audio component at 256 times the sampling frequency.

All SPI interfaces can be served by the DMA controller.

S interfaces (multiplexed with SPI2 and SPI3) supporting four different audio

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Functional overview STM32G441xB

3.33 Serial audio interfaces (SAI)

The device embeds 1 SAI. The SAI bus interface handles communications between the microcontroller and the serial audio protocol.

3.33.1 SAI peripheral supports

• Two independent audio sub-blocks which can be transmitters or receivers with their

respective FIFO.

• 8-word integrated FIFOs for each audio sub-block.

• Synchronous or asynchronous mode between the audio sub-blocks.

• Master or slave configuration independent for both audio sub-blocks.

• Clock generator for each audio block to target independent audio frequency sampling

when both audio sub-blocks are configured in master mode.

• Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit.

• Peripheral with large configurability and flexibility allowing to target as example the

following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF out.

• Up to 16 slots available with configurable size and with the possibility to select which

ones are active in the audio frame.

• Number of bits by frame may be configurable.

• Frame synchronization active level configurable (offset, bit length, level).

• First active bit position in the slot is configurable.

• LSB first or MSB first for data transfer.

• Mute mode.

• Stereo/Mono audio frame capability.

• Communication clock strobing edge configurable (SCK).

• Error flags with associated interrupts if enabled respectively. – Overrun and underrun

detection. – Anticipated frame synchronization signal detection in slave mode. – Late frame synchronization signal detection in slave mode. – Codec not ready for the AC’97 mode in reception.

• Interruption sources when enabled: – Errors. – FIFO requests.

• DMA interface with 2 dedicated channels to handle access to the dedicated integrated

FIFO of each SAI audio sub-block.

Table 10. SAI implementation for the features implementation

SAI features Support

(1)

I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 X

Mute mode X

Stereo/Mono audio frame capability X

16 slots X

Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit X

FIFO size X (8 word)

SPDIF X

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1. X: supported.

3.34 Controller area network (FDCAN1)

The controller area network (CAN) subsystem consists of one CAN module and message RAM memory.

The CAN module (FDCAN) is compliant with ISO 11898-1 (CAN protocol specification version 2.0 part A, B) and CAN FD protocol specification version 1.0.

A 1-Kbyte message RAM memory implements filters, receive FIFOs, receive buffers, transmit event FIFOs, transmit buffers.

3.35 Universal serial bus (USB)

The STM32G441xB devices embed a full-speed USB device peripheral compliant with the USB specification version 2.0. The internal USB PHY supports USB FS signaling, embedded DP pull-up and also battery charging detection according to Battery Charging Specification Revision 1.2. The USB interface implements a full-speed (12 Mbit/s) function interface with added support for USB 2.0 Link Power Management. It has softwareconfigurable endpoint setting with packet memory up-to 1 Kbyte and suspend/resume support. It requires a precise 48 MHz clock which can be generated from the internal main PLL (the clock source must use a HSE crystal oscillator) or by the internal 48 MHz oscillator in automatic trimming mode. The synchronization for this oscillator can be taken from the USB data stream itself (SOF signalization) which allows crystal less operation.

3.36 USB Type-C™ / USB Power Delivery controller (UCPD)

The device embeds one controller (UCPD) compliant with USB Type-C Rev. 1.2 and USB Power Delivery Rev. 3.0 specifications.

The controller uses specific I/Os supporting the USB Type-C and USB Power Delivery requirements, featuring:

• USB Type-C pull-up (Rp, all values) and pull-down (Rd) resistors

• “Dead battery” support

• USB Power Delivery message transmission and reception

• FRS (fast role swap) support

The digital controller handles notably:

• USB Type-C level detection with de-bounce, generating interrupts

• FRS detection, generating an interrupt

• Byte-level interface for USB Power Delivery payload, generating interrupts (DMA

compatible)

• USB Power Delivery timing dividers (including a clock pre-scaler)

• CRC generation/checking

• 4b5b encode/decode

• Ordered sets (with a programmable ordered set mask at receive)

• Frequency recovery in receiver during preamble

DS12960 Rev 1 43/192

Functional overview STM32G441xB

The interface offers low-power operation compatible with Stop mode, maintaining the capacity to detect incoming USB Power Delivery messages and FRS signaling.

3.37 Clock recovery system (CRS)

The devices embed a special block which allows automatic trimming of the internal 48 MHz oscillator to guarantee its optimal accuracy over the whole device operational range. This automatic trimming is based on the external synchronization signal, which could be either derived from USB SOF signalization, from LSE oscillator, from an external signal on CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also possible to combine automatic trimming with manual trimming action.

3.38 Development support

3.38.1 Serial wire JTAG debug port (SWJ-DP)

The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

3.38.2 Embedded trace macrocell™

The Arm embedded trace macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32G441xB devices through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. Real-time instruction and data flow activity be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors.

The Embedded trace macrocell operates with third party debugger software tools.

44/192 DS12960 Rev 1

STM32G441xB Pinouts and pin description

MSv47174V1

UFQFPN32

VDD

PF0-OSC_IN

PF1-OSC_OUT

PG10-NRST

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

32 31

PB0

VSSA

VDD

PA10

PA14

VDDA

VSS

PA11

PA8

PA9

PA12

PA13

VSS

PB8-BOOT0

PB7

PB6

PB5

PB4

PB3

PA15

30 29 28 27 26 25

9 10 111213141516

Exposed pad

MSv47175V1

LQFP32

VDD

PF0-OSC_IN

PF1-OSC_OUT

PG10-NRST

PA0

PA1

PA2

PA3

323130

91011

PA4

PA5

PB0

VSS

PA6

PA7

VSSA

VDDA

PA14

PA13

PA12

PA11

PA10

PA9

PA8

VDD

VSS

PB8-BOOT0

PB5

PA15

PB7

PB6

PB4

PB3

4 Pinouts and pin description

4.1 UFQFPN32 pinout description

Figure 5. STM32G441xB UFQFPN32 pinout

1. The above figure shows the package top view.

4.2 LQFP32 pinout description

Figure 6. STM32G441xB LQFP32 pinout

1. The above figure shows the package top view

DS12960 Rev 1 45/192

Pinouts and pin description STM32G441xB

MSv47172V1

UFQFPN48

VBAT

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

PF0-OSC_IN

PF1-OSC_OUT

PG10-NRST

PA0

PA1

PA2

PA3

PA4

393740

484746

222421

131415

PA5

PA6

PB0

VREF+

PB11

PA7

PC4

VDDA

PB1

PB2

PB10

VDD

PA13

VDD

PA12

PA11

PA10

PA9

PA8

PC6

PB15

PB14

PB13

PB12

VDD

PB9

PB6

PB3

PA14

PB8-BOOT0

PB7

PC11

PB5

PB4

PC10

PA15

Exposed pad

VSS

MSv42659V2

LQFP48

VBAT

PC13

PC14 - OSC32_IN

PC15 - OSC32_OUT

PF0 - OSC_IN

PF1 - OSC_OUT

PG10 - NRST

PA0

PA1

PA2

PA3

PA4

393740

484746

222421

131415

PA5

PA6

PB1

VREF+

VDD

PA7

PB0

VDDA

PB2

VSSA

PB10

VSS

VDD

VSS

PA12

PA11

PA10

PA9

PA8

PB15

PB14

PB13

PB12

PB11

VDD

VSS

PB7

PB4

PA13

PB9

PB8-BOOT0

PB3

PB6

PB5

PA15

PA14

4.3 UFQFPN48 pinout description

Figure 7. STM32G441xB UFQFPN48 pinout

1. The above figure shows the package top view

2. VSS pads are connected to the exposed pad.

4.4 LQFP48 pinout description

Figure 8. STM32G441xB LQFP48 pinout

46/192 DS12960 Rev 1

1. The above figure shows the package top view

STM32G441xB Pinouts and pin description

MSv47176V2

1234567

PA15 PC11 PB3 PB5 PB7 VSS VDD

PA12 PA13 PA14 PB4

PB8-

BOOT0

PB9 VBAT

PA11 PA10 PA 9 PB6 PC13

PG10NRST

PC14-

OSC32_IN

PC6 PA8 PB14 PC4 PA7 PA1

PC15-

OSC32_O

PB15 PB13 PB11 PB1 PA4

PF1-

OSC_OUT

PF0-

OSC_IN

PB12 PB10 VREF+ PB2 PA5 PA 2 PA0

VDD VSS VDDA VSSA PB0 PA6 PA3

4.5 WLCSP49 ballout description

Figure 9. STM32G441xB WLCSP49 ballout

1. The above figure shows the package top view

DS12960 Rev 1 47/192

Pinouts and pin description STM32G441xB

MSv60826V1

LQFP80

767574

PA7

PB0

VSSA

PE8

PC4

PC5

VREF+

PE10

PB1

PB2

PE11

VDDA

PE7

PE9

PE12

PC8

PC6

VDD

VSS

PD10

PD9

PD8

PB15

PB14

PB13

PB12

PB11

VDD

PC7

PB7

PB6

PB3

PD0

PA15

PB5

PB4

PC12

PD2

PD1

PC11

PC10

PA14

PC1

PC2

PC3

PA0

PA1

PA2

VSS

3132333435

36PE13

PE14

PA9

PC9

PA8

PB8-BOOT0

PB9

VSS

VDD

PC13 2

VBAT

PC14-OSC32_IN 3

PC15-OSC32_OUT

PF0-OSC_IN

PF1-OSC_OUT

PG10-NRST

PC0

VDD

PA4

PA5

PA6

PA3

38PE15

39PB10

40VSS

60 PA12

PA11

PA10

63 PA13

62 VDD

61 VSS

4.6 LQFP80 pinout description

Figure 10. STM32G441xB LQFP80 pinout

48/192 DS12960 Rev 1

1. The above figure shows the package top view.

STM32G441xB Pinouts and pin description

MSv47177V2

VDD PB9 PB7 PB6 PB3 PC12 PA15 VDD

PC13 VSS PB8-BOOT0 PB5 PD2 PC11 VSS PA12

PC14-

OSC32_IN

VBAT PC1 PB4 PC10 PA11

PC15-

OSC32_OUT

PG10-NRST PC2

PF0-OSC_IN PC0 PA1

PF1-OSC_OUT PA0

PC3 VSS_2

VDD_2

PA3

PA7

PA6

PA2

VDDA

VREF+

PB1

PB0

PC4

PB2

VSSA

PC5

PA5

PA4

PB11

VSS

PB15

PC7

PA9

PB10

PB13

PC8

PA8

PA10

PA14 PA13

VDD

PB12

PB14

PC6

PC9

12345678

4.7 UFBGA64 ballout description

Figure 11. STM32G441xB UFBGA64 ballout

1. The above figure shows the package top view

DS12960 Rev 1 49/192

Pinouts and pin description STM32G441xB

4.8 Pin definition

Table 11. Legend/abbreviations used in the pinout table

Name Abbreviation Definition

Pin name

Pin type

I/O structure

Notes Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset

Pin functions

Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name

S Supply pin

I Input only pin

I/O Input / output pin

FT 5 V tolerant I/O

TT 3.6 V tolerant I/O

B Dedicated BOOT0 pin

NRST Bidirectional reset pin with embedded weak pull-up resistor

Option for TT or FT I/Os

_a I/O, with Analog switch function supplied by V

_c I/O, USB Type-C PD capable

_d I/O, USB Type-C PD Dead Battery function

_f I/O, Fm+ capable

(1)

Alternate functions

Additional

functions

I/O, with USB function

Functions selected through GPIOx_AFR registers

Functions directly selected/enabled through peripheral registers

DDA

1. The related I/O structures in Table 12 are FT_u.

50/192 DS12960 Rev 1

STM32G441xB Pinouts and pin description

Table 12. STM32G441xB pin definition

Pin Number

Pin name

(function

after reset)

LQFP32

UFQFPN32

----- - - - 1 PE2 I/O FT -

----- - -

--11B71C2

--22C52B1

--33C73C1

--44D74D1

----- - -

2255E75E1

3366E66F1613

4 4 7 7 C6 7 D2 7 14 PG10-NRST I/O FT -

LQFP48

UFQFPN48

WLCSP49

LQFP64

LQFP80

UFBGA64

LQFP100

- 2 PE3 I/O FT -

- 3 PE4 I/O FT -

- 4 PE5 I/O FT -

- 5 PE6 I/O FT -

1 6 VBAT S - - - -

2 7 PC13 I/O FT

- 10 PF9 I/O FT -

- 11 PF10 I/O FT -

5 12 PF0-OSC_IN I FT_f -

PC14-

OSC32_IN

PC15-

OSC32_OUT

PF1-

OSC_OUT

Pin type

I/O FT

OFT -

(1)

Alternate function

Notes

Additional

functions

I/O structure

TRACECK, TIM3_CH1,

SAI1_CK1,

SAI1_MCLK_A,

EVENTOUT

TRACED0, TIM3_CH2,

SAI1_SD_B, EVENTOUT

TRACED1, TIM3_CH3,

SAI1_D2, SAI1_FS_A,

EVENTOUT

TRACED2, TIM3_CH4,

SAI1_CK2, SAI1_SCK_A,

EVENTOUT

TRACED3,

SAI1_D1,

SAI1_SD_A, EVENTOUT

(2)

(3)

(2)

(3)

(2)

(3)

TIM1_BKIN, TIM1_CH1N, TIM8_CH4N,

EVENTOUT

EVENTOUT OSC32_IN

EVENTOUT OSC32_OUT

TIM15_CH1,

SPI2_SCK, SAI1_FS_B, EVENTOUT

TIM15_CH2,

SPI2_SCK,

SAI1_D3,

EVENTOUT

I2C2_SDA,

SPI2_NSS/

I2S2_WS, TIM1_CH3N,

EVENTOUT

SPI2_SCK/

I2S2_CK,

EVENTOUT

MCO,

EVENTOUT

WKUP3,

RTC_TAMP3

WKUP2,

RTC_TAMP1,

RTC_TS,

RTC_OUT1

ADC1_IN10,

OSC_IN

ADC2_IN10,

COMP3_INM,

OSC_OUT

NRST

DS12960 Rev 1 51/192

Pinouts and pin description STM32G441xB

Table 12. STM32G441xB pin definition

(1)

(continued)

Pin Number

Pin name

(function

after reset)

LQFP32

UFQFPN32

- - - - - 8 E2 8 15 PC0 I/O FT_a -

- - - - - 9 C3 9 16 PC1 I/O TT -

- - - - - 10 D3 10 17 PC2 I/O FT_a -

- - - - - 11 G1 11 18 PC3 I/O FT_a -

- - - - - - - - 19 PF2 I/O FT - I2C2_SMBA, EVENTOUT -

5 5 8 8 F7 12 F2 12 20 PA0 I/O TT -

6 6 9 9 D6 13 E3 13 21 PA1 I/O TT -

7 7 10 10 F6 14 F3 14 22 PA2 I/O TT -

- - - - - 15 G2 15 23 VSS_2 S - - - -

-----16H11624 VDD_2 S - - - -

8 8 11 11 G7 17 H2 17 25 PA3 I/O TT -

LQFP48

UFQFPN48

WLCSP49

LQFP64

LQFP80

UFBGA64

LQFP100

Pin type

I/O structure

Alternate function

Notes

LPTIM1_IN1, TIM1_CH1,

LPUART1_RX,

EVENTOUT

LPTIM1_OUT,

TIM1_CH2,

LPUART1_TX,

SAI1_SD_A,

EVENTOUT

LPTIM1_IN2, TIM1_CH3,

COMP3_OUT,

EVENTOUT

LPTIM1_ETR,

TIM1_CH4,

SAI1_D1,

TIM1_BKIN2,

SAI1_SD_A,

EVENTOUT

TIM2_CH1,

USART2_CTS,

COMP1_OUT, TIM8_BKIN, TIM8_ETR, TIM2_ETR, EVENTOUT

RTC_REFIN,

TIM2_CH2,

USART2_RTS_DE,

TIM15_CH1N,

EVENTOUT

TIM2_CH3, USART2_TX,

COMP2_OUT,

TIM15_CH1,

LPUART1_TX,

UCPD1_FRSTX,

EVENTOUT

TIM2_CH4, SAI1_CK1,

USART2_RX,

TIM15_CH2,

LPUART1_RX,

SAI1_MCLK_A,

EVENTOUT

Additional

functions

ADC12_IN6,

COMP3_INM

ADC12_IN7,

COMP3_INP

ADC12_IN8

ADC12_IN9

ADC12_IN1,

COMP1_INM,

COMP3_INP,

RTC_TAMP2,

WKUP1

ADC12_IN2,

COMP1_INP, OPAMP1_VINP, OPAMP3_VINP

ADC1_IN3,

COMP2_INM,

OPAMP1_VOUT,

WKUP4/

LSCO

ADC1_IN4,

COMP2_INP,

OPAMP1_VINM/

OPAMP1_VINP

52/192 DS12960 Rev 1

STM32G441xB Pinouts and pin description

Table 12. STM32G441xB pin definition

(1)

(continued)

Pin Number

Pin name

(function

after reset)

LQFP32

UFQFPN32

9 9 12 12 E5 18 D4 18 26 PA4 I/O TT -

10 10 13 13 F5 19 E4 19 27 PA5 I/O TT -

11 11 14 14 G6 20 G3 20 28 PA6 I/O TT -

12 12 15 15 D5 21 H3 21 29 PA7 I/O TT -

- - 16 - D422D52230 PC4 I/OFT_fa -

- - - - - 23 F4 23 31 PC5 I/O TT -

13 13 17 16 G5 24 E5 24 32 PB0 I/O TT -

- - 18 17 E4 25 F5 25 33 PB1 I/O TT -

- - 19 18 F4 26 H4 26 34 PB2 I/O TT -

14 14 - 19 G4 27 G4 27 35 VSSA S - - - -

- - 20 20 F3 28 G5 28 36 VREF+ S - - - VREFBUF_OUT

15 15 21 21 G3 29 H5 29 37 VDDA S - - - -

LQFP48

UFQFPN48

WLCSP49

LQFP64

LQFP80

UFBGA64

LQFP100

Pin type

I/O structure

Alternate function

Notes

TIM3_CH2, SPI1_NSS,

SPI3_NSS/

I2S3_WS, USART2_CK,

SAI1_FS_B, EVENTOUT

TIM2_CH1, TIM2_ETR,

SPI1_SCK,

UCPD1_FRSTX,

EVENTOUT

TIM16_CH1, TIM3_CH1, TIM8_BKIN, SPI1_MISO,

TIM1_BKIN,

COMP1_OUT,

LPUART1_CTS,

EVENTOUT

TIM17_CH1, TIM3_CH2,

TIM8_CH1N,

SPI1_MOSI,

TIM1_CH1N,

COMP2_OUT,

UCPD1_FRSTX,

EVENTOUT

TIM1_ETR, I2C2_SCL,

USART1_TX,

EVENTOUT

TIM15_BKIN, SAI1_D3,

TIM1_CH4N,

USART1_RX,

EVENTOUT

TIM3_CH3, TIM8_CH2N,

TIM1_CH2N,

UCPD1_FRSTX,

EVENTOUT

TIM3_CH4, TIM8_CH3N,

TIM1_CH3N,

COMP4_OUT,

LPUART1_RTS_DE,

EVENTOUT

RTC_OUT2,

LPTIM1_OUT,

I2C3_SMBA, EVENTOUT

Additional

functions

ADC2_IN17,

DAC1_OUT1,

COMP1_INM

ADC2_IN13, DAC1_OUT2, COMP2_INM,

OPAMP2_VINM

ADC2_IN3,

OPAMP2_VOUT

ADC2_IN4,

COMP2_INP, OPAMP1_VINP, OPAMP2_VINP

ADC2_IN5

ADC2_IN11, OPAMP1_VINM, OPAMP2_VINM,

WKUP5

ADC1_IN15,

COMP4_INP, OPAMP2_VINP, OPAMP3_VINP

ADC1_IN12,

COMP1_INP,

OPAMP3_VOUT

ADC2_IN12,

COMP4_INM,

OPAMP3_VINM

DS12960 Rev 1 53/192

Pinouts and pin description STM32G441xB

Table 12. STM32G441xB pin definition

Pin Number

Pin name

(function

after reset)

LQFP32

UFQFPN32

- - - - - - - 30 38 PE7 I/O TT -

----- - -

- - 22 22 F2 30 H6

16 16 - 23 G2 31 G7

17 17 23 24 G1 32 H8

- - 24 25 E3 33 H7

- - 25 26 F1 34 G8

- - 26 27 E2 35 G6

- - 27 28 D3 36 F8

LQFP48

UFQFPN48

WLCSP49

LQFP64

LQFP80

UFBGA64

LQFP100

31 39 PE8 I/O FT_a -

32 40 PE9 I/O FT -

33 41 PE10 I/O FT -

34 42 PE11 I/O FT - TIM1_CH2, EVENTOUT -

35 43 PE12 I/O FT - TIM1_CH3N, EVENTOUT -

36 44 PE13 I/O FT - TIM1_CH3, EVENTOUT -

37 45 PE14 I/O FT -

38 46 PE15 I/O FT -

39 47 PB10 I/O TT -

40 48 VSS S - - - -

41 49 VDD S - - - -

42 50 PB11 I/O FT_a -

43 51 PB12 I/O FT_a -

44 52 PB13 I/O TT -

45 53 PB14 I/O TT -

Pin type

I/O structure

(1)

(continued)

Alternate function

Notes

TIM1_ETR, SAI1_SD_B,

EVENTOUT

TIM1_CH1N,

SAI1_SCK_B,

EVENTOUT

TIM1_CH1, SAI1_FS_B,

EVENTOUT

TIM1_CH2N,

SAI1_MCLK_B,

EVENTOUT

TIM1_CH4, TIM1_BKIN2,

EVENTOUT

TIM1_BKIN, TIM1_CH4N,

USART3_RX,

EVENTOUT

TIM2_CH3, USART3_TX,

LPUART1_RX,

TIM1_BKIN,

SAI1_SCK_A,

EVENTOUT

TIM2_CH4, USART3_RX,

LPUART1_TX,

EVENTOUT

I2C2_SMBA, SPI2_NSS/

I2S2_WS, TIM1_BKIN,

USART3_CK,

LPUART1_RTS_DE,

EVENTOUT

SPI2_SCK/I2S2_CK,

TIM1_CH1N,

USART3_CTS,

LPUART1_CTS,

EVENTOUT

TIM15_CH1, SPI2_MISO,

TIM1_CH2N,

USART3_RTS_DE,

COMP4_OUT,

EVENTOUT

Additional

functions

COMP4_INP

COMP4_INM

OPAMP3_VINM

ADC12_IN14

ADC1_IN11

OPAMP3_VINP

ADC1_IN5,

OPAMP2_VINP

54/192 DS12960 Rev 1

STM32G441xB Pinouts and pin description

Table 12. STM32G441xB pin definition

(1)

(continued)

Pin Number

Pin name

(function

after reset)

LQFP32

UFQFPN32

- - 28 29 E1 37 F7 46 54 PB15 I/O FT_a -

----- - -

--------58 PD11 I/OFT_a-

- - - - - - - - 59 PD12 I/O TT -

- - - - - - - - 60 PD13 I/O FT - TIM4_CH2, EVENTOUT -

- - - - - - - - 61 PD14 I/O FT_a - TIM4_CH3, EVENTOUT OPAMP2_VINP

- - - - - - - - 62 PD15 I/O FT -

----- - -

--29-D138E8

-----39E7

-----40F6

-----41D8

18 18 30 30 D2 42 E6

LQFP48

UFQFPN48

WLCSP49

LQFP64

LQFP80

UFBGA64

LQFP100

47 55 PD8 I/O FT_a -

48 56 PD9 I/O FT -

49 57 PD10 I/O FT -

50 63 VSS S - - - -

51 64 VDD S - - - -

52 65 PC6 I/O FT -

53 66 PC7 I/O FT -

54 67 PC8 I/O FT_f -

55 68 PC9 I/O FT_f -

56 69 PA8 I/O -

Pin type

I/O structure

Alternate function

Notes

RTC_REFIN,

TIM15_CH2, TIM15_CH1N, COMP3_OUT,

TIM1_CH3N,

SPI2_MOSI/

I2S2_SD,

EVENTOUT

USART3_TX,

EVENTOUT

USART3_RX,

EVENTOUT

USART3_CK,

EVENTOUT

USART3_CTS,

EVENTOUT

TIM4_CH1,

USART3_RTS_DE,

EVENTOUT

TIM4_CH4, SPI2_NSS,

EVENTOUT

TIM3_CH1, TIM8_CH1,

I2S2_MCK, EVENTOUT

TIM3_CH2, TIM8_CH2,

I2S3_MCK, EVENTOUT

TIM3_CH3, TIM8_CH3, I2C3_SCL, EVENTOUT

TIM3_CH4, TIM8_CH4, I2SCKIN, TIM8_BKIN2, I2C3_SDA, EVENTOUT

MCO, I2C3_SCL,

I2C2_SDA, I2S2_MCK,

TIM1_CH1, USART1_CK,

TIM4_ETR, SAI1_CK2,

SAI1_SCK_A,

EVENTOUT

Additional

functions

ADC2_IN15

DS12960 Rev 1 55/192

Pinouts and pin description STM32G441xB

Table 12. STM32G441xB pin definition

Pin Number

Pin name

(function

after reset)

LQFP32

UFQFPN32

19 19 31 31 C3 43 D7 57 70 PA9 I/O FT_f -

20 20 32 32 C2 44 D6

21 21 33 33 C1 45 C8

22 22 34 34 B1 46 B8

---35-47B7

--3536-48A8

23 23 36 37 B2 49 C7

24 24 37 38 B3 50 C6

LQFP48

UFQFPN48

WLCSP49

LQFP64

LQFP80

UFBGA64

LQFP100

58 71 PA10 I/O

59 72 PA11 I/O FT -

60 73 PA12 I/O FT -

61 74 VSS S - - - -

62 75 VDD S - - - -

63 76 PA13 I/O FT_f

64 77 PA14 I/O FT_f

Pin type

I/O structure

FT_d

(1)

(continued)

Alternate function

Notes

I2C3_SMBA, I2C2_SCL,

I2S3_MCK, TIM1_CH2,

USART1_TX, TIM15_BKIN, TIM2_CH3, SAI1_FS_A, EVENTOUT

TIM17_BKIN,

USB_CRS_SYNC, I2C2_SMBA, SPI2_MISO, TIM1_CH3, USART1_RX,

TIM2_CH4, TIM8_BKIN,

SAI1_D1, SAI1_SD_A,

EVENTOUT

SPI2_MOSI/

I2S2_SD,

TIM1_CH1N,

USART1_CTS,

COMP1_OUT, FDCAN1_RX,

TIM4_CH1, TIM1_CH4,

TIM1_BKIN2,

EVENTOUT

TIM16_CH1,

I2SCKIN,

TIM1_CH2N,

USART1_RTS_DE,

COMP2_OUT,

FDCAN1_TX, TIM4_CH2,

TIM1_ETR,

EVENTOUT

SWDIO-JTMS,

TIM16_CH1N,

I2C1_SCL,

(4)

IR_OUT,

USART3_CTS,

TIM4_CH3,

SAI1_SD_B,

EVENTOUT

SWCLK-JTCK,

LPTIM1_OUT,

I2C1_SDA, TIM8_CH2,

TIM1_BKIN,

USART2_TX,

SAI1_FS_B,

EVENTOUT

Additional

functions

UCPD1_DBCC1

UCPD1_DBCC2

USB_DM

USB_DP

56/192 DS12960 Rev 1

STM32G441xB Pinouts and pin description

Table 12. STM32G441xB pin definition

Pin Number

Pin name

(function

after reset)

LQFP32

UFQFPN32

25 25 38 39 A1 51 A7 65 78 PA15 I/O FT_f

--39--52C5

--40-A253B6

-----54A6

----- - -

-----55B5

----- - -

LQFP48

UFQFPN48

WLCSP49

LQFP64

LQFP80

UFBGA64

LQFP100

66 79 PC10 I/O FT -

67 80 PC11 I/O FT_f -

68 81 PC12 I/O FT -

69 82 PD0 I/O FT -

70 83 PD1 I/O FT -

71 84 PD2 I/O FT -

- 85 PD3 I/O FT -

- 86 PD4 I/O FT -

- 87 PD5 I/O FT -

- 88 PD6 I/O FT -

Pin type

(1)

(continued)

Alternate function

Notes

Additional

functions

I/O structure

JTDI,

TIM2_CH1, TIM8_CH1,

I2C1_SCL, SPI1_NSS,

(4)

SPI3_NSS/

I2S3_WS, USART2_RX,

UART4_RTS_DE,

TIM1_BKIN, TIM2_ETR,

EVENTOUT

TIM8_CH1N,

UART4_TX,

SPI3_SCK/

I2S3_CK,

USART3_TX,

EVENTOUT

TIM8_CH2N, UART4_RX,

SPI3_MISO,

USART3_RX, I2C3_SDA,

EVENTOUT

TIM8_CH3N,

SPI3_MOSI/

I2S3_SD,

USART3_CK,

UCPD1_FRSTX,

EVENTOUT

TIM8_CH4N,

FDCAN1_RX,

EVENTOUT

TIM8_CH4, TIM8_BKIN2,

FDCAN1_TX,

EVENTOUT

TIM3_ETR, TIM8_BKIN,

EVENTOUT

TIM2_CH1/ TIM2_ETR,

USART2_CTS,

EVENTOUT

TIM2_CH2,

USART2_RTS_DE,

EVENTOUT

USART2_TX,

EVENTOUT

TIM2_CH4,

SAI1_D1, USART2_RX,

SAI1_SD_A,

EVENTOUT

DS12960 Rev 1 57/192

Pinouts and pin description STM32G441xB

Table 12. STM32G441xB pin definition

Pin Number

Pin name

(function

after reset)

LQFP32

UFQFPN32

----- - - - 89 PD7 I/O FT -

26 26 41 40 A3 56 A5

27 27 42 41 B4 57 C4

28 28 43 42

29 29 44 43 C4 59 A4

30 30 45 44 A5 60 A3

LQFP48

UFQFPN48

WLCSP49

LQFP64

58 B4

LQFP80

UFBGA64

LQFP100

72 90 PB3 I/O FT

73 91 PB4 I/O FT

74 92 PB5 I/O FT_f -

75 93 PB6 I/O FT_ -

76 94 PB7 I/O FT_f -

Pin type

I/O structure

(1)

(continued)

Alternate function

Notes

TIM2_CH3, USART2_CK,

EVENTOUT

JTDO-TRACESWO,

TIM2_CH2, TIM4_ETR,

USB_CRS_SYNC,

TIM8_CH1N, SPI1_SCK,

(4)

SPI3_SCK/

I2S3_CK,

USART2_TX,

TIM3_ETR,

SAI1_SCK_B,

EVENTOUT

JTRST,

TIM16_CH1,

TIM3_CH1,

TIM8_CH2N,

SPI1_MISO,

SPI3_MISO, USART2_RX, TIM17_BKIN,

SAI1_MCLK_B,

EVENTOUT

TIM16_BKIN, TIM3_CH2,

TIM8_CH3N,

I2C1_SMBA, SPI1_MOSI,

SPI3_MOSI/

I2S3_SD,

USART2_CK, I2C3_SDA,

TIM17_CH1, LPTIM1_IN1,

SAI1_SD_B, EVENTOUT

TIM16_CH1N,

TIM4_CH1, TIM8_CH1,

TIM8_ETR, USART1_TX,

COMP4_OUT,

TIM8_BKIN2,

LPTIM1_ETR,

SAI1_FS_B, EVENTOUT

TIM17_CH1N,

TIM4_CH2, I2C1_SDA,

TIM8_BKIN, USART1_RX,

COMP3_OUT,

TIM3_CH4, LPTIM1_IN2,

UART4_CTS,

EVENTOUT

Additional

functions

UCPD1_CC2

UCPD1_CC1

PVD_IN

58/192 DS12960 Rev 1

STM32G441xB Pinouts and pin description

Table 12. STM32G441xB pin definition

(1)

(continued)

Pin Number

Pin name

(function

after reset)

LQFP32

UFQFPN32

31 31 46 45 B5 61 B3 77 95 PB8-BOOT0 I/O FT_f

- - 47 46 B6 62 A2

----- - -

32 32 - 47 A6 63 B2

1 1 48 48 A7 64 A1

1. Function availability depends on the chosen device.

2. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:

- The speed should not exceed 2 MHz with a maximum load of 30 pF

- These GPIOs must not be used as current sources (e.g. to drive an LED).

3. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to the Backup domain and RTC register descriptions in the reference manual RM0440 "STM32G4 Series advanced Arm 32-bit MCUs".

4. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are activated.

5. It is recommended to set PB8 in another mode than analog mode after startup to limit consumption if the pin is left unconnected

LQFP48

UFQFPN48

WLCSP49

LQFP64

LQFP80

UFBGA64

LQFP100

78 96 PB9 I/O FT_f -

- 97 PE0 I/O FT -

- 98 PE1 I/O FT -

79 99 VSS S - - - -

VDD S - - - -

Pin type

I/O structure

Alternate function

Notes

TIM16_CH1, TIM4_CH3,

SAI1_CK1, I2C1_SCL,

USART3_RX,

(5)

COMP1_OUT,

FDCAN1_RX, TIM8_CH2,

TIM1_BKIN,

SAI1_MCLK_A,

EVENTOUT

TIM17_CH1, TIM4_CH4,

SAI1_D2, I2C1_SDA,

IR_OUT, USART3_TX,

COMP2_OUT, FDCAN1_TX, TIM8_CH3, TIM1_CH3N, SAI1_FS_A,

EVENTOUT

TIM4_ETR, TIM16_CH1,

USART1_TX,

EVENTOUT

TIM17_CH1,

USART1_RX,

EVENTOUT

Additional

functions

-based

DS12960 Rev 1 59/192

60/192 DS12960 Rev 1

4.9 Alternate functions

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Pinouts and pin description STM32G441xB

Table 13. Alternate function

Port

Port A

SYS_AF

PA0 -

PA1

PA2 -

PA3 -

PA4 - - TIM3_CH2 - - SPI1_NSS

PA5 -

PA6 -

PA7 -

PA8 MCO - I2C3_SCL - I2C2_SDA I2S2_MCK TIM1_CH1

PA9 - -

PA1 0 -

PA11 - - - - -

PA1 2 -

PA1 3

PA1 4

PA1 5 J TDI

RTC_

REFIN

SWDIO-

JTMS

SWCLK-

JTCK

LPTIM1/TI

M2/5/15/1

6/17

TIM2_

CH1

TIM2_

CH2

TIM2_

CH3

TIM2_

CH4

TIM2_

CH1

TIM16_

CH1

TIM17_

CH1

TIM17_

BKIN

TIM16_

CH1

TIM16_

CH1N

LPTIM1_

OUT

TIM2_

CH1

I2C3/TIM1/ 2/3/4/8/15/

GPCOMP1

TIM2_ETR--SPI1_SCK--------

TIM3_CH1 - TIM8_BKIN SPI1_MISO TIM1_BKIN -

TIM3_CH2 -

I2C3_ SMBA

TIM8_CH1 - I2C1_SCL SPI1_NSS

I2C3/SAI1/

USB/TIM8/

15/

GPCOMP3

- ----

-SAI1_CK1---

---I2SCKIN

- - I2C1_SCL IR_OUT -

- - I2C1_SDA TIM8_CH2 TIM1_BKIN

USB_

CRS_SYNC

I2C1/2/3/

TIM1/8/16/

TIM8_ CH1N

- I2C2_SCL I2S3_MCK TIM1_ CH2

I2C2_ SMBA

SPI1/2/3/

I2S2/3/

UART4

/TIM8/Infra

SPI1_MOSI

SPI2_MISO TIM1_CH3

SPI2_MOSI

/I2S2_SD

red

SPI2/3/ I2S2/3/ TIM1/8/

Infrared

SPI3_NSS/

I2S3_WS

TIM1_ CH1N

TIM1_ CH2N

SPI3_NSS/

I2S3_WS

I2C3/4

USART1/2/

3/CAN

USART2_

CTS

USART2_

RTS_DE

USART2_TXCOMP2_

USART2_

USART1_

CTS

USART1_

RTS_DE

USART3_

CTS

USART2_

USART2_RXUART4_

/UART4/

LPUART1/

GPCOMP1/

2/3

COMP1_

OUT

-----SAI1_FS_B-

COMP1_

OUT

COMP2_

OUT

- - TIM4_ETR - SAI1_CK2 -

- - TIM2_CH4 TIM8_BKIN SAI1_D1 -

COMP1_

OUT

COMP2_

OUT

--TIM4_CH3--

-----SAI1_FS_B-

RTS_DE

CAN/TIM1/ 8/15/FDCA

TIM8_BKIN TIM8_ETR - - - TIM2_ETR

TIM15_

CH1N

TIM15_

FDCAN1_R

FDCAN1_T

TIM1_BKIN----TIM2_ETR

TIM2/3/4/8/

CH1

CH2

---

-----

TIM2_CH3 - - - SAI1_FS_A

BKIN

TIM4_CH1 TIM1_CH4

TIM4_CH2 TIM1_ETR - - -

LPTIM1/TI

M1/8/FDCA

-----

LPUART1/ SAI1/TIM1

LPUART1_

LPUART1_RXSAI1_

LPUART1_

CTS

TIM1_ BKIN2

OPAMP2

MCLK_A

SAI1_SD_

UART4/SAI

SAI1/

1/TIM2/15/

UCPD1

UCPD1_

FRSTX

UCPD1_

FRSTX

UCPD1_

FRSTX

SAI1_

SCK_A

SAI1_SD_AEVENT

EVENT

OUT

Table 13. Alternate function (continued)

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

STM32G441xB Pinouts and pin description

DS12960 Rev 1 61/192

Port

Port B

SYS_AF

PB0 - - TIM3_CH3 -

PB1 - - TIM3_CH4 -

PB2 RTC_OUT2

JTDO-

PB3

TRACESWO

PB4 JTRST

PB5 -

PB6 -

PB7 -

PB8 -

PB9 -

PB10 -

PB11 -

PB12 - - - -

LPTIM1/TI

M2/5/15/1

6/17

LPTIM1_

OUT

TIM2_

CH2

TIM16_

CH1

TIM16_

BKIN

TIM16_

CH1N

TIM17_

CH1N

TIM16_

CH1

TIM17_

CH1

TIM2_

CH3

TIM2_

CH4

I2C3/TIM1/

2/3/4/8/15/

GPCOMP1

TIM4_ETR

TIM3_CH1 -

TIM3_CH2

TIM4_CH1 - - TIM8_CH1 TIM8_ETR

TIM4_CH2 - I2C1_SDA TIM8_BKIN -

TIM4_CH3 SAI1_CK1 I2C1_SCL - -

TIM4_CH4 SAI1_D2 I2C1_SDA - IR_OUT

- ----

I2C3/SAI1/

USB/TIM8/

15/

GPCOMP3

USB_CRS_

SYNC

TIM8_

CH3N

I2C1/2/3/

TIM1/8/16/

TIM8_ CH2N

TIM8_ CH3N

I2C3_ SMBA

TIM8_ CH1N

TIM8_ CH2N

I2C1_ SMBA

I2C2_ SMBA

SPI1/2/3/

I2S2/3/ UART4

/TIM8/Infra

red

SPI1_SCK

SPI1_MISO SPI3_MISO

SPI1_MOSI

SPI2_NSS/

I2S2_WS

SPI2/3/ I2S2/3/ TIM1/8/

Infrared

----------

TIM1_ CH2N

TIM1_ CH3N

SPI3_SCK/

I2S3_CK

SPI3_MOSI

/I2S3_SD

TIM1_BKIN

USART1/2/

3/CAN

-------

USART2_

USART1_TXCOMP4_

USART1_RXCOMP3_

USART3_RXCOMP1_

USART3_TXCOMP2_

USART3_TXLPUART1_

USART3_RXLPUART1_

USART3_CKLPUART1_

I2C3/4

/UART4/

LPUART1/

GPCOMP1/

COMP4_

I2C3_SDA -

RTS_DE

CAN/TIM1/ 8/15/FDCA

2/3

OUT

--TIM3_ETR---

OUT

FDCAN1_R

OUT

FDCAN1_T

OUT

TIM2/3/4/8/

---

TIM17_

BKIN

TIM17_

- TIM3_CH4

---TIM1_BKIN-

------

TIM8_ BKIN2

TIM8_CH2 - TIM1_BKIN -

TIM8_CH3 -

CH1

LPTIM1/TI

M1/8/FDCA

LPTIM1_

LPUART1/ SAI1/TIM1

LPUART1_

RTS_DE

---

SAI1_SD_

IN1

ETR

IN2

- - SAI1_FS_B

TIM1_ CH3N

SAI1/

OPAMP2

UART4/SAI

1/TIM2/15/

UCPD1

UCPD1_FR

STX

SAI1_SCK_BEVENT

SAI1_

MCLK_B

UART4_

CTS

SAI1_

MCLK_A

-SAI1_FS_A

SAI1_

SCK_A

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

PB13 - - - - -

PB14 -

PB15 RTC_REFIN

TIM15_

CH1

TIM15_

CH2

- - - SPI2_MISO

TIM15_

CH1N

COMP3_

OUT

TIM1_ CH3N

SPI2_SCK/

I2S2_CK

SPI2_MOSI

/I2S2_SD

TIM1_ CH1N

TIM1_ CH2N

USART3_

RTS_DE

---------

CTS

LPUART1_

CTS

COMP4_

OUT

------

EVENT

OUT

EVENT

OUT

EVENT

OUT

62/192 DS12960 Rev 1

Table 13. Alternate function (continued)

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Pinouts and pin description STM32G441xB

Port

Port C

SYS_AF

PC0 -

PC1 -

PC2 -

PC3 -

PC4 - - TIM1_ETR - I2C2_SCL - -

PC5 - -

PC6 - - TIM3_CH1 -

PC7 - - TIM3_CH2 -

PC8 - - TIM3_CH3 -

PC9 - - TIM3_CH4 -

PC10 - - - -

PC11 - - - -

PC12 - - - -

LPTIM1/TI

M2/5/15/1

6/17

LPTIM1_

IN1

LPTIM1_

OUT

LPTIM1_

IN2

LPTIM1_

ETR

I2C3/TIM1/

2/3/4/8/15/

GPCOMP1

TIM1_CH1-----

TIM1_CH2-----

TIM1_CH3

TIM1_CH4 SAI1_D1 - -

TIM15_

BKIN

I2C3/SAI1/

USB/TIM8/

15/

GPCOMP3

COMP3_

OUT

SAI1_D3 - -

I2C1/2/3/

TIM1/8/16/

TIM8_

CH1

TIM8_

CH2

TIM8_

CH3

TIM8_

CH4

TIM8_ CH1N

TIM8_ CH2N

TIM8_ CH3N

SPI1/2/3/

I2S2/3/

UART4

/TIM8/Infra

red

-----------

-I2S2_MCK--------

-I2S3_MCK--------

---I2C3_SCL------

I2SCKIN

UART4_TX

UART4_RX SPI3_MISO

SPI2/3/ I2S2/3/ TIM1/8/

Infrared

TIM1_ BKIN2

TIM1_ CH4N

TIM8_ BKIN2

SPI3_SCK/

I2S3_CK

SPI3_MOSI

/I2S3_SD

I2C3/4

USART1/2/

3/CAN

USART1_

USART3_

/UART4/

LPUART1/

GPCOMP1/

LPUART1_

------

-I2C3_SDA------

I2C3_SDA------

CAN/TIM1/ 8/15/FDCA

2/3

-------

------

TIM2/3/4/8/

------

----

LPTIM1/TI

M1/8/FDCA

LPUART1/ SAI1/TIM1

OPAMP2

SAI1_SD_

SAI1/

UART4/SAI

1/TIM2/15/

UCPD1

UCPD1_

FRSTX

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

PC13 - - TIM1_BKIN -

PC14- --- -----------

PC15- --- -----------

TIM1_ CH1N

TIM8_ CH4N

--------

EVENT

OUT

EVENT

OUT

EVENT

OUT

Table 13. Alternate function (continued)

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

STM32G441xB Pinouts and pin description

DS12960 Rev 1 63/192

Port

SYS_AF

PD0 - - - - - -

PD1 - - - - TIM8_CH4 -

PD2- -TIM3_ETR-TIM8_BKIN----------

PD3 - -

PD4 - - TIM2_CH2 - - - -

PD5- -- - ---

PD6 - - TIM2_CH4 SAI1_D1 - - -

PD7 - - TIM2_CH3 - - - -

Port D

PD8- -- - ---

PD9- -- - ---

PD10- --- ---

PD11- -- ----

PD12 - - TIM4_CH1 - - - -

PD13- -TIM4_CH2------------

PD14- -TIM4_CH3------------

PD15- -TIM4_CH4---SPI2_NSS--------

LPTIM1/TI

M2/5/15/1

6/17

I2C3/TIM1/

2/3/4/8/15/

GPCOMP1

TIM2_CH1/

TIM2_ETR

I2C3/SAI1/

USB/TIM8/

15/

GPCOMP3

I2C1/2/3/

TIM1/8/16/

----

SPI1/2/3/

I2S2/3/

UART4

/TIM8/Infra

red

SPI2/3/ I2S2/3/ TIM1/8/

Infrared

TIM8_ CH4N

TIM8_ BKIN2

USART1/2/

3/CAN

USART2_

CTS

USART2_

RTS_DE

USART2_

USART3_

CTS

USART3_

RTS_DE

I2C3/4

/UART4/

LPUART1/

GPCOMP1/

CAN/TIM1/ 8/15/FDCA

2/3

FDCAN1_R

FDCAN1_T

-------

-----

-------

TIM2/3/4/8/

LPTIM1/TI

M1/8/FDCA

-----

LPUART1/ SAI1/TIM1

OPAMP2

SAI1_SD_

SAI1/

UART4/SAI

1/TIM2/15/

UCPD1

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

64/192 DS12960 Rev 1

Table 13. Alternate function (continued)

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Pinouts and pin description STM32G441xB

Port

Port E

SYS_AF

PE0 - - TIM4_ETR -

PE1 - - - -

PE2 TRACECK -

PE3 TRACED0 -

PE4 TRACED1 -

PE5 TRACED2 -

PE6TRACED3--SAI1_D1---------

PE7 - -

PE8 - -

PE9 - -

PE10 - -

PE11 - -

PE12 - -

PE13 - -

PE14 - -

PE15 - -

LPTIM1/TI

M2/5/15/1

6/17

I2C3/TIM1/

2/3/4/8/15/

GPCOMP1

TIM3_

CH1

TIM3_

CH2

TIM3_

CH3

TIM3_

CH4

TIM1_

ETR

TIM1_ CH1N

TIM1_

CH1

TIM1_ CH2N

TIM1_

CH2

TIM1_ CH3N

TIM1_

CH3

TIM1_

CH4

TIM1_

BKIN

I2C3/SAI1/

USB/TIM8/

15/

GPCOMP3

SAI1_CK1---------

SAI1_D2---------

SAI1_CK2---------

I2C1/2/3/

TIM1/8/16/

TIM16_

CH1

TIM17_

CH1

----------

------------

---

SPI1/2/3/

I2S2/3/

UART4

/TIM8/Infra

red

SPI2/3/ I2S2/3/ TIM1/8/

Infrared

TIM1_ BKIN2

TIM1_ CH4N

USART1/2/

3/CAN

USART1_

USART3_

--------

I2C3/4

/UART4/

LPUART1/

GPCOMP1/

CAN/TIM1/ 8/15/FDCA

2/3

-------

TIM2/3/4/8/

LPTIM1/TI

M1/8/FDCA

LPUART1/ SAI1/TIM1

SAI1/

OPAMP2

SAI1_

MCLK_A

SAI1_ SD_B

SAI1_ FS_A

SAI1_

SCK_A

SAI1_ SD_A

SAI1_ SD_B

SAI1_

SCK_B

SAI1_ FS_B

SAI1_

MCLK_B

UART4/SAI

1/TIM2/15/

UCPD1

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

Table 13. Alternate function (continued)

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

STM32G441xB Pinouts and pin description

DS12960 Rev 1 65/192

Port

Port F

Port G

SYS_AF

PF0 - - - -

PF1 - - - - -

PF2 - - - -

PF9- --TIM15_CH1-SPI2_SCK-------SAI1_FS_B-

PF10- --TIM15_CH2-SPI2_SCK-------SAI1_D3-

PG10MCO--- -----------

LPTIM1/TI

M2/5/15/1

6/17

I2C3/TIM1/

2/3/4/8/15/

GPCOMP1

I2C3/SAI1/

USB/TIM8/

15/

GPCOMP3

I2C1/2/3/

TIM1/8/16/

I2C2_

SDA

I2C2_ SMBA

SPI1/2/3/

I2S2/3/

UART4

/TIM8/Infra

red

SPI2_NSS/

I2S2_WS

SPI2_SCK/

I2S2_CK

SPI2/3/ I2S2/3/ TIM1/8/

Infrared

TIM1_ CH3N

----------

USART1/2/

3/CAN

--------

---------

I2C3/4

/UART4/

LPUART1/

GPCOMP1/

2/3

CAN/TIM1/ 8/15/FDCA

TIM2/3/4/8/

LPTIM1/TI

M1/8/FDCA

LPUART1/ SAI1/TIM1

SAI1/

OPAMP2

UART4/SAI

1/TIM2/15/

UCPD1

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

Electrical characteristics STM32G441xB

MS19210V1

MCU pin

C = 50 pF

MS19211V1

MCU pin

5 Electrical characteristics

5.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

5.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at T the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3).

5.1.2 Typical values

= 25 °C and TA = TAmax (given by

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = V are given only as design guidelines and are not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated

5.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

5.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 12.

5.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 13.

Figure 12. Pin loading conditions Figure 13. Pin input voltage

(mean ±2).

= 3 V. They

DDA

66/192 DS12960 Rev 1

STM32G441xB Electrical characteristics

MS60206V1

Level shifter

logic

Kernel logic (CPU, Digital & Memories)

Backup circuitry

(LSE, RTC,

Backup registers)

OUT

Regulator

GPIOs

1.55 – 3.6 V

n x 100 nF

+1 x 4.7 μF

n x VSS

n x VDD

VBAT

CORE

Power switch

DDIO

ADCs/ DACs/ OPAMPs/ COMPs/ VREFBUF

VREF-

DDA

10 nF +1 μF

VDDA

VSSA

REF

100 nF

+1 μF

VREF+

Reset block

Temp. sensor

PLL, HSI16, HSI48

Standby circuitry

(Wakeup logic,

IWDG)

5.1.6 Power supply scheme

Figure 14. Power supply scheme

Caution: Each power supply pair (V

capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device.

DD/VSS

, V

DDA/VSSA

etc.) must be decoupled with filtering ceramic

DS12960 Rev 1 67/192

160

Electrical characteristics STM32G441xB

MS60200V1

DD_VBAT

BAT

DDA

5.1.7 Current consumption measurement

Figure 15. Current consumption measurement

The I including the current supplying V

parameters given in Table 21 to Table 26 represent the total MCU consumption

DD_ALL

, V

DDA

5.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 14: Voltage characteristics,

Table 15: Current characteristics and Table 16: Thermal characteristics may cause

permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 qualification standard, extended mission profiles are available on demand.

Symbol Ratings Min Max Unit

- V

External main supply voltage (including

Input voltage on FT_xxx pins except FT_c pins

(2)

Input voltage on FT_c pins V

Input voltage on TT_xx pins V

Input voltage on any other pins V

|V

DDx

SSx-VSS

1. All main power (VDD, V power supply, in the permitted range.

2. VIN maximum must always be respected. Refer to Table 15: Current characteristics for the maximum allowed injected current values.

Variations between different V

pins of the same domain

Variations between all the different ground

pins

Table 14. Voltage characteristics

, V

(5)

DDA

and V

, V

BAT

)

BAT

) and ground (VSS, V

and V

DDX

SSA

BAT

(1)

-0.3 4.0

power

min (V

0.3

0.3 5.5

0.3 4.0

-50

4.0

, V

(3)(4)

DDA

)

-50

) pins must always be connected to the external

68/192 DS12960 Rev 1

STM32G441xB Electrical characteristics

3. This formula has to be applied only on the power supplies related to the IO structure described in the pin definition table.

4. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.

5. Include VREF- pin.

Table 15. Current characteristics

Symbol Ratings Max Unit

(1)

150

100

IV

DD(PIN)

SS(PIN)

Total current into sum of all V

Total current out of sum of all V

Maximum current into each V

Maximum current out of each V

power lines (source)

ground lines (sink)

power pin (source)

ground pin (sink)

Output current sunk by any I/O and control pin except FT_f 20

IO(PIN)

Output current sunk by any FT_f pin 20

Output current sourced by any I/O and control pin 20

I

Total output current sunk by sum of all I/Os and control pins

IO(PIN)

INJ(PIN)

|I

INJ(PIN)

1. All main power (VDD, V power supplies, in the permitted range.

2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.

3. Positive injection (when V lower than the specified maximum value.

4. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 14:

Voltage characteristics for the minimum allowed input voltage values.

5. When several inputs are submitted to a current injection, the maximum |I the negative injected currents (instantaneous values).

Total output current sourced by sum of all I/Os and control pins

(3)

Injected current on FT_xxx, TT_xx, NRST pins -5/0

| Total injected current (sum of all I/Os and control pins)

, V

DDA

) and ground (VSS, V

BAT

> VDD) is not possible on these I/Os and does not occur for input voltages

) pins must always be connected to the external

SSA

(2)

(5)

is the absolute sum of

INJ(PIN)

100

(4)

±25

Table 16. Thermal characteristics

Symbol Ratings Value Unit

STG

Storage temperature range –65 to +150 °C

Maximum junction temperature 150 °C

DS12960 Rev 1 69/192

160

Electrical characteristics STM32G441xB

5.3 Operating conditions

5.3.1 General operating conditions

Table 17. General operating conditions

Symbol Parameter Conditions Min Max Unit

HCLK

PCLK1

PCLK2

Internal AHB clock frequency - 0 170

Internal APB1 clock frequency - 0 170

Internal APB2 clock frequency - 0 170

Standard operating voltage - 1.71

(1)

MHzf

3.6 V

ADC or COMP used 1.62

3.6

DAC 1 MSPS or DAC 15 MSPS 1.71

Analog supply voltage

DDA

OPAMP used 2.0 3.6

VREFBUF used 2.4

3.6

+0.3

ADC, DAC, OPAMP, COMP, VREFBUF not used

Backup operating voltage - 1.55 3.6 V

BAT

TT_xx I/O -0.3 V

FT_c I/O -0.3 5

I/O input voltage

All I/O except TT_xx and FT_c -0.3

MIN(MIN(V

)+3.6 V,

DDA

(2)(3)

5.5 V)

LQFP100 - - 337

LQFP80 - - TBD

LQFP64 - - 321

LQFP48 - - 317

Power dissipation at

= 85 °C for suffix 6

(4)

LQFP32 - - 317

UFBGA64 - - 452

UFQFPN48 - - 699

UFQFPN32 - - 565

WLCSP49 - - 339

70/192 DS12960 Rev 1

STM32G441xB Electrical characteristics

Table 17. General operating conditions (continued)

Symbol Parameter Conditions Min Max Unit

LQFP100 - - 84

LQFP80 - - TBD

LQFP64 - - 80

LQFP48 - - 79

Power dissipation at

= 125 °C for suffix 3

Ambient temperature for the suffix 6 version

Ambient temperature for the suffix 3 version

Junction temperature range

(5)

LQFP32 - - 79

UFBGA64 - - 113

UFQFPN48 - - 175

UFQFPN32 - - 141

WLCSP49 - - 85

Maximum power dissipation -40 85

Low-power dissipation

(6)

-40 105

Maximum power dissipation -40 125

Low-power dissipation

(6)

-40 130

Suffix 6 version -40 105

Suffix 3 version -40 130

°C

1. When RESET is released functionality is guaranteed down to V

2. This formula has to be applied only on the power supplies related to the IO structure described by the pin definition table. Maximum I/O input voltage is the smallest value between MIN(V

, V

3. For operation with voltage higher than Min (V disabled.

is lower, higher PD values are allowed as long as TJ does not exceed T

4. If T

characteristics).

is lower, higher PD values are allowed as long as TJ does not exceed T

5. If T

characteristics).

6. In low-power dissipation state, T

Thermal characteristics).

can be extended to this range as long as TJ does not exceed T

) +0.3 V, the internal Pull-up and Pull-Down resistors must be

DDA

BOR0

Min.

, V

)+3.6 V and 5.5V.

DDA

(see Section 6.10: Thermal

Jmax

(see Section 6.10: Thermal

Jmax

(see Section 6.10:

Jmax

DS12960 Rev 1 71/192

160

Electrical characteristics STM32G441xB

5.3.2 Operating conditions at power-up / power-down

The parameters given in Table 18 are derived from tests performed under the ambient temperature condition summarized in Table 17.

Symbol Parameter Conditions Min Max Unit

Table 18. Operating conditions at power-up / power-down

VDD

VDDA

VDD rise time rate

fall time rate 10 

rise time rate

DDA

fall time rate 10 

DDA

0 

5.3.3 Embedded reset and power control block characteristics

The parameters given in Table 19 are derived from tests performed under the ambient temperature conditions summarized in Table 17: General operating conditions.

RSTTEMPO

Table 19. Embedded reset and power control block characteristics

Symbol Parameter Conditions

Reset temporization after

BOR0

(2)

BOR0 is detected

(2)

Brown-out reset threshold 0

rising - 250 400 s

Rising edge 1.62 1.66 1.7

Falling edge 1.6 1.64 1.69

Rising edge 2.06 2.1 2.14

BOR1

Brown-out reset threshold 1

Falling edge 1.96 2 2.04

(1)

Min Typ Max Unit

µs/V

BOR2

Brown-out reset threshold 2

Falling edge 2.16 2.20 2.24

Rising edge 2.56 2.61 2.66

Rising edge 2.26 2.31 2.35

BOR3

Brown-out reset threshold 3

Falling edge 2.47 2.52 2.57

Rising edge 2.85 2.90 2.95

BOR4

PVD0

Brown-out reset threshold 4

Programmable voltage detector threshold 0

Falling edge 2.76 2.81 2.86

Rising edge 2.1 2.15 2.19

Falling edge 2 2.05 2.1

Rising edge 2.26 2.31 2.36

PVD1

PVD threshold 1

Falling edge 2.15 2.20 2.25

Rising edge 2.41 2.46 2.51

PVD2

PVD threshold 2

Falling edge 2.31 2.36 2.41

Rising edge 2.56 2.61 2.66

PVD3

PVD threshold 3

Falling edge 2.47 2.52 2.57

72/192 DS12960 Rev 1

STM32G441xB Electrical characteristics

Table 19. Embedded reset and power control block characteristics (continued)

Symbol Parameter Conditions

(1)

Min Typ Max Unit

PVD4

PVD5

PVD6

hyst_BORH0

hyst_BOR_PVD

PVM1

PVM2

(2)

(BOR_PVD)

hyst_PVM1

hyst_PVM2

(PVM1/PVM2)

PVD threshold 4

Falling edge 2.59 2.64 2.69

Rising edge 2.85 2.91 2.96

Rising edge 2.69 2.74 2.79

PVD threshold 5

Falling edge 2.75 2.81 2.86

Rising edge 2.92 2.98 3.04

PVD threshold 6

Falling edge 2.84 2.90 2.96

Hysteresis in

Hysteresis voltage of BORH0

Hysteresis voltage of BORH (except BORH0) and PVD

(3)

BOR

(except BOR0) and

PVD consumption from V

peripheral voltage

DDA

monitoring (COMP/ADC)

peripheral voltage

DDA

monitoring (OPAMP/DAC)

continuous mode

Hysteresis in other mode

--100-mV

--1.11.6µA

Rising edge 1.61 1.65 1.69

Falling edge 1.6 1.64 1.68

Rising edge 1.78 1.82 1.86

Falling edge 1.77 1.81 1.85

-20-

-30-

PVM1 hysteresis - - 10 - mV

PVM2 hysteresis - - 10 - mV

PVM1 and PVM2 consumption from V

--2-µA

1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.

2. Guaranteed by design.

3. BOR0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply current characteristics tables.

DS12960 Rev 1 73/192

160

Electrical characteristics STM32G441xB

5.3.4 Embedded voltage reference

The parameters given in Table 20 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 17: General operating

conditions.

Symbol Parameter Conditions Min Typ Max Unit

Table 20. Embedded internal voltage reference

REFINT

Internal reference voltage

–40 °C < T

< +130 °C 1.182 1.212 1.232 V

ADC sampling time

S_vrefint

(1)

internal reference

-4

(2)

when reading the

voltage

Start time of reference

start_vrefint

voltage buffer when

--812

ADC is enable

DD(VREFINTBUF

V consumption from VDD

)

when converted by

REFINT

buffer

--12.520

ADC

Internal reference

V

REFINT

voltage spread over

VDD = 3 V - 5 7.5

the temperature range

Coeff

DDCoeff

REFINT_DIV1

REFINT_DIV2

REFINT_DIV3

1. The shortest sampling time is determined in the application by multiple iterations.

2. Guaranteed by design.

Average temperature coefficient

Long term stability 1000 hours, T = 25°C - 300 1000

Average voltage coefficient

1/4 reference voltage

1/2 reference voltage 49 50 51

3/4 reference voltage 74 75 76

–40°C < T

3.0 V < V

< +130°C - 30 50

< 3.6 V - 250 1200

24 25 26

--µs

(2)

µs

µA

ppm/°C

ppm

ppm/V

REFINT

74/192 DS12960 Rev 1

STM32G441xB Electrical characteristics

MSv40169V2

1.185

1.19

1.195

1.2

1.205

1.21

1.215

1.22

1.225

1.23

1.235

-40 -20 0 20 40 60 80 100 120

°C

Mean Min Max

Figure 16. V

5.3.5 Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code

versus temperature

REFINT

The current consumption is measured as described in Figure 15: Current consumption

measurement.

Typical and maximum current consumption

The MCU is placed under the following conditions:

• All I/O pins are in analog input mode

• All peripherals are disabled except when explicitly mentioned

• The Flash memory access time is adjusted with the minimum wait states number,

depending on the f to CPU clock (HCLK) frequency” available in the reference manual RM0440 "STM32G4 Series advanced Arm

• When the peripherals are enabled f

• The voltage scaling Range 1 is adjusted to f

– Voltage Range 1 Boost mode for 150 MHz < f

– Voltage Range 1 Normal mode for 26 MHz < f

The parameters given in Table 21 to Table 26 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 17: General

operating conditions.

frequency (refer to the table “number of wait states according

HCLK

-based 32-bit MCUs").

= f

PCLK

HCLK

frequency as follows:

HCLK

 170 MHz

HCLK

 150 MHz

HCLK

DS12960 Rev 1 75/192

160

76/192 DS12960 Rev 1

Electrical characteristics STM32G441xB

Table 21. Current consumption in Run and Low-power run modes, code with data

processing running from Flash in single Bank, ART enable (Cache ON Prefetch OFF)

Symbol Parameter

IDD (Run)

Supply current in Run mode

Condition

= f

HCLK

HSE

up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable

Voltage scaling

Range 2

Range 1 Boost mode

Range 1

Typ M ax

HCLK

25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

26 MHz 3.20 3.35 3.60 4.15 5.05 3.50 3.80 4.80 6.10 8.20

16 MHz 2.05 2.15 2.50 3.05 3.95 2.30 2.60 3.60 4.90 7.00

8 MHz 1.10 1.25 1.60 2.10 3.05 1.30 1.60 2.60 3.90 6.10

4 MHz 0.635 0.755 1.15 1.65 2.60 0.750 1.10 2.10 3.40 5.40

2 MHz 0.400 0.525 0.910 1.45 2.35 0.500 0.830 1.80 3.10 5.20

1 MHz 0.280 0.415 0.800 1.35 2.25 0.370 0.700 1.70 3.00 5.00

100 KHz 0.170 0.305 0.690 1.20 2.15 0.260 0.590 1.50 2.90 4.90

170 MHz 25.5 26.0 27.0 27.5 29.0 27.0 28.0 29.0 31.0 34.0

150 MHz 21.0 21.5 22.0 23.0 24.0 23.0 23.0 24.0 25.0 28.0

120 MHz 17.0 17.5 18.0 18.5 20.0 18.0 19.0 20.0 21.0 24.0

80 MHz 11.5 11.5 12.5 13.0 14.0 12.0 13.0 14.0 16.0 18.0

72 MHz 10.5 10.5 11.0 12.0 13.0 11.0 12.0 13.0 14.0 17.0

64 MHz 9.30 9.50 10.0 11.0 12.0 9.70 11.0 12.0 13.0 16.0

48 MHz 6.95 7.15 7.45 8.15 9.30 7.40 7.80 9.00 11.0 14.0

Unit

32 MHz 4.70 4.90 5.25 5.95 7.10 5.10 5.50 6.70 8.40 12.0

24 MHz 3.60 3.80 4.20 4.85 6.00 3.90 4.40 5.60 7.20 9.90

16 MHz 2.45 2.65 3.10 3.75 4.90 2.80 3.20 4.40 6.00 8.60

Table 21. Current consumption in Run and Low-power run modes, code with data

processing running from Flash in single Bank, ART enable (Cache ON Prefetch OFF) (continued)

STM32G441xB Electrical characteristics

DS12960 Rev 1 77/192

Symbol Parameter

Supply current

IDD (LPRun)

in Low-power run mode

Condition

= f

HCLK

HSE

all peripherals disable

= f

HCLK

HSI

/ HPRE

all peripherals disable

Voltage scaling

Typ M ax

HCLK

25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

2 MHz 350 525 990 1600 2650 500 840 2100 3600 5700

1 MHz 255 410 860 1500 2550 360 690 2000 3400 5700

250 KHz 145 300 750 1400 2450 240 640 1700 3300 5600

62.5 KHz 99.5 270 725 1350 2400 210 610 1700 3300 5600

2 MHz 865 1050 1500 2150 3200 1100 1600 2700 4200 6000

1 MHz 820 965 1400 2050 3100 980 1500 2600 4000 5700

250 KHz 725 875 1300 1950 3000 880 1400 2500 4000 5700

62.5 KHz 685 860 1300 1900 2950 850 1300 2500 4000 5700

Unit

A

78/192 DS12960 Rev 1

Table 22. Current consumption in Run and Low-power run modes,

Electrical characteristics STM32G441xB

code with data processing running from Flash in single Bank, ART disable

Symbol Parameter

IDD (Run)

Supply current in Run mode

Condition

= f

HCLK

HSE

up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable

Voltage scaling

Range 2

Range 1 Boost mode

Range 1

Typ M ax

HCLK

25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

26 MHz 2.95 3.10 3.40 3.95 4.85 3.20 3.60 4.50 5.80 7.90

16 MHz 2.25 2.35 2.70 3.25 4.15 2.50 2.80 3.80 5.00 7.20

8 MHz 1.20 1.35 1.70 2.25 3.15 1.40 1.70 2.70 4.00 5.60

4 MHz 0.690 0.795 1.20 1.75 2.65 0.810 1.10 2.10 3.40 5.40

2 MHz 0.425 0.540 0.940 1.50 2.40 0.530 0.860 1.80 3.20 5.20

1 MHz 0.295 0.420 0.820 1.35 2.25 0.390 0.720 1.70 3.00 5.00

100 KHz 0.175 0.300 0.695 1.25 2.15 0.260 0.590 1.50 2.90 4.90

170 MHz 17.5 18.0 18.5 19.5 21.0 18.0 19.0 20.0 22.0 25.0

150 MHz 15.5 15.5 16.5 17.0 18.5 16.0 17.0 18.0 19.0 22.0

120 MHz 13.5 14.0 14.5 15.5 16.5 14.0 15.0 16.0 18.0 20.0

80 MHz 10.5 11.0 11.5 12.5 13.5 12.0 12.0 13.0 15.0 17.0

72 MHz 9.75 9.95 10.5 11.5 12.5 10.0 11.0 12.0 14.0 16.0

64 MHz 8.65 8.95 9.50 10.5 11.5 9.00 9.40 11.0 13.0 15.0

Unit

48 MHz 6.50 6.75 7.05 7.75 8.90 6.80 7.30 8.40 10.0 13.0

32 MHz 5.25 5.50 5.85 6.60 7.75 5.70 6.10 7.30 9.00 12.0

24 MHz 4.00 4.20 4.65 5.35 6.50 4.40 4.80 6.10 7.70 11.0

16 MHz 2.75 2.95 3.40 4.10 5.20 3.10 3.50 4.70 6.60 9.10

Table 22. Current consumption in Run and Low-power run modes,

code with data processing running from Flash in single Bank, ART disable (continued)

STM32G441xB Electrical characteristics

DS12960 Rev 1 79/192

Symbol Parameter

Supply current

IDD (LPRun)

in Low-power run mode

Condition

= f

HCLK

HSE

all peripherals disable

= f

HCLK

HSI

/ HPRE

all peripherals disable

Voltage scaling

Typ M ax

HCLK

25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

2 MHz 385 575 1050 1650 2700 560 960 2100 3600 5800

1 MHz 265 410 880 1500 2550 400 780 1800 3500 5600

250 KHz 135 285 760 1400 2450 260 640 1700 3300 5600

62.5 KHz 110 260 730 1350 2400 230 610 1700 3300 5600

2 MHz 915 1100 1550 2200 3250 1200 1600 2800 4100 5800

1 MHz 830 950 1400 2050 3100 990 1500 2600 4000 5700

250 KHz 725 865 1300 1950 3000 880 1400 2600 4000 5700

62.5 KHz 670 840 1300 1950 3000 850 1300 2500 4000 5700

Unit

A

80/192 DS12960 Rev 1

Table 23. Current consumption in Run and Low-power run modes,

code with data processing running from SRAM1

Electrical characteristics STM32G441xB

Symbol Parameter

IDD (Run)

Supply current in Run mode

Condition

= f

HCLK

HSE

up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable

Voltage scaling

Range 2

Range 1 Boost mode

Range 1

Typ M ax

HCLK

25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

26 MHz 2.85 3.00 3.30 3.85 4.75 3.10 3.40 4.40 5.60 7.70

16 MHz 1.80 1.95 2.30 2.85 3.75 2.00 2.40 3.30 4.60 6.70

8 MHz 0.995 1.15 1.50 2.05 2.95 1.20 1.50 2.50 3.80 5.70

4 MHz 0.580 0.725 1.10 1.65 2.55 0.690 1.00 2.00 3.30 5.30

2 MHz 0.370 0.510 0.900 1.45 2.35 0.470 0.800 1.80 3.10 5.10

1 MHz 0.270 0.405 0.790 1.35 2.25 0.360 0.690 1.60 2.90 5.00

100 KHz 0.170 0.310 0.695 1.25 2.15 0.260 0.580 1.50 2.80 4.90

170 MHz 23.0 23.5 24.0 25.0 26.5 24.0 24.0 25.0 27.0 30.0

150 MHz 19.0 19.5 20.0 20.5 22.0 20.0 20.0 21.0 23.0 25.0

120 MHz 15.5 15.5 16.0 17.0 18.0 16.0 16.0 17.0 19.0 22.0

80 MHz 10.5 10.5 11.0 12.0 13.0 11.0 11.0 12.0 14.0 17.0

72 MHz 9.35 9.55 10.0 11.0 12.0 9.40 9.80 11.0 13.0 16.0

64 MHz 8.35 8.55 9.15 9.85 11.0 8.40 8.80 10.0 12.0 15.0

48 MHz 6.25 6.45 6.75 7.45 8.65 6.40 6.80 8.00 9.60 13.0

Unit

32 MHz 4.25 4.45 4.80 5.50 6.65 4.50 4.90 6.20 7.80 11.0

24 MHz 3.25 3.45 3.85 4.55 5.65 3.50 3.90 5.20 6.70 9.30

16 MHz 2.25 2.40 2.85 3.55 4.70 2.50 2.90 4.10 5.50 8.10

Table 23. Current consumption in Run and Low-power run modes,

code with data processing running from SRAM1 (continued)

STM32G441xB Electrical characteristics

DS12960 Rev 1 81/192

Symbol Parameter

Supply current

IDD (LPRun)

in Low-power run mode

Condition

= f

HCLK

HSE

all peripherals disable

= f

HCLK

HSI

/ HPRE

all peripherals disable

Voltage scaling

Typ M ax

HCLK

25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

2 MHz 350 495 965 1600 2650 450 860 2000 3600 5700

1 MHz 210 370 845 1500 2550 330 740 1800 3400 5600

250 KHz 115 275 755 1400 2450 230 640 1700 3300 5600

62.5 KHz 98.0 255 725 1350 2400 200 590 1700 3300 5600

2 MHz 850 1000 1500 2100 3150 1000 1600 2800 4200 5900

1 MHz 770 900 1400 2000 3050 950 1500 2700 4200 5800

250 KHz 720 840 1300 1950 3000 870 1400 2600 4000 5800

62.5 KHz 665 830 1300 1900 2950 870 1300 2500 3900 5700

Unit

A

82/192 DS12960 Rev 1

Table 24. Typical current consumption in Run and Low-power run modes, with different codes

Electrical characteristics STM32G441xB

running from Flash, ART enable (Cache ON Prefetch OFF)

Symbol Parameter

IDD (Run)

Supply current in Run mode

Conditions

- Voltage scaling 25°C 25°C

= f

HCLK

HSE

up to 48 MHZ included, bypass mode PLL ON above 48 MHz all peripherals disable

Range2

=26MHz

HCLK

Range 1

= 150 MHz

HCLK

Range 1 Boost mode f

= 170 MHz

HCLK

Code

TYP

Single Bank

Mode

Unit

TYP

Single Bank

Mode

Pseudo-dhrystone 3.20 mA 123

Coremark 3.15 mA 121

Dhrystone2.1 3.20 mA 123

Fibonacci 3.60 mA 138

While(1) 3.00 mA 115

Pseudo-dhrystone 21.0 mA 140

Coremark 21.0 mA 140

Dhrystone2.1 21.0 mA 140

Fibonacci 23.5 mA 157

While(1) 20.0 mA 133

Pseudo-dhrystone 25.5 mA 150

Coremark 25.0 mA 147

Dhrystone2.1 26.0 mA 153

Fibonacci 28.5 mA 168

Unit

µA/MHz

IDD (LPRun)

Supply current in Low-power run

SYSCLK source is HSI f

= 2 MHz

HCLK

all peripherals disable

While(1) 24.5 mA 144

Pseudo-dhrystone 865 µA 433

Coremark 855 µA 428

Dhrystone2.1 875 µA 438

Fibonacci 905 µA 453

While(1) 870 µA 435

µA/MHz

Table 25. Typical current consumption in Run and Low-power run modes,

STM32G441xB Electrical characteristics

with different codes running from Flash, ART disable

DS12960 Rev 1 83/192

Symbol Parameter

Supply

IDD (Run)

current in Run mode

Conditions

- Voltage scaling 25°C 25°C

= f

HCLK

up to 48 MHZ

HSE

included, bypass mode PLL ON above 48 MHz all peripherals disable

Range 2 f

= 26 MHz

HCLK

Range 1

= 150 MHz

HCLK

Range 1 Boost mode f

= 170 MHz

HCLK

TYP

Single Bank

Mode

Code

TYP

Single Bank

Mode

Unit

Pseudo-dhrystone 2.95 mA 113

Coremark 2.95 mA 113

Dhrystone2.1 2.95 mA 113

Fibonacci 2.70 mA 104

While(1) 2.95 mA 113

Pseudo-dhrystone 15.5 mA 103

Coremark 15.0 mA 100

Dhrystone2.1 15.5 mA 103

Fibonacci 14.0 mA 93

While(1) 20.0 mA 133

Pseudo-dhrystone 17.5 mA 103

Coremark 17.0 mA 100

Dhrystone2.1 17.5 mA 103

Fibonacci 16.0 mA 94

Unit

µA/MHz

IDD (LPRun)

Supply current in Low-power run

SYSCLK source is HSI f

= 2 MHz

HCLK

all peripherals disable

While(1) 24.0 mA 141

Pseudo-dhrystone 915 µA 458

Coremark 890 µA 445

Dhrystone2.1 965 µA 483

Fibonacci 930 µA 465

While(1) 895 µA 448

µA/MHz

84/192 DS12960 Rev 1

Electrical characteristics STM32G441xB

Symbol Parameter

IDD (Run)

Supply current in Run mode

Table 26. Typical current consumption in Run and Low-power run modes, with different codes

running from SRAM1

Conditions

- Voltage scaling

= f

HCLK

up to 48 MHZ

HSE

included, bypass mode PLL ON above 48 MHz all peripherals disable

Range2 f

=26 MHz

HCLK

Range 1 f

= 150 MHz

HCLK

Range 1 Boost mode

= 170 MHz

HCLK

Code

Pseudo-dhrystone 2.85 mA 110

Coremark 2.95 mA 113

Dhrystone2.1 2.85 mA 110

Fibonacci 2.85 mA 110

While(1) 3.05 mA 117

Pseudo-dhrystone 19.0 mA 127

Coremark 19.5 mA 130

Dhrystone2.1 19.0 mA 127

Fibonacci 20.5 mA 137

While(1) 18.5 mA 123

Pseudo-dhrystone 23.0 mA 135

Coremark 24.0 mA 141

Dhrystone2.1 23.0 mA 135

Fibonacci 24.5 mA 144

TYP 25°C

Single bank

mode

Unit

TYP 25°C

Single

bank

mode

Unit

µA/MHz

IDD (LPRun)

Supply current in Low-power run

SYSCLK source is HSI

= 2 MHz

HCLK

all peripherals disable

While(1) 22.0 mA 129

Pseudo-dhrystone 850 µA 425

Coremark 870 µA 435

Dhrystone2.1 840 µA 420

Fibonacci 855 µA 428

While(1) 820 µA 410

µA/MHz

Table 27. Typical current consumption in Run and Low-power run modes, with different codes

STM32G441xB Electrical characteristics

running from SRAM2

DS12960 Rev 1 85/192

Symbol Parameter

IDD (Run)

Supply current in Run mode

Conditions

- Voltage scaling

= f

HCLK

up to 48 MHZ

HSE

included, bypass mode PLL ON above 48 MHz all peripherals disable

Range2 f

=26 MHz

HCLK

Range 1

= 150 MHz

HCLK

Range 1 Boost mode f

= 170 MHz

HCLK

Code

TYP 25°C

Single bank

mode

Unit

TYP 25°C

Single

bank

mode

Pseudo-dhrystone 2.40 mA 92

Coremark 2.50 mA 96

Dhrystone2.1 2.40 mA 92

Fibonacci 2.35 mA 90

While(1) 2.25 mA 87

Pseudo-dhrystone 15.5 mA 103

Coremark 16.5 mA 110

Dhrystone2.1 15.5 mA 103

Fibonacci 15.5 mA 103

While(1) 14.5 mA 97

Pseudo-dhrystone 19.0 mA 112

Coremark 20.0 mA 118

Dhrystone2.1 19.0 mA 112

Fibonacci 19.0 mA 112

Unit

µA/MHz

IDD (LPRun)

Supply current in Low-power run

SYSCLK source is HSI

= 2 MHz

HCLK

all peripherals disable

While(1) 18.0 mA 106

Pseudo-dhrystone 835 µA 418

Coremark 825 µA 413

Dhrystone2.1 830 µA 415

Fibonacci 830 µA 415

While(1) 815 µA 408

µA/MHz

86/192 DS12960 Rev 1

Table 28. Typical current consumption in Run and Low-power run modes, with different codes

Electrical characteristics STM32G441xB

running from CCM

Symbol Parameter

IDD (Run)

Supply current in Run mode

Conditions

- Voltage scaling

= f

HCLK

up to 48 MHZ

HSE

included, bypass mode PLL ON above 48 MHz all peripherals disable

Range2 f

=26 MHz

HCLK

Range 1

= 150 MHz

HCLK

Range 1 Boost mode f

= 170 MHz

HCLK

Code

TYP 25°C

Single bank

mode

Unit

TYP 25°C

Single

bank

mode

Pseudo-dhrystone 2.65 mA 102

Coremark 2.80 mA 108

Dhrystone2.1 2.65 mA 102

Fibonacci 3.25 mA 125

While(1) 3.25 mA 125

Pseudo-dhrystone 17.5 mA 117

Coremark 19.0 mA 127

Dhrystone2.1 17.5 mA 117

Fibonacci 21.5 mA 143

While(1) 21.5 mA 143

Pseudo-dhrystone 21.5 mA 126

Coremark 23.0 mA 135

Dhrystone2.1 21.5 mA 126

Fibonacci 26.0 mA 153

Unit

µA/MHz

IDD (LPRun)

Supply current in Low-power run

SYSCLK source is HSI

= 2 MHz

HCLK

all peripherals disable

While(1) 26.0 mA 153

Pseudo-dhrystone 845 µA 423

Coremark 825 µA 413

Dhrystone2.1 820 µA 410

Fibonacci 885 µA 443

While(1) 890 µA 445

µA/MHz

Table 29. Current consumption in Sleep and Low-power sleep mode Flash ON

STM32G441xB Electrical characteristics

DS12960 Rev 1 87/192

Symbol Parameter

IDD (Sleep)

Supply current in Sleep mode

Condition

= f

HCLK

HSE

up to 48 MHz included, bypass mode PLL ON above 48 MHz all peripherals disable

Voltage scaling

Range 2

Range 1 Boost mode

Range 1

Typ M ax

HCLK

25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

26 MHz 1.05 1.15 1.45 2.00 2.90 1.30 1.60 2.60 3.90 6.10

16 MHz 0.690 0.810 1.15 1.70 2.60 0.910 1.30 2.30 3.50 5.60

8 MHz 0.425 0.545 0.920 1.45 2.35 0.590 0.930 1.90 3.20 5.20

4 MHz 0.300 0.400 0.815 1.35 2.25 0.420 0.760 1.70 3.00 5.10

2 MHz 0.230 0.355 0.755 1.30 2.20 0.340 0.670 1.60 2.90 5.00

1 MHz 0.200 0.320 0.725 1.25 2.15 0.290 0.620 1.60 2.90 4.90

100 KHz 0.165 0.285 0.690 1.25 2.15 0.250 0.580 1.50 2.80 4.90

170 MHz 7.40 7.65 8.30 9.10 10.5 7.70 8.20 9.90 12.0 15.0

150 MHz 6.10 6.30 6.90 7.60 8.80 6.40 6.90 8.10 9.70 13.0

120 MHz 4.95 5.15 5.70 6.40 7.60 5.30 5.70 6.90 8.50 12.0

80 MHz 3.45 3.65 4.15 4.85 6.00 3.70 4.10 5.40 7.00 9.60

72 MHz 3.15 3.35 3.85 4.55 5.70 3.40 3.80 5.10 6.60 9.20

64 MHz 2.85 3.00 3.55 4.25 5.40 3.10 3.50 4.70 6.30 8.90

Unit

48 MHz 2.10 2.30 2.55 3.25 4.40 2.40 2.90 4.10 5.60 8.20

32 MHz 1.50 1.65 2.00 2.70 3.80 1.80 2.30 3.50 5.10 7.70

24 MHz 1.15 1.35 1.75 2.40 3.55 1.50 1.90 3.20 4.80 7.40

16 MHz 0.850 1.05 1.45 2.15 3.25 1.10 1.60 2.80 4.40 7.00

88/192 DS12960 Rev 1

Table 29. Current consumption in Sleep and Low-power sleep mode Flash ON (continued)

Electrical characteristics STM32G441xB

Symbol Parameter

Supply current

IDD (LPRun)

in Low-power run mode

Symbol Parameter

IDD (LPSleep)

Supply current in low-power sleep mode

Condition

Voltage scaling

HCLK

25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

Typ M ax

2 MHz 180 335 810 1450 2500 1300 1800 2700 4200 5900

= f

HCLK

HSE

all peripherals disable

1 MHz 135 300 770 1400 2450 790 1400 2200 3700 5800

250 KHz 115 265 740 1350 2400 350 840 1700 3300 5600

62.5 KHz 89.5 255 730 1350 2400 340 840 1700 3200 5500

2 MHz 730 875 1350 1950 3000 1000 1900 2900 4200 5900

= f

HCLK

/ HPRE

HSI

all peripherals disable

1 MHz 675 830 1300 1950 3000 1000 1600 2800 4100 5800

250 KHz 655 820 1300 1950 3000 1000 1600 2700 4000 5800

62.5 KHz 680 850 1300 1950 3000 1000 1600 2500 3900 5700

Table 30. Current consumption in low-power sleep modes, Flash in power-down

Condition

= f

HCLK

HSE

all peripherals disable

= f

HCLK

HSI

all peripherals disable

Voltage scaling

HCLK

25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

2 MHz 175 290 805 1450 2500 300 660 1900 3400 5600

1 MHz 125 280 765 1400 2450 260 640 1800 3300 5600

250 KHz 105 240 735 1350 2400 220 620 1700 3300 5600

62.5 KHz 105 245 725 1350 2400 210 610 1700 3300 5500

2 MHz 670 830 1350 1950 3000 890 1400 2600 4000 5700

1 MHz 655 825 1300 1950 3000 880 1400 2600 3900 5700

250 KHz 635 825 1300 1900 2950 870 1200 2500 3900 5700

62.5 KHz 640 840 1300 1900 2950 850 1200 2200 3500 5500

Typ M ax

Unit

A

Unit

A

Symbol Parameter

IDD (Stop 1)

Supply current in Stop 1 mode, RTC disabled

Conditions TYP MAX

RTC disabled

RTC clocked by LSI

Table 31. Current consumption in Stop 1 mode

STM32G441xB Electrical characteristics

(1)

Unit

VDD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

1.8 V 58.5 175 550 1050 1900 160 510 1700 2800 8500

2.4 V 58.5 175 550 1050 1950 160 510 1700 4000 8800

3.0 V 59.0 175 555 1050 1950 160 520 1700 4100 8900

3.6 V 59.5 180 560 1100 1950 160 520 1700 4200 9000

1.8 V 59.0 175 550 1050 1950 160 510 1700 2900 8500

2.4 V 59.5 175 555 1050 1950 160 510 1700 4000 8800

3.0 V 59.5 175 555 1050 1950 160 520 1700 4100 8900

DS12960 Rev 1 89/192

IDD (Stop 1 with RTC)

Supply current

in Stop 1 mode,

RTC enabled

RTC clocked by LSE bypassed at 32768 Hz

RTC clocked by LSE quartz in low drive mode at 32768 Hz

Wakeup clock is HSI

IDD (Stop 1 with RTC)

Supply current during wakeup

from

Stop 1 mode

= 16 MHz,

Wakeup clock is

HSI = 4 MHz,

(HPRE divider=4),

voltage Range 2

1. Guaranteed by characterization results, unless otherwise specified.

3.6 V 60.5 180 560 1100 1950 160 520 1700 4200 9000 µA

1.8 V 58.5 175 550 1050 1900 - - - - -

2.4 V 59.0 175 555 1050 1950 - - - - -

3.0 V 60.0 180 555 1050 1950 - - - - -

3.6 V 62.0 180 565 1100 1950 - - - - -

1.8 V 58.5 150 445 890 - - - - - -

2.4 V 59.0 150 445 890 - - - - - -

3.0 V 59.5 150 445 890 - - - - - -

3.6 V 61.0 150 450 895 - - - - - -

3.0 V1.39---------

3.0 V0.93---------

90/192 DS12960 Rev 1

Conditions TYP MAX

Symbol Parameter

VDD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

1.8 V 150 280 680 1200 2100 260 640 2000 4200 9700

IDD(Stop 0)

Supply current in Stop 0 mode, RTC disabled

2.4 V 150 280 680 1200 2100 260 650 2000 4300 9800

3 V 155 280 685 1200 2150 270 650 2000 4400 9900

3.6 V 155 285 685 1200 2150 270 650 2000 4500 10000

1. Guaranteed by characterization results, unless otherwise specified.

Table 32. Current consumption in Stop 0 mode

Electrical characteristics STM32G441xB

(1)

Unit

µA

Symbol Parameter

Supply current in Standby

IDD

(Standby)

mode (backup registers retained),

RTC disabled

Table 33. Current consumption in Standby mode

Conditions TYP MAX

No independent watchdog

With independent watchdog

VDD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

1.8 V 92.0 205 870 2250 5600 220 1500 4100 6300 16000

2.4 V 100 240 1000 2600 6450 250 1900 4500 7200 18000

3 V 120 280 1200 3050 7400 280 2000 5300 8200 20000

3.6 V 175 385 1550 3800 9200 380 2100 6400 9600 24000

1.8 V 275 - - - - - - - - -

2.4 V 335 - - - - - - - - -

3 V400- - - - --- - -

3.6 V 510 - - - - - - - - -

(1)

Unit

Symbol Parameter

Table 33. Current consumption in Standby mode (continued)

Conditions TYP MAX

VDD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

STM32G441xB Electrical characteristics

(1)

Unit

DS12960 Rev 1 91/192

IDD

(Standby with RTC)

Supply current in Standby mode (backup registers retained),

RTC enabled

RTC clocked by LSI, no independent watchdog

RTC clocked by LSI, with independent watchdog

RTC clocked by LSE bypassed at 32768 Hz

RTC clocked by LSE quartz drive mode

(2)

in low

1.8 V 490 605 1300 2650 5950 650 1700 4300 6600 16000

2.4 V 630 765 1550 3100 6950 800 2100 5300 7600 18000

3 V 785 955 1850 3700 8050 980 2300 6300 8900 21000

3.6 V 1000 1200 2350 4600 9950 1300 2900 7500 11000 24000 nA

1.8 V 530 - - - - - - - - -

2.4 V 685 - - - - - - - - -

3 V860- - - - --- - -

3.6 V 1100 - - - - - - - - -

1.8 V 360 470 1100 2450 5750 - - - - -

2.4 V 480 625 1400 3000 6800 - - - - -

3 V 825 1100 2200 4200 8700 - - - - -

3.6 V 2550 3400 5250 8000 13500 - - - - nA

1.8 V 355 490 990 2150 4800 - - - - -

2.4 V 455 605 1200 2550 5550 - - - - -

3 V 595 775 1450 3100 6400 - - - - -

3.6 V 810 1200 2050 3900 7750 - - - - -

92/192 DS12960 Rev 1

Symbol Parameter

Supply current to be added in Standby mode when SRAM2 is retained

IDD

(SRAM2)

(3)

Supply current to be added in Standby mode when SRAM2 is retained

Table 33. Current consumption in Standby mode (continued)

Conditions TYP MAX

All clock OFF

VDD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

1.8 V 218 530 1680 3500 6900 - - - - -

2.4 V 220 525 1700 3500 7050 - - - - -

3 V 215 530 1650 3500 7100 - - - - -

3.6 V 220 545 1700 3600 6800 - - - - -

1.8 V 310 735 2550 5750 12500 - - - - -

2.4 V 320 765 2700 6100 13500 - - - - -

3 V 335 810 2850 6550 14500 - - - - -

3.6 V 395 930 3250 7400 16000 - - - - -

Electrical characteristics STM32G441xB

(1)

Unit

Symbol Parameter

Table 33. Current consumption in Standby mode (continued)

Conditions TYP MAX

VDD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

STM32G441xB Electrical characteristics

(1)

Unit

IDD (wakeup

from Standby)

1. Guaranteed by characterization results, unless otherwise specified.

2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.

3. The supply current in Standby with SRAM2 mode is: + RTC) +

4. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 37: Low-power mode wakeup timings.

Supply current during wakeup from Standby mode

IDD_ALL(SRAM2).

Wakeup clock is HSI16 = 16 MHz

3 V2.0- - - - --- - -mA

(4)

IDD_ALL(Standby) + IDD_ALL(SRAM2). The supply current in Standby with RTC with SRAM2 mode is: IIDD_ALL(Standby

Table 34. Current consumption in Shutdown mode

Conditions TYP MAX

DS12960 Rev 1 93/192

Symbol Parameter

Supply current in Shutdown

IDD

(Shutdown)

mode (backup registers

VDD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

1.8 V 14.0 94.0 570 1600 4350 190 430 2100 4600 13000

2.4 V 22.0 120 670 1900 4950 290 490 2300 5200 14000

3 V 35.0 150 805 2200 5750 330 660 2500 5900 16000

retained) RTC disabled

3.6 V 74.0 245 1100 2900 7350 340 770 3000 7000 19000

(1)

Unit

94/192 DS12960 Rev 1

Symbol Parameter

Table 34. Current consumption in Shutdown mode (continued)

Conditions TYP MAX

VDD 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

Electrical characteristics STM32G441xB

(1)

Unit

IDD (Shutdown with

RTC)

Supply current in Shutdown mode (backup registers retained) RTC enabled

RTC clocked by LSE bypassed at 32768 Hz

RTC clocked by LSE quartz

1.8 V 280 355 800 1800 4500 - - - - -

2.4 V 400 500 1050 2250 5350 - - - - -

3 V 745 985 1850 3400 7100 - - - - -

3.6 V 2450 3250 4850 7100 11500 - - - - -

1.8 V 275 375 775 1650 - - - - - -

2.4 V 375 495 950 2050 - - - - - -

(2)

3 V 515 640 1200 2550 - - - - - -

low drive mode

IDD(wakeup from Shutdown)

1. Guaranteed by characterization results, unless otherwise specified.

2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.

3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 37: Low-power mode wakeup timings.

Supply current during wakeup from Shutdown mode

Wakeup clock is HSI16 = 16 MHz

3.6 V 710 925 1750 3300 - - - - - -

3 V0.24- - - - -----mA

(3)

Symbol Parameter

Table 35. Current consumption in VBAT mode

Conditions TYP MAX

VBAT 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C

1.8 V4.0021.0105280685-----

STM32G441xB Electrical characteristics

(1)

Unit

RTC disabled

2.4 V5.0024.0120310765-----

3 V6.0028.0140360865-----

3.6 V15.054.02406151500-----

IDD(VBAT)

Backup domain supply current

RTC enabled and clocked by LSE

1.8 V270275330475------

2.4 V385400490690------

3 V72586511501550------

bypassed at

DS12960 Rev 1 95/192

32768 Hz

RTC enabled and

3.6 V 2500 3050 3900 4700 ------

1.8 V2653154156701000-----

2.4 V3554155308651150-----

clocked by LSE

(2)

quartz

1. Guaranteed by characterization results, unless otherwise specified.

2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.

3 V48054571010501250-----

3.6 V675870110015001700-----

Electrical characteristics STM32G441xB

DDIOxfSW

C××=

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 55: I/O static characteristics.

For the output pins, any external pull-down or external load must also be considered to estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC, OPAMP, COMP input pins which should be configured as analog inputs.

Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,

as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This is done either by using pull-up/down resistors or by configuring the pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption measured previously (see

Table 37: Low-power mode wakeup timings), the I/Os used by an application also contribute

to the current consumption. When an I/O pin switches, it uses the current from the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin:

where

is the current sunk by a switching I/O to charge/discharge the capacitive load

is the I/O supply voltage

is the I/O switching frequency

C is the total capacitance seen by the I/O pin: C = C

INT

+ C

EXT + CS

CS is the PCB board capacitance including the pad pin.

The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.

96/192 DS12960 Rev 1

STM32G441xB Electrical characteristics

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in Table 37. The MCU is placed under the following conditions:

• All I/O pins are in Analog mode

• The given value is calculated by measuring the difference of the current consumptions:

– when the peripheral is clocked on

– when the peripheral is clocked off

• Ambient operating temperature and supply voltage conditions summarized in Table 14:

Voltage characteristics

• The power consumption of the digital part of the on-chip peripherals is given in

Table 37. The power consumption of the analog part of the peripherals (where

applicable) is indicated in each related section of the datasheet.

Table 36. Peripheral current consumption

BUS Peripheral

AHB Bus Matrix 5.31 5.00 4.07 4.97 µA/MHz

DMA1 3.21 2.95 2.45 2.68

DMA2 3.10 2.86 2.37 2.59

DMAMUX 7.48 6.97 5.74 6.43

AHB1

CORDIC 1.61 1.50 1.24 1.34

FMAC 3.70 3.47 2.86 3.27

FLASH 6.10 5.66 4.64 5.33

SRAM1 0.31 0.32 0.26 0.38

Range 1

Boost Mode

Range 1 Range 2

Low-power

run and sleep

Unit

µA/MHz

DS12960 Rev 1 97/192

160

Electrical characteristics STM32G441xB

Table 36. Peripheral current consumption (continued)

BUS Peripheral

CRC 1.11 1.05 0.86 0.90

GPIOA 1.00 0.91 0.73 0.93

GPIOB 0.55 0.50 0.41 0.54

GPIOC 0.56 0.51 0.42 0.43

GPIOD 0.35 0.33 0.26 0.26

GPIOE 0.59 0.55 0.45 0.41

GPIOF 0.46 0.43 0.36 0.31

GPIOG 0.38 0.36 0.29 0.26

AHB2

CCMSRAM 0.32 0.31 0.26 0.25

SRAM2 0.70 0.66 0.55 0.55

ADC12 AHB clock domain 6.72 6.27 5.17 5.95

ADC12 independent clock domain 0.61 0.59 0.46 0.56

DAC1 5.57 5.17 4.40 4.99

DAC3 5.67 5.30 NA NA

AES 2.84 2.64 2.19 2.43

RNG clock domain 3.63 3.37 NA Na

RNG independent clock domain 1.06 1.00 NA NA

Range 1

Boost Mode

Range 1 Range 2

Low-power

run and sleep

Unit

µA/MHz

AHB ALL AHB peripherals 79.97 74.54 57.83 66.98 µA/MHz

AHB to APB1 bridge 0.47 0.37 0.32 0.08

TIM2 10.84 10.04 8.21 9.31

TIM3 9.32 8.65 7.10 8.02

TIM4 8.60 8.00 6.61 7.53

TIM6 2.88 2.69 2.22 2.66

TIM7 2.72 2.53 2.09 2.41

CRS 0.65 0.62 0.50 0.57

APB1

RTC 3.72 3.49 2.92 3.73

WWDG 0.77 0.74 0.60 0.71

SPI2 4.96 4.63 3.82 4.33

SPI3 5.33 4.98 4.09 4.67

I2S2 clock domain 3.45 3.23 2.65 2.95

I2S2 independent clock domain 1.51 1.40 1.17 1.38

I2S3 clock domain 3.86 3.62 2.97 3.49

I2S3 independent clock domain 1.47 1.36 1.12 1.18

µA/MHz

98/192 DS12960 Rev 1

STM32G441xB Electrical characteristics

Table 36. Peripheral current consumption (continued)

BUS Peripheral

USART2 clock domain 3.57 3.36 2.76 3.22

USART2 independent clock domain 7.93 7.36 6.10 6.84

USART3 clock domain 3.50 3.29 2.68 3.12

USART3 independent clock domain 7.69 7.14 5.94 6.71

UART4 clock domain 3.30 3.10 2.54 2.91

UART4 independent clock domain 6.53 6.06 5.02 5.61

I2C1 clock domain 1.69 1.60 1.31 1.53

I2C1 independent clock domain 3.95 3.68 3.05 3.47

I2C2 clock domain 1.69 1.60 1.31 1.53

I2C2 independent clock domain 4.04 3.76 3.11 3.58

USB clock domain 0.57 0.55 0.44 0.51

USB independent clock domain 1.19 1.10 5.28 NA

APB1

FDCAN clock domain 9.52 8.90 7.32 8.29

FDCAN independent clock domain 4.82 4.48 3.70 4.37

PWR 1.26 1.19 0.96 1.04

I2C3 clock domain 1.68 1.59 1.30 1.53

I2C3 independent clock domain 2.48 2.30 1.92 2.19

Range 1

Boost Mode

Range 1 Range 2

Low-power

run and sleep

Unit

µA/MHz

LPTIM1 clock domain 1.52 1.45 1.17 1.43

LPTIM1 independent clock domain 4.38 4.05 3.38 3.68

LPUART1 clock domain 2.42 2.29 1.87 2.15

LPUART1 independent clock domain

4.65 4.30 3.59 4.14

ALL APB1 on 138.92 129.50 105.42 120.34

AHB to APB2 bridge 0.43 0.36 0.30 0.19

UCPD clock domain 3.67 3.42 2.82 3.24

UCPD independent clock domain 1.28 1.20 5.73 NA

DS12960 Rev 1 99/192

160

Electrical characteristics STM32G441xB

Table 36. Peripheral current consumption (continued)

BUS Peripheral

SYSCFG/VREFBUF/COMP 1.94 1.81 1.49 1.82

TIM1 12.00 11.16 9.20 10.41

SPI1 2.47 2.32 1.92 2.18

TIM8 11.65 10.83 8.93 10.17

USART1 clock domain 2.84 2.65 2.18 2.48

USART1 independent clock domain 7.01 6.53 5.38 6.17

SPI4 2.47 2.32 1.92 2.18

APB2

TIM15 6.00 5.57 4.61 5.26

TIM16 4.18 3.89 3.20 3.57

TIM17 4.37 4.06 3.33 3.76

SAI1 clock domain 3.08 2.88 2.36 2.79

SAI1 independent clock domain 3.07 2.84 2.35 2.63

ALL APB2 on 62.79 58.41 52.90 53.64

ALL peripherals 250.00 210.44 179.05 1152.53

Range 1

Boost Mode

Range 1 Range 2

Low-power

run and sleep

Unit

µA/MHz

100/192 DS12960 Rev 1

ST MICROELECTRONICS STM32G441RBT6 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Table 1. Device summary

1 Introduction

2 Description

Figure 1. STM32G441xB block diagram

3 Functional overview

3.1 Arm® Cortex®-M4 core with FPU

3.2 Adaptive real-time memory accelerator (ART accelerator)

3.3 Memory protection unit

3.4 Embedded Flash memory

3.5 Embedded SRAM

3.6 Multi-AHB bus matrix

Figure 2. Multi-AHB bus matrix

3.7 Boot modes

3.8 CORDIC

3.9 Filter mathematical accelerator (FMAC)

3.10 Cyclic redundancy check calculation unit (CRC)

3.11 Power supply management

3.11.1 Power supply schemes

3.11.2 Power supply supervisor

3.11.3 Voltage regulator

3.11.4 Low-power modes

3.11.5 Reset mode

3.11.6 VBAT operation

3.12 Interconnect matrix

Table 3. STM32G441xB peripherals interconnect matrix

3.13 Clocks and startup

3.14 General-purpose inputs/outputs (GPIOs)

3.15 Direct memory access controller (DMA)

Table 4. DMA implementation

3.16 DMA request router (DMAMux)

3.17 Interrupts and events

3.17.1 Nested vectored interrupt controller (NVIC)

3.17.2 Extended interrupt/event controller (EXTI)

3.18 Analog-to-digital converter (ADC)

3.18.1 Temperature sensor

Table 5. Temperature sensor calibration values

Table 6. Internal voltage reference calibration values

3.19 Digital to analog converter (DAC)

Figure 3. Voltage reference buffer

3.21 Comparators (COMP)

3.22 Operational amplifier (OPAMP)

3.23 Random number generator (RNG)

3.24 Advanced encryption standard hardware accelerator (AES)

3.25 Timers and watchdogs

3.25.1 Advanced motor control timer (TIM1, TIM8)

3.25.2 General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16, TIM17)

3.25.3 Basic timers (TIM6 and TIM7)

3.25.4 Low-power timer (LPTIM1)

3.25.5 Independent watchdog (IWDG)

3.25.6 System window watchdog (WWDG)

3.25.7 SysTick timer

3.26 Real-time clock (RTC) and backup registers

3.27 Tamper and backup registers (TAMP)

3.28 Infrared transmitter

Figure 4. Infrared transmitter

3.29 Inter-integrated circuit interface (I2C)

Table 8. I2C implementation

3.30 Universal synchronous/asynchronous receiver transmitter (USART)

3.31 Low-power universal asynchronous receiver transmitter (LPUART)

3.32 Serial peripheral interface (SPI)

3.33 Serial audio interfaces (SAI)

3.33.1 SAI peripheral supports

Table 10. SAI implementation for the features implementation

3.34 Controller area network (FDCAN1)

3.35 Universal serial bus (USB)

3.36 USB Type-C™ / USB Power Delivery controller (UCPD)

3.37 Clock recovery system (CRS)

3.38 Development support

3.38.1 Serial wire JTAG debug port (SWJ-DP)

3.38.2 Embedded trace macrocell™

4 Pinouts and pin description

4.1 UFQFPN32 pinout description

Figure 5. STM32G441xB UFQFPN32 pinout

4.2 LQFP32 pinout description

Figure 6. STM32G441xB LQFP32 pinout

4.3 UFQFPN48 pinout description