STM32G431x6 STM32G431x8
LQFP48 (7 x 7 mm)
LQFP64 (10 x 10 mm)
LQFP80 (12 x 12 mm)
LQFP32 (7 x 7 mm)
UFBGA64
(5 x 5 mm)
UFQFPN32 (5 x 5 mm)
UFQFPN48 (7 x 7 mm)
WLCSP49
(Pitch 0.4)
FBGA
LQFP100 (14 x 14 mm)
Arm® Cortex®-M4 32b MCU+FPU, 170 MHz / 213DMIPS,
up to 128 KB Flash, 32KB SRAM, rich analog, math accelerator
Features
• Core: Arm® 32-bit Cortex®-M4 CPU with FPU,
Adaptive real-time accelerator (ART
Accelerator) allowing 0-wait-state execution
from Flash memory, frequency up to 170 MHz
with 213 DMIPS, MPU, DSP instructions
• Operating conditions:
– VDD, VDDA voltage range:
1.71 V to 3.6 V
• Mathematical hardware accelerators
– CORDIC for trigonometric functions
acceleration
– FMAC: Filter mathematical accelerator
• Memories
– 128 Kbytes of Flash memory with ECC
support, proprietary code readout
protection (PCROP), securable memory
area, 1 Kbyte OTP
– 22 Kbytes of SRAM, with hardware parity
check implemented on the first 16 Kbytes
– Routine booster: 10 Kbytes of SRAM on
instruction and data bus, with hardware
parity check (CCM SRAM)
• Reset and supply management
– Power-on/power-down reset
(POR/PDR/BOR)
– Programmable voltage detector (PVD)
– Low-power modes: sleep, stop, standby
and shutdown
–V
• Clock management
–4
– 32 kHz oscillator with calibration
– Internal 16 MHz RC with PLL option (± 1%)
–
• Up to 86 fast I/Os
– All mappable on external interrupt vectors
– Several I/Os with 5 V tolerant capability
supply for RTC and backup registers
BAT
to 48 MHz crystal oscillator
Internal 32 kHz RC oscillator (± 5%)
STM32G431xB
Datasheet - production data
• Interconnect matrix
• 12-channel DMA controller
• 2 x ADCs 0.25 µs(up to 23 channels).
Resolution up to 16-bit with hardware
oversampling, 0 to 3.6 V conversion range
• 4 x 12-bit DAC channels
– 2 x buffered external channels 1 MSPS
– 2 x unbuffered internal channels 15 MSPS
• 4 x ultra-fast rail-to-rail analog comparators
• 3 x operational amplifiers that can be used in
PGA mode, all terminals accessible
• Internal voltage reference buffer (VREFBUF)
supporting three output voltages (2.048 V,
2.5 V, 2.95 V)
• 14 timers:
– 1 x 32-bit timer and 2 x 16-bit timers with up
to four IC/OC/PWM or pulse counter and
quadrature (incremental) encoder input
– 2 x 16-bit 8-channel advanced motor
control timers, with up to 8 x PWM
channels, dead time generation and
emergency stop
– 1 x 16-bit timer with 2 x IC/OCs, one
OCN/PWM, dead time generation and
emergency stop
– 2 x 16-bit timers with IC/OC/OCN/PWM,
dead time generation and emergency stop
– 2 x watchdog timers (independent, window)
– 1 x SysTick timer: 24-bit downcounter
– 2 x 16-bit basic timers
– 1 x low-power timer
May 2019 DS12589 Rev 1 1/198
This is information on a product in full production.
www.st.com
STM32G431x6 STM32G431x8 STM32G431xB
• Calendar RTC with alarm, periodic wakeup
from stop/standby
• Communication interfaces
– 1 x FDCAN controller supporting flexible
data rate
– 3 x I
2
C Fast mode plus (1 Mbit/s) with
20 mA current sink, SMBus/PMBus,
wakeup from stop
– 4 x USART/UARTs (ISO 7816 interface,
LIN, IrDA, modem control)
–1 x LPUART
– 3 x SPIs, 4 to 16 programmable bit frames,
2 x with multiplexed half duplex I
2
S
– 1 x SAI (serial audio interface)
– USB 2.0 full-speed interface with LPM and
BCD support
– IRTIM (infrared interface)
– USB Type-C™ /USB power delivery
controller (UCPD)
• True random number generator (RNG)
• CRC calculation unit, 96-bit unique ID
• Development support: serial wire debug
(SWD), JTAG, Embedded trace macrocell™
interface
Table 1. Device summary
Reference Part number
STM32G431x6 STM32G431C6, STM32G431K6, STM32G431R6, STM32G431V6, STM32G431M6
STM32G431x8 STM32G431C8, STM32G431K8, STM32G431R8, STM32G431V8, STM32G431M8
STM32G431xB STM32G431CB, STM32G431KB, STM32G431RB, STM32G431VB, STM32G431MB
2/198 DS12589 Rev 1
STM32G431x6 STM32G431x8 STM32G431xB Contents
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1 Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2 Adaptive real-time memory accelerator (ART accelerator) . . . . . . . . . . . 17
3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.6 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.7 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.8 CORDIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.9 Filter mathematical accelerator (FMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.10 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 21
3.11 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.11.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.11.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.11.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.11.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.11.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.11.6 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.12 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.13 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.14 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.15 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.16 DMA request router (DMAMux) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.17 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.17.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 28
3.17.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 28
3.18 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.18.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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Contents STM32G431x6 STM32G431x8 STM32G431xB
3.18.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.18.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.19 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.20 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.21 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.22 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.23 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.24 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.24.1 Advanced motor control timer (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . 33
3.24.2 General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16,
TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.24.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.24.4 Low-power timer (LPTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.24.5 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.24.6 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.24.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.25 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 36
3.26 Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.27 Infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.28 Inter-integrated circuit interface (I
2
C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.29 Universal synchronous/asynchronous receiver transmitter (USART) . . . 39
3.30 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 40
3.31 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.32 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.32.1 SAI peripheral supports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.33 Controller area network (FDCAN1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.34 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.35 USB Type-C™ / USB Power Delivery controller (UCPD) . . . . . . . . . . . . . 42
3.36 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.37 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.37.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.37.2 Embedded trace macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.1 UFQFPN32 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
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4.2 LQFP32 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.3 UFQFPN48 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.4 LQFP48 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.5 WLCSP49 ballout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.6 LQFP64 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.7 LQFP80 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.8 UFBGA64 ballout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.9 LQFP100 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.10 Pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.11 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 73
5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 73
5.3.4 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.3.6 Wakeup time from low-power modes and voltage scaling
transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
5.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 103
5.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 108
5.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
5.3.10 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
5.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
5.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
5.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
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Contents STM32G431x6 STM32G431x8 STM32G431xB
5.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
5.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5.3.16 Extended interrupt and event controller input (EXTI) characteristics . . 122
5.3.17 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.3.18 Analog-to-digital converter characteristics . . . . . . . . . . . . . . . . . . . . . . 123
5.3.19 Digital-to-Analog converter characteristics . . . . . . . . . . . . . . . . . . . . . 134
5.3.20 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 141
5.3.21 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
5.3.22 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 145
5.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
5.3.24 V
5.3.25 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
5.3.26 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 151
5.3.27 UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
BAT
6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
6.1 UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
6.2 LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
6.3 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
6.4 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
6.5 WLCSP49 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
6.6 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
6.7 LQFP80 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
6.8 UFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
6.9 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
6.10 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
6.10.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
6.10.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 194
7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
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List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table 2. STM32G431x6/x8/xB features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3. STM32G431x6/x8/xB peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 4. DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 5. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 6. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 7. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 8. I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 9. USART/UART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 10. SAI implementation for the features implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 11. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 12. STM32G431x6/x8/xB pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 13. Alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 14. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 15. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 16. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 17. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 18. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 19. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 20. Embedded internal voltage reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 21. Current consumption in Run and Low-power run modes, code with data
processing running from Flash in single Bank, ART enable (Cache ON Prefetch OFF) . . 77
Table 22. Current consumption in Run and Low-power run modes,
code with data processing running from Flash in single Bank, ART disable . . . . . . . . . . . 79
Table 23. Current consumption in Run and Low-power run modes,
code with data processing running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 24. Typical current consumption in Run and Low-power run modes, with different codes
running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . . 83
Table 25. Typical current consumption in Run and Low-power run modes,
with different codes running from Flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 26. Typical current consumption in Run and Low-power run modes, with different codes
running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 27. Typical current consumption in Run and Low-power run modes, with different codes
running from SRAM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 28. Typical current consumption in Run and Low-power run modes, with different codes
running from CCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 29. Current consumption in Sleep and Low-power sleep mode Flash ON . . . . . . . . . . . . . . . . 88
Table 30. Current consumption in low-power sleep modes, Flash in power-down. . . . . . . . . . . . . . . 89
Table 31. Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 32. Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 33. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 34. Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 35. Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 36. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 37. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 38. Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 39. Wakeup time using USART/LPUART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 40. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
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Table 41. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 42. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 43. LSE oscillator characteristics (f
= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
LSE
Table 44. HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 45. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 46. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 47. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 48. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 49. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 50. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 51. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 52. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 53. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 54. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 55. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 56. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 57. I/O (except FT_c) AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 58. I/O FT_c AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 59. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 60. EXTI input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 61. Analog switches booster characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 62. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 63. Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 64. ADC accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 65. ADC accuracy - limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 66. ADC accuracy - limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 67. DAC 1MSPS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 68. DAC 1MSPS accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 69. DAC 15MSPS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 70. DAC 15MSPS accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 71. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 72. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 73. OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 74. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 75. V
Table 76. V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
BAT
charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
BAT
Table 77. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 78. IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 79. WWDG min/max timeout value at 170 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 80. Minimum I2CCLK frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 81. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 82. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 83. I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 84. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 85. USB electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 86. USART electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 87. UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 88. UFQFPN - 32 pins, 5 x 5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 89. LQFP - 32-pin, 7 x 7 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 90. UFQFPN - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
8/198 DS12589 Rev 1
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package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 91. LQFP - 48 pins, 7 x 7 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Table 92. WLCSP - 49 balls, 3.15 x 3.13 mm, 0.4 mm pitch, wafer level chip scale
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 93. WLCSP49 recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 94. LQFP - 64 pins, 10 x 10 mm low-profile quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 95. LQFP - 80 pins, 12 x 12 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 96. UFBGA – 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid
array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 97. UFBGA64 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . 187
Table 98. LQPF - 100 pins, 14 x 14 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 99. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 100. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 101. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
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List of figures STM32G431x6 STM32G431x8 STM32G431xB
List of figures
Figure 1. STM32G431x6/x8/xB block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 2. Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 3. Voltage reference buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 4. Infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 5. STM32G431x6/x8/xB UFQFPN32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 6. STM32G431x6/x8/xB LQFP32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 7. STM32G431x6/x8/xB UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 8. STM32G431x6/x8/xB LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 9. STM32G431x6/x8/xB WLCSP49 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 10. STM32G431x6/x8/xB LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 11. STM32G431x6/x8/xB LQFP80 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 12. STM32G431x6/x8/xB UFBGA64 ballout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 13. STM32G431x6/x8/xB LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 14. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 15. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 16. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 17. Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 18. VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 19. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 20. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 21. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 22. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 23. HSI16 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 24. HSI48 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 25. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 26. I/O AC characteristics definition
Figure 27. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 28. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 29. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 30. 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 31. VREFOUT_TEMP in case VRS = 00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 32. VREFOUT_TEMP in case VRS = 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 33. VREFOUT_TEMP in case VRS = 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 34. OPAMP noise density @ 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 35. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 36. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 37. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 38. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 39. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 40. UFQFPN - 32 pins, 5 x 5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 41. UFQFPN - 32 pins, 5 x 5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 42. UFQFPN32, 5 x 5 mm, 0.5 mm pitch package top view example . . . . . . . . . . . . . . . . . 164
Figure 43. LQFP - 32-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . 165
Figure 44. LQFP - 32-pin, 7 x 7 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 45. LQFP32, 7 x 7 mm, low-profile quad flat package top view example . . . . . . . . . . . . . . . 168
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
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Figure 46. UFQFPN - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 47. UFQFPN - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 48. UFQFPN48, 7 x 7 mm, low-profile quad flat package top view example . . . . . . . . . . . . . 171
Figure 49. LQFP - 48 pins, 7 x 7 mm low-profile quad flat package outline. . . . . . . . . . . . . . . . . . . . 172
Figure 50. LQFP - 48 pins, 7 x 7 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Figure 51. LQFP48, 7 x 7 mm, low-profile quad flat package top view example . . . . . . . . . . . . . . . . 175
Figure 52. WLCSP - 49 balls, 3.15 x 3.13 mm, 0.4 mm pitch, wafer level chip scale
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 53. WLCSP - 49 balls, 3.14x 3.15 mm, 0.4 mm pitch, wafer level chip scale
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 54. WLCSP49, 0.4 mm pitch wafer level chip scale package
top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 55. LQFP - 64 pins, 10 x 10 mm low-profile quad flat package outline. . . . . . . . . . . . . . . . . . 180
Figure 56. LQFP - 64 pins, 10 x 10 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 57. LQFP64, 10 x 10 mm, low-profile quad flat package top view example . . . . . . . . . . . . . 182
Figure 58. LQFP - 80 pins, 12 x 12 mm low-profile quad flat package outline. . . . . . . . . . . . . . . . . . 183
Figure 59. LQFP - 80 pins, 12 x 12 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 60. LQFP80, 12 x 12 mm, low-profile quad flat package top view example . . . . . . . . . . . . . . 185
Figure 61. UFBGA – 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid
array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Figure 62. UFBGA – 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid
array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 63. UFBGA64, 5 × 5 × 0.5 mm ultra thin fine-pitch ball grid array
package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 64. LQFP - 100 pins, 14 x 14 mm low-profile quad flat package outline. . . . . . . . . . . . . . . . . 189
Figure 65. LQFP - 100 pins, 14 x 14 mm low-profile quad flat
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Figure 66. LQFP100 - 14 x 14 mm, low-profile quad flat package top view example . . . . . . . . . . . . 191
DS12589 Rev 1 11/198
11
Introduction STM32G431x6 STM32G431x8 STM32G431xB
1 Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32G431x6/x8/xB microcontrollers.
This document should be read in conjunction with the reference manual RM0440
“STM32G4 Series advanced Arm
®
32-bit MCUs”. The reference manual is available from
the STMicroelectronics website www.st.com.
For information on the Arm
®(a)
Cortex®-M4 core, refer to the Cortex®-M4 technical
reference manual, available from the www.arm.com website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
12/198 DS12589 Rev 1
STM32G431x6 STM32G431x8 STM32G431xB Description
2 Description
The STM32G431x6/x8/xB devices are based on the high-performance Arm® Cortex®-M4
32-bit RISC core. They operate at a frequency of up to 170 MHz.
The Cortex-M4 core features a single-precision floating-point unit (FPU), which supports all
the Arm single-precision data-processing instructions and all the data types. It also
implements a full set of DSP (digital signal processing) instructions and a memory protection
unit (MPU) which enhances the application’s security.
These devices embed high-speed memories (128 Kbytes of Flash memory, and 32 Kbytes
of SRAM), an extensive range of enhanced I/Os and peripherals connected to two APB
buses, two AHB buses and a 32-bit multi-AHB bus matrix.
The devices also embed several protection mechanisms for embedded Flash memory and
SRAM: readout protection, write protection, securable memory area and proprietary code
readout protection.
The devices embed peripherals allowing mathematical/arithmetic function acceleration
(CORDIC for trigonometric functions and FMAC unit for filter functions).
They offer two fast 12-bit ADCs (5 Msps), four comparators, three operational amplifiers,
four DAC channels (2 external and 2 internal), an internal voltage reference buffer, a low-
power RTC, one general-purpose 32-bit timers, two 16-bit PWM timers dedicated to motor
control, seven general-purpose 16-bit timers, and one 16-bit low-power timer.
They also feature standard and advanced communication interfaces such as:
• Three I2Cs
• Three SPIs multiplexed with two half duplex I2Ss
• Three USARTs, one UART and one low-power UART.
• One FDCAN
• One SAI
• USB device
• UCPD
The devices operate in the -40 to +85 °C (+105 °C junction), -40 to +105 °C (+125 °C
junction) and -40 to +125 °C (+130 °C junction) temperature ranges from a 1.71 to 3.6 V
power supply. A comprehensive set of power-saving modes allows the design of low-power
applications.
Some independent power supplies are supported including an analog independent supply
input for ADC, DAC, OPAMPs and comparators. A VBAT input allows backup of the RTC
and the registers.
The STM32G431x6/x8/xB family offers 9 packages from 32-pin to 100-pin.
DS12589 Rev 1 13/198
43
Description STM32G431x6 STM32G431x8 STM32G431xB
Table 2. STM32G431x6/x8/xB features and peripheral counts
Peripheral STM32G431Kx STM32G431Cx STM32G431Rx STM32G431Mx STM32G431Vx
Flash memory
32 KB64 KB128 KB32 KB64 KB128KB32KB64 KB128KB32 KB64 KB128 KB32 KB64 KB128
SRAM 32 (16 + 6 + 10) KB
Advanced
motor control
General
purpose
2 (16-bit)
5 (16-bit)
1 (32-bit)
Basic 2 (16-bit)
Low power 1 (16-bit)
SysTick timer 1
Timers
Watchdog
timers
(independent,
2
window)
PWM channels
(all)
23 31 35 35 35
PWM channels
(except
19 24 24 24 24
complementary)
SPI(I2S)
2
I
(1)
C3
3 (2)
KB
USART 2 3
UART 0 1
Comm.
interfaces
LPUART 1
FDCANs 1
USB device Yes
UCPD Yes
SAI Yes
RTC Yes
Tamper pins 1 2 2 3
Random number generator Yes
AES No
CORDIC Yes
FMAC Yes
GPIOs
Wakeup pins
26
2
38 in LQFP48
42 in UFQFPN48
41 in WLCSP49
3
52
66
4
4
86
5
14/198 DS12589 Rev 1
STM32G431x6 STM32G431x8 STM32G431xB Description
Table 2. STM32G431x6/x8/xB features and peripheral counts (continued)
Peripheral STM32G431Kx STM32G431Cx STM32G431Rx STM32G431Mx STM32G431Vx
2
12-bit ADCs
Number of channels
11
12-bit DAC
Number of channels
Internal voltage reference
buffer
Analog comparator 4
Operational amplifiers 3
Max. CPU frequency 170 MHz
Operating voltage 1.71 V to 3.6 V
Operating temperature Ambient operating temperature: -40 to 85 °C / -40 to 105 °C / -40 to 125 °C
17 in LQFP48
18 in UFQFPN48
18 in WLCSP49
4 (2 external + 2 internal)
23 23 23
2
Yes
Packages
1. The SPI2/3 interfaces can work in an exclusive way in either the SPI mode or the I2S audio mode.
LQFP32/
UFQFPN32
LQFP48/
UFQFPN48/
WLCSP49
LQFP64/
UFBGA64
LQFP80 LQFP100
DS12589 Rev 1 15/198
43
GPIO PORT A
AHB/APB2
USART 2MBps
EXT IT. WKUP
140 AFP
USART 2MBps
GPIO PORT B
PB(15:0)
USART 2MBps
GPIO PORT C
PC(15:0)
USART 2MBps
RX, TX, SCK,CTS,
RTS as AF
USART 2MBps
GPIO PORT D
PD(15:0)
USART 2MBps
GPIO PORT E
PE(15:0)
USART 2MBps
SPI 1
MOSI, MISO
SCK, NSS as AF
APB2 60MHzAPB1
4 CH, ETR as AF
TIMER2
4 CH, ETR as AF
TIMER3&4
RX, TX, SCK,
CTS, RTS as AF
USART2&3
UART4
MOSI, MISO, SCK
SPI2&3
NSS, as AF
OUT1/OUT2
DAC1
TIMER6
RTC_OUT
RTC_TS
RTC_TAMPx
OSC_IN
OSC_OUT
VDD, VSS,
VDDA, VSSA,
RESET
VBAT = 1.55 to 3.6V
AHB/APB1
JTAG & SW
Arm
®
Cortex-M4
150MHz
S-BUS
ETM
MPU
TRACECK
TRACED(3:0)
JTRST, JTDI,
JTCK/SWCLK
JTDO/SWD, JTDO
GP-DMA2
GP-DMA1
6 Chan
FLASH 128 KB
ACCEL/
CACHE
AHB1
@VDDA
POR / BOR
SUPPLY
@VDD
SUPERVISION
Reset
Int
POR
XTAL OSC
4-48MHz
XTAL 32kHz
RTC
AWU
BKPREG
LSI
Standby Interface
IWDG
@VBAT
@VDD
RESET&
CLOCKCTRL
PLL
VDD = 1.71 to 3.6V
VSS
VOLT. REG.
3.3V TO 1.2V
VDD12
POWER MNGT
AHB BUS-MATRIX 5M / 7S
APB2
peripheralclocks
RTC Interface
FPU
WinWATCHDOG
and system
LP timer1
AHB2
SAR ADC2
Ain ADC
SysCfg
CRC
LP_UART1
I2C1&2&3
SCL, SDA, SMBAL as AF
RNG
RNB1
analog
COMP
1,2,3,4
SRAM2 6 KB
PWRCTRL
CAN1
FIFO
RX,TX as AF
Vref_Buf
CRS
6 Chan
SRAM1 16 KB
CCM SRAM 10 KB
DMAMUX
HSI
SAR ADC1
IF
@VDDA
16b trigg
TIMER7
16b trigg
USBPD
PHY
CC1
CC2
HSI48
CH2
USB
Device
PHY
D+
D-
FIFO
I2S half
duplex
CH1
OPAMP
1,2,3
USART 2MBps
GPIO PORT F
PF(10:9,2:0)
DAC3
CH2
CH1
USART 2MBps
GPIO PORT G
PG(10:10)
CORDIC
FMAC
SAI1
FS, SCK, SD,
MCLK as AF
MSv62521V1
irDA
Smcard
irDA
RX, TX, CTS,
RTS as AF
RX, TX as AF
OSC32_IN
OSC_OUT
@VDDA
NVIC
I-BUS
D-BUS
PVD, PWM
PA(15:0)
TIMER1
16b PWM
TIMER8
16b PWM
USART 2MBps
CH as AF
TIMER15
16b
USART 2MBps
CH as AF
TIMER16
16b
USART 2MBps
TIMER17
CH as AF16b
16b
4 PWM,4PWM,
ETR,BKIN as F
4 PWM,4PWM,
ETR,BKIN as F
USART1
Smcard
irDA
Description STM32G431x6 STM32G431x8 STM32G431xB
Figure 1. STM32G431x6/x8/xB block diagram
Note: AF: alternate function on I/O pins.
16/198 DS12589 Rev 1
STM32G431x6 STM32G431x8 STM32G431xB Functional overview
3 Functional overview
3.1 Arm® Cortex®-M4 core with FPU
The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
the MCU implementation, with a reduced pin count and with low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.
The Arm
efficiency, delivering the expected high-performance from an Arm core in a memory size
usually associated with 8-bit and 16-bit devices.
The processor supports a set of DSP instructions which allows an efficient signal processing
and a complex algorithm execution. Its single precision FPU speeds up the software
development by using metalanguage development tools to avoid saturation.
With its embedded Arm core, the STM32G431x6/x8/xB family is compatible with all Arm
tools and software.
Figure 1 shows the general block diagram of the STM32G431x6/x8/xB devices.
®
Cortex®-M4 with FPU 32-bit RISC processor features an exceptional code-
3.2 Adaptive real-time memory accelerator (ART accelerator)
The ART accelerator is a memory accelerator that is optimized for the STM32 industrystandard Arm
the Arm
processor to wait for the Flash memory at higher frequencies.
®
®
Cortex®-M4 processors. It balances the inherent performance advantage of
Cortex®-M4 over Flash memory technologies, which normally requires the
3.3 Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to the memory
and to prevent one task to accidentally corrupt the memory or the resources used by any
other active task. This memory area is organized into up to 8 protected areas, which can be
divided in up into 8 subareas each. The protection area sizes range between 32 bytes and
the whole 4 gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
3.4 Embedded Flash memory
The STM32G431x6/x8/xB devices feature 128 kbytes of embedded Flash memory which is
available for storing programs and data.
Flexible protections can be configured thanks to the option bytes:
DS12589 Rev 1 17/198
43
Functional overview STM32G431x6 STM32G431x8 STM32G431xB
• Readout protection (RDP) to protect the whole memory. Three levels of protection are
available:
– Level 0: no readout protection
– Level 1: memory readout protection; the Flash memory cannot be read from or written
to if either the debug features are connected or the boot in RAM or bootloader are
selected
– Level 2: chip readout protection; the debug features (Cortex-M4 JTAG and serial
wire), the boot in RAM and the bootloader selection are disabled (JTAG fuse). This
selection is irreversible.
• Write protection (WRP): the protected area is protected against erasing and
programming.
• Proprietary code readout protection (PCROP): a part of the Flash memory can be
protected against read and write from third parties. The protected area is execute-only
and it can only be reached by the STM32 CPU as an instruction code, while all other
accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited. An
additional option bit (PCROP_RDP) allows to select if the PCROP area is erased or not
when the RDP protection is changed from Level 1 to Level 0.
• Securable memory area: a part of Flash memory can be configured by option bytes to
be securable. After reset this securable memory area is not secured and it behaves like
the remainder of main Flash memory (execute, read, write access). When secured, any
access to this securable memory area generates corresponding read/write error.
Purpose of the Securable memory area is to protect sensitive code and data (secure
keys storage) which can be executed only once at boot, and never again unless a new
reset occurs.
The Flash memory embeds the error correction code (ECC) feature supporting:
• Single error detection and correction
• Double error detection
• The address of the ECC fail can be read in the ECC register
• 1 Kbyte (128 double word) OTP (one-time programmable) bytes for user data. The
OTP area is available in Bank 1 only. The OTP data cannot be erased and can be
written only once.
3.5 Embedded SRAM
STM32G431x6/x8/xB devices feature 32 Kbytes of embedded SRAM. This SRAM is split
into three blocks:
• 16 Kbytes mapped at address 0x2000 0000 (SRAM1). The CM4 can access the
SRAM1 through the System Bus or through the I-Code/D-Code bus.
• 6 Kbytes mapped at address 0x2000 4000 (SRAM2). The CM4 can access the SRAM2
through the System Bus or through the I-Code/D-Code bus. SRAM2 can be kept in
stop and standby modes.
• 10 Kbytes mapped at address 0x1000 0000 (CCM SRAM). It is accessed by the CPU
through I-Code/D-Code bus for maximum performance.
It is also aliased at 0x2000 5800 address to be accessed by all masters (CPU, DMA1,
DMA2) through SBUS contiguously to SRAM1 and SRAM2.
18/198 DS12589 Rev 1
STM32G431x6 STM32G431x8 STM32G431xB Functional overview
MS47544V1
Cortex®-M4
with FPU
DMA1 DMA2
CCM
SRAM
AHB1
peripherals
AHB2
peripherals
SRAM1
FLASH
128 KB
ACCEL
S-bus
D-bus
ICode
DCode
I-bus
BusMatrix-S
SRAM2
3.6 Multi-AHB bus matrix
The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs) and the slaves
(Flash memory, RAM, AHB and APB peripherals). It also ensures a seamless and efficient
operation even when several high-speed peripherals work simultaneously.
Figure 2. Multi-AHB bus matrix
3.7 Boot modes
At startup, a BOOT0 pin (or nBOOT0 option bit)and an nBOOT1 option bit are used to select
one of three boot options:
• Boot from user Flash
• Boot from system memory
• Boot from embedded SRAM
The BOOT0 value may come from the PB8-BOOT0 pin or from an nBOOT0 option bit
depending on the value of a user nBOOT_SEL option bit to free the GPIO pad if needed.
The boot loader is located in the system memory. It is used to reprogram the Flash memory
by using USART, I2C, SPI, and USB through the DFU (device firmware upgrade).
DS12589 Rev 1 19/198
43
Functional overview STM32G431x6 STM32G431x8 STM32G431xB
3.8 CORDIC
The CORDIC provides hardware acceleration of certain mathematical functions, notably
trigonometric, commonly used in motor control, metering, signal processing and many other
applications.
It speeds up the calculation of these functions compared to a software implementation,
allowing a lower operating frequency, or freeing up processor cycles in order to perform
other tasks.
Cordic features
• 24-bit CORDIC rotation engine
• Circular and Hyperbolic modes
• Rotation and Vectoring modes
• Functions: Sine, Cosine, Sinh, Cosh, Atan, Atan2, Atanh, Modulus, Square root,
Natural logarithm
• Programmable precision up to 20-bit
• Fast convergence: 4 bits per clock cycle
• Supports 16-bit and 32-bit fixed point input and output formats
• Low latency AHB slave interface
• Results can be read as soon as ready without polling or interrupt
• DMA read and write channels
3.9 Filter mathematical accelerator (FMAC)
The filter mathematical accelerator unit performs arithmetic operations on vectors. It
comprises a multiplier/accumulator (MAC) unit, together with address generation logic,
which allows it to index vector elements held in local memory.
The unit includes support for circular buffers on input and output, which allows digital filters
to be implemented. Both finite and infinite impulse response filters can be realized.
The unit allows frequent or lengthy filtering operations to be offloaded from the CPU, freeing
up the processor for other tasks. In many cases it can accelerate such calculations
compared to a software implementation, resulting in a speed-up of time critical tasks.
20/198 DS12589 Rev 1
STM32G431x6 STM32G431x8 STM32G431xB Functional overview
FMAC features
• 16 x 16-bit multiplier
• 24+2-bit accumulator with addition and subtraction
• 16-bit input and output data
• 256 x 16-bit local memory
• Up to three areas can be defined in memory for data buffers (two input, one output),
defined by programmable base address pointers and associated size registers
• Input and output sample buffers can be circular
• Buffer “watermark” feature reduces overhead in interrupt mode
• Filter functions: FIR, IIR (direct form 1)
• AHB slave interface
• DMA read and write data channels
3.10 Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator with polynomial value and size.
Among other applications, the CRC-based techniques are used to verify data transmission
or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a mean to verify
the Flash memory integrity.
The CRC calculation unit helps to compute a signature of the software during runtime, which
can be ulteriorly compared with a reference signature generated at link-time and which can
be stored at a given memory location.
3.11 Power supply management
3.11.1 Power supply schemes
The STM32G431x6/x8/xB devices require a 1.71 V to 3.6 V V
Several independent supplies, can be provided for specific peripherals:
• V
• V
= 1.71 V to 3.6 V
DD
V
is the external power supply for the I/Os, the internal regulator and the system
DD
analog such as reset, power management and internal clocks. It is provided externally
through the VDD pins.
= 1.62 V to 3.6 V (see Section 5: Electrical characteristics for the minimum VDDA
DDA
voltage required for ADC, DAC, COMP, OPAMP, VREFBUF operation).
V
is the external analog power supply for A/D converters, D/A converters, voltage
DDA
reference buffer, operational amplifiers and comparators. The V
operating voltage supply.
DD
voltage level is
DDA
DS12589 Rev 1 21/198
43
Functional overview STM32G431x6 STM32G431x8 STM32G431xB
independent from the V
DD
these peripherals are not used.
• V
= 1.55 V to 3.6 V
BAT
V
is the power supply for RTC, external clock 32 kHz oscillator and backup registers
BAT
(through power switch) when V
• V
REF-, VREF+
V
is the input reference voltage for ADCs and DACs. It is also the output of the
REF+
internal voltage reference buffer when enabled.
When V
When V
DDA
DDA
< 2 V V
2 V V
must be equal to V
REF+
must be between 2 V and V
REF+
The internal voltage reference buffer supports three output voltages, which are
configured with VRS bits in the VREFBUF_CSR register:
–V
–V
–V
V
REF-
= 2.048 V
REF+
= 2.5 V
REF+
= 2.95 V
REF+
is double bonded with V
3.11.2 Power supply supervisor
The device has an integrated ultra-low-power brown-out reset (BOR) active in all modes
(except for Shutdown mode). The BOR ensures proper operation of the device after poweron and during power down. The device remains in reset mode when the monitored supply
voltage V
The lowest BOR level is 1.71 V at power on, and other higher thresholds can be selected
through option bytes.The device features an embedded programmable voltage detector
(PVD) that monitors the V
interrupt can be generated when V
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
is below a specified threshold, without the need for an external reset circuit.
DD
power supply and compares it to the VPVD threshold. An
DD
voltage and should preferably be connected to VDD when
is not present.
DD
.
DDA
.
DDA
.
SSA
drops below the VPVD threshold and/or when VDD is
DD
In addition, the device embeds a peripheral voltage monitor which compares the
independent supply voltages V
, with a fixed threshold in order to ensure that the
DDA
peripheral is in its functional supply range.
3.11.3 Voltage regulator
Two embedded linear voltage regulators, main regulator (MR) and low-power regulator
(LPR), supply most of digital circuitry in the device. The MR is used in Run and Sleep
modes. The LPR is used in Low-power run, Low-power sleep and Stop modes. In Standby
and Shutdown modes, both regulators are powered down and their outputs set in highimpedance state, such as to bring their current consumption close to zero.
The device supports dynamic voltage scaling to optimize its power consumption in Run
mode. the voltage from the main regulator that supplies the logic (VCORE) can be adjusted
according to the system’s maximum operating frequency.
The main regulator (MR) operates in the following ranges:
• Range 1 boost mode with the CPU running at up to 170 MHz.
• Range 1 normal mode with CPU running at up to 150 MHz.
• Range 2 with a maximum CPU frequency of 26 MHz.
22/198 DS12589 Rev 1
STM32G431x6 STM32G431x8 STM32G431xB Functional overview
3.11.4 Low-power modes
By default, the microcontroller is in Run mode after system or power Reset. It is up to the
user to select one of the low-power modes described below:
• Sleep mode: In Sleep mode, only the CPU is stopped. All peripherals continue to
operate and can wake up the CPU when an interrupt/event occurs.
• Low-power run mode: This mode is achieved with VCORE supplied by the low-power
regulator to minimize the regulator's operating current. The code can be executed from
SRAM or from Flash, and the CPU frequency is limited to 2 MHz. The peripherals with
independent clock can be clocked by HSI16.
• Stop mode: In Stop mode, the device achieves the lowest power consumption while
retaining the SRAM and register contents. All clocks in the VCORE domain are
stopped. The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are
disabled. The LSE or LSI keep running. The RTC can remain active (Stop mode with
RTC, Stop mode without RTC). Some peripherals with wakeup capability can enable
the HSI16 RC during Stop mode, so as to get clock for processing the wakeup event.
• Standby mode: The Standby mode is used to achieve the lowest power consumption
with brown-out reset, BOR. The internal regulator is switched off to power down the
VCORE domain. The PLL, as well as the HSI16 RC oscillator and the HSE crystal
oscillator are also powered down. The RTC can remain active (Standby mode with
RTC, Standby mode without RTC). The BOR always remains active in Standby mode.
For each I/O, the software can determine whether a pull-up, a pull-down or no resistor
shall be applied to that I/O during Standby mode. Upon entering Standby mode, SRAM
and register contents are lost except for registers in the RTC domain and standby
circuitry. The device exits Standby mode upon external reset event (NRST pin), IWDG
reset event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC
event (alarm, periodic wakeup, timestamp, tamper), or when a failure is detected on
LSE (CSS on LSE).
• Shutdown mode: The Shutdown mode allows to achieve the lowest power
consumption. The internal regulator is switched off to power down the VCORE domain.
The PLL, as well as the HSI16 and LSI RC-oscillators and HSE crystal oscillator are
also powered down. The RTC can remain active (Shutdown mode with RTC, Shutdown
mode without RTC). The BOR is not available in Shutdown mode. No power voltage
monitoring is possible in this mode. Therefore, switching to RTC domain is not
supported. SRAM and register contents are lost except for registers in the RTC
domain. The device exits Shutdown mode upon external reset event (NRST pin),
IWDG reset event, wakeup event (WKUP pin, configurable rising or falling edge) or
RTC event (alarm, periodic wakeup, timestamp, tamper).
3.11.5 Reset mode
In order to improve the consumption under reset, the I/Os state under and after reset is
“analog state” (the I/O schmitt trigger is disabled). In addition, the internal reset pull-up is
deactivated when the reset source is internal.
3.11.6 VBAT operation
The VBAT pin allows to power the device VBAT domain from an external battery, an external
supercapacitor, or from V
supercapacitor is present. The VBAT pin supplies the RTC with LSE and the backup
registers. Three anti-tamper detection pins are available in VBAT mode.
when there is no external battery and when an external
DD
DS12589 Rev 1 23/198
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Functional overview STM32G431x6 STM32G431x8 STM32G431xB
The VBAT operation is automatically activated when VDD is not present. An internal VBAT
battery charging circuit is embedded and can be activated when V
is present.
DD
Note: When the microcontroller is supplied from VBAT, neither external interrupts nor RTC
alarm/events exit the microcontroller from the VBAT operation.
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STM32G431x6 STM32G431x8 STM32G431xB Functional overview
3.12 Interconnect matrix
Several peripherals have direct connections between them. This allows autonomous
communication between peripherals, saving CPU resources thus power supply
consumption. In addition, these hardware connections allow fast and predictable latency.
Depending on peripherals, these interconnections can operate in Run, Sleep and Stop
modes.
Table 3. STM32G431x6/x8/xB peripherals interconnect matrix
Interconnect source
TIMx
TIM16/TIM17 IRTIM Infrared interface output generation Y Y Y -
COMPx
ADCx TIM1, 8 Timer triggered by analog watchdog Y Y Y -
RTC
All clocks sources (internal
and external)
USB TIM2 Timer triggered by USB SOF Y Y - -
CSS
CPU (hard fault)
RAM (parity error)
Flash memory (ECC error)
COMPx
PVD
Interconnect
destination
TIMx Timers synchronization or chaining Y Y Y -
ADCx
DACx
DMA Memory to memory transfer trigger Y Y Y -
COMPx Comparator output blanking Y Y Y -
TIM1, 8
TIM2, 3, 4
LPTIMER1
TIM16
LPTIMER1
TIM15, 16, 17
TIM1,8
TIM15,16,17
TIMx External trigger Y Y Y -
Conversion triggers Y Y Y -
Timer input channel, trigger, break
from analog signals comparison
Low-power timer triggered by
analog signals comparison
Timer input channel from RTC
events
Low-power timer triggered by RTC
alarms or tampers
Clock source used as input channel
for RC measurement and trimming
Timer break Y Y Y -
Interconnect action
Run
Sleep
Low-power run
YYY -
YYYY
YYY -
YYYY
YYY -
Stop
GPIO
LPTIMER1 External trigger Y Y Y -
ADCx
DACx
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Conversion external trigger Y Y Y -
43
Functional overview STM32G431x6 STM32G431x8 STM32G431xB
3.13 Clocks and startup
The clock controller distributes the clocks coming from different oscillators to the core and
the peripherals. It also manages clock gating for low-power modes and ensures clock
robustness. It features:
• Clock prescaler: to get the best trade-off between speed and current consumption,
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler
• Safe clock switching: clock sources can be changed safely on the fly in run mode
through a configuration register.
• Clock management: to reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
• System clock source: three different sources can deliver SYSCLK system clock:
– 4 - 48 MHz high-speed oscillator with external crystal or ceramic resonator (HSE).
It can supply clock to system PLL. The HSE can also be configured in bypass
mode for an external clock.
– 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software. It can
supply clock to system PLL.
– System PLL with maximum output frequency of 170 MHz. It can be fed with HSE
or HSI16 clocks.
• RC48 with clock recovery system (HSI48): internal HSIRC48 MHz clock source can
be used to drive the USB or the RNG peripherals.
• Auxiliary clock source: two ultra-low-power clock sources for the real-time clock
(RTC):
– 32.768 kHz low-speed oscillator with external crystal (LSE), supporting four drive
capability modes. The LSE can also be configured in bypass mode for using an
external clock.
– 32 kHz low-speed internal RC oscillator (LSI) with ±5% accuracy, also used to
clock an independent watchdog.
• Peripheral clock sources: several peripherals (I2S, USART, I2C, LPTimer, ADC, SAI,
RNG) have their own clock independent of the system clock.
• Clock security system (CSS): in the event of HSE clock failure, the system clock is
automatically switched to HSI16 and, if enabled, a software interrupt is generated. LSE
clock failure can also be detected and generate an interrupt.
• Clock-out capability:
– MCO: microcontroller clock output: it outputs one of the internal clocks for external
use by the application
– LSCO: low speed clock output: it outputs LSI or LSE in all low-power modes.
Several prescalers allow to configure the AHB frequency, the High-speed APB (APB2) and
the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB
domains is 170 MHz.
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STM32G431x6 STM32G431x8 STM32G431xB Functional overview
3.14 General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be
achieved thanks to their mapping on the AHB2 bus.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
3.15 Direct memory access controller (DMA)
The device embeds 2 DMAs. Refer to Table 4: DMA implementation for the features
implementation.
Direct memory access (DMA) is used in order to provide a high-speed data transfer
between peripherals and memory as well as from memory to memory. Data can be quickly
moved by DMA without any CPU actions. This keeps the CPU resources free for other
operations.
The two DMA controllers have 12 channels in total, each one dedicated to manage memory
access requests from one or more peripherals. Each controller has an arbiter for handling
the priority between DMA requests.
The DMA supports:
• 12 independently configurable channels (requests)
– Each channel is connected to a dedicated hardware DMA request, a software
trigger is also supported on each channel. This configuration is done by software.
• Priorities between requests from channels of one DMA are both software
programmable (4 levels: very high, high, medium, low) or hardware programmable in
case of equality (request 1 has priority over request 2, etc.)
• Independent source and destination transfer size (byte, half word, word), emulating
packing and unpacking. Source/destination addresses must be aligned on the data
size.
• Support for circular buffer management
• 3 event flags (DMA half transfer, DMA transfer complete and DMA transfer error)
logically ORed together in a single interrupt request for each channel
• Memory-to-memory transfer
• Peripheral-to-memory, memory-to-peripheral, and peripheral-to-peripheral transfers
• Access to Flash, SRAM, APB and AHB peripherals as source and destination
• Programmable number of data to be transferred: up to 65536.
DMA features DMA1 DMA2
Number of regular channels 6 6
Table 4. DMA implementation
DS12589 Rev 1 27/198
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Functional overview STM32G431x6 STM32G431x8 STM32G431xB
3.16 DMA request router (DMAMux)
When a peripheral indicates a request for DMA transfer by setting its DMA request line, the
DMA request is pending until it is served and the corresponding DMA request line is reset.
The DMA request router allows to route the DMA control lines between the peripherals and
the DMA controllers of the product.
An embedded multi-channel DMA request generator can be considered as one of such
peripherals. The routing function is ensured by a multi-channel DMA request line
multiplexer. Each channel selects a unique set of DMA control lines, unconditionally or
synchronously with events on synchronization inputs.
For simplicity, the functional description is limited to DMA request lines. The other DMA
control lines are not shown in figures or described in the text. The DMA request generator
produces DMA requests following events on DMA request trigger inputs.
3.17 Interrupts and events
3.17.1 Nested vectored interrupt controller (NVIC)
The STM32G431x6/x8/xB devices embed a nested vectored interrupt controller which is
able to manage 16 priority levels, and to handle up to 71 maskable interrupt channels plus
the 16 interrupt lines of the Cortex
®
-M4.
The NVIC benefits are the following:
• Closely coupled NVIC gives low latency interrupt processing
• Interrupt entry vector table address passed directly to the core
• Allows early processing of interrupts
• Processing of late arriving higher priority interrupts
• Support for tail chaining
• Processor state automatically saved
• Interrupt entry restored on interrupt exit with no instruction overhead
The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.
3.17.2 Extended interrupt/event controller (EXTI)
The extended interrupt/event controller consists of 39 edge detector lines used to generate
interrupt/event requests and to wake-up the system from the Stop mode. Each external line
can be independently configured to select the trigger event (rising edge, falling edge, both)
and can be masked independently.
A pending register maintains the status of the interrupt requests. The internal lines are
connected to peripherals with wakeup from Stop mode capability. The EXTI can detect an
external line with a pulse width shorter than the internal clock period. Up to 86 GPIOs can
be connected to the 16 external interrupt lines.
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STM32G431x6 STM32G431x8 STM32G431xB Functional overview
3.18 Analog-to-digital converter (ADC)
The device embeds two successive approximation analog-to-digital converters with the
following features:
• 12-bit native resolution, with built-in calibration
• 4 Msps maximum conversion rate with full resolution
– Down to 25 ns sampling time
– Increased conversion rate for lower resolution (up to 6.66 Msps for 6-bit
resolution)
• One external reference pin is available on all packages, allowing the input voltage
range to be independent from the power supply
• Single-ended and differential mode inputs
• Low-power design
– Capable of low-current operation at low conversion rate (consumption decreases
linearly with speed)
– Dual clock domain architecture: ADC speed independent from CPU frequency
• Highly versatile digital interface
– Single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups
of analog signals conversions can be programmed to differentiate background and
high-priority real-time conversions
– Each ADC support multiple trigger inputs for synchronization with on-chip timers
and external signals
– Results stored into a data register or in RAM with DMA controller support
– Data pre-processing: left/right alignment and per channel offset compensation
– Built-in oversampling unit for enhanced SNR
– Channel-wise programmable sampling time
– Analog watchdog for automatic voltage monitoring, generating interrupts and
trigger for selected timers
– Hardware assistant to prepare the context of the injected channels to allow fast
context switching
– Flexible sample time control
– Hardware gain and offset compensation
3.18.1 Temperature sensor
The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature.
The temperature sensor is internally connected to the ADC1_IN16 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
DS12589 Rev 1 29/198
43
Functional overview STM32G431x6 STM32G431x8 STM32G431xB
Calibration value name Description Memory address
TS_CAL1
TS_CAL2
Table 5. Temperature sensor calibration values
TS ADC raw data acquired at a
temperature of 30 °C (± 5 °C),
V
DDA
TS ADC raw data acquired at a
temperature of 110 °C (± 5 °C),
V
DDA
3.18.2 Internal voltage reference (V
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for
the ADC and the comparators. The VREFINT is internally connected to the ADC1_IN18
input channel. The precise voltage of VREFINT is individually measured for each part by ST
during production test and stored in the system memory area. It is accessible in read-only
mode.
Calibration value name Description Memory address
Table 6. Internal voltage reference calibration values
Raw data acquired at a
VREFINT
temperature of 30 °C (± 5 °C),
V
DDA
= V
REF+
= V
REF+
REFINT
= V
REF+
0x1FFF 75A8 - 0x1FFF 75A9
= 3.0 V (± 10 mV)
0x1FFF 75CA - 0x1FFF 75CB
= 3.0 V (± 10 mV)
)
0x1FFF 75AA - 0x1FFF 75AB
= 3.0 V (± 10 mV)
3.18.3 V
battery voltage monitoring
BAT
This embedded hardware enables the application to measure the V
the internal ADC1_IN17 channel. As the V
voltage may be higher than the VDDA, and
BAT
thus outside the ADC input range, the VBAT pin is internally connected to a bridge divider by
3. As a consequence, the converted digital value is one third of the V
3.19 Digital to analog converter (DAC)
Four 12 bit DAC channels (2 external buffered and 2 internal unbuffered) can be used to
convert digital signals into analog voltage signal outputs. The chosen design structure is
composed of integrated resistor strings and an amplifier in inverting configuration.
battery voltage using
BAT
voltage.
BAT
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