STM32G0B1xB/C/xE
LQFP64
UFQFPN48
UFQFPN32
LQFP48
LQFP32
WLCSP52
3.09 × 3.15 mm
UFBGA64
5
×
5mm
10
×
10 mm
7
×
7mm
7
×
7mm
7×7mm
5×5mm
LQFP100
14
×
14 mm
UFBGA100
7
×
7mm
LQFP80
12
×
12 mm
Arm® Cortex®-M0+ 32-bit MCU, up to 512KB Flash, 144KB RAM,
6x USART, timers, ADC, DAC, comm. I/Fs, 1.7-3.6V
Datasheet - production data
Features
• Core: Arm® 32-bit Cortex®-M0+ CPU,
frequency up to 64 MHz
• -40°C to 85°C/105°C/125°C operating
temperature
• Memories
– Up to 512 Kbytes of Flash memory with
protection and securable area, two banks,
read-while-write support
– 144 Kbytes of SRAM (128 Kbytes with HW
parity check)
• CRC calculation unit
• Reset and power management
– Voltage range: 1.7 V to 3.6 V
– Separate I/O supply pin (1.6 V to 3.6 V)
– Power-on/Power-down reset (POR/PDR)
– Programmable Brownout reset (BOR)
– Programmable voltage detector (PVD)
– Low-power modes:
Sleep, Stop, Standby, Shutdown
–V
supply for RTC and backup registers
BAT
• Clock management
– 4 to 48 MHz crystal oscillator
– 32 kHz crystal oscillator with calibration
– Internal 16 MHz RC with PLL option (±1 %)
– Internal 32 kHz RC oscillator (±5 %)
• Up to 94 fast I/Os
– All mappable on external interrupt vectors
– Multiple 5 V-tolerant I/Os
• 12-channel DMA controller with flexible
mapping
• 12-bit, 0.4 µs ADC (up to 16 ext. channels)
– Up to 16-bit with hardware oversampling
– Conversion range: 0 to 3.6V
• Two 12-bit DACs, low-power sample-and-hold
• Three fast low-power analog comparators, with
programmable input and output, rail-to-rail
• 15 timers (two 128 MHz capable): 16-bit for
advanced motor control, one 32-bit and six 16bit general-purpose, two basic 16-bit, two lowpower 16-bit, two watchdogs, SysTick timer
• Calendar RTC with alarm and periodic wakeup
from Stop/Standby/Shutdown
• Communication interfaces
– Three I
2
C-bus interfaces supporting Fastmode Plus (1 Mbit/s) with extra current
sink, two supporting SMBus/PMBus and
wakeup from Stop mode
– Six USARTs with master/slave
synchronous SPI; three supporting
ISO7816 interface, LIN, IrDA capability,
auto baud rate detection and wakeup
feature
– Two low-power UARTs
– Three SPIs (32 Mbit/s) with 4- to 16-bit
programmable bitframe, two multiplexed
2
with I
S interface
– HDMI CEC interface, wakeup on header
• USB 2.0 FS device (crystal-less) and host
controller
• USB Type-C™ Power Delivery controller
• Two FDCAN controllers
• Development support: serial wire debug (SWD)
• 96-bit unique ID
• All packages ECOPACK
Reference Part number
STM32G0B1xC
STM32G0B1xE
STM32G0B1xB
Table 1. Device summary
STM32G0B1CC, STM32G0B1KC,
STM32G0B1MC, STM32G0B1RC,
STM32G0B1CE, STM32G0B1KE,
STM32G0B1ME, STM32G0B1NE,
STM32G0B1RE, STM32G0B1VE
STM32G0B1CB, STM32G0B1KB,
STM32G0B1MB, STM32G0B1RB,
2 compliant
STM32G0B1VC
STM32G0B1VB
November 2020 DS13560 Rev 1 1/159
This is information on a product in full production.
www.st.com
Contents STM32G0B1xB/C/xE
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 Arm® Cortex®-M0+ core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3.1 Securable area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.6 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 16
3.7 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.7.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.7.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.7.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.7.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.7.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.7.6 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.8 Interconnect of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.9 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.10 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.11 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.12 DMA request multiplexer (DMAMUX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.13 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.13.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 24
3.13.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 24
3.14 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.14.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.14.2 Internal voltage reference (V
3.14.3 V
battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
BAT
) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
REFINT
3.15 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.16 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2/159 DS13560 Rev 1
STM32G0B1xB/C/xE Contents
3.17 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.18 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.18.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.18.2 General-purpose timers (TIM2, 3, 4, 14, 15, 16, 17) . . . . . . . . . . . . . . . 29
3.18.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.18.4 Low-power timers (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . 29
3.18.5 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.18.6 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.18.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.19 Real-time clock (RTC), tamper (TAMP) and backup registers . . . . . . . . . 30
2
3.20 Inter-integrated circuit interface (I
C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.21 Universal synchronous/asynchronous receiver transmitter (USART) . . . 32
3.22 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 33
3.23 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.24 Universal serial bus device (USB) and host (USBH) . . . . . . . . . . . . . . . . 34
3.25 USB Type-C™ Power Delivery controller . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.26 Controller area network (FDCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.27 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.27.1 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4 Pinouts, pin description and alternate functions . . . . . . . . . . . . . . . . . 36
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 68
5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 68
DS13560 Rev 1 3/159
5
Contents STM32G0B1xB/C/xE
5.3.4 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.3.6 Wakeup time from low-power modes and voltage scaling
transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
5.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.3.10 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
5.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
5.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5.3.15 NRST input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
5.3.16 Analog switch booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
5.3.17 Analog-to-digital converter characteristics . . . . . . . . . . . . . . . . . . . . . . 100
5.3.18 Digital-to-analog converter characteristics . . . . . . . . . . . . . . . . . . . . . . 107
5.3.19 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 111
5.3.20 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
5.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
5.3.22 V
5.3.23 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
5.3.24 Characteristics of communication interfaces . . . . . . . . . . . . . . . . . . . . 115
5.3.25 UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
BAT
6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
6.1 UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
6.2 LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.3 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.4 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6.5 WLCSP52 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
6.6 UFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
6.7 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
6.8 LQFP80 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
6.9 UFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
6.10 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
6.11 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
4/159 DS13560 Rev 1
STM32G0B1xB/C/xE Contents
6.11.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
6.11.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 155
7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
DS13560 Rev 1 5/159
5
List of tables STM32G0B1xB/C/xE
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 15
Table 4. Interconnect of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 5. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 6. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 7. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 8. I
Table 9. USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 10. SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 11. Terms and symbols used in Table 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 12. Pin assignment and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 13. Port A alternate function mapping (AF0 to AF7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 14. Port A alternate function mapping (AF8 to AF15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 15. Port B alternate function mapping (AF0 to AF7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 16. Port B alternate function mapping (AF8 to AF15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 17. Port C alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 18. Port D alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 19. Port E alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 20. Port F alternate function mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 21. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 22. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 23. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 24. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 25. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 26. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 27. Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 28. Current consumption in Run and Low-power run modes
Table 29. Typical current consumption in Run and Low-power run modes,
Table 30. Current consumption in Sleep and Low-power sleep modes . . . . . . . . . . . . . . . . . . . . . . . 74
Table 31. Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 32. Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 33. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 34. Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 35. Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 36. Current consumption of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 37. Low-power mode wakeup times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 38. Regulator mode transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 39. Wakeup time using LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 40. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 41. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 42. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 43. LSE oscillator characteristics (f
Table 44. HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 45. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 46. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
2
C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
at different die temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
depending on code executed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
LSE
6/159 DS13560 Rev 1
STM32G0B1xB/C/xE List of tables
Table 47. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 48. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 49. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 50. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 51. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 52. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 53. Electrical sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 54. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 55. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 56. Input characteristics of FT_e I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 57. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 58. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 59. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 60. Analog switch booster characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 61. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 62. Maximum ADC R
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
AIN
Table 63. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 64. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 65. DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 66. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 67. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 68. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 69. V
Table 70. V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
BAT
charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
BAT
Table 71. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 72. IWDG min/max timeout period at 32 kHz LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 73. Minimum I2CCLK frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 74. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 75. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 76. I
2
S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 77. USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 78. USB OTG DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 79. USB OTG electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 80. USB BCD DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 81. UCPD operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 82. UFQFPN32 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 83. LQFP32 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 84. UFQFPN48 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 85. LQFP48 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 86. WLCSP52 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 87. Recommended PCB pad design rules for WLCSP52 package . . . . . . . . . . . . . . . . . . . . 139
Table 88. UFBGA64 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 89. Recommended PCB design rules for UFBGA64 package . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 90. LQFP64 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 91. LQFP80 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 92. UFBGA100 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 93. UFBGA100 recommended PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 94. LQFP100 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 95. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 96. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
DS13560 Rev 1 7/159
7
List of figures STM32G0B1xB/C/xE
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 2. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 3. STM32G0B1VxT LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 4. STM32G0B1VxI UFBGA100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 5. STM32G0B1MxT LQFP80 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 6. STM32G0B1RxT LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 7. STM32G0B1RxI UFBGA64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 8. STM32G0B1NxY WLCSP52 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 9. STM32G0B1CxT LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 10. STM32G0B1CxU UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 11. STM32G0B1KxT LQFP32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 12. STM32G0B1KxU UFQFPN32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 13. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 14. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 15. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 16. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 17. V
Figure 18. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 19. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 20. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 21. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 22. HSI16 frequency vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 23. HSI48 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 24. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 25. Current injection into FT_e input with diode active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 26. I/O AC characteristics definition
Figure 27. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 28. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 29. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 30. 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 31. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 32. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 33. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 34. I
Figure 35. I
2
2
Figure 36. USB OTG timings – definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . 123
Figure 37. UFQFPN32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 38. Recommended footprint for UFQFPN32 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 39. UFQFPN32 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 40. LQFP32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 41. Recommended footprint for LQFP32 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 42. LQFP32 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 43. UFQFPN48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 44. Recommended footprint for UFQFPN48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 45. UFQFPN48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 46. LQFP48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 47. Recommended footprint for LQFP48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 48. LQFP48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
REFINT
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
S master timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
8/159 DS13560 Rev 1
STM32G0B1xB/C/xE List of figures
Figure 49. WLCSP52 package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 50. Recommended PCB pad design for WLCSP52 package. . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 51. WLCSP52 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 52. UFBGA64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 53. Recommended footprint for UFBGA64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 54. UFBGA64 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 55. LQFP64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 56. Recommended footprint for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 57. LQFP64 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 58. LQFP80 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Figure 59. Recommended footprint for LQFP80 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 60. LQFP80 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 61. UFBGA100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 62. Recommended footprint for UFBGA100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 63. UFBGA100 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 64. LQFP100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 65. Recommended footprint for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 66. LQFP100 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
DS13560 Rev 1 9/159
9
Introduction STM32G0B1xB/C/xE
1 Introduction
This document provides information on STM32G0B1xB/C/xE microcontrollers, such as
description, functional overview, pin assignment and definition, electrical characteristics,
packaging, and ordering codes.
Information on memory mapping and control registers is object of reference manual.
Information on Arm
®(a)
Cortex®-M0+ core is available from the www.arm.com website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
10/159 DS13560 Rev 1
STM32G0B1xB/C/xE Description
2 Description
The STM32G0B1xB/C/xE mainstream microcontrollers are based on high-performance
®
Arm
Cortex®-M0+ 32-bit RISC core operating at up to 64 MHz frequency. Offering a high
level of integration, they are suitable for a wide range of applications in consumer, industrial
and appliance domains and ready for the Internet of Things (IoT) solutions.
The devices incorporate a memory protection unit (MPU), high-speed embedded memories
(144 Kbytes of SRAM and up to 512 Kbytes of Flash program memory with read protection,
write protection, proprietary code protection, and securable area), DMA, an extensive range
of system functions, enhanced I/Os, and peripherals. The devices offer standard
communication interfaces (three I
USB, two FD CANs, and six USARTs), one 12-bit ADC (2.5 MSps) with up to 19 channels,
one 12-bit DAC with two channels, three fast comparators, an internal voltage reference
buffer, a low-power RTC, an advanced control PWM timer running at up to double the CPU
frequency, six general-purpose 16-bit timers with one running at up to double the CPU
frequency, a 32-bit general-purpose timer, two basic timers, two low-power 16-bit timers,
two watchdog timers, and a SysTick timer. The devices provide a fully integrated USB TypeC Power Delivery controller.
The devices operate within ambient temperatures from -40 to 125°C and with supply
voltages from 1.7 V to 3.6 V. Optimized dynamic consumption combined with a
comprehensive set of power-saving modes, low-power timers and low-power UART, allows
the design of low-power applications.
2
Cs, three SPIs / two I2S, one HDMI CEC, one full-speed
VBAT direct battery input allows keeping RTC and backup registers powered.
The devices come in packages with 32 to 100 pins.
Peripheral
Flash memory (Kbyte)
SRAM (Kbyte) 128 (parity-protected) or 144 (not parity-protected)
Advanced control 1 (16-bit) high frequency
General-purpose 6 (16-bit) + 1 (16-bit) high frequency + 1 (32-bit)
Basic 2 (16-bit)
Timers
Low-power 2 (16-bit)
SysTick 1
Watchdog 2
Table 2. Features and peripheral counts
STM32G0B1_
_KB/
_KC/
_KE
128/256/
512
_KBxxN/
_KCxxN/
_KExxN
128/256
/512
_CB/
_CC/
_CE
128/256
/512
_CBxxN/
_CCxxN/
_CExxN
128/256
/512
_NE
512
_RB/
_RC/
_RE
128/256
/512
_RBxxN/
_RCxxN/
_RExxN
128/256
/512
_MB/
_MC/
_ME
128/256
/512
_VB/
_VC/
_VE
128/256
/512
DS13560 Rev 1 11/159
35
Description STM32G0B1xB/C/xE
Table 2. Features and peripheral counts (continued)
STM32G0B1_
Peripheral
SPI [I2S]
2
C3
I
_KB/
_KC/
_KE
(1)
_KBxxN/
_KCxxN/
_KExxN
_CB/
_CC/
_CE
_CBxxN/
_CCxxN/
_CExxN
_NE
3 [2]
_RB/
_RC/
_RE
_RBxxN/
_RCxxN/
_RExxN
_MB/
_MC/
_ME
USART 6
LPUART 2
USB 1
Comm. interfaces
UCPD 1
(2)
21 2 1 2
FDCAN 2
CEC 1
RTC Yes
Tamper pins 3
VDDIO2 pin / VSS pin No/No Yes/No No/No Yes/Yes Yes/Yes No/No Yes/Yes Yes/Yes Yes/Yes
Random number generator No
AES No
GPIOs 30 2944424660587494
Wakeup pins 4 3 4 5 7 8
ADC channels (ext. + int.) 11 + 2 10 + 2 14 + 3 12 + 3 14 + 3 16 + 3 14 + 3 16 + 3 16 + 3
DAC channels 2
Internal voltage reference
buffer
No Yes
Analog comparators 3
Max. CPU frequency 64 MHz
Operating voltage 1.7 to 3.6 V
Operating temperature
(3)
Ambient: -40 to 85 °C / -40 to 105 °C / -40 to 125 °C
Junction: -40 to 105 °C / -40 to 125 °C / -40 to 130 °C
Number of pins 32 48 52 64 80 100
1. The numbers in brackets denote the count of SPI interfaces configurable as I
2
S interface.
2. One port with only one CC line available (supporting limited number of use cases).
3. Depends on order code. Refer to Section 7: Ordering information for details.
_VB/
_VC/
_VE
12/159 DS13560 Rev 1
MSv63193V1
Parity
FDCAN1 & 2
I2C2
SPI1/I2S
LPUART& & 2
UCPD
USART3/4
LPTIMER 1/2
TIMER 16/17
Power domain of analog blocks :
V
BAT
4 channels
BKIN, BKIN2, ETR
System and
peripheral
clocks
MOSI/SD
MISO/MCK
SCK/CK
NSS/WS
SWCLK
SWDIO
16x IN
OSC_IN
OSC_OUT
VBAT
OSC32_IN
OSC32_OUT
RTC_OUT
RTC_REFIN
RTC_TS
MOSI, MISO
SCK, NSS
HSI16
LSI
PLLPCLK
V
DD
IR_OUT
1 channel
BKIN
ETR, IN, OUT
1 channel
4 channels
ETR
4 channels
ETR
CPU
CORTEX-M0+
f
max
= 64 MHz
SWD
NVIC
EXTI
SPI/I2S 1 & 2
SPI3
AHB-to-APB
RCC
Reset & clock control
I/F
XTAL OSC
4-48 MHz
IWDG
I/F
ADC
RTC, TAMP
Backup regs
I/F
RC 16 MHz
RC 32 kHz
PLL
decoder
XTAL32 kHz
Bus matrix
I/F
V
DD
2 channels
BKIN
RX, TX
CTS, RTS
CEC
TIM6
TIM7
COMP1
COMP2
IN+, IN-,
OUT
V
DDA
SUPPLY
SUPERVISION
POWER
V
CORE
POR
Reset
Int
VDD/VDDA
VSS/VSSA
NRST
PVD
POR/BOR
Voltage
regulator
USART1 to 6
LPTIM1 & 2
TIM16 & 17
TIM15
TIM14
TIM3 & 4
TIM2 (32-bit)
TIM1
GPIOs
IOPORT
HSE
PLLQCLK
PLLRCLK
LSE
LSE
T sensor
RX, TX,
CTS, RTS
LPUART1 & 2
TAMP_IN
APB
APB
AHB
CC, DBCC
FRSTX
UCPD1 & 2
HDMI-CEC
VREFBUF
DAC
I/F
DAC_OUT1
DAC_OUT2
CRC
VREF+
SCL, SDA
SCL, SDA
SMBA, SMBUS
I2C1 & 2
I2C3
DBGMCU
WWDG
PWRCTRL
SYSCFG
DMA
DMAMUX
V
DDA
V
DDIO1
Low-voltage
detector
V
DD
Flash memory
up to 512 KB
V
DDIO1
/V
DDIO2
IRTIM
from peripherals
PFx
Port F
Port D
PDx
PCx
Port C
PBx
Port B
PAx
Port A
Port E
PEx
NOE, DM,
DP
USB FS
RX, TX
FDCAN1 & 2
VDDIO2
V
DDIO2
COMP3
SRAM
144 KB
STM32G0B1xB/C/xE Description
Figure 1. Block diagram
DS13560 Rev 1 13/159
35
Functional overview STM32G0B1xB/C/xE
3 Functional overview
3.1 Arm® Cortex®-M0+ core with MPU
The Cortex-M0+ is an entry-level 32-bit Arm Cortex processor designed for a broad range of
embedded applications. It offers significant benefits to developers, including:
• a simple architecture, easy to learn and program
• ultra-low power, energy-efficient operation
• excellent code density
• deterministic, high-performance interrupt handling
• upward compatibility with Cortex-M processor family
• platform security robustness, with integrated Memory Protection Unit (MPU).
The Cortex-M0+ processor is built on a highly area- and power-optimized 32-bit core, with a
2-stage pipeline Von Neumann architecture. The processor delivers exceptional energy
efficiency through a small but powerful instruction set and extensively optimized design,
providing high-end processing hardware including a single-cycle multiplier.
The Cortex-M0+ processor provides the exceptional performance expected of a modern
32-bit architecture, with a higher code density than other 8-bit and 16-bit microcontrollers.
Owing to embedded Arm core, the STM32G0B1xB/C/xE devices are compatible with Arm
tools and software.
The Cortex-M0+ is tightly coupled with a nested vectored interrupt controller (NVIC)
described in Section 3.13.1.
3.2 Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
3.3 Embedded Flash memory
STM32G0B1xB/C/xE devices feature up to 512 Kbytes of embedded Flash memory
available for storing code and data.
14/159 DS13560 Rev 1
STM32G0B1xB/C/xE Functional overview
Flexible protections can be configured thanks to option bytes:
• Readout protection (RDP) to protect the whole memory. Three levels are available:
– Level 0: no readout protection
– Level 1: memory readout protection: the Flash memory cannot be read from or
written to if either debug features are connected, boot in RAM or bootloader is
selected
– Level 2: chip readout protection: debug features (Cortex-M0+ serial wire), boot in
RAM and bootloader selection are disabled. This selection is irreversible.
Table 3. Access status versus readout protection level and execution modes
Area
User
memory
System
memory
Option
bytes
Backup
registers
1. Erased upon RDP change from Level 1 to Level 0.
Protection
level
1 Yes Yes Yes No No No
2 Yes Yes Yes N/A N/A N/A
1 Yes No No Yes No No
2 Yes No No N/A N/A N/A
1 Yes Yes Yes Yes Yes Yes
2 Yes No No N/A N/A N/A
1YesYesN/A
2 Yes Yes N/A N/A N/A N/A
User execution
Read Write Erase Read Write Erase
(1)
Debug, boot from RAM or boot
from system memory (loader)
No No N/A
• Write protection (WRP): the protected area is protected against erasing and
programming. Two areas per bank can be selected, with 2-Kbyte granularity.
• Proprietary code readout protection (PCROP): a part of the Flash memory can be
protected against read and write from third parties. The protected area is execute-only:
it can only be reached by the STM32 CPU as instruction code, while all other accesses
(DMA, debug and CPU data read, write and erase) are strictly prohibited. An additional
option bit (PCROP_RDP) determines whether the PCROP area is erased or not when
the RDP protection is changed from Level 1 to Level 0.
(1)
The whole non-volatile memory embeds the error correction code (ECC) feature supporting:
• single error detection and correction
• double error detection
• readout of the ECC fail address from the ECC register
3.3.1 Securable area
A part of the Flash memory can be hidden from the application once the code it contains is
executed. As soon as the write-once SEC_PROT bit is set, the securable memory cannot be
accessed until the system resets. The securable area generally contains the secure boot
code to execute only once at boot. This helps to isolate secret code from untrusted
application code.
DS13560 Rev 1 15/159
35
Functional overview STM32G0B1xB/C/xE
3.4 Embedded SRAM
STM32G0B1xB/C/xE devices have 128 Kbytes of embedded SRAM with parity. Hardware
parity check allows memory data errors to be detected, which contributes to increasing
functional safety of applications.
When the parity protection is not required because the application is not safety-critical, the
parity memory bits can be used as additional SRAM, to increase its total size to 144 Kbytes.
The memory can be read/write-accessed at CPU clock speed, with 0 wait states.
3.5 Boot modes
At startup, the boot pin and boot selector option bit are used to select one of the three boot
options:
• boot from User Flash memory
• boot from System memory
• boot from embedded SRAM
The boot pin is shared with a standard GPIO and can be enabled through the boot selector
option bit. The boot loader is located in System memory. It manages the Flash memory
reprogramming through one of the following interfaces:
• USART on pins PA9/PA10, PC10/PC11, or PA2/PA3
2
• I
C-bus on pins PB6/PB7 or PB10/PB11
• SPI on pins PA4/PA5/PA6/PA7 or PB12/PB13/PB14/PB15
• USB on pins PA11/PA12
• FDCAN on pins PD0/PD1
3.6 Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link
time and stored at a given memory location.
16/159 DS13560 Rev 1
STM32G0B1xB/C/xE Functional overview
3.7 Power supply management
3.7.1 Power supply schemes
The STM32G0B1xB/C/xE devices require a 1.7 V to 3.6 V operating supply voltage (VDD).
Several different power supplies are provided to specific peripherals:
• V
• V
• V
• V
• V
• V
• V
= 1.7 (1.6) to 3.6 V
DD
V
is the external power supply for the internal regulator and the system analog such
DD
as reset, power management and internal clocks. It is provided externally through
VDD/VDDA pin.
The minimum voltage of 1.7 V corresponds to power-on reset release threshold
V
(max). Once this threshold is crossed and power-on reset is released, the
POR
functionality is guaranteed down to power-down reset threshold V
= 1.62 V (ADC and COMP) / 1.8 V (DAC) / 2.4 V (VREFBUF) to 3.6 V
DDA
V
is the analog power supply for the A/D converter, D/A converter, voltage
DDA
reference buffer and comparators. V
voltage level is identical to VDD voltage as it is
DDA
PDR
(min).
provided externally through VDD/VDDA pin.
= V
DDIO1
V
DDIO1
DD
is the power supply for the I/Os. V
voltage level is identical to VDD voltage
DDIO1
as it is provided externally through VDD/VDDA pin.
= 1.6 to 3.6 V
DDIO2
V
independent of V
TAMP, low-speed external 32.768 kHz oscillator and backup registers when V
present. V
is the power supply from VDDIO2 pin for selected I/Os. Although V
DDIO2
= 1.55 V to 3.6 V. V
BAT
BAT
DD
or V
, it must not be applied without valid VDD.
DDA
is the power supply (through a power switch) for RTC,
BAT
is provided externally through VBAT pin. When this pin is not available
DDIO2
DD
is
is not
on the package, VBAT bonding pad is internally bonded to the VDD/VDDA pin.
is the analog peripheral input reference voltage, or the output of the internal
REF+
voltage reference buffer (when enabled). When V
V
. When V
DDA
when the analog peripherals using V
DDA
2 V, V
must be between 2 V and V
REF+
are not active.
REF+
DDA
< 2 V, V
must be equal to
REF+
. It can be grounded
DDA
The internal voltage reference buffer supports two output voltages, which is configured
with VRS bit of the VREFBUF_CSR register:
–V
–V
V
REF+
internally connected with V
around 2.048 V (requiring V
REF+
around 2.5 V (requiring V
REF+
equal to or higher than 2.4 V)
DDA
equal to or higher than 2.8 V)
DDA
is delivered through VREF+ pin. On packages without VREF+ pin, V
, and the internal voltage reference buffer must be kept
DD
REF+
is
disabled (refer to datasheets for package pinout description).
CORE
An embedded linear voltage regulator is used to supply the V
power. V
The Flash memory is also supplied with V
is the power supply for digital peripherals, SRAM and Flash memory.
CORE
DD
.
internal digital
CORE
DS13560 Rev 1 17/159
35
Functional overview STM32G0B1xB/C/xE
MSv63104V1
V
DDA
domain
RTC domain
D/A converter
A/D converter
Standby circuitry
(Wakeup, IWDG)
Voltage
regulator
Core
SRAM
Digital
peripherals
Low-voltage
detector
LSE crystal 32.768 kHz osc
BKP registers
RCC BDCR register
RTC and TAMP
Comparators
Voltage reference buffer
I/O ring
V
CORE
domain
Temp. sensor
Reset block
PLL, HSI
Flash memory
V
DDIO1
VREF+
V
DD
domain
V
CORE
VSS/VSSA
VDD/VDDA
VBAT
V
DDA
V
REF+
V
SSA
V
SS
V
DD
V
DDIO1
domain
I/O ring
V
DDIO2
domain
VDDIO2
V
DDIO2
Figure 2. Power supply overview
3.7.2 Power supply supervisor
The device has an integrated power-on/power-down (POR/PDR) reset active in all power
modes except Shutdown and ensuring proper operation upon power-on and power-down. It
maintains the device in reset when the supply voltage is below V
the need for an external reset circuit. Brownout reset (BOR) function allows extra flexibility. It
can be enabled and configured through option bytes, by selecting one of four thresholds for
rising V
The device also features an embedded programmable voltage detector (PVD) that monitors
the V
when V
falling and rising. The interrupt service routine can then generate a warning message and/or
put the MCU into a safe state. The PVD is enabled by software.
3.7.3 Voltage regulator
Two embedded linear voltage regulators, main regulator (MR) and low-power regulator
(LPR), supply most of digital circuitry in the device.
18/159 DS13560 Rev 1
The MR is used in Run and Sleep modes. The LPR is used in Low-power run, Low-power
sleep and Stop modes.
In Standby and Shutdown modes, both regulators are powered down and their outputs set in
high-impedance state, such as to bring their current consumption close to zero. However,
SRAM data retention is possible in Standby mode, in which case the LPR remains active
and it only supplies the SRAM.
and other four for falling VDD.
DD
power supply and compares it to V
DD
level crosses the V
DD
PVD
threshold, selectively while falling, while rising, or while
PVD
POR/PDR
threshold, without
threshold. It allows generating an interrupt
STM32G0B1xB/C/xE Functional overview
3.7.4 Low-power modes
By default, the microcontroller is in Run mode after system or power reset. It is up to the
user to select one of the low-power modes described below:
• Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
• Low-power run mode
This mode is achieved with V
regulator's operating current. The code can be executed from SRAM or from Flash,
and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can
be clocked by HSI16.
• Low-power sleep mode
This mode is entered from the low-power run mode. Only the CPU clock is stopped.
When wakeup is triggered by an event or an interrupt, the system reverts to the Lowpower run mode.
• Stop 0 and Stop 1 modes
In Stop 0 and Stop 1 modes, the device achieves the lowest power consumption while
retaining the SRAM and register contents. All clocks in the V
The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are
disabled. The LSE or LSI keep running. The RTC can remain active (Stop mode with
RTC, Stop mode without RTC).
Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode,
so as to get clock for processing the wakeup event. The main regulator remains active
in Stop 0 mode while it is turned off in Stop 1 mode.
• Standby mode
The Standby mode is used to achieve the lowest power consumption, with POR/PDR
always active in this mode. The main regulator is switched off to power down V
domain. The low-power regulator is either switched off or kept active. In the latter case,
it only supplies SRAM to ensure data retention. The PLL, as well as the HSI16 RC
oscillator and the HSE crystal oscillator are also powered down. The RTC can remain
active (Standby mode with RTC, Standby mode without RTC).
For each I/O, the software can determine whether a pull-up, a pull-down or no resistor
shall be applied to that I/O during Standby mode.
Upon entering Standby mode, register contents are lost except for registers in the RTC
domain and standby circuitry. The SRAM contents can be retained through register
setting.
The device exits Standby mode upon external reset event (NRST pin), IWDG reset
event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event
(alarm, periodic wakeup, timestamp, tamper), or when a failure is detected on LSE
(CSS on LSE).
• Shutdown mode
The Shutdown mode allows to achieve the lowest power consumption. The internal
regulator is switched off to power down the V
supplied by the low-power regulator to minimize the
CORE
domain are stopped.
CORE
domain. The PLL, as well as the
CORE
CORE
DS13560 Rev 1 19/159
35
Functional overview STM32G0B1xB/C/xE
HSI16 and LSI RC-oscillators and HSE crystal oscillator are also powered down. The
RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).
The BOR is not available in Shutdown mode. No power voltage monitoring is possible
in this mode. Therefore, switching to RTC domain is not supported.
SRAM and register contents are lost except for registers in the RTC domain.
The device exits Shutdown mode upon external reset event (NRST pin), IWDG reset
event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event
(alarm, periodic wakeup, timestamp, tamper).
3.7.5 Reset mode
During and upon exiting reset, the schmitt triggers of I/Os are disabled so as to reduce
power consumption. In addition, when the reset source is internal, the built-in pull-up
resistor on NRST pin is deactivated.
3.7.6 VBAT operation
The V
power domain, consuming very little energy, includes RTC, and LSE oscillator and
BAT
backup registers.
In VBAT mode, the RTC domain is supplied from VBAT pin. The power source can be, for
example, an external battery or an external supercapacitor. Two anti-tamper detection pins
are available.
The RTC domain can also be supplied from VDD/VDDA pin.
By means of a built-in switch, an internal voltage supervisor allows automatic switching of
RTC domain powering between V
voltage of the RTC domain (V
BAT
and voltage from VBAT pin to ensure that the supply
DD
) remains within valid operating conditions. If both voltages
are valid, the RTC domain is supplied from VDD/VDDA pin.
An internal circuit for charging the battery on VBAT pin can be activated if the V
voltage is
DD
within a valid range.
Note: External interrupts and RTC alarm/events cannot cause the microcontroller to exit the VBAT
mode, as in that mode the V
is not within a valid range.
DD
3.8 Interconnect of peripherals
Several peripherals have direct connections between them. This allows autonomous
communication between peripherals, saving CPU resources thus power supply
consumption. In addition, these hardware connections allow fast and predictable latency.
Depending on peripherals, these interconnections can operate in Run, Sleep and Stop
modes.
20/159 DS13560 Rev 1
STM32G0B1xB/C/xE Functional overview
Interconnect source
TIMx
COMPx
ADCx TIM1 Timer triggered by analog watchdog Y Y -
RTC
All clock sources (internal and
external)
Table 4. Interconnect of peripherals
Interconnect
destination
TIMx Timer synchronization or chaining Y Y -
ADCx
DACx
Conversion triggers Y Y -
DMA Memory-to-memory transfer trigger Y Y -
COMPx Comparator output blanking Y Y -
TIM1,2,3,4
LPTIMERx
Timer input channel, trigger, break
from analog signals comparison
Low-power timer triggered by analog
signals comparison
TIM16 Timer input channel from RTC events Y Y -
LPTIMERx
TIM14,16,17
Low-power timer triggered by RTC
alarms or tampers
Clock source used as input channel for
RC measurement and trimming
Interconnect action
Run
Sleep
Low-power run
YY -
YYY
YYY
YY -
Stop
Low-power sleep
CSS
RAM (parity error)
Flash memory (ECC error)
TIM1,15,16,17 Timer break Y Y -
COMPx
PVD
CPU (hard fault) TIM1,15,16,17 Timer break Y - -
TIMx External trigger Y Y -
GPIO
LPTIMERx External trigger Y Y Y
ADC
DACx
Conversion external trigger Y Y -
DS13560 Rev 1 21/159
35
Functional overview STM32G0B1xB/C/xE
3.9 Clocks and startup
The clock controller distributes the clocks coming from different oscillators to the core and
the peripherals. It also manages clock gating for low-power modes and ensures clock
robustness. It features:
• Clock prescaler: to get the best trade-off between speed and current consumption,
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler
• Safe clock switching: clock sources can be changed safely on the fly in run mode
through a configuration register.
• Clock management: to reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
• System clock source: three different sources can deliver SYSCLK system clock:
– 4-48 MHz high-speed oscillator with external crystal or ceramic resonator (HSE). It
can supply clock to system PLL. The HSE can also be configured in bypass mode
for an external clock.
– 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software. It can
supply clock to system PLL.
– System PLL with maximum output frequency of 64 MHz. It can be fed with HSE or
HSI16 clocks.
• Auxiliary clock source: two ultra-low-power clock sources for the real-time clock
(RTC):
– 32.768 kHz low-speed oscillator with external crystal (LSE), supporting four drive
capability modes. The LSE can also be configured in bypass mode for using an
external clock.
– 32 kHz low-speed internal RC oscillator (LSI) with ±5% accuracy, also used to
clock an independent watchdog.
• Peripheral clock sources: several peripherals ( I2S, USARTs, I2Cs, LPTIMs, ADC,
USB FS) have their own clock independent of the system clock.
• Clock security system (CSS): in the event of HSE clock failure, the system clock is
automatically switched to HSI16 and, if enabled, a software interrupt is generated. LSE
clock failure can also be detected and generate an interrupt. The CCS feature can be
enabled by software.
• Clock output:
– MCO (microcontroller clock output) provides one of the internal clocks for
external use by the application
– LSCO (low speed clock output) provides LSI or LSE in all low-power modes
(except in VBAT operation).
Several prescalers allow the application to configure AHB and APB domain clock
frequencies, 64 MHz at maximum.
3.10 General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function (AF). Most of
the GPIO pins are shared with special digital or analog functions.
22/159 DS13560 Rev 1
STM32G0B1xB/C/xE Functional overview
Through a specific sequence, this special function configuration of I/Os can be locked, such
as to avoid spurious writing to I/O control registers.
3.11 Direct memory access controller (DMA)
The direct memory access (DMA) controller is a bus master and system peripheral with
single-AHB architecture.
With 12 channels, it performs data transfers between memory-mapped peripherals and/or
memories, to offload the CPU.
Each channel is dedicated to managing memory access requests from one or more
peripherals. The unit includes an arbiter for handling the priority between DMA requests.
Main features of the DMA controller:
• Single-AHB master
• Peripheral-to-memory, memory-to-peripheral, memory-to-memory and peripheral-to-
peripheral data transfers
• Access, as source and destination, to on-chip memory-mapped devices such as Flash
memory, SRAM, and AHB and APB peripherals
• All DMA channels independently configurable:
– Each channel is associated either with a DMA request signal coming from a
peripheral, or with a software trigger in memory-to-memory transfers. This
configuration is done by software.
– Priority between the requests is programmable by software (four levels per
channel: very high, high, medium, low) and by hardware in case of equality (such
as request to channel 1 has priority over request to channel 2).
– Transfer size of source and destination are independent (byte, half-word, word),
emulating packing and unpacking. Source and destination addresses must be
aligned on the data size.
– Support of transfers from/to peripherals to/from memory with circular buffer
management
– Programmable number of data to be transferred: 0 to 2
• Generation of an interrupt request per channel. Each interrupt request originates from
any of the three DMA events: transfer complete, half transfer, or transfer error.
16
- 1
3.12 DMA request multiplexer (DMAMUX)
The DMAMUX request multiplexer enables routing a DMA request line between the
peripherals and the DMA controller. Each channel selects a unique DMA request line,
unconditionally or synchronously with events from its DMAMUX synchronization inputs.
DMAMUX may also be used as a DMA request generator from programmable events on its
input trigger signals.
3.13 Interrupts and events
The device flexibly manages events causing interrupts of linear program execution, called
exceptions. The Cortex-M0+ processor core, a nested vectored interrupt controller (NVIC)
DS13560 Rev 1 23/159
35
Functional overview STM32G0B1xB/C/xE
and an extended interrupt/event controller (EXTI) are the assets contributing to handling the
exceptions. Exceptions include core-internal events such as, for example, a division by zero
and, core-external events such as logical level changes on physical lines. Exceptions result
in interrupting the program flow, executing an interrupt service routine (ISR) then resuming
the original program flow.
The processor context (contents of program pointer and status registers) is stacked upon
program interrupt and unstacked upon program resume, by hardware. This avoids context
stacking and unstacking in the interrupt service routines (ISRs) by software, thus saving
time, code and power. The ability to abandon and restart load-multiple and store-multiple
operations significantly increases the device’s responsiveness in processing exceptions.
3.13.1 Nested vectored interrupt controller (NVIC)
The configurable nested vectored interrupt controller is tightly coupled with the core. It
handles physical line events associated with a non-maskable interrupt (NMI) and maskable
interrupts, and Cortex-M0+ exceptions. It provides flexible priority management.
The tight coupling of the processor core with NVIC significantly reduces the latency between
interrupt events and start of corresponding interrupt service routines (ISRs). The ISR
vectors are listed in a vector table, stored in the NVIC at a base address. The vector
address of an ISR to execute is hardware-built from the vector table base address and the
ISR order number used as offset.
If a higher-priority interrupt event happens while a lower-priority interrupt event occurring
just before is waiting for being served, the later-arriving higher-priority interrupt event is
served first. Another optimization is called tail-chaining. Upon a return from a higher-priority
ISR then start of a pending lower-priority ISR, the unnecessary processor context
unstacking and stacking is skipped. This reduces latency and contributes to power
efficiency.
Features of the NVIC:
• Low-latency interrupt processing
• 4 priority levels
• Handling of a non-maskable interrupt (NMI)
• Handling of 32 maskable interrupt lines
• Handling of 10 Cortex-M0+ exceptions
• Later-arriving higher-priority interrupt processed first
• Tail-chaining
• Interrupt vector retrieval by hardware
3.13.2 Extended interrupt/event controller (EXTI)
The extended interrupt/event controller adds flexibility in handling physical line events and
allows identifying wake-up events at processor wakeup from Stop mode.
The EXTI controller has a number of channels, of which some with rising, falling or rising,
and falling edge detector capability. Any GPIO and a few peripheral signals can be
connected to these channels.
The channels can be independently masked.
The EXTI controller can capture pulses shorter than the internal clock period.
24/159 DS13560 Rev 1
STM32G0B1xB/C/xE Functional overview
A register in the EXTI controller latches every event even in Stop mode, which allows the
software to identify the origin of the processor's wake-up from Stop mode or, to identify the
GPIO and the edge event having caused an interrupt.
3.14 Analog-to-digital converter (ADC)
A native 12-bit analog-to-digital converter is embedded into STM32G0B1xB/C/xE devices. It
can be extended to 16-bit resolution through hardware oversampling. The ADC has up to 16
external channels and 3 internal channels (temperature sensor, voltage reference, V
monitoring). It performs conversions in single-shot or scan mode. In scan mode, automatic
conversion is performed on a selected group of analog inputs.
The ADC frequency is independent from the CPU frequency, allowing maximum sampling
rate of ~2 MSps even with a low CPU speed. An auto-shutdown function guarantees that
the ADC is powered off except during the active conversion phase.
BAT
The ADC can be served by the DMA controller. It can operate in the whole V
range.
The ADC features a hardware oversampler up to 256 samples, improving the resolution to
16 bits (refer to AN2668).
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all scanned channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers (TIMx) can be internally connected to
the ADC start triggers, to allow the application to synchronize A/D conversions with timers.
3.14.1 Temperature sensor
The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature.
The temperature sensor is internally connected to an ADC input to convert the sensor
output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor may
vary from part to part due to process variation, the uncalibrated internal temperature sensor
is suitable only for relative temperature measurements.
To improve the accuracy of the temperature sensor, each part is individually factorycalibrated by ST. The resulting calibration data are stored in the part’s engineering bytes,
accessible in read-only mode.
Table 5. Temperature sensor calibration values
supply
DD
Calibration value name Description Memory address
TS ADC raw data acquired at a
TS_CAL1
TS_CAL2
temperature of 30 °C (± 5 °C),
V
= V
DDA
TS ADC raw data acquired at a
temperature of 130 °C (± 5 °C),
V
= V
DDA
DS13560 Rev 1 25/159
= 3.0 V (± 10 mV)
REF+
= 3.0 V (± 10 mV)
REF+
0x1FFF 75A8 - 0x1FFF 75A9
0x1FFF 75CA - 0x1FFF 75CB
35
Functional overview STM32G0B1xB/C/xE
3.14.2 Internal voltage reference (V
The internal voltage reference (V
ADC and comparators. V
REFINT
REFINT
is internally connected to an ADC input. The V
REFINT
)
) provides a stable (bandgap) voltage output for the
voltage is individually precisely measured for each part by ST during production test and
stored in the part’s engineering bytes. It is accessible in read-only mode.
3.14.3 V
Calibration value name Description Memory address
battery voltage monitoring
BAT
Table 6. Internal voltage reference calibration values
Raw data acquired at a
V
REFINT
temperature of 30 °C (± 5 °C),
V
DDA
= V
= 3.0 V (± 10 mV)
REF+
This embedded hardware feature allows the application to measure the V
using an internal ADC input. As the V
voltage may be higher than V
BAT
the ADC input range, the VBAT pin is internally connected to a bridge divider by three. As a
consequence, the converted digital value is one third the V
3.15 Digital-to-analog converter (DAC)
REFINT
0x1FFF 75AA - 0x1FFF 75AB
battery voltage
BAT
and thus outside
DDA
voltage.
BAT
The 2-channel 12-bit buffered DAC converts a digital value into an analog voltage available
on the channel output. The architecture of either channel is based on integrated resistor
string and an inverting amplifier. The digital circuitry is common for both channels.
Features of the DAC:
• Two DAC output channels
• 8-bit or 12-bit output mode
• Buffer offset calibration (factory and user trimming)
• Left or right data alignment in 12-bit mode
• Synchronized update capability
• Noise-wave generation
• Triangular-wave generation
• Independent or simultaneous conversion for DAC channels
• DMA capability for either DAC channel
• Triggering with timer events, synchronized with DMA
• Triggering with external events
• Sample-and-hold low-power mode, with internal or external capacitor
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STM32G0B1xB/C/xE Functional overview
3.16 Voltage reference buffer (VREFBUF)
When enabled, an embedded buffer provides the internal reference voltage to analog
blocks (for example ADC) and to VREF+ pin for external components.
The internal voltage reference buffer supports two voltages:
• 2.048 V
• 2.5 V
An external voltage reference can be provided through the VREF+ pin when the internal
voltage reference buffer is disabled.
On some packages, the VREF+ pad of the silicon die is double-bonded with supply pad to
common VDD/VDDA pin and so the internal voltage reference buffer cannot be used.
3.17 Comparators (COMP)
Three embedded rail-to-rail analog comparators have programmable reference voltage
(internal or external), hysteresis, speed (low for low-power) and output polarity.
The reference voltage can be one of the following:
• external, from an I/O
• internal, from DAC
• internal reference voltage (V
The comparators can wake up the device from Stop mode, generate interrupts, breaks or
triggers for the timers and can be also combined into a window comparator.
) or its submultiple (1/4, 1/2, 3/4)
REFINT
3.18 Timers and watchdogs
The device includes an advanced-control timer, seven general-purpose timers, two basic
timers, two low-power timers, two watchdog timers and a SysTick timer. Table 7 compares
features of the advanced-control, general-purpose and basic timers.
Timer type Timer
Advanced-
control
TIM1 16-bit
Counter
resolution
Table 7. Timer feature comparison
Counter
type
Up, down,
up/down
Maximum
operating
frequency
128 MHz
Prescaler
factor
Integer from
1 to 2
16
DMA
request
generation
Yes 4 3
Capture/
compare
channels
Complementary
outputs
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35
Functional overview STM32G0B1xB/C/xE
Table 7. Timer feature comparison (continued)
Maximum
operating
frequency
64 MHz
64 MHz
64 MHz
Timer type Timer
TIM2 32-bit
TIM3 16-bit
General-
purpose
Basic
Low-power
TIM4 16-bit
TIM14 16-bit Up 64 MHz
TIM15 16-bit Up 128 MHz
TIM16
TIM17
TIM6
TIM7
LPTIM1
LPTIM2
Counter
resolution
16-bit Up 64 MHz
16-bit Up 64 MHz
16-bit Up 64 MHz
Counter
type
Up, down,
up/down
Up, down,
up/down
Up, down,
up/down
3.18.1 Advanced-control timer (TIM1)
Prescaler
factor
Integer from
Integer from
Integer from
Integer from
Integer from
Integer from
Integer from
16
1 to 2
16
1 to 2
16
1 to 2
16
1 to 2
16
1 to 2
16
1 to 2
16
1 to 2
2n where
n=0 to 7
DMA
request
generation
Yes 4 -
Yes 4 -
Yes 4 -
No 1 -
Yes 2 1
Yes 1 1
Yes - -
No N/A -
Capture/
compare
channels
Complementary
outputs
The advanced-control timer can be seen as a three-phase PWM unit multiplexed on 6
channels. It has complementary PWM outputs with programmable inserted dead-times. It
can also be seen as a complete general-purpose timer. The four independent channels can
be used for:
• input capture
• output compare
• PWM output (edge or center-aligned modes) with full modulation capability (0-100%)
• one-pulse mode output
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled, so as to turn off any power switches driven by these outputs.
Many features are shared with those of the general-purpose TIMx timers (described in
Section 3.18.2) using the same architecture, so the advanced-control timers can work
together with the TIMx timers via the Timer Link feature for synchronization or event
chaining.
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STM32G0B1xB/C/xE Functional overview
3.18.2 General-purpose timers (TIM2, 3, 4, 14, 15, 16, 17)
There are seven synchronizable general-purpose timers embedded in the device (refer to
Tab l e 7 for comparison). Each general-purpose timer can be used to generate PWM outputs
or act as a simple timebase.
• TIM2, TIM3, and TIM4
These are full-featured general-purpose timers:
– TIM2 with 32-bit auto-reload up/downcounter and 16-bit prescaler
– TIM3 and TIM4 with 16-bit auto-reload up/downcounter and 16-bit prescaler
They have four independent channels for input capture/output compare, PWM or onepulse mode output. They can operate in combination with other general-purpose timers
via the Timer Link feature for synchronization or event chaining. They can generate
independent DMA request and support quadrature encoders. Their counter can be
frozen in debug mode.
• TIM14
This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. It has one
channel for input capture/output compare, PWM output or one-pulse mode output. Its
counter can be frozen in debug mode.
• TIM15, TIM16, TIM17
These are general-purpose timers featuring:
– 16-bit auto-reload upcounter and 16-bit prescaler
– 2 channels and 1 complementary channel for TIM15
– 1 channel and 1 complementary channel for TIM16 and TIM17
All channels can be used for input capture/output compare, PWM or one-pulse mode
output. The timers can operate together via the Timer Link feature for synchronization
or event chaining. They can generate independent DMA request. Their counters can
be frozen in debug mode.
3.18.3 Basic timers (TIM6 and TIM7)
These timers are mainly used for triggering DAC conversions. They can also be used as
generic 16-bit timebases.
3.18.4 Low-power timers (LPTIM1 and LPTIM2)
These timers have an independent clock. When fed with LSE, LSI or external clock, they
keep running in Stop mode and they can wake up the system from it.
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35
Functional overview STM32G0B1xB/C/xE
Features of LPTIM1 and LPTIM2:
• 16-bit up counter with 16-bit autoreload register
• 16-bit compare register
• Configurable output (pulse, PWM)
• Continuous/one-shot mode
• Selectable software/hardware input trigger
• Selectable clock source:
– Internal: LSE, LSI, HSI16 or APB clocks
– External: over LPTIM input (working even with no internal clock source running,
used by pulse counter application)
• Programmable digital glitch filter
• Encoder mode
3.18.5 Independent watchdog (IWDG)
The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with
user-defined refresh window. It is clocked from an independent 32 kHz internal RC (LSI).
Independent of the main clock, it can operate in Stop and Standby modes. It can be used
either as a watchdog to reset the device when a problem occurs, or as a free-running timer
for application timeout management. It is hardware- or software-configurable through the
option bytes. Its counter can be frozen in debug mode.
3.18.6 System window watchdog (WWDG)
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked by the
system clock. It has an early-warning interrupt capability. Its counter can be frozen in debug
mode.
3.18.7 SysTick timer
This timer is dedicated to real-time operating systems, but it can also be used as a standard
down counter.
Features of SysTick timer:
• 24-bit down counter
• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0
• Programmable clock source
3.19 Real-time clock (RTC), tamper (TAMP) and backup registers
The device embeds an RTC and five 32-bit backup registers, located in the RTC domain of
the silicon die.
The ways of powering the RTC domain are described in Section 3.7.6.
The RTC is an independent BCD timer/counter.
30/159 DS13560 Rev 1
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