ST MICROELECTRONICS STM32G0B1RET6 Datasheet

Download

STM32G0B1xB/C/xE

LQFP64

UFQFPN48

UFQFPN32

LQFP48

LQFP32

WLCSP52

3.09 × 3.15 mm

UFBGA64

5mm

10 mm

7mm

7×7mm

5×5mm

LQFP100

14 mm

UFBGA100 7

7mm

LQFP80

12 mm

Arm® Cortex®-M0+ 32-bit MCU, up to 512KB Flash, 144KB RAM,

6x USART, timers, ADC, DAC, comm. I/Fs, 1.7-3.6V

Datasheet - production data

Features

• Core: Arm® 32-bit Cortex®-M0+ CPU, frequency up to 64 MHz

• -40°C to 85°C/105°C/125°C operating temperature

• Memories – Up to 512 Kbytes of Flash memory with

protection and securable area, two banks, read-while-write support

– 144 Kbytes of SRAM (128 Kbytes with HW

parity check)

• CRC calculation unit

• Reset and power management

– Voltage range: 1.7 V to 3.6 V – Separate I/O supply pin (1.6 V to 3.6 V) – Power-on/Power-down reset (POR/PDR) – Programmable Brownout reset (BOR) – Programmable voltage detector (PVD) – Low-power modes:

Sleep, Stop, Standby, Shutdown

–V

supply for RTC and backup registers

BAT

• Clock management – 4 to 48 MHz crystal oscillator – 32 kHz crystal oscillator with calibration – Internal 16 MHz RC with PLL option (±1 %) – Internal 32 kHz RC oscillator (±5 %)

• Up to 94 fast I/Os – All mappable on external interrupt vectors – Multiple 5 V-tolerant I/Os

• 12-channel DMA controller with flexible mapping

• 12-bit, 0.4 µs ADC (up to 16 ext. channels) – Up to 16-bit with hardware oversampling – Conversion range: 0 to 3.6V

• Two 12-bit DACs, low-power sample-and-hold

• Three fast low-power analog comparators, with

programmable input and output, rail-to-rail

• 15 timers (two 128 MHz capable): 16-bit for advanced motor control, one 32-bit and six 16bit general-purpose, two basic 16-bit, two lowpower 16-bit, two watchdogs, SysTick timer

• Calendar RTC with alarm and periodic wakeup from Stop/Standby/Shutdown

• Communication interfaces – Three I

C-bus interfaces supporting Fastmode Plus (1 Mbit/s) with extra current sink, two supporting SMBus/PMBus and wakeup from Stop mode

– Six USARTs with master/slave

synchronous SPI; three supporting ISO7816 interface, LIN, IrDA capability, auto baud rate detection and wakeup feature

– Two low-power UARTs – Three SPIs (32 Mbit/s) with 4- to 16-bit

programmable bitframe, two multiplexed

with I

S interface

– HDMI CEC interface, wakeup on header

• USB 2.0 FS device (crystal-less) and host controller

• USB Type-C™ Power Delivery controller

• Two FDCAN controllers

• Development support: serial wire debug (SWD)

• 96-bit unique ID

• All packages ECOPACK

Reference Part number

STM32G0B1xC

STM32G0B1xE

STM32G0B1xB

Table 1. Device summary

STM32G0B1CC, STM32G0B1KC,

STM32G0B1MC, STM32G0B1RC,

STM32G0B1CE, STM32G0B1KE,

STM32G0B1ME, STM32G0B1NE,

STM32G0B1RE, STM32G0B1VE

STM32G0B1CB, STM32G0B1KB,

STM32G0B1MB, STM32G0B1RB,

2 compliant

STM32G0B1VC

STM32G0B1VB

November 2020 DS13560 Rev 1 1/159

This is information on a product in full production.

www.st.com

Contents STM32G0B1xB/C/xE

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.1 Arm® Cortex®-M0+ core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.3.1 Securable area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.5 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.6 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 16

3.7 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.7.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.7.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.7.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.7.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.7.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.7.6 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.8 Interconnect of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.9 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.10 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.11 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.12 DMA request multiplexer (DMAMUX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.13 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.13.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 24

3.13.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 24

3.14 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.14.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.14.2 Internal voltage reference (V

3.14.3 V

battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

BAT

) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

REFINT

3.15 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.16 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2/159 DS13560 Rev 1

STM32G0B1xB/C/xE Contents

3.17 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.18 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.18.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.18.2 General-purpose timers (TIM2, 3, 4, 14, 15, 16, 17) . . . . . . . . . . . . . . . 29

3.18.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.18.4 Low-power timers (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . 29

3.18.5 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.18.6 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.18.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.19 Real-time clock (RTC), tamper (TAMP) and backup registers . . . . . . . . . 30

3.20 Inter-integrated circuit interface (I

C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.21 Universal synchronous/asynchronous receiver transmitter (USART) . . . 32

3.22 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 33

3.23 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.24 Universal serial bus device (USB) and host (USBH) . . . . . . . . . . . . . . . . 34

3.25 USB Type-C™ Power Delivery controller . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.26 Controller area network (FDCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.27 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.27.1 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4 Pinouts, pin description and alternate functions . . . . . . . . . . . . . . . . . 36

5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 68

5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 68

DS13560 Rev 1 3/159

Contents STM32G0B1xB/C/xE

5.3.4 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

5.3.6 Wakeup time from low-power modes and voltage scaling

transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

5.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

5.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

5.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

5.3.10 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

5.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

5.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

5.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

5.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

5.3.15 NRST input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

5.3.16 Analog switch booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

5.3.17 Analog-to-digital converter characteristics . . . . . . . . . . . . . . . . . . . . . . 100

5.3.18 Digital-to-analog converter characteristics . . . . . . . . . . . . . . . . . . . . . . 107

5.3.19 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 111

5.3.20 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

5.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

5.3.22 V

5.3.23 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

5.3.24 Characteristics of communication interfaces . . . . . . . . . . . . . . . . . . . . 115

5.3.25 UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

BAT

6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

6.1 UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

6.2 LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

6.3 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

6.4 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

6.5 WLCSP52 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

6.6 UFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

6.7 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

6.8 LQFP80 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

6.9 UFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

6.10 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

6.11 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

4/159 DS13560 Rev 1

STM32G0B1xB/C/xE Contents

6.11.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

6.11.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 155

7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

DS13560 Rev 1 5/159

List of tables STM32G0B1xB/C/xE

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 3. Access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 15

Table 4. Interconnect of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 5. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 6. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 7. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 8. I

Table 9. USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 10. SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 11. Terms and symbols used in Table 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 12. Pin assignment and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 13. Port A alternate function mapping (AF0 to AF7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 14. Port A alternate function mapping (AF8 to AF15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 15. Port B alternate function mapping (AF0 to AF7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 16. Port B alternate function mapping (AF8 to AF15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 17. Port C alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 18. Port D alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 19. Port E alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 20. Port F alternate function mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 21. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 22. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 23. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 24. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 25. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 26. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 27. Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 28. Current consumption in Run and Low-power run modes

Table 29. Typical current consumption in Run and Low-power run modes,

Table 30. Current consumption in Sleep and Low-power sleep modes . . . . . . . . . . . . . . . . . . . . . . . 74

Table 31. Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 32. Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 33. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 34. Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 35. Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 36. Current consumption of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 37. Low-power mode wakeup times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 38. Regulator mode transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 39. Wakeup time using LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 40. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 41. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 42. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 43. LSE oscillator characteristics (f

Table 44. HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 45. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 46. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

at different die temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

depending on code executed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

LSE

6/159 DS13560 Rev 1

STM32G0B1xB/C/xE List of tables

Table 47. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 48. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 49. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 50. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 51. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 52. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 53. Electrical sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 54. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 55. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 56. Input characteristics of FT_e I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 57. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 58. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 59. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 60. Analog switch booster characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 61. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 62. Maximum ADC R

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

AIN

Table 63. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 64. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 65. DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Table 66. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table 67. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Table 68. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 69. V Table 70. V

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

BAT

charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

BAT

Table 71. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 72. IWDG min/max timeout period at 32 kHz LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Table 73. Minimum I2CCLK frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Table 74. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Table 75. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 76. I

S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Table 77. USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Table 78. USB OTG DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 79. USB OTG electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Table 80. USB BCD DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Table 81. UCPD operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Table 82. UFQFPN32 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Table 83. LQFP32 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Table 84. UFQFPN48 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Table 85. LQFP48 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Table 86. WLCSP52 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Table 87. Recommended PCB pad design rules for WLCSP52 package . . . . . . . . . . . . . . . . . . . . 139

Table 88. UFBGA64 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Table 89. Recommended PCB design rules for UFBGA64 package . . . . . . . . . . . . . . . . . . . . . . . . 141

Table 90. LQFP64 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Table 91. LQFP80 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Table 92. UFBGA100 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Table 93. UFBGA100 recommended PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Table 94. LQFP100 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Table 95. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Table 96. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

DS13560 Rev 1 7/159

List of figures STM32G0B1xB/C/xE

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 2. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 3. STM32G0B1VxT LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 4. STM32G0B1VxI UFBGA100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 5. STM32G0B1MxT LQFP80 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 6. STM32G0B1RxT LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 7. STM32G0B1RxI UFBGA64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 8. STM32G0B1NxY WLCSP52 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 9. STM32G0B1CxT LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 10. STM32G0B1CxU UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 11. STM32G0B1KxT LQFP32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 12. STM32G0B1KxU UFQFPN32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 13. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 14. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 15. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 16. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 17. V

Figure 18. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 19. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 20. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 21. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 22. HSI16 frequency vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 23. HSI48 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 24. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 25. Current injection into FT_e input with diode active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 26. I/O AC characteristics definition

Figure 27. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 28. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 29. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 30. 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Figure 31. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 32. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 33. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 34. I Figure 35. I

Figure 36. USB OTG timings – definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . 123

Figure 37. UFQFPN32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Figure 38. Recommended footprint for UFQFPN32 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Figure 39. UFQFPN32 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Figure 40. LQFP32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Figure 41. Recommended footprint for LQFP32 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Figure 42. LQFP32 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Figure 43. UFQFPN48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Figure 44. Recommended footprint for UFQFPN48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Figure 45. UFQFPN48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Figure 46. LQFP48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Figure 47. Recommended footprint for LQFP48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Figure 48. LQFP48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

REFINT

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

S master timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

8/159 DS13560 Rev 1

STM32G0B1xB/C/xE List of figures

Figure 49. WLCSP52 package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Figure 50. Recommended PCB pad design for WLCSP52 package. . . . . . . . . . . . . . . . . . . . . . . . . 138

Figure 51. WLCSP52 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Figure 52. UFBGA64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Figure 53. Recommended footprint for UFBGA64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Figure 54. UFBGA64 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Figure 55. LQFP64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Figure 56. Recommended footprint for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Figure 57. LQFP64 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Figure 58. LQFP80 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Figure 59. Recommended footprint for LQFP80 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Figure 60. LQFP80 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Figure 61. UFBGA100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Figure 62. Recommended footprint for UFBGA100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Figure 63. UFBGA100 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Figure 64. LQFP100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Figure 65. Recommended footprint for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Figure 66. LQFP100 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

DS13560 Rev 1 9/159

Introduction STM32G0B1xB/C/xE

1 Introduction

This document provides information on STM32G0B1xB/C/xE microcontrollers, such as description, functional overview, pin assignment and definition, electrical characteristics, packaging, and ordering codes.

Information on memory mapping and control registers is object of reference manual.

Information on Arm

®(a)

Cortex®-M0+ core is available from the www.arm.com website.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

10/159 DS13560 Rev 1

STM32G0B1xB/C/xE Description

2 Description

The STM32G0B1xB/C/xE mainstream microcontrollers are based on high-performance

Arm

Cortex®-M0+ 32-bit RISC core operating at up to 64 MHz frequency. Offering a high level of integration, they are suitable for a wide range of applications in consumer, industrial and appliance domains and ready for the Internet of Things (IoT) solutions.

The devices incorporate a memory protection unit (MPU), high-speed embedded memories (144 Kbytes of SRAM and up to 512 Kbytes of Flash program memory with read protection, write protection, proprietary code protection, and securable area), DMA, an extensive range of system functions, enhanced I/Os, and peripherals. The devices offer standard communication interfaces (three I USB, two FD CANs, and six USARTs), one 12-bit ADC (2.5 MSps) with up to 19 channels, one 12-bit DAC with two channels, three fast comparators, an internal voltage reference buffer, a low-power RTC, an advanced control PWM timer running at up to double the CPU frequency, six general-purpose 16-bit timers with one running at up to double the CPU frequency, a 32-bit general-purpose timer, two basic timers, two low-power 16-bit timers, two watchdog timers, and a SysTick timer. The devices provide a fully integrated USB TypeC Power Delivery controller.

The devices operate within ambient temperatures from -40 to 125°C and with supply voltages from 1.7 V to 3.6 V. Optimized dynamic consumption combined with a comprehensive set of power-saving modes, low-power timers and low-power UART, allows the design of low-power applications.

Cs, three SPIs / two I2S, one HDMI CEC, one full-speed

VBAT direct battery input allows keeping RTC and backup registers powered.

The devices come in packages with 32 to 100 pins.

Peripheral

Flash memory (Kbyte)

SRAM (Kbyte) 128 (parity-protected) or 144 (not parity-protected)

Advanced control 1 (16-bit) high frequency

General-purpose 6 (16-bit) + 1 (16-bit) high frequency + 1 (32-bit)

Basic 2 (16-bit)

Timers

Low-power 2 (16-bit)

SysTick 1

Watchdog 2

Table 2. Features and peripheral counts

STM32G0B1_

_KB/ _KC/

_KE

128/256/

512

_KBxxN/ _KCxxN/

_KExxN

128/256

/512

_CB/ _CC/

_CE

128/256

/512

_CBxxN/ _CCxxN/

_CExxN

128/256

/512

_NE

512

_RB/ _RC/

_RE

128/256

/512

_RBxxN/ _RCxxN/

_RExxN

128/256

/512

_MB/ _MC/

_ME

128/256

/512

_VB/ _VC/

_VE

128/256

/512

DS13560 Rev 1 11/159

Description STM32G0B1xB/C/xE

Table 2. Features and peripheral counts (continued)

STM32G0B1_

Peripheral

SPI [I2S]

_KB/ _KC/

_KE

(1)

_KBxxN/ _KCxxN/

_KExxN

_CB/ _CC/

_CE

_CBxxN/ _CCxxN/

_CExxN

_NE

3 [2]

_RB/ _RC/

_RE

_RBxxN/ _RCxxN/

_RExxN

_MB/ _MC/

_ME

USART 6

LPUART 2

USB 1

Comm. interfaces

UCPD 1

(2)

21 2 1 2

FDCAN 2

CEC 1

RTC Yes

Tamper pins 3

VDDIO2 pin / VSS pin No/No Yes/No No/No Yes/Yes Yes/Yes No/No Yes/Yes Yes/Yes Yes/Yes

Random number generator No

AES No

GPIOs 30 2944424660587494

Wakeup pins 4 3 4 5 7 8

ADC channels (ext. + int.) 11 + 2 10 + 2 14 + 3 12 + 3 14 + 3 16 + 3 14 + 3 16 + 3 16 + 3

DAC channels 2

Internal voltage reference

buffer

No Yes

Analog comparators 3

Max. CPU frequency 64 MHz

Operating voltage 1.7 to 3.6 V

Operating temperature

(3)

Ambient: -40 to 85 °C / -40 to 105 °C / -40 to 125 °C

Junction: -40 to 105 °C / -40 to 125 °C / -40 to 130 °C

Number of pins 32 48 52 64 80 100

1. The numbers in brackets denote the count of SPI interfaces configurable as I

S interface.

2. One port with only one CC line available (supporting limited number of use cases).

3. Depends on order code. Refer to Section 7: Ordering information for details.

_VB/ _VC/

_VE

12/159 DS13560 Rev 1

MSv63193V1

Parity

FDCAN1 & 2

I2C2

SPI1/I2S

LPUART& & 2

UCPD

USART3/4

LPTIMER 1/2

TIMER 16/17

Power domain of analog blocks :

BAT

4 channels BKIN, BKIN2, ETR

System and

peripheral

clocks

MOSI/SD

MISO/MCK

SCK/CK

NSS/WS

SWCLK

SWDIO

16x IN

OSC_IN OSC_OUT

VBAT

OSC32_IN OSC32_OUT

RTC_OUT RTC_REFIN RTC_TS

MOSI, MISO

SCK, NSS

HSI16

LSI

PLLPCLK

IR_OUT

1 channel BKIN

ETR, IN, OUT

1 channel

4 channels ETR

CPU

CORTEX-M0+

max

= 64 MHz

SWD

NVIC

EXTI

SPI/I2S 1 & 2

SPI3

AHB-to-APB

RCC

Reset & clock control

I/F

XTAL OSC

4-48 MHz

IWDG

I/F

ADC

RTC, TAMP Backup regs

I/F

RC 16 MHz

RC 32 kHz

PLL

decoder

XTAL32 kHz

Bus matrix

I/F

2 channels BKIN

RX, TX CTS, RTS

CEC

TIM6

TIM7

COMP1

COMP2

IN+, IN-,

OUT

DDA

SUPPLY

SUPERVISION

POWER

CORE

POR

Reset

Int

VDD/VDDA VSS/VSSA

NRST

PVD

POR/BOR

Voltage

regulator

USART1 to 6

LPTIM1 & 2

TIM16 & 17

TIM15

TIM14

TIM3 & 4

TIM2 (32-bit)

TIM1

GPIOs

IOPORT

HSE

PLLQCLK PLLRCLK

LSE

T sensor

RX, TX, CTS, RTS

LPUART1 & 2

TAMP_IN

APB

AHB

CC, DBCC

FRSTX

UCPD1 & 2

HDMI-CEC

VREFBUF

DAC

I/F

DAC_OUT1

DAC_OUT2

CRC

VREF+

SCL, SDA

SCL, SDA SMBA, SMBUS

I2C1 & 2

I2C3

DBGMCU

WWDG

PWRCTRL

SYSCFG

DMA

DMAMUX

DDA

DDIO1

Low-voltage

detector

Flash memory

up to 512 KB

DDIO1

DDIO2

IRTIM

from peripherals

PFx

Port F

Port D

PDx

PCx

Port C

PBx

Port B

PAx

Port A

Port E

PEx

NOE, DM,

USB FS

RX, TX

FDCAN1 & 2

VDDIO2

DDIO2

COMP3

SRAM

144 KB

STM32G0B1xB/C/xE Description

Figure 1. Block diagram

DS13560 Rev 1 13/159

Functional overview STM32G0B1xB/C/xE

3 Functional overview

3.1 Arm® Cortex®-M0+ core with MPU

The Cortex-M0+ is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:

• a simple architecture, easy to learn and program

• ultra-low power, energy-efficient operation

• excellent code density

• deterministic, high-performance interrupt handling

• upward compatibility with Cortex-M processor family

• platform security robustness, with integrated Memory Protection Unit (MPU).

The Cortex-M0+ processor is built on a highly area- and power-optimized 32-bit core, with a 2-stage pipeline Von Neumann architecture. The processor delivers exceptional energy efficiency through a small but powerful instruction set and extensively optimized design, providing high-end processing hardware including a single-cycle multiplier.

The Cortex-M0+ processor provides the exceptional performance expected of a modern 32-bit architecture, with a higher code density than other 8-bit and 16-bit microcontrollers.

Owing to embedded Arm core, the STM32G0B1xB/C/xE devices are compatible with Arm tools and software.

The Cortex-M0+ is tightly coupled with a nested vectored interrupt controller (NVIC) described in Section 3.13.1.

3.2 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task.

The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

3.3 Embedded Flash memory

STM32G0B1xB/C/xE devices feature up to 512 Kbytes of embedded Flash memory available for storing code and data.

14/159 DS13560 Rev 1

STM32G0B1xB/C/xE Functional overview

Flexible protections can be configured thanks to option bytes:

• Readout protection (RDP) to protect the whole memory. Three levels are available:

– Level 0: no readout protection

– Level 1: memory readout protection: the Flash memory cannot be read from or

written to if either debug features are connected, boot in RAM or bootloader is selected

– Level 2: chip readout protection: debug features (Cortex-M0+ serial wire), boot in

RAM and bootloader selection are disabled. This selection is irreversible.

Table 3. Access status versus readout protection level and execution modes

Area

User

memory

System

memory

Option

bytes

Backup

registers

1. Erased upon RDP change from Level 1 to Level 0.

Protection

level

1 Yes Yes Yes No No No

2 Yes Yes Yes N/A N/A N/A

1 Yes No No Yes No No

2 Yes No No N/A N/A N/A

1 Yes Yes Yes Yes Yes Yes

2 Yes No No N/A N/A N/A

1YesYesN/A

2 Yes Yes N/A N/A N/A N/A

User execution

Read Write Erase Read Write Erase

(1)

Debug, boot from RAM or boot

from system memory (loader)

No No N/A

• Write protection (WRP): the protected area is protected against erasing and

programming. Two areas per bank can be selected, with 2-Kbyte granularity.

• Proprietary code readout protection (PCROP): a part of the Flash memory can be

protected against read and write from third parties. The protected area is execute-only: it can only be reached by the STM32 CPU as instruction code, while all other accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited. An additional option bit (PCROP_RDP) determines whether the PCROP area is erased or not when the RDP protection is changed from Level 1 to Level 0.

(1)

The whole non-volatile memory embeds the error correction code (ECC) feature supporting:

• single error detection and correction

• double error detection

• readout of the ECC fail address from the ECC register

3.3.1 Securable area

A part of the Flash memory can be hidden from the application once the code it contains is executed. As soon as the write-once SEC_PROT bit is set, the securable memory cannot be accessed until the system resets. The securable area generally contains the secure boot code to execute only once at boot. This helps to isolate secret code from untrusted application code.

DS13560 Rev 1 15/159

Functional overview STM32G0B1xB/C/xE

3.4 Embedded SRAM

STM32G0B1xB/C/xE devices have 128 Kbytes of embedded SRAM with parity. Hardware parity check allows memory data errors to be detected, which contributes to increasing functional safety of applications.

When the parity protection is not required because the application is not safety-critical, the parity memory bits can be used as additional SRAM, to increase its total size to 144 Kbytes.

The memory can be read/write-accessed at CPU clock speed, with 0 wait states.

3.5 Boot modes

At startup, the boot pin and boot selector option bit are used to select one of the three boot options:

• boot from User Flash memory

• boot from System memory

• boot from embedded SRAM

The boot pin is shared with a standard GPIO and can be enabled through the boot selector option bit. The boot loader is located in System memory. It manages the Flash memory reprogramming through one of the following interfaces:

• USART on pins PA9/PA10, PC10/PC11, or PA2/PA3

• I

C-bus on pins PB6/PB7 or PB10/PB11

• SPI on pins PA4/PA5/PA6/PA7 or PB12/PB13/PB14/PB15

• USB on pins PA11/PA12

• FDCAN on pins PD0/PD1

3.6 Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link time and stored at a given memory location.

16/159 DS13560 Rev 1

STM32G0B1xB/C/xE Functional overview

3.7 Power supply management

3.7.1 Power supply schemes

The STM32G0B1xB/C/xE devices require a 1.7 V to 3.6 V operating supply voltage (VDD). Several different power supplies are provided to specific peripherals:

• V

= 1.7 (1.6) to 3.6 V

is the external power supply for the internal regulator and the system analog such

as reset, power management and internal clocks. It is provided externally through VDD/VDDA pin.

The minimum voltage of 1.7 V corresponds to power-on reset release threshold V

(max). Once this threshold is crossed and power-on reset is released, the

POR

functionality is guaranteed down to power-down reset threshold V

= 1.62 V (ADC and COMP) / 1.8 V (DAC) / 2.4 V (VREFBUF) to 3.6 V

DDA

is the analog power supply for the A/D converter, D/A converter, voltage

DDA

reference buffer and comparators. V

voltage level is identical to VDD voltage as it is

DDA

PDR

(min).

provided externally through VDD/VDDA pin.

= V

DDIO1

is the power supply for the I/Os. V

voltage level is identical to VDD voltage

DDIO1

as it is provided externally through VDD/VDDA pin.

= 1.6 to 3.6 V

DDIO2

V independent of V

TAMP, low-speed external 32.768 kHz oscillator and backup registers when V present. V

is the power supply from VDDIO2 pin for selected I/Os. Although V

DDIO2

= 1.55 V to 3.6 V. V

BAT

or V

, it must not be applied without valid VDD.

DDA

is the power supply (through a power switch) for RTC,

BAT

is provided externally through VBAT pin. When this pin is not available

DDIO2

is not

on the package, VBAT bonding pad is internally bonded to the VDD/VDDA pin.

is the analog peripheral input reference voltage, or the output of the internal

REF+

voltage reference buffer (when enabled). When V V

. When V

DDA

when the analog peripherals using V

DDA

 2 V, V

must be between 2 V and V

REF+

are not active.

REF+

DDA

< 2 V, V

must be equal to

REF+

. It can be grounded

DDA

The internal voltage reference buffer supports two output voltages, which is configured with VRS bit of the VREFBUF_CSR register:

–V

REF+

internally connected with V

around 2.048 V (requiring V

REF+

around 2.5 V (requiring V

REF+

equal to or higher than 2.4 V)

DDA

equal to or higher than 2.8 V)

DDA

is delivered through VREF+ pin. On packages without VREF+ pin, V

, and the internal voltage reference buffer must be kept

REF+

disabled (refer to datasheets for package pinout description).

CORE

An embedded linear voltage regulator is used to supply the V power. V The Flash memory is also supplied with V

is the power supply for digital peripherals, SRAM and Flash memory.

CORE

internal digital

CORE

DS13560 Rev 1 17/159

Functional overview STM32G0B1xB/C/xE

MSv63104V1

DDA

domain

RTC domain

D/A converter

A/D converter

Standby circuitry (Wakeup, IWDG)

Voltage

regulator

Core

SRAM

Digital

peripherals

Low-voltage

detector

LSE crystal 32.768 kHz osc

BKP registers

RCC BDCR register

RTC and TAMP

Comparators

Voltage reference buffer

I/O ring

CORE

domain

Temp. sensor

Reset block

PLL, HSI

Flash memory

DDIO1

VREF+

domain

CORE

VSS/VSSA

VDD/VDDA

VBAT

DDA

REF+

SSA

DDIO1

domain

I/O ring

DDIO2

domain

VDDIO2

DDIO2

Figure 2. Power supply overview

3.7.2 Power supply supervisor

The device has an integrated power-on/power-down (POR/PDR) reset active in all power modes except Shutdown and ensuring proper operation upon power-on and power-down. It maintains the device in reset when the supply voltage is below V the need for an external reset circuit. Brownout reset (BOR) function allows extra flexibility. It can be enabled and configured through option bytes, by selecting one of four thresholds for rising V

The device also features an embedded programmable voltage detector (PVD) that monitors the V when V falling and rising. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

3.7.3 Voltage regulator

Two embedded linear voltage regulators, main regulator (MR) and low-power regulator (LPR), supply most of digital circuitry in the device.

18/159 DS13560 Rev 1

The MR is used in Run and Sleep modes. The LPR is used in Low-power run, Low-power sleep and Stop modes.

In Standby and Shutdown modes, both regulators are powered down and their outputs set in high-impedance state, such as to bring their current consumption close to zero. However, SRAM data retention is possible in Standby mode, in which case the LPR remains active and it only supplies the SRAM.

and other four for falling VDD.

power supply and compares it to V

level crosses the V

PVD

threshold, selectively while falling, while rising, or while

PVD

POR/PDR

threshold, without

threshold. It allows generating an interrupt

STM32G0B1xB/C/xE Functional overview

3.7.4 Low-power modes

By default, the microcontroller is in Run mode after system or power reset. It is up to the user to select one of the low-power modes described below:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

• Low-power run mode

This mode is achieved with V regulator's operating current. The code can be executed from SRAM or from Flash, and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can be clocked by HSI16.

• Low-power sleep mode

This mode is entered from the low-power run mode. Only the CPU clock is stopped. When wakeup is triggered by an event or an interrupt, the system reverts to the Lowpower run mode.

• Stop 0 and Stop 1 modes

In Stop 0 and Stop 1 modes, the device achieves the lowest power consumption while retaining the SRAM and register contents. All clocks in the V The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are disabled. The LSE or LSI keep running. The RTC can remain active (Stop mode with RTC, Stop mode without RTC).

Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode, so as to get clock for processing the wakeup event. The main regulator remains active in Stop 0 mode while it is turned off in Stop 1 mode.

• Standby mode

The Standby mode is used to achieve the lowest power consumption, with POR/PDR always active in this mode. The main regulator is switched off to power down V domain. The low-power regulator is either switched off or kept active. In the latter case, it only supplies SRAM to ensure data retention. The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are also powered down. The RTC can remain active (Standby mode with RTC, Standby mode without RTC).

For each I/O, the software can determine whether a pull-up, a pull-down or no resistor shall be applied to that I/O during Standby mode.

Upon entering Standby mode, register contents are lost except for registers in the RTC domain and standby circuitry. The SRAM contents can be retained through register setting.

The device exits Standby mode upon external reset event (NRST pin), IWDG reset event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event (alarm, periodic wakeup, timestamp, tamper), or when a failure is detected on LSE (CSS on LSE).

• Shutdown mode

The Shutdown mode allows to achieve the lowest power consumption. The internal regulator is switched off to power down the V

supplied by the low-power regulator to minimize the

CORE

domain are stopped.

CORE

domain. The PLL, as well as the

CORE

DS13560 Rev 1 19/159

Functional overview STM32G0B1xB/C/xE

HSI16 and LSI RC-oscillators and HSE crystal oscillator are also powered down. The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).

The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode. Therefore, switching to RTC domain is not supported.

SRAM and register contents are lost except for registers in the RTC domain.

The device exits Shutdown mode upon external reset event (NRST pin), IWDG reset event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event (alarm, periodic wakeup, timestamp, tamper).

3.7.5 Reset mode

During and upon exiting reset, the schmitt triggers of I/Os are disabled so as to reduce power consumption. In addition, when the reset source is internal, the built-in pull-up resistor on NRST pin is deactivated.

3.7.6 VBAT operation

The V

power domain, consuming very little energy, includes RTC, and LSE oscillator and

BAT

backup registers.

In VBAT mode, the RTC domain is supplied from VBAT pin. The power source can be, for example, an external battery or an external supercapacitor. Two anti-tamper detection pins are available.

The RTC domain can also be supplied from VDD/VDDA pin.

By means of a built-in switch, an internal voltage supervisor allows automatic switching of RTC domain powering between V voltage of the RTC domain (V

BAT

and voltage from VBAT pin to ensure that the supply

) remains within valid operating conditions. If both voltages

are valid, the RTC domain is supplied from VDD/VDDA pin.

An internal circuit for charging the battery on VBAT pin can be activated if the V

voltage is

within a valid range.

Note: External interrupts and RTC alarm/events cannot cause the microcontroller to exit the VBAT

mode, as in that mode the V

is not within a valid range.

3.8 Interconnect of peripherals

Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections allow fast and predictable latency.

Depending on peripherals, these interconnections can operate in Run, Sleep and Stop modes.

20/159 DS13560 Rev 1

STM32G0B1xB/C/xE Functional overview

Interconnect source

TIMx

COMPx

ADCx TIM1 Timer triggered by analog watchdog Y Y -

RTC

All clock sources (internal and

external)

Table 4. Interconnect of peripherals

Interconnect

destination

TIMx Timer synchronization or chaining Y Y -

ADCx DACx

Conversion triggers Y Y -

DMA Memory-to-memory transfer trigger Y Y -

COMPx Comparator output blanking Y Y -

TIM1,2,3,4

LPTIMERx

Timer input channel, trigger, break from analog signals comparison

Low-power timer triggered by analog signals comparison

TIM16 Timer input channel from RTC events Y Y -

LPTIMERx

TIM14,16,17

Low-power timer triggered by RTC alarms or tampers

Clock source used as input channel for RC measurement and trimming

Interconnect action

Run

Sleep

Low-power run

YY -

YYY

YY -

Stop

Low-power sleep

CSS

RAM (parity error)

Flash memory (ECC error)

TIM1,15,16,17 Timer break Y Y -

COMPx

PVD

CPU (hard fault) TIM1,15,16,17 Timer break Y - -

TIMx External trigger Y Y -

GPIO

LPTIMERx External trigger Y Y Y

ADC

DACx

Conversion external trigger Y Y -

DS13560 Rev 1 21/159

Functional overview STM32G0B1xB/C/xE

3.9 Clocks and startup

The clock controller distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. It features:

• Clock prescaler: to get the best trade-off between speed and current consumption,

the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler

• Safe clock switching: clock sources can be changed safely on the fly in run mode

through a configuration register.

• Clock management: to reduce power consumption, the clock controller can stop the

clock to the core, individual peripherals or memory.

• System clock source: three different sources can deliver SYSCLK system clock:

– 4-48 MHz high-speed oscillator with external crystal or ceramic resonator (HSE). It

can supply clock to system PLL. The HSE can also be configured in bypass mode for an external clock.

– 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software. It can

supply clock to system PLL.

– System PLL with maximum output frequency of 64 MHz. It can be fed with HSE or

HSI16 clocks.

• Auxiliary clock source: two ultra-low-power clock sources for the real-time clock

(RTC):

– 32.768 kHz low-speed oscillator with external crystal (LSE), supporting four drive

capability modes. The LSE can also be configured in bypass mode for using an external clock.

– 32 kHz low-speed internal RC oscillator (LSI) with ±5% accuracy, also used to

clock an independent watchdog.

• Peripheral clock sources: several peripherals ( I2S, USARTs, I2Cs, LPTIMs, ADC,

USB FS) have their own clock independent of the system clock.

• Clock security system (CSS): in the event of HSE clock failure, the system clock is

automatically switched to HSI16 and, if enabled, a software interrupt is generated. LSE clock failure can also be detected and generate an interrupt. The CCS feature can be enabled by software.

• Clock output:

– MCO (microcontroller clock output) provides one of the internal clocks for

external use by the application

– LSCO (low speed clock output) provides LSI or LSE in all low-power modes

(except in VBAT operation).

Several prescalers allow the application to configure AHB and APB domain clock frequencies, 64 MHz at maximum.

3.10 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function (AF). Most of the GPIO pins are shared with special digital or analog functions.

22/159 DS13560 Rev 1

STM32G0B1xB/C/xE Functional overview

Through a specific sequence, this special function configuration of I/Os can be locked, such as to avoid spurious writing to I/O control registers.

3.11 Direct memory access controller (DMA)

The direct memory access (DMA) controller is a bus master and system peripheral with single-AHB architecture.

With 12 channels, it performs data transfers between memory-mapped peripherals and/or memories, to offload the CPU.

Each channel is dedicated to managing memory access requests from one or more peripherals. The unit includes an arbiter for handling the priority between DMA requests.

Main features of the DMA controller:

• Single-AHB master

• Peripheral-to-memory, memory-to-peripheral, memory-to-memory and peripheral-to-

peripheral data transfers

• Access, as source and destination, to on-chip memory-mapped devices such as Flash

memory, SRAM, and AHB and APB peripherals

• All DMA channels independently configurable:

– Each channel is associated either with a DMA request signal coming from a

peripheral, or with a software trigger in memory-to-memory transfers. This configuration is done by software.

– Priority between the requests is programmable by software (four levels per

channel: very high, high, medium, low) and by hardware in case of equality (such as request to channel 1 has priority over request to channel 2).

– Transfer size of source and destination are independent (byte, half-word, word),

emulating packing and unpacking. Source and destination addresses must be aligned on the data size.

– Support of transfers from/to peripherals to/from memory with circular buffer

management

– Programmable number of data to be transferred: 0 to 2

• Generation of an interrupt request per channel. Each interrupt request originates from

any of the three DMA events: transfer complete, half transfer, or transfer error.

- 1

3.12 DMA request multiplexer (DMAMUX)

The DMAMUX request multiplexer enables routing a DMA request line between the peripherals and the DMA controller. Each channel selects a unique DMA request line, unconditionally or synchronously with events from its DMAMUX synchronization inputs. DMAMUX may also be used as a DMA request generator from programmable events on its input trigger signals.

3.13 Interrupts and events

The device flexibly manages events causing interrupts of linear program execution, called exceptions. The Cortex-M0+ processor core, a nested vectored interrupt controller (NVIC)

DS13560 Rev 1 23/159

Functional overview STM32G0B1xB/C/xE

and an extended interrupt/event controller (EXTI) are the assets contributing to handling the exceptions. Exceptions include core-internal events such as, for example, a division by zero and, core-external events such as logical level changes on physical lines. Exceptions result in interrupting the program flow, executing an interrupt service routine (ISR) then resuming the original program flow.

The processor context (contents of program pointer and status registers) is stacked upon program interrupt and unstacked upon program resume, by hardware. This avoids context stacking and unstacking in the interrupt service routines (ISRs) by software, thus saving time, code and power. The ability to abandon and restart load-multiple and store-multiple operations significantly increases the device’s responsiveness in processing exceptions.

3.13.1 Nested vectored interrupt controller (NVIC)

The configurable nested vectored interrupt controller is tightly coupled with the core. It handles physical line events associated with a non-maskable interrupt (NMI) and maskable interrupts, and Cortex-M0+ exceptions. It provides flexible priority management.

The tight coupling of the processor core with NVIC significantly reduces the latency between interrupt events and start of corresponding interrupt service routines (ISRs). The ISR vectors are listed in a vector table, stored in the NVIC at a base address. The vector address of an ISR to execute is hardware-built from the vector table base address and the ISR order number used as offset.

If a higher-priority interrupt event happens while a lower-priority interrupt event occurring just before is waiting for being served, the later-arriving higher-priority interrupt event is served first. Another optimization is called tail-chaining. Upon a return from a higher-priority ISR then start of a pending lower-priority ISR, the unnecessary processor context unstacking and stacking is skipped. This reduces latency and contributes to power efficiency.

Features of the NVIC:

• Low-latency interrupt processing

• 4 priority levels

• Handling of a non-maskable interrupt (NMI)

• Handling of 32 maskable interrupt lines

• Handling of 10 Cortex-M0+ exceptions

• Later-arriving higher-priority interrupt processed first

• Tail-chaining

• Interrupt vector retrieval by hardware

3.13.2 Extended interrupt/event controller (EXTI)

The extended interrupt/event controller adds flexibility in handling physical line events and allows identifying wake-up events at processor wakeup from Stop mode.

The EXTI controller has a number of channels, of which some with rising, falling or rising, and falling edge detector capability. Any GPIO and a few peripheral signals can be connected to these channels.

The channels can be independently masked.

The EXTI controller can capture pulses shorter than the internal clock period.

24/159 DS13560 Rev 1

STM32G0B1xB/C/xE Functional overview

A register in the EXTI controller latches every event even in Stop mode, which allows the software to identify the origin of the processor's wake-up from Stop mode or, to identify the GPIO and the edge event having caused an interrupt.

3.14 Analog-to-digital converter (ADC)

A native 12-bit analog-to-digital converter is embedded into STM32G0B1xB/C/xE devices. It can be extended to 16-bit resolution through hardware oversampling. The ADC has up to 16 external channels and 3 internal channels (temperature sensor, voltage reference, V monitoring). It performs conversions in single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs.

The ADC frequency is independent from the CPU frequency, allowing maximum sampling rate of ~2 MSps even with a low CPU speed. An auto-shutdown function guarantees that the ADC is powered off except during the active conversion phase.

BAT

The ADC can be served by the DMA controller. It can operate in the whole V range.

The ADC features a hardware oversampler up to 256 samples, improving the resolution to 16 bits (refer to AN2668).

An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all scanned channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

The events generated by the general-purpose timers (TIMx) can be internally connected to the ADC start triggers, to allow the application to synchronize A/D conversions with timers.

3.14.1 Temperature sensor

The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature.

The temperature sensor is internally connected to an ADC input to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor may vary from part to part due to process variation, the uncalibrated internal temperature sensor is suitable only for relative temperature measurements.

To improve the accuracy of the temperature sensor, each part is individually factorycalibrated by ST. The resulting calibration data are stored in the part’s engineering bytes, accessible in read-only mode.

Table 5. Temperature sensor calibration values

supply

Calibration value name Description Memory address

TS ADC raw data acquired at a

TS_CAL1

TS_CAL2

temperature of 30 °C (± 5 °C), V

= V

DDA

TS ADC raw data acquired at a temperature of 130 °C (± 5 °C), V

= V

DDA

DS13560 Rev 1 25/159

= 3.0 V (± 10 mV)

REF+

= 3.0 V (± 10 mV)

REF+

0x1FFF 75A8 - 0x1FFF 75A9

0x1FFF 75CA - 0x1FFF 75CB

Functional overview STM32G0B1xB/C/xE

3.14.2 Internal voltage reference (V

The internal voltage reference (V ADC and comparators. V

REFINT

is internally connected to an ADC input. The V

REFINT

)

) provides a stable (bandgap) voltage output for the

voltage is individually precisely measured for each part by ST during production test and stored in the part’s engineering bytes. It is accessible in read-only mode.

3.14.3 V

Calibration value name Description Memory address

battery voltage monitoring

BAT

Table 6. Internal voltage reference calibration values

Raw data acquired at a

REFINT

temperature of 30 °C (± 5 °C), V

DDA

= V

= 3.0 V (± 10 mV)

REF+

This embedded hardware feature allows the application to measure the V using an internal ADC input. As the V

voltage may be higher than V

BAT

the ADC input range, the VBAT pin is internally connected to a bridge divider by three. As a consequence, the converted digital value is one third the V

3.15 Digital-to-analog converter (DAC)

REFINT

0x1FFF 75AA - 0x1FFF 75AB

battery voltage

BAT

and thus outside

DDA

voltage.

BAT

The 2-channel 12-bit buffered DAC converts a digital value into an analog voltage available on the channel output. The architecture of either channel is based on integrated resistor string and an inverting amplifier. The digital circuitry is common for both channels.

Features of the DAC:

• Two DAC output channels

• 8-bit or 12-bit output mode

• Buffer offset calibration (factory and user trimming)

• Left or right data alignment in 12-bit mode

• Synchronized update capability

• Noise-wave generation

• Triangular-wave generation

• Independent or simultaneous conversion for DAC channels

• DMA capability for either DAC channel

• Triggering with timer events, synchronized with DMA

• Triggering with external events

• Sample-and-hold low-power mode, with internal or external capacitor

26/159 DS13560 Rev 1

STM32G0B1xB/C/xE Functional overview

3.16 Voltage reference buffer (VREFBUF)

When enabled, an embedded buffer provides the internal reference voltage to analog blocks (for example ADC) and to VREF+ pin for external components.

The internal voltage reference buffer supports two voltages:

• 2.048 V

• 2.5 V

An external voltage reference can be provided through the VREF+ pin when the internal voltage reference buffer is disabled.

On some packages, the VREF+ pad of the silicon die is double-bonded with supply pad to common VDD/VDDA pin and so the internal voltage reference buffer cannot be used.

3.17 Comparators (COMP)

Three embedded rail-to-rail analog comparators have programmable reference voltage (internal or external), hysteresis, speed (low for low-power) and output polarity.

The reference voltage can be one of the following:

• external, from an I/O

• internal, from DAC

• internal reference voltage (V

The comparators can wake up the device from Stop mode, generate interrupts, breaks or triggers for the timers and can be also combined into a window comparator.

) or its submultiple (1/4, 1/2, 3/4)

REFINT

3.18 Timers and watchdogs

The device includes an advanced-control timer, seven general-purpose timers, two basic timers, two low-power timers, two watchdog timers and a SysTick timer. Table 7 compares features of the advanced-control, general-purpose and basic timers.

Timer type Timer

Advanced-

control

TIM1 16-bit

Counter

resolution

Table 7. Timer feature comparison

Counter

type

Up, down,

up/down

Maximum operating

frequency

128 MHz

Prescaler

factor

Integer from

1 to 2

DMA

request

generation

Yes 4 3

Capture/ compare

channels

Complementary

outputs

DS13560 Rev 1 27/159

Functional overview STM32G0B1xB/C/xE

Table 7. Timer feature comparison (continued)

Maximum operating

frequency

64 MHz

Timer type Timer

TIM2 32-bit

TIM3 16-bit

General-

purpose

Basic

Low-power

TIM4 16-bit

TIM14 16-bit Up 64 MHz

TIM15 16-bit Up 128 MHz

TIM16 TIM17

TIM6 TIM7

LPTIM1 LPTIM2

Counter

resolution

16-bit Up 64 MHz

Counter

type

Up, down,

up/down

Up, down,

up/down

Up, down,

up/down

3.18.1 Advanced-control timer (TIM1)

Prescaler

factor

Integer from

1 to 2

2n where

n=0 to 7

DMA

request

generation

Yes 4 -

No 1 -

Yes 2 1

Yes 1 1

Yes - -

No N/A -

Capture/ compare

channels

Complementary

outputs

The advanced-control timer can be seen as a three-phase PWM unit multiplexed on 6 channels. It has complementary PWM outputs with programmable inserted dead-times. It can also be seen as a complete general-purpose timer. The four independent channels can be used for:

• input capture

• output compare

• PWM output (edge or center-aligned modes) with full modulation capability (0-100%)

• one-pulse mode output

In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled, so as to turn off any power switches driven by these outputs.

Many features are shared with those of the general-purpose TIMx timers (described in

Section 3.18.2) using the same architecture, so the advanced-control timers can work

together with the TIMx timers via the Timer Link feature for synchronization or event chaining.

28/159 DS13560 Rev 1

STM32G0B1xB/C/xE Functional overview

3.18.2 General-purpose timers (TIM2, 3, 4, 14, 15, 16, 17)

There are seven synchronizable general-purpose timers embedded in the device (refer to

Tab l e 7 for comparison). Each general-purpose timer can be used to generate PWM outputs

or act as a simple timebase.

• TIM2, TIM3, and TIM4

These are full-featured general-purpose timers:

– TIM2 with 32-bit auto-reload up/downcounter and 16-bit prescaler

– TIM3 and TIM4 with 16-bit auto-reload up/downcounter and 16-bit prescaler

They have four independent channels for input capture/output compare, PWM or onepulse mode output. They can operate in combination with other general-purpose timers via the Timer Link feature for synchronization or event chaining. They can generate independent DMA request and support quadrature encoders. Their counter can be frozen in debug mode.

• TIM14

This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. It has one channel for input capture/output compare, PWM output or one-pulse mode output. Its counter can be frozen in debug mode.

• TIM15, TIM16, TIM17

These are general-purpose timers featuring:

– 16-bit auto-reload upcounter and 16-bit prescaler

– 2 channels and 1 complementary channel for TIM15

– 1 channel and 1 complementary channel for TIM16 and TIM17

All channels can be used for input capture/output compare, PWM or one-pulse mode output. The timers can operate together via the Timer Link feature for synchronization or event chaining. They can generate independent DMA request. Their counters can be frozen in debug mode.

3.18.3 Basic timers (TIM6 and TIM7)

These timers are mainly used for triggering DAC conversions. They can also be used as generic 16-bit timebases.

3.18.4 Low-power timers (LPTIM1 and LPTIM2)

These timers have an independent clock. When fed with LSE, LSI or external clock, they keep running in Stop mode and they can wake up the system from it.

DS13560 Rev 1 29/159

Functional overview STM32G0B1xB/C/xE

Features of LPTIM1 and LPTIM2:

• 16-bit up counter with 16-bit autoreload register

• 16-bit compare register

• Configurable output (pulse, PWM)

• Continuous/one-shot mode

• Selectable software/hardware input trigger

• Selectable clock source:

– Internal: LSE, LSI, HSI16 or APB clocks

– External: over LPTIM input (working even with no internal clock source running,

used by pulse counter application)

• Programmable digital glitch filter

• Encoder mode

3.18.5 Independent watchdog (IWDG)

The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with user-defined refresh window. It is clocked from an independent 32 kHz internal RC (LSI). Independent of the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. Its counter can be frozen in debug mode.

3.18.6 System window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked by the system clock. It has an early-warning interrupt capability. Its counter can be frozen in debug mode.

3.18.7 SysTick timer

This timer is dedicated to real-time operating systems, but it can also be used as a standard down counter.

Features of SysTick timer:

• 24-bit down counter

• Autoreload capability

• Maskable system interrupt generation when the counter reaches 0

• Programmable clock source

3.19 Real-time clock (RTC), tamper (TAMP) and backup registers

The device embeds an RTC and five 32-bit backup registers, located in the RTC domain of the silicon die.

The ways of powering the RTC domain are described in Section 3.7.6.

The RTC is an independent BCD timer/counter.

30/159 DS13560 Rev 1

STM32G0B1xB/C/xE Functional overview

Features of the RTC:

• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,

month, year, in BCD (binary-coded decimal) format

• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month

• Programmable alarm

• On-the-fly correction from 1 to 32767 RTC clock pulses, usable for synchronization with

a master clock

• Reference clock detection - a more precise second-source clock (50 or 60 Hz) can be

used to improve the calendar precision

• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal

inaccuracy

• Two anti-tamper detection pins with programmable filter

• Timestamp feature to save a calendar snapshot, triggered by an event on the

timestamp pin or a tamper event, or by switching to VBAT mode

• 17-bit auto-reload wakeup timer (WUT) for periodic events, with programmable

resolution and period

• Multiple clock sources and references:

– A 32.768 kHz external crystal (LSE)

– An external resonator or oscillator (LSE)

– The internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)

– The high-speed external clock (HSE) divided by 32

When clocked by LSE, the RTC operates in VBAT mode and in all low-power modes. When clocked by LSI, the RTC does not operate in VBAT mode, but it does in low-power modes except for the Shutdown mode.

All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt and wake the device up from the low-power modes.

The backup registers allow keeping 20 bytes of user application data in the event of V failure, if a valid backup supply voltage is provided on VBAT pin. They are not affected by the system reset, power reset, and upon the device’s wakeup from Standby or Shutdown modes.

3.20 Inter-integrated circuit interface (I2C)

The device embeds three I2C peripherals. Refer to Tab le 8 for the features.

The I

C-bus interface handles communication between the microcontroller and the serial

C-bus. It controls all I2C-bus-specific sequencing, protocol, arbitration and timing.

DS13560 Rev 1 31/159

Functional overview STM32G0B1xB/C/xE

Features of the I2C peripheral:

• I

C-bus specification and user manual rev. 5 compatibility:

– Slave and master modes, multimaster capability

– Standard-mode (Sm), with a bitrate up to 100 kbit/s

– Fast-mode (Fm), with a bitrate up to 400 kbit/s

– Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and extra output drive I/Os

– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses

– Programmable setup and hold times

– Clock stretching

• SMBus specification rev 3.0 compatibility:

– Hardware PEC (packet error checking) generation and verification with ACK

control

– Command and data acknowledge control

– Address resolution protocol (ARP) support

– Host and Device support

– SMBus alert

– Timeouts and idle condition detection

• PMBus rev 1.3 standard compatibility

• Independent clock: a choice of independent clock sources allowing the I2C

communication speed to be independent of the PCLK reprogramming

• Wakeup from Stop mode on address match

• Programmable analog and digital noise filters

• 1-byte buffer with DMA capability

Table 8. I

C implementation

I2C features

Standard mode (up to 100 kbit/s) X X

Fast mode (up to 400 kbit/s) X X

Fast Mode Plus (up to 1 Mbit/s) with extra output drive I/Os X X

Programmable analog and digital noise filters X X

SMBus/PMBus hardware support X -

Independent clock X -

Wakeup from Stop mode on address match X -

1. X: supported

(1)

I2C1 I2C2

I2C3

3.21 Universal synchronous/asynchronous receiver transmitter (USART)

The device embeds universal synchronous/asynchronous receivers/transmitters that communicate at speeds of up to 8 Mbit/s.

32/159 DS13560 Rev 1

STM32G0B1xB/C/xE Functional overview

They provide hardware management of the CTS, RTS and RS485 DE signals, multiprocessor communication mode, master synchronous communication and single-wire half-duplex communication mode. Some can also support SmartCard communication (ISO

7816), IrDA SIR ENDEC, LIN Master/Slave capability and auto baud rate feature, and have a clock domain independent of the CPU clock, which allows them to wake up the MCU from Stop mode. The wakeup events from Stop mode are programmable and can be:

• start bit detection

• any received data frame

• a specific programmed data frame

All USART interfaces can be served by the DMA controller.

Table 9. USART implementation

USART modes/features

Hardware flow control for modem X X

Continuous communication using DMA X X

Multiprocessor communication X X

Synchronous mode X X

Smartcard mode X -

Single-wire half-duplex communication X X

IrDA SIR ENDEC block X -

LIN mode X -

Dual clock domain and wakeup from Stop mode X -

Receiver timeout interrupt X -

Modbus communication X -

Auto baud rate detection X -

Driver Enable X X

1. X: supported

(1)

USART1 USART2 USART3

USART4 USART5 USART6

3.22 Low-power universal asynchronous receiver transmitter (LPUART)

The device embeds two LPUARTs. The peripheral supports asynchronous serial communication with minimum power consumption. It supports half duplex single wire communication and modem operations (CTS/RTS). It allows multiprocessor communication.

The LPUART has a clock domain independent of the CPU clock, and can wakeup the system from Stop mode. The Stop mode wakeup events are programmable and can be:

• start bit detection

• any received data frame

• a specific programmed data frame

DS13560 Rev 1 33/159

Functional overview STM32G0B1xB/C/xE

Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while having an extremely low energy consumption. Higher speed clock can be used to reach higher baudrates.

The LPUART interface can be served by the DMA controller.

3.23 Serial peripheral interface (SPI)

The device contains three SPIs running at up to 32 Mbits/s in master and slave modes. It supports half-duplex, full-duplex and simplex communications. A 3-bit prescaler gives eight master mode frequencies. The frame size is configurable from 4 bits to 16 bits. The SPI peripherals support NSS pulse mode, TI mode and hardware CRC calculation.

The SPI peripherals can be served by the DMA controller.

The I

S interface mode of the SPI peripheral (if supported, see the following table) supports four different audio standards can operate as master or slave, in half-duplex communication mode. It can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data resolution and synchronized by a specific signal. Audio sampling frequency from 8 kHz up to 192 kHz can be set by an 8-bit programmable linear prescaler. When operating in master mode, it can output a clock for an external audio component at 256 times the sampling frequency.

Table 10. SPI/I2S implementation

SPI features

Hardware CRC calculation X X

Rx/Tx FIFO X X

NSS pulse mode X X

S mode X -

TI mode X X

1. X = supported.

(1)

SPI1 SPI2

3.24 Universal serial bus device (USB) and host (USBH)

The devices embed a USB controller with full-speed USB device and host functionality compliant with the USB specification version 2.0. The internal USB PHY supports USB FS signaling, embedded DP pull-up and also battery charging detection according to Battery Charging Specification Revision 1.2. The USB interface implements a full-speed (12 Mbit/s) function interface with added support for USB 2.0 Link Power Management. It has softwareconfigurable endpoint setting with packet memory up to 1 KB and suspend/resume support. It requires a precise 48 MHz clock that is generated from the internal main PLL (the clock source must use a HSE crystal oscillator) or by the internal 48 MHz oscillator in automatic trimming mode. The synchronization for this oscillator can be taken from the USB data stream itself (SOF signalization) which allows crystal less operation.

SPI3

34/159 DS13560 Rev 1

STM32G0B1xB/C/xE Functional overview

3.25 USB Type-C™ Power Delivery controller

The device embeds two controllers (UCPD1 and UCPD2) compliant with USB Type-C Rev.

1.2 and USB Power Delivery Rev. 3.0 specifications.

The controllers use specific I/Os supporting the USB Type-C and USB Power Delivery requirements, featuring:

• USB Type-C pull-up (Rp, all values) and pull-down (Rd) resistors

• “Dead battery” support

• USB Power Delivery message transmission and reception

• FRS (fast role swap) support

The digital controller handles notably:

• USB Type-C level detection with de-bounce, generating interrupts

• FRS detection, generating an interrupt

• byte-level interface for USB Power Delivery payload, generating interrupts (DMA

compatible)

• USB Power Delivery timing dividers (including a clock pre-scaler)

• CRC generation/checking

• 4b5b encode/decode

• ordered sets (with a programmable ordered set mask at receive)

• frequency recovery in receiver during preamble

The interface offers low-power operation compatible with Stop mode, maintaining the capacity to detect incoming USB Power Delivery messages and FRS signaling.

3.26 Controller area network (FDCAN)

The controller area network (CAN) subsystem consists of two CAN modules and a message RAM.

The CAN modules are compliant with ISO 11898-1 (CAN protocol specification version 2.0 part A, B) and CAN FD protocol specification version 1.0.

The 1-Kbyte message RAM per CAN module implements filters, receive FIFOs, receive buffers, transmit event FIFOs, and transmit buffers.

3.27 Development support

3.27.1 Serial wire debug port (SW-DP)

An Arm SW-DP interface is provided to allow a serial wire debugging tool to be connected to the MCU.

DS13560 Rev 1 35/159

Pinouts, pin description and alternate functions STM32G0B1xB/C/xE

Top view

LQFP100

787679

878685

384037

293031

919089

464845

444943

969594

100

VDDIO2 VSS

PF8

PA13

PA12 [PA10] PA11 [PA9] PA10

PA15

PD9 PD8 PC7 PC6

PD15 PD14 PD13 PD12

PB15 PB14 PB13 PB12

PA3

PA4

PA5

PA6

PA7

PC4

PC5

PB0

PB1

PE7

PE8

PE9

PE10

PE11

PE12

PE13

PE14

PE15

PB10

PB11

PB9 PC10 PC11

PE4

PE5

VBAT

PC14-OSC32_IN

PC15-OSC32_OUT

PA8

PF9

PF0-OSC_IN

PF2-NRST

PF3

PF4

PF5

PC0

PC2

VSS/VSSA

PC1

VDD/VDDA

PA0

PA1

PA2

PC13

PF1-OSC_OUT

PB8

PB7

PE3

PE2

PE1

PE0

PB5

PB4

PB3

PD7

PD6

PD5

PD4

PD3

PD2

PD0

PC12

PE6

PC8

VREF+

PC3

PB2

PF6

PF7

PA9

PD11 PD10

PA14-BOOT0

PC9

PD1

PF10

PF11

PB6

PF12

PF13

4 Pinouts, pin description and alternate functions

The devices housed in 32-pin, 48-pin, and 64-pin packages come in two variants - “GP” and “N” (the latter with ordering code having N behind the temperature range digit). Refer to

Table 2: Features and peripheral counts for differences.

Figure 3. STM32G0B1VxT LQFP100 pinout

36/159 DS13560 Rev 1

1. The I/O pins supplied by V

are shown in gray.

DDIO2

STM32G0B1xB/C/xE Pinouts, pin description and alternate functions

PC14-

OSC32

_IN

PC12

PE5

PC15-

OSC32

_OUT

VBAT

PC13

VDD VREF+

VSS

PF2-

NRST

PF0-

OSC_I

PF4 PF3

PB8 PE3 PE2 PE0 PB3

PC11 PC10

PB7

PE1 PB4

PE6 PE4

PB9

PB6 PB5

PF13 PF11 PF9

PF12

PF10 PD7

PD3

12345678

PF1-

OSC_

OUT

PF5 PC1

PF8

PA10

PA9

PD6 PD5

PD4 PD0

PD1 PC8

PB15

910

PC0 PC2 PA0 PA3

PA1 PA4 PC4

PA7

PB0 PB2

PE9

PF7 PE10

PE14 PB12

PE12 PE15

PC3

PA2 PA5 PA 6 PC5

PB1 PF6 PE7 PE8 PE11 PE13

PD15

PD14

PD12

PD11

PD9

PD2

PA15

PA13

PC6

PA11 [PA9]

PD13

VDDIO

VSS

PD10

PC9

PA14-

BOOT0

PA12

[PA10]

PD8

PB14

PB11

PC7

PA8

PB10 PB13

11 12

Top view

Figure 4. STM32G0B1VxI UFBGA100 pinout

1. The I/O pads supplied by V

are shown in gray.

DDIO2

DS13560 Rev 1 37/159

Pinouts, pin description and alternate functions STM32G0B1xB/C/xE

Top view

LQFP80

787679

676665

384037

293031

717069

252224

737574

VDDIO2

VSS

PA13

PA12 [PA10]

PA11 [PA9]

PA10

PD9

PD8

PC7

PC6

PD15

PD14

PD13

PD12

PB15

PA3

PA4

PA5

PA6

PA7

PC4

PC5

PB0

PB1

PE7

PE8

PE9

PE10

PB10

PB11

PB9

PC10

PC11

VBAT

PC14-OSC32_IN

PA8

PF0-OSC_IN

PF2-NRST

PC0

PC2

VSS

PC1

VDD

PA0

PA2

PC13

PF1-OSC_OUT

PB8

PB7

PE3

PE1

PE0

PB5

PB4

PB3

PD7

PD6

PD5

PD4

PD3

PD2

PD0

PC12

PC8

VREF+

PC3

PB2

PA9

PD11

PD10

PA14-BOOT0

PC9

PD1

PB6

PC15-OSC32_OUT

PA1

PB12

PB13

PB14

PA15

Figure 5. STM32G0B1MxT LQFP80 pinout

1. The I/O pins supplied by V

38/159 DS13560 Rev 1

are shown in gray.

DDIO2

STM32G0B1xB/C/xE Pinouts, pin description and alternate functions

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

PC4

PC5

PB0

PB1

PB2

PB10

PB11

PB12

PC11

PC12

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

VBAT

VREF+

VDD/VDDA

VSS/VSSA

PF2-NRST

PF0-OSC_IN

PF1-OSC_OUT

PC0

PC1

PC2

PC3

PC8

PA15

PA14-BOOT0

PA1 3

PA12 [PA10]

PA11 [PA9]

PA10

VDDIO2

VSS

PC7

PC6

PA9

PA8

PB15

PB14

PB13

PC9

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PB3

PB4

PB5

PB6

PB7

PB8

PB9

PC10

Top view

LQFP64

5352515049

646362

2829303132

171819

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

PC4

PC5

PB0

PB1

PB2

PB10

PB11

PB12

PC11

PC12

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

VBAT

VREF+

VDD/VDDA

VSS/VSSA

PF2-NRST

PF0-OSC_IN

PF1-OSC_OUT

PC0

PC1

PC2

PC3

PC8

PA15

PA14-BOOT0

PA13

PA12 [PA10]

PA11 [PA9]

PA10

PD9

PD8

PC7

PC6

PA9

PA8

PB15

PB14

PB13

PC9

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PB3

PB4

PB5

PB6

PB7

PB8

PB9

PC10

Top view

LQFP64

5352515049

646362

2829303132

171819

GP version

N version

(_RxTxN)

(_RxT)

Figure 6. STM32G0B1RxT LQFP64 pinout

1. The I/O pins supplied by V

DDIO2

are shown in gray.

DS13560 Rev 1 39/159

Pinouts, pin description and alternate functions STM32G0B1xB/C/xE

VDD/

VDDA

VREF+

VBAT

PB5 PD3

VSS/

VSSA

PF2-

NRST

PC0

PA7 PC7

PF0-

OSC_I

PC1

PA3

PA6 PB0

PF1-

OSC_

OUT

PC2

PA2

PA5 PB1

PC3 PA 0 PA1 PA 4 PC4

PC11 PC10 PB7 PB6 PD6

PC15-

OSC32

_OUT

PC12

PB8

PB3 PD5

PC14-

OSC32

_IN

PC13

PB9

PB4 PD4

PA10

PA13

VDDIO

PA9

PC6 VSS

PB14

PB15 PA 8

PB10

PB12 PB13

PC5 PB2 PB11

PD2 PD0 PC8

PD1

PC9

PA12

[PA10]

PA15

PA14-

BOOT0

PA11 [PA9]

12345678

Top view

N version

(_RxIxN)

Figure 7. STM32G0B1RxI UFBGA64 pinout

1. The I/O pads supplied by V

are shown in gray.

DDIO2

40/159 DS13560 Rev 1

STM32G0B1xB/C/xE Pinouts, pin description and alternate functions

Top view

12345678

910111213

VDDIO

PC7 PC6

VSS PA9

PA8 PB15 PB11

PB14 PB2

PB13 PB10 PB1

PA15 PD0

PA12

[PA10]

PA13

PA14-

BOOT0

PA11 [PA9]

PA10

PB7

PB12 PA 2

PA6

PC5 PC4

PB0

PD3 PB3

PD2

PD1 PB6

PB9

PA1

PA5

PA4

PA7

PB5

PB4

VBAT

VREF+

PF2-

NRST

PA3

PC13

VDD/

VDDA

VSS/

VSSA

PF0-

OSC_IN

PF1-

OSC_

OUT

PA0

PB8

PC14-

OSC32

_IN

PC15-

OSC32

_OUT

Figure 8. STM32G0B1NxY WLCSP52 pinout

1. The I/O pads supplied by V

are shown in gray.

DDIO2

DS13560 Rev 1 41/159

Pinouts, pin description and alternate functions STM32G0B1xB/C/xE

PA2

PA3

PA4

PA5

PA6

PA7

PB0

PB1

PB2

PB10

PB11

PB12

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

VBAT

VREF+

VDD/VDDA

VSS/VSSA

PF2-NRST

PF0-OSC_IN

PF1-OSC_OUT

PA0 PA1

PA14-BOOT0 PA13 PA12 [PA10] PA11 [ PA9] PA10 VDDIO2 VSS PA9 PA8 PB15 PB14 PB13

PA15

PD0

PD1

PD2

PD3

PB3

PB4

PB5

PB6

PB7

PB8

PB9

Top view

LQFP48

393740

484746

222421

131415

N version

(_RxTxN)

PA2

PA3

PA4

PA5

PA6

PA7

PB0

PB1

PB2

PB10

PB11

PB12

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

VBAT

VREF+

VDD/VDDA

VSS/VSSA

PF2-NRST

PF0-OSC_IN

PF1-OSC_OUT

PA0 PA1

PA14-BOOT0 PA13 PA12 [PA10] PA11 [PA9] PA10 PC7 PC6 PA9 PA8 PB15 PB14 PB13

PA15

PD0

PD1

PD2

PD3

PB3

PB4

PB5

PB6

PB7

PB8

PB9

Top view

LQFP48

393740

484746

222421

131415

GP version

(_RxT)

Figure 9. STM32G0B1CxT LQFP48 pinout

1. The I/O pins supplied by V

42/159 DS13560 Rev 1

are shown in gray.

DDIO2

STM32G0B1xB/C/xE Pinouts, pin description and alternate functions

Exposed pad

Top view

393740

484746

222421

131415

VSS

PA2

PA3

PA4

PA5

PA6

PA7

PB0

PB1

PB2

PB10

PB11

PB12

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

VBAT

VREF+

VDD/VDDA

VSS/VSSA

PF2-NRST

PF0-OSC_IN

PF1-OSC_OUT

PA0 PA1

PA14-BOOT0 PA13 PA12 [PA10] PA11 [ PA9] PA10 VDDIO2 VSS PA9 PA8 PB15 PB14 PB13

PA15

PD0

PD1

PD2

PD3

PB3

PB4

PB5

PB6

PB7

PB8

PB9

Exp

891

363534

3029282726

UFQFPN48

N version

(_CxTxN)

Exposed pad

Top view

Exp

UFQFPN48

393740

484746

222421

131415

VSS

PA2

PA3

PA4

PA5

PA6

PA7

PB0

PB1

PB2

PB10

PB11

PB12

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

VBAT

VREF+

VDD/VDDA

VSS/VSSA

PF2-NRST

PF0-OSC_IN

PF1-OSC_OUT

PA0 PA1

PA14-BOOT0 PA13 PA12 [PA10] PA11 [ PA9] PA10 PC7 PC6 PA9 PA8 PB15 PB14 PB13

PA15

PD0

PD1

PD2

PD3

PB3

PB4

PB5

PB6

PB7

PB8

PB9

GP version

(_CxT)

Figure 10. STM32G0B1CxU UFQFPN48 pinout

osed pa

1. The I/O leads supplied by V

osed pa

are shown in dark gray.

DDIO2

DS13560 Rev 1 43/159

Pinouts, pin description and alternate functions STM32G0B1xB/C/xE

PA2

PA3

PA4

PA5

PA6

PA7

PB0

PB1

PB9

PC14-OSC32_IN

PC15-OSC32_OUT

VDD/VDDA

VSS/VSSA

PF2-NRST

PA0

PA1

PA13

PA12 [PA10]

PA11 [PA9]

PA10

VDDIO2

PA9

PA8

PB15

PA14-BOOT0

PD0

PD1

PD2

PD3

PB6

PB7

PB8

Top view

LQFP32

323130

MSv39712V3

PA2

PA3

PA4

PA5

PA6

PA7

PB0

PB1

PB9

PC14-OSC32_IN

PC15-OSC32_OUT

VDD/VDDA

VSS/VSSA

PF2-NRST

PA0

PA1

PA13

PA12 [PA10]

PA11 [PA9]

PA10

PC6

PA9

PA8

PB2

PA14-BOOT0

PA15

PB3

PB4

PB5

PB6

PB7

PB8

Top view

LQFP32

323130

GP version

N version

(_KxTxN)

(_KxT)

Figure 11. STM32G0B1KxT LQFP32 pinout

1. The I/O pins supplied by V

are shown in dark gray.

DDIO2

44/159 DS13560 Rev 1

STM32G0B1xB/C/xE Pinouts, pin description and alternate functions

Exposed pad

PA2

PA3

PA4

PA5

PA6

PA7

PB0

PB1

PB9

PC14-OSC32_IN

PC15-OSC32_OUT

VDD/VDDA

VSS/VSSA PF2-NRST

PA0 PA1

PA13 PA12 [PA10] PA11 [PA9] PA10 VDDIO2 PA9 PA8 PB15

PA14-BOOT0

PD0

PD1

PD2

PD3

PB6

PB7

PB8

Top view

Exp

UFQFPN32

323130

VSS

MSv39715V3

PA2

PA3

PA4

PA5

PA6

PA7

PB0

PB1

PB9

PC14-OSC32_IN

PC15-OSC32_OUT

VDD/VDDA

VSS/VSSA PF2-NRST

PA0 PA1

PA13 PA12 [PA10] PA11 [PA9] PA10 PC6 PA9 PA8 PB2

PA14-BOOT0

PA15

PB3

PB4

PB5

PB6

PB7

PB8

Top view

UFQFPN32

323130

VSS

GP version

(_KxU)

N version

(_KxUxN)

Figure 12. STM32G0B1KxU UFQFPN32 pinout

1. The I/O leads supplied by V

are shown in dark gray.

DDIO2

DS13560 Rev 1 45/159

osed pa

Pinouts, pin description and alternate functions STM32G0B1xB/C/xE

Table 11. Terms and symbols used in Table 12

Column Symbol Definition

Pin name

Terminal name corresponds to its by-default function at reset, unless otherwise specified in parenthesis under the pin name.

S Supply pin

Pin type

I Input only pin

I/O Input / output pin

FT 5 V tolerant I/O

TT 3.6 V tolerant I/O

RST Bidirectional reset pin with embedded weak pull-up resistor

I/O structure

Options for TT or FT I/Os

_f I/O, Fm+ capable

_a I/O, with analog switch function

_c I/O, USB Type-C PD capable

_e I/O, with switchable diode to V

_d I/O, USB Type-C PD Dead Battery function

Note Upon reset, all I/Os are set as analog inputs, unless otherwise specified.

functions

Alternate functions

Additional

functions

Functions selected through GPIOx_AFR registers

Functions directly selected/enabled through peripheral registers

46/159 DS13560 Rev 1

47/159 DS13560 Rev 1

Pin number

WLCSP52

LQFP64 - GP

Pinouts, pin description and alternate functions STM32G0B1xB/C/xE

Table 12. Pin assignment and description

Pin name

Alternate

(function

upon reset)

LQFP100

LQFP64 - N

UFBGA80

UFBGA64 - N

UFBGA100

Pin type

Note

I/O structure

functions

Additional

functions

LQFP32 / UFQFPN32 - N

LQFP32 / UFQFPN32 - GP

- - - - - 64 64 A2 2 2 B2 PC10 I/O FT - USART3_TX, USART4_TX, TIM1_CH3, SPI3_SCK -

- - - - - 1 1 A1 3 3 B1 PC11 I/O FT - USART3_RX, USART4_RX, TIM1_CH4, SPI3_MISO -

---- - --- - 4C2 PE4 I/OFT - TIM3_CH2 -

---- - --- - 5D3 PE5 I/OFT - TIM3_CH3 -

- - - - - - - - - 6 C1 PE6 I/O FT - TIM3_CH4 TAMP_IN3, WKUP3

---- - 22B247D2 PC12 I/OFT -

- - 1 1 B11 3 3 C2 5 8 E3 PC13 I/O FT

--22B1344C16 9D1

22------- - -

3333C1255B1710E1

- - 4 4 C10 6 6 D3 8 11 E2 VBAT S - - - -

- - 5 5 D11 7 7 D2 9 12 F2 VREF+ S - - - VREFBUF_OUT

4 4 6 6 D13 8 8 D1 10 13 F1 VDD/VDDA S - - -

5 5 7 7 E12 9 9 E1 11 14 G1 VSS/VSSA S - - -

LQFP48 / UFQFPN48 - N

LQFP48 / UFQFPN48 - GP

PC14-

OSC32_IN

(PC14)

PC14-

OSC32_IN

(PC14)

PC15-

OSC32_OUT

(PC15)

I/O FT

(1)(2)

LPTIM1_IN1, UCPD1_FRSTX, TIM14_CH1,

USART5_TX, SPI3_MOSI

TIM1_BKIN

TIM1_BKIN2 OSC32_IN

TIM1_BKIN2 OSC32_IN, OSC_IN

OSC32_EN, OSC_EN, TIM15_BKIN OSC32_OUT

TAMP_IN1, RTC_TS, RTC_OUT1, WKUP2

Pin number

WLCSP52

LQFP64 - GP

LQFP64 - N

UFBGA64 - N

Table 12. Pin assignment and description (continued)

Pin name

LQFP100

UFBGA80

(function

upon reset)

UFBGA100

Pin type

Note

I/O structure

Alternate

functions

STM32G0B1xB/C/xE Pinouts, pin description and alternate functions

Additional

functions

DS13560 Rev 1 48/159

LQFP32 / UFQFPN32 - N

LQFP32 / UFQFPN32 - GP

--88F131010F11215H1

--99G121111G11316J1

6 6 10 10 F11 12 12 E2 14 17 G2 PF2-NRST I/O - MCO, LPUART2_TX, LPUART2_RTS_DE NRST

- - - - - - - - - 18 H3 PF3 I/O FT - LPUART2_RX, USART6_RTS_DE_CK -

---- - --- -19H2 PF4 I/OFT - LPUART1_TX -

---- - --- -20J2 PF5 I/OFT - LPUART1_RX -

---- -1313E31521K1 PC0 I/OFT -

---- -1414F21622J3 PC1 I/OFT -

---- -1515G21723K2 PC2 I/OFT -

---- -1616H11824L1 PC3 I/OFT -

7 7 11 11 H1 3 1 7 17 H 2 1 9 25 K 3 PA0 I/ O FT_a -

8 81212E101818H32026L2 PA1 I/OFT_a -

LQFP48 / UFQFPN48 - GP

LQFP48 / UFQFPN48 - N

PF0-OSC_IN

(PF0)

PF1-

OSC_OUT

(PF1)

I/O FT - CRS1_SYNC, EVENTOUT, TIM14_CH1 OSC_IN

I/O FT - OSC_EN, EVENTOUT, TIM15_CH1N OSC_OUT

LPTIM1_IN1, LPUART1_RX, LPTIM2_IN1,

LPUART2_TX, USART6_TX, I2C3_SCL,

COMP3_OUT

LPTIM1_OUT, LPUART1_TX, TIM15_CH1,

LPUART2_RX, USART6_RX, I2C3_SDA

LPTIM1_IN2, SPI2_MISO/I2S2_MCK, TIM15_CH2,

FDCAN2_RX, COMP3_OUT

LPTIM1_ETR, SPI2_MOSI/I2S2_SD, LPTIM2_ETR,

FDCAN2_TX

SPI2_SCK/I2S2_CK, USART2_CTS,

TIM2_CH1_ETR, USART4_TX, LPTIM1_OUT,

UCPD2_FRSTX, COMP1_OUT

SPI1_SCK/I2S1_CK, USART2_RTS_DE_CK,

TIM2_CH2, USART4_RX, TIM15_CH1N,

I2C1_SMBA, EVENTOUT

COMP3_INM7

COMP3_INP1

COMP1_INM8, ADC_IN0,

TAMP_IN2, WKUP1

COMP1_INP2, ADC_IN1

49/159 DS13560 Rev 1

Pin number

WLCSP52

LQFP64 - GP

LQFP64 - N

UFBGA64 - N

Table 12. Pin assignment and description (continued)

Pin name

LQFP100

UFBGA80

(function

upon reset)

UFBGA100

Pin type

Note

I/O structure

Alternate

functions

Pinouts, pin description and alternate functions STM32G0B1xB/C/xE

Additional

functions

LQFP32 / UFQFPN32 - N

LQFP32 / UFQFPN32 - GP

9 9 13 13 E8 19 19 G3 21 27 M1 PA2 I/O FT_a -

10 10 14 14 H11 20 20 F3 22 28 K4 PA3 I/O FT_a -

- -1515G102121H42329L3 PA4 I/OTT_a -

1111-------- - PA4 I/OTT_a-

12 12 16 16 F9 22 22 G4 24 30 M2 PA5 I/O TT_a -

13 13 17 17 F7 23 23 F4 25 31 M3 PA6 I/O FT_a -

14 14 18 18 H9 24 24 E4 26 32 K5 PA7 I/O FT_a -

- - - - G8 25 25 H5 27 33 L4 PC4 I/O FT_a -

LQFP48 / UFQFPN48 - GP

LQFP48 / UFQFPN48 - N

SPI1_MOSI/I2S1_SD, USART2_TX, TIM2_CH3,

UCPD1_FRSTX, TIM15_CH1, LPUART1_TX,

COMP2_OUT

SPI2_MISO/I2S2_MCK, USART2_RX, TIM2_CH4,

UCPD2_FRSTX, TIM15_CH2, LPUART1_RX,

EVENTOUT

SPI1_NSS/I2S1_WS, SPI2_MOSI/I2S2_SD,

USB_NOE, USART6_TX, TIM14_CH1,

LPTIM2_OUT, UCPD2_FRSTX, EVENTOUT,

SPI3_NSS

SPI1_NSS/I2S1_WS, SPI2_MOSI/I2S2_SD,

USB_NOE, USART6_TX, TIM14_CH1,

LPTIM2_OUT, UCPD2_FRSTX, EVENTOUT,

SPI3_NSS

SPI1_SCK/I2S1_CK, CEC, TIM2_CH1_ETR,

USART6_RX, USART3_TX, LPTIM2_ETR,

UCPD1_FRSTX, EVENTOUT

SPI1_MISO/I2S1_MCK, TIM3_CH1, TIM1_BKIN,

USART6_CTS, USART3_CTS, TIM16_CH1,

LPUART1_CTS, COMP1_OUT, I2C2_SDA,

I2C3_SDA

SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM1_CH1N,

USART6_RTS_DE_CK, TIM14_CH1, TIM17_CH1,

UCPD1_FRSTX, COMP2_OUT, I2C2_SCL,

I2C3_SCL

USART3_TX, USART1_TX, TIM2_CH1_ETR,

FDCAN1_RX

COMP2_INM8, ADC_IN2,

WKUP4, LSCO

COMP2_INP2, ADC_IN3

ADC_IN4, DAC1_OUT1,

RTC_OUT2

ADC_IN4, DAC1_OUT1,

TAMP_IN1, RTC_TS, RTC_OUT1, WKUP2

ADC_IN5, DAC1_OUT2

ADC_IN6

ADC_IN7

COMP1_INM7, ADC_IN17

Pin number

WLCSP52

LQFP64 - GP

LQFP64 - N

UFBGA64 - N

Table 12. Pin assignment and description (continued)

Pin name

LQFP100

UFBGA80

(function

upon reset)

UFBGA100

Pin type

Note

I/O structure

Alternate

functions

STM32G0B1xB/C/xE Pinouts, pin description and alternate functions

Additional

functions

DS13560 Rev 1 50/159

LQFP32 / UFQFPN32 - N

LQFP32 / UFQFPN32 - GP

- - - - G6 26 26 H6 28 34 M4 PC5 I/O FT_a -

15 15 19 19 H7 27 27 F5 29 35 L5 PB0 I/O FT_a -

16 16 20 20 H5 28 28 G5 30 36 M5 PB1 I/O FT_a -

17 - 2121G42929H731 37 L6 PB2 I/OFT_a -

---- - --- -38M6 PF6 I/OFT - LPUART1_RTS_DE -

---- - --- -39L7 PF7 I/OFT - LPUART1_CTS, USART5_CTS -

- - - - - - - - 32 40 M7 PE7 I/O FT - TIM1_ETR, USART5_RTS_DE_CK COMP3_INP2

- - - - - - - - 33 41 M8 PE8 I/O FT - USART4_TX, TIM1_CH1N COMP3_INM8

- - - - - - - - 34 42 K8 PE9 I/O FT - USART4_RX, TIM1_CH1 -

- - - - - - - - 35 43 L8 PE10 I/O FT - TIM1_CH2N, USART5_TX -

- - - - - - - - - 44 M9 PE11 I/O FT - TIM1_CH2, USART5_RX -

- - - - - - - - - 45 L9 PE12 I/O FT - SPI1_NSS/I2S1_WS, TIM1_CH3N -

- - - - - - - - - 46 M10 PE13 I/O FT - SPI1_SCK/I2S1_CK, TIM1_CH3 -

- - - - - - - - - 47 K9 PE14 I/O FT - SPI1_MISO/I2S1_MCK, TIM1_CH4, TIM1_BKIN2 -

- - - - - - - - - 48 L10 PE15 I/O FT - SPI1_MOSI/I2S1_SD, TIM1_BKIN -

LQFP48 / UFQFPN48 - GP

LQFP48 / UFQFPN48 - N

USART3_RX, USART1_RX, TIM2_CH2,

FDCAN1_TX

SPI1_NSS/I2S1_WS, TIM3_CH3, TIM1_CH2N,

FDCAN2_RX, USART3_RX, LPTIM1_OUT,

UCPD1_FRSTX, COMP1_OUT, USART5_TX,

LPUART2_CTS

TIM14_CH1, TIM3_CH4, TIM1_CH3N, FDCAN2_TX,

USART3_RTS_DE_CK, LPTIM2_IN1,

LPUART1_RTS_DE, COMP3_OUT, USART5_RX,

LPUART2_RTS_DE

SPI2_MISO/I2S2_MCK, MCO2, USART3_TX,

LPTIM1_OUT, EVENTOUT

COMP1_INP0, ADC_IN18,

WKUP5

COMP3_INP0, ADC_IN8

COMP1_INM6, ADC_IN9

COMP1_INP1,

COMP3_INM6, ADC_IN10

51/159 DS13560 Rev 1

Pin number

WLCSP52

LQFP64 - GP

LQFP64 - N

UFBGA64 - N

Table 12. Pin assignment and description (continued)

Pin name

LQFP100

UFBGA80

(function

upon reset)

UFBGA100

Pin type

Note

I/O structure

Alternate

functions

Pinouts, pin description and alternate functions STM32G0B1xB/C/xE

Additional

functions

LQFP32 / UFQFPN32 - N

LQFP32 / UFQFPN32 - GP

- - 22 22 H3 30 30 G6 36 49 M11 PB10 I/O FT_fa -

- - 23 23 F5 31 31 H8 37 50 L11 PB11 I/O FT_fa -

- - 24 24 E6 32 32 G7 38 51 K10 PB12 I/O FT_fa -

- - 25 25 H1 33 33 G8 39 52 M12 PB13 I/O FT_f -

- - 26 26 G2 34 34 F6 40 53 K11 PB14 I/O FT_f -

- 172727 F3 3535F7 41 54J10 PB15 I/OFT_f -

18 18 28 28 F1 36 36 F8 42 55 L12 PA8 I/O FT_f -

19 19 29 29 E4 37 37 E6 43 56 H10 PA9 I/O FT_fd -

20 - 30 - D5 38 38 E7 44 57 J11 PC6 I/O FT -

- - 31 - D3 39 39 E5 45 58 K12 PC7 I/O FT -

LQFP48 / UFQFPN48 - GP

LQFP48 / UFQFPN48 - N

CEC, LPUART1_RX, TIM2_CH3, USART3_TX, SPI2_SCK/I2S2_CK, I2C2_SCL, COMP1_OUT

SPI2_MOSI/I2S2_SD, LPUART1_TX, TIM2_CH4,

USART3_RX, I2C2_SDA, COMP2_OUT

SPI2_NSS/I2S2_WS, LPUART1_RTS_DE,

TIM1_BKIN, FDCAN2_RX, TIM15_BKIN,

UCPD2_FRSTX, EVENTOUT, I2C2_SMBA

SPI2_SCK/I2S2_CK, LPUART1_CTS, TIM1_CH1N,

FDCAN2_TX, USART3_CTS, TIM15_CH1N,

I2C2_SCL, EVENTOUT

SPI2_MISO/I2S2_MCK, UCPD1_FRSTX,

TIM1_CH2N, USART3_RTS_DE_CK, TIM15_CH1,

I2C2_SDA, EVENTOUT, USART6_RTS_DE_CK

SPI2_MOSI/I2S2_SD, TIM1_CH3N, TIM15_CH1N,

TIM15_CH2, EVENTOUT, USART6_CTS

MCO, SPI2_NSS/I2S2_WS, TIM1_CH1,

CRS1_SYNC, LPTIM2_OUT, EVENTOUT,

I2C2_SMBA

MCO, USART1_TX, TIM1_CH2,

SPI2_MISO/I2S2_MCK, TIM15_BKIN, I2C1_SCL,

EVENTOUT, I2C2_SCL

UCPD1_FRSTX, TIM3_CH1, TIM2_CH3,

LPUART2_TX

UCPD2_FRSTX, TIM3_CH2, TIM2_CH4,

LPUART2_RX

ADC_IN11

ADC_IN15

ADC_IN16

UCPD1_CC2, RTC_REFIN

UCPD1_CC1

UCPD1_DBCC1

Pin number

WLCSP52

LQFP64 - GP

LQFP64 - N

UFBGA64 - N

Table 12. Pin assignment and description (continued)

Pin name

LQFP100

UFBGA80

(function

upon reset)

UFBGA100

Pin type

Note

I/O structure

Alternate

functions

STM32G0B1xB/C/xE Pinouts, pin description and alternate functions

Additional

functions

DS13560 Rev 1 52/159

LQFP32 / UFQFPN32 - N

LQFP32 / UFQFPN32 - GP

- - - - - 40 - - 46 59 J12 PD8 I/O FT - USART3_TX, SPI1_SCK/I2S1_CK, LPTIM1_OUT -

- - - - - 41 - - 47 60 H11 PD9 I/O FT - USART3_RX, SPI1_NSS/I2S1_WS, TIM1_BKIN2 -

- - - - - - - - 48 61 H12 PD10 I/O FT - MCO -

- - - - - - - - 49 62 G11 PD11 I/O FT - USART3_CTS, LPTIM2_ETR -

- - - 30 E2 - 40 E8 50 63 G12 VSS S - - -

-20-31D1-41D85164F12 VDDIO2 S - - -

---- - ---5265F11 PD12 I/OFT -

- - - - - - - - 53 66 E12 PD13 I/O FT - LPTIM2_OUT, TIM4_CH2, FDCAN1_TX -

- - - - - - - - 54 67 E11 PD14 I/O FT - LPUART2_CTS, TIM4_CH3, FDCAN2_RX -

---- - ---5568D11 PD15 I/OFT -

21 21 32 32 C4 42 42 D6 56 69 E10 PA10 I/O FT_fd -

22 22 33 33 C2 43 43 C8 57 70 D12 PA11 [PA9]

23 23 34 34 B1 44 44 B8 58 71 C12 PA12 [PA10]

---- - --- -72D10 PF8 I/OFT - - -

LQFP48 / UFQFPN48 - GP

LQFP48 / UFQFPN48 - N

(3)

I/O FT_f -

(3)

I/O FT_f -

USART3_RTS_DE_CK, LPTIM2_IN1, TIM4_CH1,

FDCAN1_RX

CRS1_SYNC, LPUART2_RTS_DE, TIM4_CH4,

FDCAN2_TX

SPI2_MOSI/I2S2_SD, USART1_RX, TIM1_CH3,

MCO2, TIM17_BKIN, I2C1_SDA, EVENTOUT,

I2C2_SDA

SPI1_MISO/I2S1_MCK, USART1_CTS, TIM1_CH4,

FDCAN1_RX, TIM1_BKIN2, I2C2_SCL,

COMP1_OUT

SPI1_MOSI/I2S1_SD, USART1_RTS_DE_CK,

TIM1_ETR, FDCAN1_TX, I2S_CKIN, I2C2_SDA,

COMP2_OUT

UCPD1_DBCC2

USB_DM

USB_DP

53/159 DS13560 Rev 1

Pin number

WLCSP52

LQFP64 - GP

LQFP64 - N

UFBGA64 - N

Table 12. Pin assignment and description (continued)

Pin name

LQFP100

UFBGA80

(function

upon reset)

UFBGA100

Pin type

Note

I/O structure

Alternate

functions

Pinouts, pin description and alternate functions STM32G0B1xB/C/xE

Additional

functions

LQFP32 / UFQFPN32 - N

LQFP32 / UFQFPN32 - GP

24 24 35 35 B3 45 45 D7 59 73 C11 PA13 I/O FT

25 25 36 36 B5 46 46 C7 60 74 B12 PA14-BOOT0 I/O FT

26 - 3737 A2 4747C6 61 75B11 PA15 I/O FT -

---- -4848A86276C10 PC8 I/OFT -

---- -4949B76377A12 PC9 I/OFT -

- 263838 A4 5050A7 64 78B10 PD0 I/OFT_c -

- 273939C6 5151B6 65 79 C9 PD1 I/OFT_d -

- 284040 B7 5252A6 66 80A11 PD2 I/OFT_c -

- 294141 A6 5353D567 81 C8 PD3 I/OFT_d -

---- -5454C56882B9 PD4 I/OFT -

---- -5555B56983A10 PD5 I/OFT -

- - - - - 56 56 A5 70 84 A9 PD6 I/O FT - USART2_RX, SPI1_MOSI/I2S1_SD, LPTIM2_OUT -

LQFP48 / UFQFPN48 - GP

LQFP48 / UFQFPN48 - N

(4)

SWDIO, IR_OUT, USB_NOE, EVENTOUT,

SWCLK, USART2_TX, EVENTOUT, LPUART2_TX BOOT0

SPI1_NSS/I2S1_WS, USART2_RX,

TIM2_CH1_ETR, MCO2, USART4_RTS_DE_CK,

USART3_RTS_DE_CK, USB_NOE, EVENTOUT,

UCPD2_FRSTX, TIM3_CH3, TIM1_CH1,

I2S_CKIN, TIM3_CH4, TIM1_CH2,

LPUART2_RTS_DE, USB_NOE

EVENTOUT, SPI2_NSS/I2S2_WS, TIM16_CH1,

EVENTOUT, SPI2_SCK/I2S2_CK, TIM17_CH1,

USART3_RTS_DE_CK, TIM3_ETR, TIM1_CH1N,

USART2_CTS, SPI2_MISO/I2S2_MCK,

USART2_RTS_DE_CK, SPI2_MOSI/I2S2_SD,

TIM1_CH3N, USART5_RTS_DE_CK

USART2_TX, SPI1_MISO/I2S1_MCK, TIM1_BKIN,

LPUART2_RX

I2C2_SMBA, SPI3_NSS

LPUART2_CTS

FDCAN1_RX

FDCAN1_TX

USART5_RX

TIM1_CH2N, USART5_TX

USART5_CTS

UCPD2_CC1

UCPD2_DBCC1

UCPD2_CC2

UCPD2_DBCC2

Pin number

WLCSP52

LQFP64 - GP

LQFP64 - N

UFBGA64 - N

Table 12. Pin assignment and description (continued)

Pin name

LQFP100

UFBGA80

(function

upon reset)

UFBGA100

Pin type

Note

I/O structure

Alternate

functions

STM32G0B1xB/C/xE Pinouts, pin description and alternate functions

Additional

functions

DS13560 Rev 1 54/159

LQFP32 / UFQFPN32 - N

LQFP32 / UFQFPN32 - GP

---- - ---7185B8 PD7 I/OFT - MCO2 -

---- - --- -86A8 PF9 I/OFT - USART6_TX -

---- - --- -87B7 PF10 I/OFT - USART6_RX -

---- - --- -88A7 PF11 I/OFT - USART6_RTS_DE_CK -

- - - - - - - - - 89 B6 PF12 I/O FT - TIM15_CH1, USART6_CTS -

---- - --- -90A6 PF13 I/OFT - TIM15_CH2 -

27 - 4242 A8 5757B472 91 A5 PB3 I/OFT_a -

28 - 4343 B9 5858C4 73 92 B5 PB4 I/OFT_a -

29 - 44 44 A10 59 59 D4 74 93 C5 PB5 I/O FT -

- - - - - - - - 75 94 A4 PE0 I/O FT - TIM16_CH1, EVENTOUT, TIM4_ETR -

- - - - - - - - 76 95 B4 PE1 I/O FT - TIM17_CH1, EVENTOUT -

---- - --- -96A3 PE2 I/OFT - TIM3_ETR -

---- - ---7797A2 PE3 I/OFT - TIM3_CH1 -

LQFP48 / UFQFPN48 - GP

LQFP48 / UFQFPN48 - N

SPI1_SCK/I2S1_CK, TIM1_CH2, TIM2_CH2,

USART5_TX, USART1_RTS_DE_CK, I2C3_SCL,

EVENTOUT, I2C2_SCL, SPI3_SCK

SPI1_MISO/I2S1_MCK, TIM3_CH1, USART5_RX,

USART1_CTS, TIM17_BKIN, I2C3_SDA,

EVENTOUT, I2C2_SDA, SPI3_MISO

SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM16_BKIN,

FDCAN2_RX, LPTIM1_IN1, I2C1_SMBA,

COMP2_OUT, USART5_RTS_DE_CK, SPI3_MOSI

COMP2_INM6

COMP2_INP0

WKUP6

55/159 DS13560 Rev 1

Pin number

WLCSP52

LQFP64 - GP

LQFP64 - N

UFBGA64 - N

Table 12. Pin assignment and description (continued)

Pin name

LQFP100

UFBGA80

(function

upon reset)

UFBGA100

Pin type

Note

I/O structure

Alternate

functions

Pinouts, pin description and alternate functions STM32G0B1xB/C/xE

Additional

functions

LQFP32 / UFQFPN32 - N

LQFP32 / UFQFPN32 - GP

30 30 45 45 C8 60 60 A4 78 98 C4 PB6 I/O FT_fa -

31 31 46 46 D7 61 61 A3 79 99 B3 PB7 I/O FT_fa -

32 32 47 47 A12 62 62 B3 80 100 A1 PB8 I/O FT_f -

1 1 48 48 D9 63 63 C3 1 1 C3 PB9 I/O FT_f -

1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:

- The speed should not exceed 2 MHz with a maximum load of 30 pF

- These GPIOs must not be used as current sources (for example to drive a LED).

2. After an RTC domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers. The RTC registers are not reset upon system reset. For details on how to manage these GPIOs, refer to the RTC domain and RTC register descriptions in the RM0444 reference manual.

3. Pins PA9/PA10 can be remapped in place of pins PA11/PA12 (default mapping), using SYSCFG_CFGR1 register.

4. Upon reset, these pins are configured as SW debug alternate functions, and the internal pull-up on PA13 pin and the internal pull-down on PA14 pin are activated.

LQFP48 / UFQFPN48 - GP

LQFP48 / UFQFPN48 - N

USART1_TX, TIM1_CH3, TIM16_CH1N,

FDCAN2_TX, SPI2_MISO/I2S2_MCK, LPTIM1_ETR,

I2C1_SCL, EVENTOUT, USART5_CTS, TIM4_CH1,

LPUART2_TX

USART1_RX, SPI2_MOSI/I2S2_SD, TIM17_CH1N,

USART4_CTS, LPTIM1_IN2, I2C1_SDA,

EVENTOUT, TIM4_CH2, LPUART2_RX

CEC, SPI2_SCK/I2S2_CK, TIM16_CH1,

FDCAN1_RX, USART3_TX, TIM15_BKIN,

I2C1_SCL, EVENTOUT, USART6_TX, TIM4_CH3

IR_OUT, UCPD2_FRSTX, TIM17_CH1, FDCAN1_TX, USART3_RX, SPI2_NSS/I2S2_WS, I2C1_SDA, EVENTOUT, USART6_RX, TIM4_CH4

COMP2_INP1

COMP2_INM7, PVD_IN

Table 13. Port A alternate function mapping (AF0 to AF7)

Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

STM32G0B1xB/C/xE

DS13560 Rev 1 56/159

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

PA8 MCO

PA9 MCO USART1_TX TIM1_CH2 -

PA1 0

PA11

PA1 2

SPI2_SCK/

I2S2_CK

SPI1_SCK/

I2S1_CK

SPI1_MOSI/

I2S1_SD

SPI2_MISO/

I2S2_MCK

SPI1_NSS/

I2S1_WS

SPI1_SCK/

I2S1_CK

SPI1_MISO/

I2S1_MCK

SPI1_MOSI/

I2S1_SD

SPI2_MOSI/

I2S2_SD

SPI1_MISO/

I2S1_MCK

SPI1_MOSI/

I2S1_SD

USART2_CTS TIM2_CH1_ETR - USART4_TX LPTIM1_OUT UCPD2_FRSTX COMP1_OUT

USART2_RTS

_DE_CK

TIM2_CH2 - USART4_RX TIM15_CH1N I2C1_SMBA EVENTOUT

USART2_TX TIM2_CH3 - UCPD1_FRSTX TIM15_CH1 LPUART1_TX COMP2_OUT

USART2_RX TIM2_CH4 - UCPD2_FRSTX TIM15_CH2 LPUART1_RX EVENTOUT

SPI2_MOSI/

I2S2_SD

USB_NOE USART6_TX TIM14_CH1 LPTIM2_OUT UCPD2_FRSTX EVENTOUT

CEC TIM2_CH1_ETR USART6_RX USART3_TX LPTIM2_ETR UCPD1_FRSTX EVENTOUT

TIM3_CH1 TIM1_BKIN USART6_CTS USART3_CTS TIM16_CH1 LPUART1_CTS COMP1_OUT

TIM3_CH2 TIM1_CH1N

SPI2_NSS/

I2S2_WS

TIM1_CH1 - CRS1_SYNC LPTIM2_OUT - EVENTOUT

USART6_RTS

_DE_CK

TIM14_CH1 TIM17_CH1 UCPD1_FRSTX COMP2_OUT

SPI2_MISO/

I2S2_MCK

TIM15_BKIN I2C1_SCL EVENTOUT

USART1_RX TIM1_CH3 MCO2 - TIM17_BKIN I2C1_SDA EVENTOUT

USART1_CTS TIM1_CH4 FDCAN1_RX - TIM1_BKIN2 I2C2_SCL COMP1_OUT

USART1_RTS

_DE_CK

TIM1_ETR FDCAN1_TX - I2S_CKIN I2C2_SDA COMP2_OUT

PA13 SWDIO IR_OUT USB_NOE - - - - EVENTOUT

PA14SWCLKUSART2_TX-----EVENTOUT

PA1 5

SPI1_NSS/

I2S1_WS

USART2_RX TIM2_CH1_ETR MCO2

USART4_RTS

_DE_CK

USART3_RTS

_DE_CK

USB_NOE EVENTOUT

57/159 DS13560 Rev 1

Table 14. Port A alternate function mapping (AF8 to AF15)

Port AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

PA0--------

PA1--------

PA2--------

PA3--------

PA4-SPI3_NSS------

PA5--------

PA6 I2C2_SDA I2C3_SDA - - - - - -

PA7I2C2_SCLI2C3_SCL------

PA8I2C2_SMBA-------

PA9I2C2_SCL-------

PA10 I2C2_SDA - - - - - - -

PA11--------

PA12--------

PA13 - - LPUART1_RX - - - - -

PA14 - - LPUART1_TX - - - - -

PA15I2C2_SMBASPI3_NSS------

STM32G0B1xB/C/xE

Table 15. Port B alternate function mapping (AF0 to AF7)

Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

STM32G0B1xB/C/xE

DS13560 Rev 1 58/159

PB0

PB1 TIM14_CH1 TIM3_CH4 TIM1_CH3N FDCAN2_TX

PB2 -

PB3

PB4

PB5

PB6 USART1_TX TIM1_CH3 TIM16_CH1N FDCAN2_TX

PB7 USART1_RX

PB8 CEC

SPI1_NSS/

I2S1_WS

SPI1_SCK/

I2S1_CK

SPI1_MISO/

I2S1_MCK

SPI1_MOSI/

I2S1_SD

TIM3_CH3 TIM1_CH2N FDCAN2_RX USART3_RX LPTIM1_OUT UCPD1_FRSTX COMP1_OUT

USART3_RTS

_DE_CK

SPI2_MISO/

I2S2_MCK

TIM1_CH2 TIM2_CH2 USART5_TX

- MCO2 USART3_TX LPTIM1_OUT - EVENTOUT

USART1_RTS

_DE_CK

TIM3_CH1 - USART5_RX USART1_CTS TIM17_BKIN I2C3_SDA EVENTOUT

TIM3_CH2 TIM16_BKIN FDCAN2_RX - LPTIM1_IN1 I2C1_SMBA COMP2_OUT

SPI2_MISO/

I2S2_MCK

SPI2_MOSI/

I2S2_SD

SPI2_SCK/

I2S2_CK

TIM17_CH1N - USART4_CTS LPTIM1_IN2 I2C1_SDA EVENTOUT

TIM16_CH1 FDCAN1_RX USART3_TX TIM15_BKIN I2C1_SCL EVENTOUT

PB9 IR_OUT UCPD2_FRSTX TIM17_CH1 FDCAN1_TX USART3_RX

PB10 CEC LPUART1_RX TIM2_CH3 - USART3_TX

PB11

PB12

PB13

SPI2_MOSI/

I2S2_SD

SPI2_NSS/

I2S2_WS

SPI2_SCK/

I2S2_CK

LPUART1_TX TIM2_CH4 - USART3_RX - I2C2_SDA COMP2_OUT

LPUART1_RTS

_DE

TIM1_BKIN FDCAN2_RX - TIM15_BKIN UCPD2_FRSTX EVENTOUT

LPUART1_CTS TIM1_CH1N FDCAN2_TX USART3_CTS TIM15_CH1N I2C2_SCL EVENTOUT

LPTIM2_IN1

LPUART1_RTS

_DE

COMP3_OUT

- I2C3_SCL EVENTOUT

LPTIM1_ETR I2C1_SCL EVENTOUT

SPI2_NSS/

I2S2_WS

SPI2_SCK/

I2S2_CK

I2C1_SDA EVENTOUT

I2C2_SCL COMP1_OUT

59/159 DS13560 Rev 1

Table 15. Port B alternate function mapping (AF0 to AF7) (continued)

Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

PB14

PB15

SPI2_MISO/

I2S2_MCK

SPI2_MOSI/

I2S2_SD

UCPD1_FRSTX TIM1_CH2N -

- TIM1_CH3N - TIM15_CH1N TIM15_CH2 - EVENTOUT

Table 16. Port B alternate function mapping (AF8 to AF15)

USART3_RTS

_DE_CK

TIM15_CH1 I2C2_SDA EVENTOUT

Port AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

PB0USART5_TX-LPUART2_CTS-----

PB1 USART5_RX -

LPUART2_RTS

_DE

-----

PB2--------

PB3I2C2_SCLSPI3_SCK------

PB4I2C2_SDASPI3_MISO------

PB5

USART5_RTS

_DE_CK

SPI3_MOSI------

PB6USART5_CTSTIM4_CH1LPUART2_TX-----

PB7-TIM4_CH2LPUART2_RX-----

PB8USART6_TXTIM4_CH3------

PB9USART6_RXTIM4_CH4------

PB10--------

PB11--------

PB12I2C2_SMBA-------

STM32G0B1xB/C/xE

PB13--------

PB14

USART6_RTS

_DE_CK

-------

PB15USART6_CTS-------

DS13560 Rev 1 60/159

Table 17. Port C alternate function mapping

Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

PC0 LPTIM1_IN1 LPUART1_RX LPTIM2_IN1 LPUART2_TX USART6_TX - I2C3_SCL COMP3_OUT

PC1 LPTIM1_OUT LPUART1_TX TIM15_CH1 LPUART2_RX USART6_RX - I2C3_SDA -

PC2 LPTIM1_IN2

PC3 LPTIM1_ETR

SPI2_MISO/

I2S2_MCK

SPI2_MOSI/

I2S2_SD

TIM15_CH2 - - - - COMP3_OUT

LPTIM2_ETR - - - - -

PC4 USART3_TX USART1_TXTIM2_CH1_ETR-----

PC5 USART3_RX USART1_RX TIM2_CH2 - - - - -

PC6 UCPD1_FRSTX TIM3_CH1 TIM2_CH3 LPUART2_TX - - - -

PC7 UCPD2_FRSTX TIM3_CH2 TIM2_CH4 LPUART2_RX - - - -

PC8 UCPD2_FRSTX TIM3_CH3 TIM1_CH1 LPUART2_CTS - - - -

PC9 I2S_CKIN TIM3_CH4 TIM1_CH2

LPUART2_RTS_

- - USB_NOE -

PC10 USART3_TX USART4_TX TIM1_CH3 - SPI3_SCK - - -

PC11 USART3_RX USART4_RX TIM1_CH4 - SPI3_MISO - - -

PC12 LPTIM1_IN1 UCPD1_FRSTX TIM14_CH1 USART5_TX SPI3_MOSI - - -

PC13 - - TIM1_BKIN - - - - -

PC14 - - TIM1_BKIN2 - - - - -

PC15 OSC32_EN OSC_EN TIM15_BKIN - - - - -

STM32G0B1xB/C/xE

61/159 DS13560 Rev 1

Table 18. Port D alternate function mapping

Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

PD0 EVENTOUT

PD1 EVENTOUT

PD2

USART3_RTS

_DE_CK

PD3 USART2_CTS

PD4

USART2_RTS

_DE_CK

PD5 USART2_TX

PD6 USART2_RX

SPI2_NSS/

I2S2_WS

SPI2_SCK/

I2S2_CK

TIM16_CH1 FDCAN1_RX - - - -

TIM17_CH1 FDCAN1_TX - - - -

TIM3_ETR TIM1_CH1N USART5_RX - - - -

SPI2_MISO/

I2S2_MCK

SPI2_MOSI/

I2S2_SD

SPI1_MISO/

I2S1_MCK

SPI1_MOSI/

I2S1_SD

TIM1_CH2N USART5_TX - - - -

TIM1_CH3N

USART5_RTS

_DE_CK

----

TIM1_BKIN USART5_CTS - - - -

LPTIM2_OUT - - - - -

PD7---MCO2----

PD8 USART3_TX

PD9 USART3_RX

PD10

MCO - -

SPI1_SCK/

I2S1_CK

SPI1_NSS/

I2S1_WS

LPTIM1_OUT - - - - -

TIM1_BKIN2-----

-----

PD11 USART3_CTS LPTIM2_ETR - - - - - -

PD12

USART3_RTS

_DE_CK

LPTIM2_IN1 TIM4_CH1 - - - - -

PD13 - LPTIM2_OUT TIM4_CH2 - - - - -

PD14 - LPUART2_CTS TIM4_CH3 - - - - -

PD15 CRS1_SYNC

LPUART2_RTS

_DE

TIM4_CH4-----

STM32G0B1xB/C/xE

DS13560 Rev 1 62/159

Table 19. Port E alternate function mapping

Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

PE0 TIM16_CH1 EVENTOUT TIM4_ETR FDCAN[1_RXFD] - - - -

PE1 TIM17_CH1 EVENTOUT - FDCAN[1_TXFD] - - - -

PE2-TIM3_ETR------

PE3-TIM3_CH1------

PE4-TIM3_CH2------

PE5-TIM3_CH3------

PE6-TIM3_CH4------

PE7 - TIM1_ETR -

USART5_RTS_D

E_CK

----

PE8USART4_TXTIM1_CH1N------

PE9USART4_RXTIM1_CH1------

PE10 - TIM1_CH2N - USART5_TX - - - -

PE11 - TIM1_CH2 - USART5_RX - - - -

PE12

PE13

SPI1_NSS/

I2S1_WS

SPI1_SCK/

I2S1_CK

TIM1_CH3N------

TIM1_CH3------

STM32G0B1xB/C/xE

63/159 DS13560 Rev 1

Table 20. Port F alternate function mapping

Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

PF0 CRS1_SYNC EVENTOUT TIM14_CH1 - - - - -

PF1 OSC_EN EVENTOUT TIM15_CH1N - - - - -

PF2 MCO LPUART2_TX -

PF3 - LPUART2_RX -

LPUART2_RTS

_DE

USART6_RTS

_DE_CK

----

PF4-LPUART1_TX------

PF5-LPUART1_RX------

PF6 -

LPUART1_RTS

_DE

------

PF7 - LPUART1_CTS - USART5_CTS - - - -

PF8--------

PF9 - - - USART6_TX - - - -

PF10 - - - USART6_RX - - - -

PF11---

USART6_RTS

_DE_CK

----

PF12 TIM15_CH1 - - USART6_CTS - - - -

PF13 TIM15_CH2 - - - - - - -

STM32G0B1xB/C/xE

Electrical characteristics STM32G0B1xB/C/xE

MCU pin

C = 50 pF

MCU pin

5 Electrical characteristics

5.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

Parameter values defined at temperatures or in temperature ranges out of the ordering information scope are to be ignored.

Packages used for characterizing certain electrical parameters may differ from the commercial packages as per the ordering information.

5.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at T the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3).

= 25 °C and TA = TA(max) (given by

5.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = V V. They are given only as design guidelines and are not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated

5.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

5.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 13.

5.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 14.

Figure 13. Pin loading conditions Figure 14. Pin input voltage

(mean ±2).

DDA

= V

DDIO2

= 3

64/159 DS13560 Rev 1

STM32G0B1xB/C/xE Electrical characteristics

MSv66839V2

Backup circuitry

(LSE, RTC and

backup registers)

Kernel logic

(CPU, digital and

memories)

Level shifter

logic

OUT

Regulator

GPIOs

1.55 V to 3.6 V

1 x 100 nF

+ 1 x 4.7 μF

VDD/VDDA

VBAT

CORE

Power switch

DDIO1

ADC DAC

COMPs

VREFBUF

VREF+

VREF-

VSS/VSSA

REF

100 nF

1 μF

SSA

DDA

VREF+

Level shifter

logic

OUT

DDIO2

VDDIO2

100 nF

+4.7 μF

DDIO2

GPIOs

5.1.6 Power supply scheme

Figure 15. Power supply scheme

Caution: Power supply pin pair (VDD/VDDA/VDDIO2 and VSS/VSSA) must be decoupled with

filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device.

DS13560 Rev 1 65/159

124

Electrical characteristics STM32G0B1xB/C/xE

MSv66840V1

DDVBAT

BAT

DDA

)

VBAT

VDD/VDDA

VDDIO2

5.1.7 Current consumption measurement

Figure 16. Current consumption measurement scheme

5.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 21, Table 22 and Table 23 may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

All voltages are defined with respect to V

Table 21. Voltage characteristics

Symbol Ratings Min Max Unit

DDIO2

BAT

REF+

1. Refer to Table 22 for the maximum allowed injected current values.

2. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.

External supply voltage - 0.3 4.0

External supply voltage for selected I/Os - 0.3 4.0

External supply voltage on VBAT pin - 0.3 4.0

External voltage on VREF+ pin - 0.3 Min(

Input voltage on FT_xx pins except FT_c

(1)

Input voltage on FT_c pins

Input voltage on any other pin

- 0.3 V

- 0.3

5.5

4.0

+ 0.4, 4.0)

(2)

4.0

66/159 DS13560 Rev 1

STM32G0B1xB/C/xE Electrical characteristics

Table 22. Current characteristics

Symbol Ratings Max Unit

DD/VDDA

/VDDIO2

SS/VSSA

Current into VDD/VDDA/VDDIO2 power pin (source)

Current out of VSS/VSSA ground pin (sink)

(1)

100

Output current sunk by any I/O and control pin except FT_f 15

IO(PIN)

Output current sunk by any FT_f pin 20

Output current sourced by any I/O and control pin 15

Total output current sunk by sum of all I/Os and control pins 80

I

IO(PIN)

INJ(PIN)

|I

INJ(PIN)

1. All main power (VDD/VDDA/VDDIO2, VBAT) and ground (VSS/VSSA) pins must always be connected to the external power supplies, in the permitted range.

2. A positive injection is induced by V exceeded. Refer also to Table 21: Voltage characteristics for the maximum allowed input voltage values.

3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.

4. On these I/Os, any current injection disturbs the analog performances of the device.

5. When several inputs are submitted to a current injection, the maximum |I injected currents (instantaneous values).

Total output current sourced by sum of all I/Os and control pins 80

Injected current on a FT_xx pin -5 / NA

(2)

Injected current on a TT_a pin

Total injected current (sum of all I/Os and control pins)

> V

(4)

(5)

while a negative injection is induced by VIN < VSS. I

DDIOx

is the absolute sum of the negative

INJ(PIN)

-5 / 0

INJ(PIN)

(3)

must never be

Table 23. Thermal characteristics

Symbol Ratings Value Unit

STG

Storage temperature range –65 to +150 °C

Maximum junction temperature 150 °C

5.3 Operating conditions

5.3.1 General operating conditions

Table 24. General operating conditions

Symbol Parameter Conditions Min Max Unit

HCLK

PCLK

DDIO2

Internal AHB clock frequency - 0 64

Internal APB clock frequency - 0 64

Standard operating voltage - 1.7

External supply voltage for selected I/Os

-1.73.6V

(1)

MHz

3.6 V

DS13560 Rev 1 67/159

124

Electrical characteristics STM32G0B1xB/C/xE

Table 24. General operating conditions (continued)

Symbol Parameter Conditions Min Max Unit

Analog supply voltage

DDA

For ADC and COMP

operation

For DAC operation 1.8 3.6

1.62 3.6

For VREFBUF operation 2.4 3.6

1. When RESET is released functionality is guaranteed down to V

2. The T

3. Temperature range digit in the order code. See Section 7: Ordering information.

Backup operating voltage - 1.55 3.6 V

BAT

Suffix 6

Ambient temperature

(2)

Suffix 3

Suffix 6

Junction temperature

Suffix 3

(max) applies to PD(max). At PD < PD(max) the ambient temperature is allowed to go higher than TA(max) provided

that the junction temperature TJ does not exceed TJ(max). Refer to Section 6.11: Thermal characteristics.

(3)

PDR

-40 85

-40 105

-40 125

-40 105

-40 125

-40 130

min.

5.3.2 Operating conditions at power-up / power-down

The parameters given in Table 25 are derived from tests performed under the ambient temperature condition summarized in Table 24.

Table 25. Operating conditions at power-up / power-down

°CSuffix 7

Symbol Parameter Conditions Min Max Unit

rising - 

VDD slew rate

VDD

falling; ULPEN = 0 10 

falling; ULPEN = 1 100  ms/V

5.3.3 Embedded reset and power control block characteristics

The parameters given in Table 26 are derived from tests performed under the ambient temperature conditions summarized in Table 24: General operating conditions.

Table 26. Embedded reset and power control block characteristics

Symbol Parameter Conditions

POR

PDR

BOR1

(2)

POR temporization when VDD crosses V

POR

Power-on reset threshold - 1.62 1.66 1.70 V

Power-down reset threshold - 1.60 1.64 1.69 V

Brownout reset threshold 1

RSTTEMPO

(1)

Min Typ Max Unit

rising - 250 400 s

rising 2.05 2.10 2.18

falling 1.95 2.00 2.08

µs/V

68/159 DS13560 Rev 1

STM32G0B1xB/C/xE Electrical characteristics

Table 26. Embedded reset and power control block characteristics (continued)

Symbol Parameter Conditions

BOR2

BOR3

BOR4

PVD0

PVD1

PVD2

PVD3

PVD4

PVD5

PVD6

Brownout reset threshold 2

Brownout reset threshold 3

Brownout reset threshold 4

Programmable voltage detector threshold 0

PVD threshold 1

PVD threshold 2

PVD threshold 3

PVD threshold 4

PVD threshold 5

PVD threshold 6

Hysteresis in

continuous

hyst_POR_PDR

Hysteresis of V

POR

and V

PDR

Hysteresis in

other mode

hyst_BOR_PVD

DD(BOR_PVD)

1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.

2. Guaranteed by design.

Hysteresis of V

(2)

BOR and PVD consumption - - 1.1 1.6 µA

BORx

and V

PVDx

(1)

Min Typ Max Unit

rising 2.20 2.31 2.38

falling 2.10 2.21 2.28

rising 2.50 2.62 2.68

falling 2.40 2.52 2.58

rising 2.80 2.91 3.00

falling 2.70 2.81 2.90

rising 2.05 2.15 2.22

falling 1.95 2.05 2.12

rising 2.20 2.30 2.37

falling 2.10 2.20 2.27

rising 2.35 2.46 2.54

falling 2.25 2.36 2.44

rising 2.50 2.62 2.70

falling 2.40 2.52 2.60

rising 2.65 2.74 2.87

falling 2.55 2.64 2.77

rising 2.80 2.91 3.03

falling 2.70 2.81 2.93

rising 2.90 3.01 3.14

falling 2.80 2.91 3.04

-20-

mode

-30-

- - 100 - mV

DS13560 Rev 1 69/159

124

Electrical characteristics STM32G0B1xB/C/xE

MSv40169V1

1.185

1.19

1.195

1.2

1.205

1.21

1.215

1.22

1.225

1.23

1.235

-40 -20 0 20 40 60 80 100 120

°C

Mean Min Max

5.3.4 Embedded voltage reference

The parameters given in Table 27 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 24: General operating

conditions.

Symbol Parameter Conditions Min Typ Max Unit

Table 27. Embedded internal voltage reference

REFINT

DD(VREFINTBUF)

1. The shortest sampling time can be determined in the application by multiple iterations.

2. Guaranteed by design.

S_vrefint

start_vrefint

V

REFINT

Coeff_vrefint

Coeff

DDCoeff

REFINT_DIV1

REFINT_DIV2

REFINT_DIV3

Internal reference voltage -40°C < TJ < 130°C 1.182 1.212 1.232 V

ADC sampling time when reading

(1)

the internal reference voltage

Start time of reference voltage buffer when ADC is enable

buffer consumption from

REFINT

VDD when converted by ADC

Internal reference voltage spread over the temperature range

-4

--812

- - 12.5 20

= 3 V - 5 7.5

Temperature coefficient - - 30 50

Long term stability 1000 hours, T = 25 °C - 300 1000

Voltage coefficient 3.0 V < VDD < 3.6 V - 250 1200

1/4 reference voltage

1/2 reference voltage 49 50 51

3/4 reference voltage 74 75 76

Figure 17. V

vs. temperature

REFINT

(2)

--µs

24 25 26

(2)

µs

µA

ppm/°C

ppm

ppm/V

REFINT

70/159 DS13560 Rev 1

STM32G0B1xB/C/xE Electrical characteristics

5.3.5 Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.

The current consumption is measured as described in Figure 16: Current consumption

measurement scheme.

Typical and maximum current consumption

The MCU is placed under the following conditions:

• All I/O pins are in analog input mode

• All peripherals are disabled except when explicitly mentioned

• The Flash memory access time is adjusted with the minimum wait states number,

depending on the f to CPU clock (HCLK) frequency” available in the RM0444 reference manual).

• When the peripherals are enabled f

• For Flash memory and shared peripherals f

Unless otherwise stated, values given in Table 29 through Table 36 are derived from tests performed under ambient temperature and supply voltage conditions summarized in

Table 24: General operating conditions.

frequency (refer to the table “Number of wait states according

HCLK

= f

PCLK

HCLK

PCLK

= f

HCLK

= f

HCLKS

DS13560 Rev 1 71/159

124

Electrical characteristics STM32G0B1xB/C/xE

Table 28. Current consumption in Run and Low-power run modes

at different die temperatures

(1)

Unit

Symbol Parameter

Supply

current in

DD(Run)

Run mode

(from Flash

memory)

General f

Range 1; PLL enabled;

= f

HCLK

HSE_bypass

(16 MHz),

= f

HCLK

(>16 MHz);

(3)

PLLRCLK

Range 2; PLL enabled;

= f

HCLK

HSE_bypass

(16 MHz),

= f

HCLK

(>16 MHz);

(3)

PLLRCLK

Conditions Typ Max

HCLK

64 MHz

Fetch

from

25°C85°C125°C25°C85°C130°

(2)

8.6 8.8 9.4 9.0 9.1 9.7

56 MHz 7.5 7.8 8.3 7.9 8.0 8.6

48 MHz 6.7 7.0 7.6 7.1 7.2 7.8

32 MHz 4.6 4.8 5.4 4.8 5.0 5.5

Flash

memory

24 MHz 3.6 3.8 4.3 3.8 4.1 4.6

16 MHz 2.3 2.5 3.0 2.4 2.6 3.2

64 MHz

8.8 8.9 9.4 9.3 9.4 9.9

56 MHz 7.7 7.8 8.3 8.2 8.3 8.8

48 MHz 6.9 7.0 7.5 7.3 7.4 7.9

SRAM

32 MHz 4.7 4.8 5.3 5.0 5.1 5.6

24 MHz 3.6 3.8 4.3 4.1 4.2 4.7

16 MHz 2.3 2.4 2.9 2.5 2.6 3.2

16 MHz

8 MHz 1.0 1.1 1.6 1.3 1.4 2.1

2 MHz 0.3 0.4 0.9 0.6 0.9 1.4

16 MHz

8 MHz 1.0 1.1 1.6 1.3 1.5 2.1

Flash

memory

SRAM

1.8 2.0 2.4 2.2 2.3 2.9

1.9 2.0 2.5 2.3 2.4 3.0

2 MHz 0.3 0.4 0.9 0.6 0.9 1.4

2 MHz

280 415 950 585 845 1515

1 MHz 155 285 820 530 835 1315

Flash

memory

250 360 855 575 835 1495

SRAM

DD(LPRun)

Supply

current in

Low-power

run mode

PLL disabled;

= f

HCLK

HSE

bypass (> 32 kHz), f

= f

HCLK

bypass (= 32 kHz);

(3)

LSE

500 kHz 90 220 750 475 795 1220

125 kHz 45 170 700 445 745 1190

32 kHz 30 155 695 430 720 1185

2 MHz

1 MHz 140 260 730 530 825 1300

500 kHz 80 205 650 475 780 1230

125 kHz 40 155 635 440 745 1200

32 kHz 30 135 625 415 715 1180

1. Based on characterization results, not tested in production.

2. Prefetch and cache enabled when fetching from Flash memory. Code compiled with high optimization for space in SRAM.

= 3.0 V for values in Typ columns and 3.6 V for values in Max columns, all peripherals disabled, cache enabled,

3. V

prefetch disabled for code and data fetch from Flash and enabled from SRAM

72/159 DS13560 Rev 1

µA

STM32G0B1xB/C/xE Electrical characteristics

Table 29. Typical current consumption in Run and Low-power run modes,

depending on code executed

Symbol Parameter

Supply

DD(Run)

current in

Run mode

General Code

Range 1;

= f

HCLK

64 MHz;

(2)

PLLRCLK

Range 2; f

HCLK

= f

HSI16

= 16 MHz, PLL disabled,

(2)

Conditions Typ

Unit

Reduced code

(3)

Fetch

from

25 °C 25 °C

(1)

8.70

Coremark 8.15 127

Dhrystone 2.1 8.00 125

Flash

memory

Fibonacci 7.30 114

While(1) loop 5.90 92

Reduced code

(3)

8.85 138

Coremark 9.10 142

Dhrystone 2.1 8.95 140

SRAM

Fibonacci 9.85 154

While(1) loop 8.85 138

Reduced code

(3)

2.45 153

Coremark 1.90 119

Dhrystone 2.1 1.90 119

Flash

memory

Fibonacci 1.70 106

While(1) loop 1.35 84

Reduced code

(3)

2.10 131

Coremark 2.10 131

Typ

Unit

136

A/MHz

Dhrystone 2.1 2.05 128

SRAM

Fibonacci 2.25 141

While(1) loop 2.05 128

Reduced code

(3)

485

243

Coremark 475 238

Dhrystone 2.1 480 240

Flash

memory

Fibonacci 500 250

DD(LPRun)

Supply

current in

Low-power

run mode

= f

HCLK

HSI16

2 MHz; PLL disabled,

(2)

/8 =

While(1) loop 515 258

Reduced code

(3)

490 245

A

Coremark 485 243

Dhrystone 2.1 480 240

SRAM

Fibonacci 510 255

While(1) loop 480 240

1. Prefetch and cache enabled when fetching from Flash. Code compiled with high optimization for space in SRAM.

VDD = 3.3 V, all peripherals disabled, cache enabled, prefetch disabled for execution in Flash and enabled in SRAM

DS13560 Rev 1 73/159

A/MHz

124

Electrical characteristics STM32G0B1xB/C/xE

3. Reduced code used for characterization results provided in Table 28.

Table 30. Current consumption in Sleep and Low-power sleep modes

Conditions Typ Max

Symbol Parameter

General

Voltage

scaling

Flash memory enabled;

= f

DD(Sleep)

Supply

current in

Sleep mode

HCLK

(16 MHz; PLL disabled), f

HCLK

(>16 MHz; PLL

= f

bypass

HSE

PLLRCLK

Range 1

enabled); All peripherals disabled

Range 2

Supply

DD(LPSleep)

current in

Low-power

sleep mode

1. Based on characterization results, not tested in production.

Flash memory disabled; PLL disabled;

= f

HCLK

bypass (> 32 kHz),

HSE

= f

bypass (= 32 kHz);

LSE

All peripherals disabled

HCLK

25°C85°C125°C25°C85°C130°

64 MHz 1.9 2.0 2.6 2.5 2.6 3.3

56 MHz 1.7 1.8 2.4 2.2 2.4 3.2

48 MHz 1.5 1.6 2.2 1.9 2.1 2.8

32 MHz 1.1 1.2 1.8 1.4 1.6 2.3

24 MHz 0.9 1.0 1.6 1.2 1.3 2.1

16 MHz 0.5 0.6 1.2 0.7 0.9 1.6

16 MHz 0.4 0.6 1.0 0.6 0.7 1.4

8 MHz 0.3 0.4 0.9 0.4 0.5 1.2

2 MHz 0.2 0.3 0.7 0.2 0.4 1.0

2 MHz 70 200 705 175 500 1325

1 MHz 48 175 685 145 438 1285

500 kHz 37 165 670 130 413 1255

125 kHz 28 155 665 105 388 1250

32 kHz 26 150 660 90 375 1210

(1)

Unit

µA

Table 31. Current consumption in Stop 0 mode

Conditions Typ Max

Symbol Parameter

HSI kernel V

1.8 V 290 370 675 370 470 850

2.4 V 295 370 680 370 470 870

Enabled

3 V 295 375 695 375 475 930

DD(Stop 0)

Supply

current in

Stop 0

3.6 V 300 380 695 375 475 1050

1.8 V 100 190 505 180 290 680

mode

2.4 V 100 195 510 180 290 685

Disabled

3 V 105 195 525 180 295 695

3.6 V 105 200 530 185 305 830

1. Based on characterization results, not tested in production.

(1)

Unit

25°C 85°C 125°C 25°C 85°C 130°C

µA

74/159 DS13560 Rev 1

STM32G0B1xB/C/xE Electrical characteristics

Table 32. Current consumption in Stop 1 mode

Conditions Typ Max

Symbol Parameter

Flash

memory

RTC

(2)

1.8 V 2.9 25 105 - - -

2.4 V 3.1 26 110 - - -

Disabled

3.6 V 3.6 26 110 - - -

1.8 V 3.3 25 105 - - -

2.4 V 3.6 26 110 - - -

DD(Stop 1)

Supply

current in

Stop 1

Not

powered

Enabled

mode

3.6 V 4.2 27 110 - - -

1.8 V 7.0 30 110 - - -

2.4 V 7.3 30 115 - - -

Powered Disabled

3.6 V 7.8 31 115 - - -

1. Based on characterization results, not tested in production.

2. Clocked by LSI

(1)

25°C 85°C 125°C 25°C 85°C 130°C

3 V 3.3 26 110 - - -

3 V 3.7 26 110 - - -

3 V 7.5 30 115 - - -

Unit

µA

Symbol Parameter

Supply current

DD(Standby)

in Standby

mode

Table 33. Current consumption in Standby mode

Conditions Typ Max

(2)

General V

RTC disabled

RTC enabled,

clocked by LSI;

IWDG enabled,

clocked by LSI

ULPEN = 0

1.8 V 0.1 2.1 9.4 0.8 14 45

2.4 V 0.1 2.5 11.5 1.2 17 54

3.0 V 0.2 3.0 13.5 1.4 18 64

3.6 V 0.3 3.5 16.0 1.8 21 74

1.8 V 0.4 2.3 9.7 2.0 15 45

2.4 V 0.5 2.8 11.5 2.5 18 55

3.0 V 0.7 3.4 14.0 3.0 20 64

3.6 V 0.9 4.0 16.0 3.3 23 75

1.8 V 0.3 2.3 9.6 2.1 14 45

2.4 V 0.4 2.7 11.5 2.3 17 54

3.0 V 0.5 3.3 13.5 2.6 19 64

3.6 V 0.7 3.8 16.0 3.0 22 74

1.8 V 0.7 2.0 9.4 - - -

2.4 V 0.9 2.4 11.0 - - -

3.0 V 1.1 2.9 13.5 - - -

3.6 V 1.3 3.4 15.5 - - -

25°C 85°C 125°C 25°C 85°C 130°C

(1)

Unit

µA

DS13560 Rev 1 75/159

124

Electrical characteristics STM32G0B1xB/C/xE

Table 33. Current consumption in Standby mode (continued)

Symbol Parameter

Conditions Typ Max

General V

Extra supply

I

DD(SRAM)

1. Based on characterization results, not tested in production.

2. Without SRAM retention and with ULPEN bit set

3. To be added to I

current to retain SRAM

(3)

content

DD(Standby)

SRAM retention

enabled

as appropriate

1.8 V------

2.4 V------

3.0 V------

3.6 V------

25°C 85°C 125°C 25°C 85°C 130°C

(1)

Unit

µA

Table 34. Current consumption in Shutdown mode

(1)

Unit

Symbol Parameter

Supply current

DD(Shutdown)

in Shutdown

mode

Conditions Typ Max

RTC V

25 °C 85 °C 125 °C 25 °C 85 °C 130 °C

1.8 V 23 840 7050 240 3210 39200

Disabled

2.4 V 38 965 8050 370 3910 44600

3.0 V 38 1100 9550 370 4700 51500

3.6 V 57 1350 11000 500 5700 59400

1.8 V 235 1050 7400 290 3850 47000

Enabled, clocked

by LSE bypass at

32.768 kHz

2.4 V 320 1250 8400 440 4690 53500

3.0 V 425 1500 9950 450 5640 61800

3.6 V 550 1850 11500 590 6840 71200

1. Based on characterization results, not tested in production.

Table 35. Current consumption in VBAT mode

Conditions Typ

Symbol Parameter

RTC V

Enabled, clocked by

LSE bypass at

32.768 kHz

Enabled, clocked by

LSE crystal at

32.768 kHz

DD(VBAT)

Supply current in

VBAT mode

Disabled

25°C 85°C 125°C

1.8 V 195 416 2015

2.4 V 320 530 2366

3.0 V 492 635 2838

3.6 V 627 908 3339

1.8 V 130 325 1550

2.4 V 160 400 1800

3.0 V 210 500 2050

3.6 V 285 605 2400

1.8 V 4 160 1450

2.4 V 4 190 1700

3.0 V 4 220 1950

3.6 V 7 270 2250

Unit

76/159 DS13560 Rev 1

STM32G0B1xB/C/xE Electrical characteristics

DDIOxfSW

C××=

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 55: I/O static characteristics.

For the output pins, any external pull-down or external load must also be considered to estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs.

Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,

as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption measured previously (seeTable 36: Current consumption of peripherals , the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin:

where

is the current sunk by a switching I/O to charge/discharge the capacitive load

C is the total capacitance seen by the I/O pin: C = C

is the I/O supply voltage

DDIOx

is the I/O switching frequency

INT

+ C

EXT + CS

CS is the PCB board capacitance including the pad pin.

The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.

DS13560 Rev 1 77/159

124

Electrical characteristics STM32G0B1xB/C/xE

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in the following table. The MCU is placed under the following conditions:

• All I/O pins are in Analog mode

• The given value is calculated by measuring the difference of the current consumptions:

– when the peripheral is clocked on

– when the peripheral is clocked off

• Ambient operating temperature and supply voltage conditions summarized in Table 21:

Voltage characteristics

• The power consumption of the digital part of the on-chip peripherals is given in the following table. The power consumption of the analog part of the peripherals (where applicable) is indicated in each related section of the datasheet.

Peripheral Bus

IOPORT Bus IOPORT 0.5 0.4 0.3

GPIOA IOPORT 3.1 2.4 3.0

GPIOB IOPORT 2.9 2.3 3.0

GPIOC IOPORT 3.0 2.4 2.8

GPIOD IOPORT 2.7 2.2 2.5

GPIOE IOPORT 1.6 1.4 1.6

GPIOF IOPORT 2.8 2.3 2.6

Bus matrix AHB 0.5 0.5 0.5

All AHB Peripherals AHB 31 26 30

DMA1/DMAMUX AHB 5.1 4.3 4.9

CRC AHB 0.4 0.4 0.5

FLASH AHB 22 18 21

All APB peripherals APB 120 110 220

AHB to APB bridge

PWR APB 0.4 0.3 0.4

WWDG APB 0.4 0.4 0.4

DMA2 APB 1.5 1.3 1.5

TIM1 APB 7.6 6.3 7.2

TIM2 APB 5.2 4.3 4.9

TIM3 APB 4.7 3.9 4.3

TIM4 APB 4.4 3.7 4.2

TIM6 APB 1.2 1.0 1.1

TIM7 APB 0.8 0.7 0.8

TIM14 APB 1.4 1.2 1.3

Table 36. Current consumption of peripherals

Consumption in µA/MHz

Range 1 Range 2

(1)

APB 0.2 0.2 0.1

Low-power run

and sleep

78/159 DS13560 Rev 1

STM32G0B1xB/C/xE Electrical characteristics

Table 36. Current consumption of peripherals (continued)

Consumption in µA/MHz

Peripheral Bus

Range 1 Range 2

TIM15 APB 4.2 3.5 3.9

TIM16 APB 2.7 2.3 2.5

TIM17 APB 0.8 0.7 0.7

LPTIM1 APB 3.3 2.7 3.1

LPTIM2 APB 3.2 2.7 3.1

I2C1 APB 3.6 3.0 3.3

I2C2 APB 3.4 2.8 3.2

I2C3 APB 0.9 0.7 0.8

SPI1 APB 2.2 1.9 2.1

SPI2 APB 2.1 1.7 2.0

SPI3 APB 1.4 1.2 1.3

USART1 APB 7.4 6.2 6.9

USART2 APB 7.4 6.2 7.0

USART3 APB 7.4 6.2 6.9

USART4 APB 2.1 1.8 2.0

USART5 APB 2.3 1.9 2.1

USART6 APB 2.2 1.8 2.1

LPUART1 APB 4.5 3.7 4.2

LPUART2 APB 4.9 4.1 4.6

ADC APB 2.4 2.0 2.3

DAC1 APB 1.9 1.6 1.8

Low-power run

and sleep

SYSCFG/VREFBUF/COMP APB 0.5 0.4 0.5

CEC APB 0.4 0.3 0.3

CRS APB 0.2 0.2 0.3

USB APB 3.3 2.7 3.0

FDCAN APB 16 13 15

UCPD1 APB 4.0 7.9 59.0

UCPD2 APB 4.0 7.9 59.5

1. The AHB to APB Bridge is automatically active when at least one peripheral is ON on the APB.

2. UCPDx are always clocked by HSI16.

DS13560 Rev 1 79/159

(2)

124

Electrical characteristics STM32G0B1xB/C/xE

5.3.6 Wakeup time from low-power modes and voltage scaling transition times

The wakeup times given in Table 37 are the latency between the event and the execution of the first user instruction.

Table 37. Low-power mode wakeup times

Symbol Parameter Conditions Typ Max Unit

Wakeup time from

WUSLEEP

Sleep to Run

-1111

mode

Transiting to Low-power-run-mode execution in Flash memory not powered in Low-power sleep mode;

HCLK = HSI16 / 8 = 2 MHz

WULPSLEEP

Wakeup time from Low-power sleep mode

Transiting to Run-mode execution in Flash memory not powered in Stop 0 mode;

HCLK = HSI16 = 16 MHz;

WUSTOP0

Wakeup time from Stop 0

Regulator in Range 1 or Range 2

Transiting to Run-mode execution in SRAM or in Flash memory powered in Stop 0 mode;

HCLK = HSI16 = 16 MHz; Regulator in Range 1 or Range 2

(1)

CPU

cycles

11 1 4

5.6 6

µs

22.4

WUSTOP1

WUSTBY

Wakeup time from Stop 1

Wakeup time from Standby mode

Transiting to Run-mode execution in Flash memory not powered in Stop 1 mode;

HCLK = HSI16 = 16 MHz; Regulator in Range 1 or Range 2

Transiting to Run-mode execution in SRAM or in Flash memory powered in Stop 1 mode;

HCLK = HSI16 = 16 MHz; Regulator in Range 1 or Range 2

Transiting to Low-power-run-mode execution in Flash memory not powered in Stop 1 mode;

HCLK = HSI16/8 = 2 MHz; Regulator in low-power mode (LPR = 1 in PWR_CR1)

Transiting to Low-power-run-mode execution in SRAM or in Flash memory powered in Stop 1 mode;

HCLK = HSI16 / 8 = 2 MHz; Regulator in low-power mode (LPR = 1 in PWR_CR1)

Transiting to Run mode; HCLK = HSI16 = 16 MHz; Regulator in Range 1

9.0 11.2

57.5

µs

22 25.3

18 23.5

14.5 30 µs

80/159 DS13560 Rev 1

STM32G0B1xB/C/xE Electrical characteristics

Table 37. Low-power mode wakeup times

(1)

(continued)

Symbol Parameter Conditions Typ Max Unit

WUSHDN

Wakeup time from Shutdown mode

Wakeup time from

WULPRUN

1. Based on characterization results, not tested in production.

2. Time until REGLPF flag is cleared in PWR_SR2.

Low-power run

(2)

mode

Transiting to Run mode; HCLK = HSI16 = 16 MHz; Regulator in Range 1

Transiting to Run mode; HSISYS = HSI16/8 = 2 MHz

Table 38. Regulator mode transition times

(1)

258 340 µs

57µs

Symbol Parameter Conditions Typ Max Unit

VOST

1. Based on characterization results, not tested in production.

2. Time until VOSF flag is cleared in PWR_SR2.

Transition times between regulator Range 1 and Range 2

(2)

Table 39. Wakeup time using LPUART

HSISYS = HSI16 20 40 µs

(1)

Symbol Parameter Conditions Typ Max Unit

Wakeup time needed to calculate the maximum

WULPUART

LPUART baud rate allowing to wakeup up from Stop mode when LPUART clock source is HSI16

1. Guaranteed by design.

Stop mode 0 - 1.7

Stop mode 1 - 8.5

5.3.7 External clock source characteristics

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 5.3.14. See

Figure 18 for recommended clock input waveform.

Table 40. High-speed external user clock characteristics

Symbol Parameter Conditions Min Typ Max Unit

HSE_ext

HSEH

HSEL

Voltage scaling Range 1

User external clock source frequency

Voltage scaling Range 2

OSC_IN input pin high level voltage - 0.7 V

OSC_IN input pin low level voltage - V

-848

-826

DDIO1

(1)

-V

-0.3 V

DDIO1

µs

MHz

DS13560 Rev 1 81/159

124

Electrical characteristics STM32G0B1xB/C/xE

MS19214V2

HSEH

f(HSE)

90%

10%

HSE

r(HSE)

HSEL

w(HSEH)

w(HSEL)

Table 40. High-speed external user clock characteristics

(1)

(continued)

Symbol Parameter Conditions Min Typ Max Unit

w(HSEH)

w(HSEL)

1. Guaranteed by design.

OSC_IN high or low time

Voltage scaling Range 1

Voltage scaling Range 2

7- -

18 - -

Figure 18. High-speed external clock source AC timing diagram

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 5.3.14. See

Figure 19 for recommended clock input waveform.

Table 41. Low-speed external user clock characteristics

Symbol Parameter Conditions Min Typ Max Unit

LSE_ext

LSEH

w(LSEH)

w(LSEL)

1. Guaranteed by design.

User external clock source frequency - - 32.768 1000 kHz

OSC32_IN input pin high level voltage - 0.7 V

OSC32_IN input pin low level voltage - V

LSEL

DDIO1

OSC32_IN high or low time - 250 - - ns

(1)

-V

- 0.3 V

DDIO1

82/159 DS13560 Rev 1

STM32G0B1xB/C/xE Electrical characteristics

MS19215V2

LSEH

f(LSE)

90%

10%

LSE

r(LSE)

LSEL

w(LSEH)

w(LSEL)

Figure 19. Low-speed external clock source AC timing diagram

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 42. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Table 42. HSE oscillator characteristics

Symbol Parameter Conditions

(2)

(1)

Min Typ Max Unit

OSC_IN

Oscillator frequency - 4 8 48 MHz

Feedback resistor - - 200 - k

During startup

= 3 V,

Rm = 30 , CL = 10 pF@8 MHz

= 3 V,

Rm = 45 , CL = 10 pF@8 MHz

= 3 V,

DD(HSE)

HSE current consumption

Rm = 30 , CL = 5 pF@48 MHz

= 3 V,

Rm = 30 , CL = 10 pF@48 MHz

= 3 V,

Rm = 30 , CL = 20 pF@48 MHz

SU(HSE)

1. Guaranteed by design.

2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

Maximum critical crystal

transconductance

(4)

Startup time VDD is stabilized - 2 - ms

Startup - - 1.5 mA/V

DS13560 Rev 1 83/159

(3)

--5.5

-0.44-

-0.45-

-0.68-

-0.94-

-1.77-

124

Electrical characteristics STM32G0B1xB/C/xE

MS19876V1

(1)

OSC_IN

OSC_OUT

Bias

controlled

gain

HSE

EXT

8 MHz

resonator

Resonator with integrated capacitors

3. This consumption level occurs during the first 2/3 of the t

4. t

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is

SU(HSE)

reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer

SU(HSE)

startup time

For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 20). C

and C

are usually the

same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C

and CL2. PCB and MCU pin capacitance must be included (10 pF

can be used as a rough estimate of the combined pin and board capacitance) when sizing C

and CL2.

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator

design guide for ST microcontrollers” available from the ST website www.st.com.

Figure 20. Typical application with an 8 MHz crystal

84/159 DS13560 Rev 1

1. R

value depends on the crystal characteristics.

EXT

Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 43. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

STM32G0B1xB/C/xE Electrical characteristics

MS30253V2

OSC32_IN

OSC32_OUT

Drive

programmable

amplifier

LSE

32.768 kHz resonator

Resonator with integrated capacitors

Symbol Parameter Conditions

Table 43. LSE oscillator characteristics (f

(2)

= 32.768 kHz)

LSE

LSEDRV[1:0] = 00 Low drive capability

LSEDRV[1:0] = 01 Medium low drive capability

DD(LSE)

LSE current consumption

LSEDRV[1:0] = 10 Medium high drive capability

LSEDRV[1:0] = 11 High drive capability

LSEDRV[1:0] = 00 Low drive capability

LSEDRV[1:0] = 01

critmax

Maximum critical crystal gm

Medium low drive capability

LSEDRV[1:0] = 10 Medium high drive capability

LSEDRV[1:0] = 11 High drive capability

(3)

SU(LSE)

1. Guaranteed by design.

2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST microcontrollers”.

3. t

SU(LSE)

reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer

Startup time VDD is stabilized - 2 - s

is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is

(1)

Min Typ Max Unit

-250-

-315-

-500-

-630-

--0.5

- - 0.75

--1.7

--2.7

µA/V

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator

Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden

design guide for ST microcontrollers” available from the ST website www.st.com.

Figure 21. Typical application with a 32.768 kHz crystal

to add one.

DS13560 Rev 1 85/159

124

Electrical characteristics STM32G0B1xB/C/xE

5.3.8 Internal clock source characteristics

The parameters given in Table 44 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 24: General operating

conditions. The provided curves are characterization results, not tested in production.

High-speed internal (HSI16) RC oscillator

Table 44. HSI16 oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

(1)

HSI16



Temp(HSI16)



VDD(HSI16)

HSI16 Frequency VDD=3.0 V, TA=30 °C 15.88 - 16.08 MHz

HSI16 oscillator frequency drift over temperature

HSI16 oscillator frequency drift over V

TRIM HSI16 frequency user trimming step

(2)

HSI16

su(HSI16)

stab(HSI16)

DD(HSI16)

1. Based on characterization results, not tested in production.

2. Guaranteed by design.

Duty Cycle - 45 - 55 %

(2)

HSI16 oscillator start-up time - - 0.8 1.2 s

(2)

HSI16 oscillator stabilization time - - 3 5 s

(2)

HSI16 oscillator power consumption - - 155 190 A

= 0 to 85 °C -1 - 1 %

= -40 to 125 °C -2 - 1.5

VDD=1.62 V to 3.6 V -0.1 - 0.05 %

From code 127 to 128 -8 -6 -4

From code 63 to 64 From code 191 to 192

For all other code increments

-5.8 -3.8 -1.8

0.2 0.3 0.4

86/159 DS13560 Rev 1

STM32G0B1xB/C/xE Electrical characteristics

MSv39299V1

15.6

15.7

15.8

15.9

16.1

16.2

16.3

16.4

MHz

min mean max

+1%

-1%

+2%

-2%

+1.5%

-1.5%

-40 -20 0 20 40 60 80 100 120 °C

Figure 22. HSI16 frequency vs. temperature

High-speed internal 48 MHz (HSI48) RC oscillator

Table 45. HSI48 oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

HSI48

HSI48 Frequency VDD=3.0V, TA=30°C - 48 - MHz

TRIM HSI48 user trimming step - - 0.11

USER TRIM COVERAGE

HSI48 user trimming coverage ±32 steps ±3

DuCy(HSI48) Duty Cycle - 45

= 3.0 V to 3.6 V,

Accuracy of the HSI48 oscillator

ACC

HSI48_REL

over temperature (factory calibrated)

(HSI48)

VDD

tsu(HSI48) HSI48 oscillator start-up time - - 2.5

IDD(HSI48)

jitter

HSI48 oscillator frequency drift with V

HSI48 oscillator power consumption

Next transition jitter Accumulated jitter on 28 cycles

Paired transition jitter Accumulated jitter on 56 cycles

= –15 to 85 °C

= 1.65 V to 3.6 V,

= –40 to 125 °C

VDD = 3 V to 3.6 V - 0.025

VDD = 1.65 V to 3.6 V - 0.05

--340

(4)

--+/-0.15

--+/-0.25

(1)

(2)

(3)

(2)

(3)

±3.5

-55

--±3

--±4.5

(3)

(2)

0.18

(2)

(3)

0.05

(3)

0.1

(2)

380

-ns

s

A

DS13560 Rev 1 87/159

124

Electrical characteristics STM32G0B1xB/C/xE

MSv40989V1

-6

-4

-2

-50 -30 -10 10 30 50 70 90 110 130

Avg min max

°C

1. VDD = 3 V, TA = –40 to 125°C unless otherwise specified.

2. Guaranteed by design.

3. Guaranteed by characterization results.

4. Jitter measurement are performed without clock source activated in parallel.

Figure 23. HSI48 frequency versus temperature

Low-speed internal (LSI) RC oscillator

Table 46. LSI oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

= 3.0 V, TA = 30 °C 31.04 - 32.96

LSI

LSI frequency

= 1.62 V to 3.6 V, TA = -40 to

125 °C

(2)

SU(LSI)

STAB(LSI)

DD(LSI)

1. Based on characterization results, not tested in production.

2. Guaranteed by design.

LSI oscillator start-up time - - 80 130 s

(2)

LSI oscillator stabilization time 5% of final frequency - 125 180 s

LSI oscillator power

(2)

consumption

- - 110 180 nA

(1)

kHz

29.5 - 34

88/159 DS13560 Rev 1

STM32G0B1xB/C/xE Electrical characteristics

5.3.9 PLL characteristics

The parameters given in Table 47 are derived from tests performed under temperature and V

supply voltage conditions summarized in Table 24: General operating conditions.

Table 47. PLL characteristics

Symbol Parameter Conditions Min Typ Max Unit

PLL_IN

PLL input clock frequency

PLL input clock duty cycle - 45 - 55 %

(2)

-2.66-16MHz

Voltage scaling Range 1 3.09 - 122

PLL_P_OUT

PLL multiplier output clock P

Voltage scaling Range 2 3.09 - 40

Voltage scaling Range 1 12 - 128

PLL_Q_OUT

PLL multiplier output clock Q

Voltage scaling Range 2 12 - 33

Voltage scaling Range 1 12 - 64

PLL_R_OUT

PLL multiplier output clock R

Voltage scaling Range 2 12 - 16

(1)

MHz

VCO_OUT

LOCK

Jitter

PLL VCO output

Voltage scaling Range 2 96 - 128

PLL lock time - - 15 40 s

RMS cycle-to-cycle jitter

-50-

System clock 56 MHz

RMS period jitter - 40 -

VCO freq = 96 MHz - 200 260

Voltage scaling Range 1 96 - 344

DD(PLL)

PLL power consumption

(1)

on V

VCO freq = 344 MHz - 520 650

1. Guaranteed by design.

2. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between the two PLLs.

5.3.10 Flash memory characteristics

Table 48. Flash memory characteristics

Symbol Parameter Conditions Typ Max Unit

prog

64-bit programming time - 85 125 µs

Normal programming 2.7 4.6

prog_row

Row (32 double word) programming time

Fast programming 1.7 2.8

Normal programming 21.8 36.6

prog_page

ERASE

prog_bank

Page (2 Kbyte) programming time

Fast programming 13.7 22.4

Page (2 Kbyte) erase time - 22.0 40.0

Bank (512 Kbyte

(2)

) programming time

Normal programming 2.8 4.7

Fast programming 1.8 2.9

Mass erase time - 22.1 40.1 ms

(1)

MHz

±ps

AVCO freq = 192 MHz - 300 380

DS13560 Rev 1 89/159

124

Electrical characteristics STM32G0B1xB/C/xE

Table 48. Flash memory characteristics

(1)

(continued)

Symbol Parameter Conditions Typ Max Unit

Programming 3 -

DD(FlashA)

Average consumption from V

Mass erase 5 -

DD(FlashP)

Maximum current (peak)

Programming, 2 µs peak duration

Erase, 41 µs peak duration 7 -

1. Guaranteed by design.

2. Values provided also apply to devices with less Flash memory than one 512 Kbyte bank

Symbol Parameter Conditions Min

RET

END

Endurance TA = -40 to +105 °C 10 kcycles

Data retention

Table 49. Flash memory endurance and data retention

1 kcycle

10 kcycles

(2)

at TA = 85 °C 30

(2)

at TA = 105 °C 15

(2)

at TA = 125 °C 7

(2)

at TA = 55 °C 30

(2)

at TA = 85 °C 15

(2)

at TA = 105 °C 10

(1)

Unit

Years

mAPage erase 3 -

1. Guaranteed by characterization results.

2. Cycling performed over the whole temperature range.

5.3.11 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until

a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

• FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V

through a 100 pF capacitor, until a functional disturbance occurs. This test is

compliant with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed.

The test results are given in Table 50. They are based on the EMS levels and classes defined in application note AN1709.

and

90/159 DS13560 Rev 1

STM32G0B1xB/C/xE Electrical characteristics

Symbol Parameter Conditions

FESD

EFTB

Voltage limits to be applied on any I/O pin to induce a functional disturbance

Fast transient voltage burst limits to be applied through 100 pF on VDD and V functional disturbance

Table 50. EMS characteristics

= 3.3 V, TA = +25 °C,

= 64 MHz, LQFP100,

HCLK

conforming to IEC 61000-4-2

VDD = 3.3 V, TA = +25 °C,

pins to induce a

= 64 MHz, LQFP100,

HCLK

conforming to IEC 61000-4-4

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• corrupted program counter

• unexpected reset

• critical data corruption (for example control registers)

Level/

Class

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading.

DS13560 Rev 1 91/159

124

Electrical characteristics STM32G0B1xB/C/xE

Table 51. EMI characteristics

Symbol Parameter Conditions

0.1 MHz to 30 MHz 9

VDD = 3.6 V, TA = 25 °C,

EMI

Peak level

LQFP100 package compliant with IEC 61967-2

30 MHz to 130 MHz 16

130 MHz to 1 GHz 4

1 GHz to 2 GHz 8

EMI level 2.5 -

5.3.12 Electrical sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the ANSI/JEDEC standard.

Table 52. ESD absolute maximum ratings

Monitored

frequency band

Max vs.

HSE/fHCLK

]

8 MHz / 64 MHz

Unit

dBµV

Symbol Ratings Conditions Class

ESD(HBM)

ESD(CDM)

1. Based on characterization results, not tested in production.

Electrostatic discharge voltage (human body model)

Electrostatic discharge voltage (charge device model)

TA = +25 °C, conforming to ANSI/ESDA/JEDEC JS-001

TA = +25 °C, conforming to ANSI/ESDA/JEDEC JS-002

2 2000

C2a 250

Maximum

(1)

value

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up performance:

• A supply overvoltage is applied to each power supply pin.

• A current is injected to each input, output and configurable I/O pin.

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Symbol Parameter Conditions Class

LU Static latch-up class T

Table 53. Electrical sensitivity

= +125 °C conforming to JESD78 II Level A

Unit

92/159 DS13560 Rev 1

STM32G0B1xB/C/xE Electrical characteristics

5.3.13 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or above V product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out-of-range parameter: ADC error above a certain limit (higher than 5 LSB TUE), induced leakage current on adjacent pins out of conventional limits (-5 µA/+0 µA range) or other functional failure (for example reset occurrence or oscillator frequency deviation).

Negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection.

(for standard, 3.3 V-capable I/O pins) should be avoided during normal

DDIOx

Table 54. I/O current injection susceptibility

(1)

Symbol Description

All except PA4, PA5, PA6, PB0,

INJ

1. Based on characterization results, not tested in production.

Injected current on pin

PB3, and PC0

PA4 , PA 5 -5 0 mA

PA6, PB0, PB3, and PC0 0 N/A mA

Functional susceptibility

Negative injection

-5 N/A mA

Positive

injection

Unit

DS13560 Rev 1 93/159

124

Electrical characteristics STM32G0B1xB/C/xE

5.3.14 I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 55 are derived from tests performed under the conditions summarized in Table 24: General operating conditions. All I/Os are designed as CMOS- and TTL-compliant.

Symbol Parameter Conditions Min Typ Max Unit

I/O input low level

(1)

voltage

I/O input high level

(1)

voltage

(3)

I/O input hysteresis

hys

Table 55. I/O static characteristics

All except

1.62 V < V

FT_c

2 V < V

FT_c

DDIOx

1.62 V < V

All except

1.62 V < V

FT_c

FT_c 1.62 V < V

TT_xx, FT_xx,

1.62 V < V

NRST

< 3.6 V - -

DDIOx

< 2.7 V - - 0.3 x V

< 2.7 V - - 0.25 x V

DDIOx

< 3.6 V

DDIOx

< 3.6 V 0.7 x V

DDIOx

< 3.6 V - 200 - mV

DDIOx

0.7 x V

+ 0.26

DDIOx

(3)

0.3 x V

0.39 x V

- 0.06

(

-5

DDIOx

(2)

DDIOx

(3)

DDIOx

V0.49 x V

FT_xx except FT_c and FT_d

lkg

Input leakage

(3)

current

FT_c

FT_d

TT_a

Weak pull-up

1. Refer to Figure 24: I/O input characteristics.

equivalent resistor

(5)

Weak pull-down

equivalent resistor

I/O pin capacitance - - 5 - pF

(5)

VIN = V

DDIOx

2. Tested in production.

3. Guaranteed by design.

 V

0 < V

DDIOx

 VIN  V

DDIOx

+1 V < VIN 

DDIOx

(3)

5.5 V

0 < V

 V

DDIOx

< VIN  5 V - - 3000

DDIOx

0 < VIN  V

DDIOx

0 < V

DDIOx

< VIN  5.5 V - - 9000

 V

DDIOx

< VIN  + 0.3 V

+1 V - - 600

DDIOx

--±70

- - 150

- - 2000

- - 4500

--±150

- - 2000

25 40 55 k

(4)

94/159 DS13560 Rev 1

STM32G0B1xB/C/xE Electrical characteristics

MSv47925V1

1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6

0.5

1.5

2.5

Minimum required

logic level 1 zone

Minimum required

logic level 0 zone

IHmin

= 0.7 V

DDIO

(CMOS standard requirement)

ILmax

= 0.3 V

DDIO

(CMOS standard requirement)

Undefined input range

IHmin

= 0.49 V

DDIO

+ 0.26

ILmax

= 0.39 V

DDIO

- 0.06

(V)

DDIO

(V)

TTL standard requirement

Device characteristics

Test thresholds

4. This value represents the pad leakage of the I/O itself. The total product pad leakage is provided by this formula: I

Total_Ileak_max

= 10 µA + [number of I/Os where VIN is applied on the pad]  I

lkg

(Max).

5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimal (~10% order).

All I/Os are CMOS- and TTL-compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters, as shown in Figure 24.

Figure 24. I/O input characteristics

Characteristics of FT_e I/Os

The following table and figure specify input characteristics of FT_e I/Os.

Symbol Parameter Conditions Min Typ Max Unit

INJ

DDIO1-VIN

Injected current on pin - - - 5 mA

Voltage over V

Diode dynamic serial resistor I

Table 56. Input characteristics of FT_e I/Os

DDIO1

= 5 mA - - 2 V

INJ

= 5 mA - - 300 

INJ

DS13560 Rev 1 95/159

124

Electrical characteristics STM32G0B1xB/C/xE

MSv63112V1

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2

INJ

(mA)

– V

DDIO1

(V)

-40°C

25°C 125°C

Figure 25. Current injection into FT_e input with diode active

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and up to ±15 mA with relaxed V

OL/VOH

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2:

• The sum of the currents sourced by all the I/Os on V consumption of the MCU sourced on V I

(see Table 21: Voltage characteristics).

VDD

• The sum of the currents sunk by all the I/Os on V the MCU sunk on V

, cannot exceed the absolute maximum rating I

cannot exceed the absolute maximum rating

DD,

, plus the maximum consumption of

plus the maximum

DDIO1,

(see Table 21:

VSS

Voltage characteristics).

Output voltage levels

Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in

Table 24: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT OR TT

unless otherwise specified).

96/159 DS13560 Rev 1

STM32G0B1xB/C/xE Electrical characteristics

Table 57. Output voltage characteristics

(1)

Symbol Parameter Conditions Min Max Unit

Output low level voltage for an I/O pin CMOS port

(2)

-0.4

|IIO| = 2 mA for FT_c I/Os

Output high level voltage for an I/O pin V

(3)

Output low level voltage for an I/O pin TTL port

= 8 mA for other I/Os

 2.7 V

DDIOx

(2)

- 0.4 -

DDIOx

-0.4

|IIO| = 2 mA for FT_c I/Os

(3)

OLFM+

1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 21:

Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always

respect the absolute maximum ratings I

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

3. Guaranteed by design.

Output high level voltage for an I/O pin 2.4 -

(3)

Output low level voltage for an I/O pin All I/Os except FT_c

(3)

Output high level voltage for an I/O pin V

(3)

Output low level voltage for an I/O pin |IIO| = 1 mA for FT_c I/Os

(3)

Output high level voltage for an I/O pin V

Output low level voltage for an FT I/O

(3)

pin in FM+ mode (FT I/O with _f option)

= 8 mA for other I/Os

 2.7 V

DDIOx

= 15 mA

IO|

 2.7 V

DDIOx

= 3 mA for other I/Os

 1.62 V

DDIOx

= 20 mA

IO|

 2.7 V

DDIOx

= 9 mA

IO|

 1.62 V

DDIOx

-1.3

- 1.3 -

DDIOx

-0.4

- 0.45 -

DDIOx

-0.4

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in Figure 26 and

Table 58, respectively.

Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 24: General

operating conditions.

Table 58. I/O AC characteristics

Speed Symbol Parameter Conditions Min Max Unit

C=50 pF, 2.7 V  V

Fmax Maximum frequency

C=50 pF, 1.6 V  V

C=10 pF, 2.7 V  V

C=10 pF, 1.6 V  V

C=50 pF, 2.7 V  V

Tr/Tf Output rise and fall time

C=50 pF, 1.6 V  V

C=10 pF, 2.7 V  V

C=10 pF, 1.6 V  V

(1)(2)

 3.6 V - 2

DDIOx

 2.7 V - 0.35

DDIOx

 3.6 V - 3

DDIOx

 2.7 V - 0.45

DDIOx

 3.6 V - 100

DDIOx

 2.7 V - 225

DDIOx

 3.6 V - 75

DDIOx

 2.7 V - 150

DDIOx

MHz

DS13560 Rev 1 97/159

124

Electrical characteristics STM32G0B1xB/C/xE

Table 58. I/O AC characteristics

(1)(2)

(continued)

Speed Symbol Parameter Conditions Min Max Unit

C=50 pF, 2.7 V  V

Fmax Maximum frequency

C=50 pF, 1.6 V  V

C=10 pF, 2.7 V  V

C=10 pF, 1.6 V  V

C=50 pF, 2.7 V  V

Tr/Tf Output rise and fall time

C=50 pF, 1.6 V  V

C=10 pF, 2.7 V  V

C=10 pF, 1.6 V  V

C=50 pF, 2.7 V  V

Fmax Maximum frequency

C=50 pF, 1.6 V  V

C=10 pF, 2.7 V  V

C=10 pF, 1.6 V  V

C=50 pF, 2.7 V  V

Tr/Tf Output rise and fall time

C=50 pF, 1.6 V  V

C=10 pF, 2.7 V  V

C=10 pF, 1.6 V  V

C=30 pF, 2.7 V  V

Fmax Maximum frequency

C=30 pF, 1.6 V  V

C=10 pF, 2.7 V  V

C=10 pF, 1.6 V  V

C=30 pF, 2.7 V  V

Tr/Tf Output rise and fall time

C=30 pF, 1.6 V  V

C=10 pF, 2.7 V  V

C=10 pF, 1.6 V  V

Fm+

1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the SYSCFG_CFGR1 register. Refer to the RM0444 reference manual for a description of GPIO Port configuration register.

2. Guaranteed by design.

3. This value represents the I/O capability but the maximum system frequency is limited to 64 MHz.

4. The fall time is defined between 70% and 30% of the output waveform, according to I

Fmax Maximum frequency

Tf Output fall time

(4)

C=50 pF, 1.6 V  V

 3.6 V - 10

DDIOx

 2.7 V - 2

DDIOx

 3.6 V - 15

DDIOx

 2.7 V - 2.5

DDIOx

 3.6 V - 30

DDIOx

 2.7 V - 60

DDIOx

 3.6 V - 15

DDIOx

 2.7 V - 30

DDIOx

 3.6 V - 30

DDIOx

 2.7 V - 15

DDIOx

 3.6 V - 60

DDIOx

 2.7 V - 30

DDIOx

 3.6 V - 11

DDIOx

 2.7 V - 22

DDIOx

 3.6 V - 4

DDIOx

 2.7 V - 8

DDIOx

 3.6 V - 60

DDIOx

 2.7 V - 30

DDIOx

 3.6 V - 80

DDIOx

 2.7 V - 40

DDIOx

 3.6 V - 5.5

DDIOx

 2.7 V - 11

DDIOx

 3.6 V - 2.5

DDIOx

 2.7 V - 5

DDIOx

 3.6 V

DDIOx

C specification.

MHz

(3)

-1MHz

-5ns

98/159 DS13560 Rev 1

STM32G0B1xB/C/xE Electrical characteristics

MS32132V2

10%

50%

90%

10%

50%

90%

Maximum frequency is achieved if (t + t (≤ 2/3)T and if the duty cycle is (45-55%)

when loaded by the specified capacitance.

r(IO)out

f(IO)out

Figure 26. I/O AC characteristics definition

1. Refer to Table 58: I/O AC characteristics.

5.3.15 NRST input characteristics

The NRST input driver uses CMOS technology. It is connected to a permanent pull-up resistor, R

Unless otherwise specified, the parameters given in the following table are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 24: General operating conditions.

Table 59. NRST pin characteristics

(1)

Symbol Parameter Conditions Min Typ Max Unit

IL(NRST)

IH(NRST)

hys(NRST)

F(NRST)

NF(NRST)

1. Guaranteed by design.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimal (~10% order)

NRST input low level voltage

NRST input high level voltage

NRST Schmitt trigger voltage hysteresis

Weak pull-up equivalent resistor

NRST input filtered pulse

NRST input not filtered pulse

(2)

VIN = V

1.7 V  V

- - - 0.3 x V

- 0.7 x V

DDIO1

--200-mV

25 40 55 k

---70ns

 3.6 V 350 - - ns

DS13560 Rev 1 99/159

124

Electrical characteristics STM32G0B1xB/C/xE

MS19878V3

Internal reset

External

reset circuit

(1)

NRST

(2)

Filter

0.1 μF

Figure 27. Recommended NRST pin protection

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the V

Table 59: NRST pin characteristics. Otherwise the reset will not be taken into account by the device.

3. The external capacitor on NRST must be placed as close as possible to the device.

max level specified in

IL(NRST)

5.3.16 Analog switch booster

Table 60. Analog switch booster characteristics

Symbol Parameter Min Typ Max Unit

SU(BOOST)

DD(BOOST)

1. Guaranteed by design.

Supply voltage 1.62 V - 3.6 V

Booster startup time - - 240 µs

Booster consumption for

1.62 V  V

 2.0 V

Booster consumption for

2.0 V  V

 2.7 V

Booster consumption for

2.7 V  V

 3.6 V

--250

--500

--900

5.3.17 Analog-to-digital converter characteristics

Unless otherwise specified, the parameters given in Table 61 are preliminary values derived from tests performed under ambient temperature, f conditions summarized in Table 24: General operating conditions.

Note: It is recommended to perform a calibration after each power-up.

Symbol Parameter Conditions

Table 61. ADC characteristics

(2)

frequency and V

PCLK

(1)

Min Typ Max Unit

(1)

supply voltage

DDA

µA

DDA

REF+

100/159 DS13560 Rev 1

Analog supply voltage - 1.62 - 3.6 V

Positive reference

voltage

 2 V 2 - V

DDA

< 2 V V

DDA

ST MICROELECTRONICS STM32G0B1RET6 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Table 1. Device summary

1 Introduction

2 Description

Figure 1. Block diagram

3 Functional overview

3.1 Arm® Cortex®-M0+ core with MPU

3.2 Memory protection unit

3.3 Embedded Flash memory

Table 3. Access status versus readout protection level and execution modes

3.3.1 Securable area

3.4 Embedded SRAM

3.5 Boot modes

3.6 Cyclic redundancy check calculation unit (CRC)

3.7 Power supply management

3.7.1 Power supply schemes

Figure 2. Power supply overview

3.7.2 Power supply supervisor

3.7.3 Voltage regulator

3.7.4 Low-power modes

3.7.5 Reset mode

3.7.6 VBAT operation

3.8 Interconnect of peripherals

Table 4. Interconnect of peripherals

3.9 Clocks and startup

3.10 General-purpose inputs/outputs (GPIOs)

3.11 Direct memory access controller (DMA)

3.12 DMA request multiplexer (DMAMUX)

3.13 Interrupts and events

3.13.1 Nested vectored interrupt controller (NVIC)

3.13.2 Extended interrupt/event controller (EXTI)

3.14 Analog-to-digital converter (ADC)

3.14.1 Temperature sensor

Table 5. Temperature sensor calibration values

Table 6. Internal voltage reference calibration values

3.15 Digital-to-analog converter (DAC)

3.16 Voltage reference buffer (VREFBUF)

3.17 Comparators (COMP)

3.18 Timers and watchdogs

3.18.1 Advanced-control timer (TIM1)

3.18.2 General-purpose timers (TIM2, 3, 4, 14, 15, 16, 17)

3.18.3 Basic timers (TIM6 and TIM7)

3.18.4 Low-power timers (LPTIM1 and LPTIM2)

3.18.5 Independent watchdog (IWDG)

3.18.6 System window watchdog (WWDG)

3.18.7 SysTick timer

3.19 Real-time clock (RTC), tamper (TAMP) and backup registers

3.20 Inter-integrated circuit interface (I2C)

3.21 Universal synchronous/asynchronous receiver transmitter (USART)

Table 9. USART implementation

3.22 Low-power universal asynchronous receiver transmitter (LPUART)

3.23 Serial peripheral interface (SPI)

Table 10. SPI/I2S implementation

3.24 Universal serial bus device (USB) and host (USBH)

3.25 USB Type-C™ Power Delivery controller

3.26 Controller area network (FDCAN)

3.27 Development support

3.27.1 Serial wire debug port (SW-DP)

4 Pinouts, pin description and alternate functions

Figure 3. STM32G0B1VxT LQFP100 pinout

Figure 4. STM32G0B1VxI UFBGA100 pinout

Figure 5. STM32G0B1MxT LQFP80 pinout

Figure 6. STM32G0B1RxT LQFP64 pinout

Figure 7. STM32G0B1RxI UFBGA64 pinout

Figure 8. STM32G0B1NxY WLCSP52 pinout

Figure 9. STM32G0B1CxT LQFP48 pinout

Figure 10. STM32G0B1CxU UFQFPN48 pinout

Figure 11. STM32G0B1KxT LQFP32 pinout

Figure 12. STM32G0B1KxU UFQFPN32 pinout

Table 11. Terms and symbols used in Table 12

Table 13. Port A alternate function mapping (AF0 to AF7)

Table 14. Port A alternate function mapping (AF8 to AF15)

Table 16. Port B alternate function mapping (AF8 to AF15)

Table 17. Port C alternate function mapping

Table 18. Port D alternate function mapping

Table 19. Port E alternate function mapping

Table 20. Port F alternate function mapping