ST MICROELECTRONICS STM32G081RBT6 Datasheet

STM32G081xB

LQFP64

UFQFPN48

UFQFPN32

UFQFPN28

LQFP48

LQFP32

WLCSP25

2.3 × 2.5 mm

UFBGA64

5

×

5mm

10

×

10 mm

7

×

7mm

7

×

7mm

7 × 7 mm

5×5mm

4×4mm

Arm® Cortex®-M0+ 32-bit MCU, 128 KB Flash, 36 KB RAM,

4x USART, timers, ADC, DAC, comm. I/Fs, AES, RNG, 1.7-3.6V

Datasheet - production data

Features

• Core: Arm® 32-bit Cortex®-M0+ CPU,
frequency up to 64 MHz

• -40°C to 85°C/125°C operating temperature

• Memories

– 128 Kbytes of Flash memory
– 36 Kbytes of SRAM (32 Kbytes with HW

parity check)

• CRC calculation unit

• Reset and power management

– Voltage range: 1.7 V to 3.6 V
– Power-on/Power-down reset (POR/PDR)
– Programmable Brownout reset (BOR)
– Programmable voltage detector (PVD)
– Low-power modes:

Sleep, Stop, Standby, Shutdown

–V

supply for RTC and backup registers

BAT

• Clock management
– 4 to 48 MHz crystal oscillator
– 32 kHz crystal oscillator with calibration
– Internal 16 MHz RC with PLL option (±1 %)
– Internal 32 kHz RC oscillator (±5 %)

• Up to 60 fast I/Os
– All mappable on external interrupt vectors
– Multiple 5 V-tolerant I/Os

• 7-channel DMA controller with flexible mapping

• 12-bit, 0.4 µs ADC (up to 16 ext. channels)

– Up to 16-bit with hardware oversampling
– Conversion range: 0 to 3.6V

• Two 12-bit DACs, low-power sample-and-hold

• Two fast low-power analog comparators, with

programmable input and output, rail-to-rail

• 14 timers (two 128 MHz capable): 16-bit for
advanced motor control, one 32-bit and five 16­bit general-purpose, two basic 16-bit, two low­power 16-bit, two watchdogs, SysTick timer

• Calendar RTC with alarm and periodic wakeup
from Stop/Standby/Shutdown

• Communication interfaces
–Two I

2

C-bus interfaces supporting Fast­mode Plus (1 Mbit/s) with extra current
sink, one supporting SMBus/PMBus and
wakeup from Stop mode

– Four USARTs with master/slave

synchronous SPI; two supporting ISO7816
interface, LIN, IrDA capability, auto baud
rate detection and wakeup feature

– Low-power UART
– Two SPIs (32 Mbit/s) with 4- to 16-bit

programmable bitframe, one multiplexed

2

with I

S interface

– HDMI CEC interface, wakeup on header

reception

• USB Type-C™ Power Delivery controller

• True random number generator (RNG)

• AES: 128/256-bit key encryption hardware

accelerator

• Development support: serial wire debug (SWD)

• 96-bit unique ID

• All packages ECOPACK

Reference Part number

STM32G081xB

Table 1. Device summary

STM32G081RB, STM32G081CB,

STM32G081KB, STM32G081GB,

®

2 compliant

STM32G081EB

November 2018 DS12231 Rev 2 1/137

This is information on a product in full production.

www.st.com

Contents STM32G081xB

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.1 Arm® Cortex®-M0+ core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.5 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.6 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 16

3.7 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.7.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.7.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.7.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.7.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.7.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.7.6 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.8 Interconnect of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.9 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.10 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.11 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.12 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.12.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 23

3.12.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 24

3.13 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.13.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.13.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.13.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.14 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.15 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.16 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

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3.17 Random-number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.18 Advanced-encryption-standard (AES) hardware accelerator . . . . . . . . . . 27

3.19 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.19.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.19.2 General-purpose timers (TIM2, TIM3, TIM14, TIM15, TIM16, TIM17) . . 29

3.19.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.19.4 Low-power timers (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . 29

3.19.5 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.19.6 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.19.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.20 Real-time clock (RTC), tamper (TAMP) and backup registers . . . . . . . . . 30

3.21 Inter-integrated circuit interface (I

2

C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.22 Universal synchronous/asynchronous receiver transmitter (USART) . . . 32

3.23 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 33

3.24 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.25 USB Type-C™ Power Delivery controller . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.26 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.26.1 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4 Pinouts, pin description and alternate functions . . . . . . . . . . . . . . . . . 36

5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 58

5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 58

5.3.4 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

DS12231 Rev 2 3/137

5

Contents STM32G081xB

5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.3.6 Wakeup time from low-power modes and voltage scaling

transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

5.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

5.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

5.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

5.3.10 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

5.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

5.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

5.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

5.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

5.3.15 NRST input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

5.3.16 Analog switch booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

5.3.17 Analog-to-digital converter characteristics . . . . . . . . . . . . . . . . . . . . . . . 87

5.3.18 Digital-to-analog converter characteristics . . . . . . . . . . . . . . . . . . . . . . . 95

5.3.19 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . . 99

5.3.20 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

5.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

5.3.22 V

5.3.23 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

5.3.24 Characteristics of communication interfaces . . . . . . . . . . . . . . . . . . . . 103

5.3.25 UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

BAT

6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

6.1 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

6.2 UFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

6.3 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

6.4 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

6.5 LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

6.6 UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

6.7 UFQFPN28 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

6.8 WLCSP25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

6.9 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

6.9.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

6.9.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 133

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STM32G081xB Contents

7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

DS12231 Rev 2 5/137

5

List of tables STM32G081xB

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. STM32G081xB family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . 12

Table 3. Access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 15

Table 4. Interconnect of STM32G081xB peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 5. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 6. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 7. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 8. I

Table 9. USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 10. SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 11. Terms and symbols used in Table 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 12. Pin assignment and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 13. Port A alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 14. Port B alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 15. Port C alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 16. Port D alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 17. Port F alternate function mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 18. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 19. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 20. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 21. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 22. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 23. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 24. Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 25. Current consumption in Run and Low-power run modes

Table 26. Typical current consumption in Run and Low-power run modes,

Table 27. Current consumption in Sleep and Low-power sleep modes . . . . . . . . . . . . . . . . . . . . . . . 64

Table 28. Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 29. Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 30. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 31. Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 32. Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 33. Current consumption of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 34. Low-power mode wakeup times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 35. Regulator mode transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 36. Wakeup time using LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 37. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 38. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 39. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 40. LSE oscillator characteristics (f

Table 41. HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 42. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 43. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 44. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 45. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 46. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

2

C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

at different die temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

depending on code executed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

LSE

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STM32G081xB List of tables

Table 47. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 48. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 49. Electrical sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 50. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 51. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 52. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 53. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 54. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 55. Analog switch booster characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 56. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 57. Maximum ADC R

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

AIN

Table 58. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 59. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 60. DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 61. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 62. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 63. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Table 64. V
Table 65. V

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

BAT

charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

BAT

Table 66. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 67. IWDG min/max timeout period at 32 kHz LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 68. Minimum I2CCLK frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 69. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 70. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 71. I

2

S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 72. USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Table 73. UCPD operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Table 74. LQFP64 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table 75. UFBGA64 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 76. Recommended PCB design rules for UFBGA64 package . . . . . . . . . . . . . . . . . . . . . . . . 115

Table 77. LQFP48 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 78. UFQFPN48 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Table 79. LQFP32 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Table 80. UFQFPN32 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Table 81. UFQFPN28 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Table 82. WLCSP25 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Table 83. Recommended PCB pad design rules for WLCSP25 package . . . . . . . . . . . . . . . . . . . . 131

Table 84. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Table 85. STM32G081xB ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Table 86. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

DS12231 Rev 2 7/137

7

List of figures STM32G081xB

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 2. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 3. STM32G081RxT LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 4. STM32G081RxH UFBGA64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 5. STM32G081CxT LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 6. STM32G081CxU UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 7. STM32G081KxT LQFP32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 8. STM32G081KxU UFQFPN32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 9. STM32G081GxU UFQFPN28 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 10. STM32G081Ex WLCSP25 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 11. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 12. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 13. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 14. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 15. VREFINT vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 16. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 17. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 18. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 19. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 20. HSI16 frequency vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 21. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 22. I/O AC characteristics definition

Figure 23. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 24. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 25. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 26. 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 27. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 28. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 29. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 30. I
Figure 31. I

Figure 32. LQFP64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Figure 33. Recommended footprint for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 34. LQFP64 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 35. UFBGA64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figure 36. Recommended footprint for UFBGA64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 37. UFBGA64 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 38. LQFP48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 39. Recommended footprint for LQFP48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 40. LQFP48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 41. UFQFPN48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 42. Recommended footprint for UFQFPN48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 43. UFQFPN48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Figure 44. LQFP32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Figure 45. Recommended footprint for LQFP32 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 46. LQFP32 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Figure 47. UFQFPN32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Figure 48. Recommended footprint for UFQFPN32 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

2

S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

2

S master timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

8/137 DS12231 Rev 2

STM32G081xB List of figures

Figure 49. UFQFPN32 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Figure 50. UFQFPN28 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Figure 51. Recommended footprint for UFQFPN28 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Figure 52. UFQFPN28 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Figure 53. WLCSP25 chip-scale package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Figure 54. Recommended PCB pad design for WLCSP25 package. . . . . . . . . . . . . . . . . . . . . . . . . 131

Figure 55. WLCSP25 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

DS12231 Rev 2 9/137

9

Introduction STM32G081xB

1 Introduction

This document provides information on STM32G081xB microcontrollers, such as
description, functional overview, pin assignment and definition, electrical characteristics,
packaging, and ordering codes.

Information on memory mapping and control registers is object of reference manual.

Information on Arm

®(a)

Cortex®-M0+ core is available from the www.arm.com website.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

10/137 DS12231 Rev 2

STM32G081xB Description

2 Description

The STM32G081xB mainstream microcontrollers are based on high-performance

®

Arm

Cortex®-M0+ 32-bit RISC core operating at up to 64 MHz frequency. Offering a high
level of integration, they are suitable for a wide range of applications in consumer, industrial
and appliance domains and ready for the Internet of Things (IoT) solutions.

The devices incorporate a memory protection unit (MPU), high-speed embedded memories
(128 Kbytes of Flash program memory and 36 Kbytes of SRAM), DMA and an extensive
range of system functions, enhanced I/Os and peripherals. The devices offer standard
communication interfaces (two I
one 12-bit ADC (2.5 MSps) with up to 19 channels, one 12-bit DAC with two channels, two
fast comparators, an internal voltage reference buffer, a low-power RTC, an advanced
control PWM timer running at up to double the CPU frequency, five general-purpose 16-bit
timers with one running at up to double the CPU frequency, a 32-bit general-purpose timer,
two basic and two low-power 16-bit timers, two watchdog timers, and a SysTick timer. The
STM32G081xB devices provide a fully integrated USB Type-C Power Delivery controller.

The devices embed AES hardware accelerator and true random number generator (RNG).

The devices operate within ambient temperatures from -40 to 125°C. They can operate with
supply voltages from 1.7 V to 3.6 V. Optimized dynamic consumption combined with a
comprehensive set of power-saving modes, low-power timers and low-power UART, allows
the design of low-power applications.

2

Cs, two SPIs / one I2S, one HDMI CEC and four USARTs),

VBAT direct battery input allows keeping RTC and backup registers powered.

The devices come in packages with 28 to 64 pins.

DS12231 Rev 2 11/137

35

Description STM32G081xB

Table 2. STM32G081xB family device features and peripheral counts

STM32G081_

Peripheral

_EB _GB

Flash memory (Kbyte) 128

SRAM (Kbyte) 32 (with parity) or 36 (without parity)

Advanced control 1 (16-bit) high frequency

General-purpose 4 (16-bit) + 1 (16-bit) high frequency + 1 (32-bit)

Basic 2 (16-bit)

Timers

Low-power 2 (16-bit)

SysTick 1

Watchdog 2

SPI [I2S]

(1)

2

I

C2

USART 4

LPUART 1

(2)

Comm. interfaces

UCPD

CEC 1

RTC Yes

Tamper pins 2

Random number generator Yes

AES Yes

GPIOs 2326 304460

Wakeup pins 4 3 4 3 4 5

12-bit ADC channels

10 ext.
+ 2 int.

12-bit DAC channels 2

Internal voltage reference buffer No Yes

_GB

xxN

2

9 ext.

+ 2 int.

_KB

2 [1]

(2)

11 ext.
+ 2 int.

_KB

xxN

10 ext.
+ 2 int.

_CB _RB

2

14 ext.
+ 3 int.

16 ext.
+ 3 int.

Analog comparators 2

Max. CPU frequency 64 MHz

Operating voltage 1.7 to 3.6 V

Operating temperature

(3)

Ambient: -40 to 85 °C / -40 to 125 °C

Junction: -40 to 105 °C / -40 to 130 °C

Number of pins 25 28 32 48 64

1. The numbers in brackets denote the count of SPI interfaces configurable as I2S interface.

2. One port with only one CC line available (supporting limited number of use cases).

3. Depends on order code. Refer to Section 7: Ordering information for details.

12/137 DS12231 Rev 2

STM32G081xB Description

MSv42181V2

UCPD

AES

RNG

USART3/4

USART1/2

LPTIMER 1/2

TIMER 16/17

Power domain of analog blocks :

V

BAT

4 channels
BKIN, BKIN2, ETR

System and

peripheral

clocks

PAx

PBx

PCx

PFx

MOSI/SD

MISO/MCK

SCK/CK

NSS/WS

SWCLK
SWDIO

16x IN

OSC_IN
OSC_OUT

VBAT

OSC32_IN
OSC32_OUT

RTC_OUT
RTC_REFIN
RTC_TS

MOSI, MISO

SCK, NSS

HSI16

LSI

PLLPCLK

V

DD

IR_OUT

1 channel
BKIN

ETR, IN, OUT

1 channel

4 channels
ETR

4 channels
ETR

CPU

CORTEX-M0+

f

max

= 64 MHz

SWD

NVIC

EXTI

SPI1/I2S

SPI2

AHB-to-APB

RCC

Reset & clock control

I/F

XTAL OSC

4-48 MHz

IWDG

SRAM
36 KB

I/F

ADC

RTC, TAMP

Backup regs

I/F

RC 16 MHz

RC 32 kHz

PLL

decoder

XTAL32 kHz

Bus matrix

I/F

V

DD

2 channels
BKIN

RX, TX
CTS, RTS, CK

RX, TX
CTS, RTS, CK

CEC

TIM6

TIM7

COMP1

COMP2

IN+, IN-,

OUT

Port D

Port C

Port B

Port A

V

DDA

SUPPLY

SUPERVISION

POWER

V

CORE

POR

Reset

Int

VDD/VDDA
VSS/VSSA

NRST

PVD

POR/BOR

Voltage

regulator

USART3 & 4

USART1 & 2

LPTIM1 & 2

TIM16 & 17

TIM15

TIM14

TIM3

TIM2 (32-bit)

TIM1

GPIOs

IOPORT

HSE

PLLQCLK
PLLRCLK

LSE

LSE

T sensor

RX, TX,
CTS, RTS

LPUART

TAMP_IN

APB

APB

AHB

CC, DBCC

FRSTX

UCPD1 & 2

HDMI-CEC

VREFBUF

DAC

I/F

DAC_OUT1

DAC_OUT2

CRC

VREF+

SCL, SDA

SCL, SDA
SMBA, SMBUS

I2C1

I2C2

DBGMCU

WWDG

PWRCTRL

SYSCFG

DMA

DMAMUX

Port F

PDx

V

DDA

V

DDIO1

Low-voltage

detector

V

DD

Parity

Flash memory

up to 128 KB

V

DDIO1

IRTIM

from peripherals

Figure 1. Block diagram

DS12231 Rev 2 13/137

35

Functional overview STM32G081xB

3 Functional overview

3.1 Arm® Cortex®-M0+ core with MPU

The Cortex-M0+ is an entry-level 32-bit Arm Cortex processor designed for a broad range of
embedded applications. It offers significant benefits to developers, including:

• a simple architecture, easy to learn and program

• ultra-low power, energy-efficient operation

• excellent code density

• deterministic, high-performance interrupt handling

• upward compatibility with Cortex-M processor family

• platform security robustness, with integrated Memory Protection Unit (MPU).

The Cortex-M0+ processor is built on a highly area- and power-optimized 32-bit core, with a
2-stage pipeline Von Neumann architecture. The processor delivers exceptional energy
efficiency through a small but powerful instruction set and extensively optimized design,
providing high-end processing hardware including a single-cycle multiplier.

The Cortex-M0+ processor provides the exceptional performance expected of a modern
32-bit architecture, with a higher code density than other 8-bit and 16-bit microcontrollers.

Owing to embedded Arm core, the STM32G081xB devices are compatible with Arm tools
and software.

The Cortex-M0+ is tightly coupled with a nested vectored interrupt controller (NVIC)
described in Section 3.12.1.

3.2 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task.

The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real­time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

3.3 Embedded Flash memory

STM32G081xB devices feature 128 Kbytes of embedded Flash memory available for
storing code and data.

14/137 DS12231 Rev 2

STM32G081xB Functional overview

Flexible protections can be configured thanks to option bytes:

• Readout protection (RDP) to protect the whole memory. Three levels are available:

– Level 0: no readout protection

– Level 1: memory readout protection: the Flash memory cannot be read from or

written to if either debug features are connected, boot in RAM or bootloader is
selected

– Level 2: chip readout protection: debug features (Cortex-M0+ serial wire), boot in

RAM and bootloader selection are disabled. This selection is irreversible.

Table 3. Access status versus readout protection level and execution modes

Area

User

memory

System

memory

Option

bytes

Backup

registers

1. Erased upon RDP change from Level 1 to Level 0.

Protection

level

1 Yes Yes Yes No No No

2 Yes Yes Yes N/A N/A N/A

1 Yes No No Yes No No

2 Yes No No N/A N/A N/A

1 Yes Yes Yes Yes Yes Yes

2 Yes No No N/A N/A N/A

1YesYesN/A

2 Yes Yes N/A N/A N/A N/A

User execution

Read Write Erase Read Write Erase

(1)

Debug, boot from RAM or boot

from system memory (loader)

No No N/A

• Write protection (WRP): the protected area is protected against erasing and

programming. Two areas per bank can be selected, with 2-Kbyte granularity.

• Proprietary code readout protection (PCROP): a part of the Flash memory can be

protected against read and write from third parties. The protected area is execute-only:
it can only be reached by the STM32 CPU as instruction code, while all other accesses
(DMA, debug and CPU data read, write and erase) are strictly prohibited. An additional
option bit (PCROP_RDP) determines whether the PCROP area is erased or not when
the RDP protection is changed from Level 1 to Level 0.

(1)

The whole non-volatile memory embeds the error correction code (ECC) feature supporting:

• single error detection and correction

• double error detection

• readout of the ECC fail address from the ECC register

3.4 Embedded SRAM

STM32G081xB devices have 32 Kbytes of embedded SRAM with parity. Hardware parity
check allows memory data errors to be detected, which contributes to increasing functional
safety of applications.

When the parity protection is not required because the application is not safety-critical, the
parity memory bits can be used as additional SRAM, to increase its total size to 36 Kbytes.

The memory can be read/write-accessed at CPU clock speed, with 0 wait states.

DS12231 Rev 2 15/137

35

Functional overview STM32G081xB

3.5 Boot modes

At startup, the boot pin and boot selector option bit are used to select one of the three boot
options:

• boot from User Flash memory

• boot from System memory

• boot from embedded SRAM

The boot pin is shared with a standard GPIO and can be disabled through the boot selector
option bit. The boot loader is located in System memory. It manages the Flash memory
reprogramming through USART on pins PA9/PA10, PC10/PC11 or PA2/PA3, through I

2

C­bus on pins PB6/PB7 or PB10/PB11, or through SPI on pins PA4/PA5/PA6/PA7 or
PB12/PB13/PB14/PB15.

3.6 Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.

Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link
time and stored at a given memory location.

3.7 Power supply management

3.7.1 Power supply schemes

The STM32G081xB devices require a 1.7 V to 3.6 V operating supply voltage (VDD).
Several different power supplies are provided to specific peripherals:

• V

• V

• V

• V

= 1.7 (2.0) to 3.6 V

DD

V

is the external power supply for the internal regulator and the system analog such

DD

as reset, power management and internal clocks. It is provided externally through
VDD/VDDA pin.

The minimum voltage of 1.7 V corresponds to power-on reset release threshold
V

POR(MAX)

. Once this threshold is crossed and power-on reset is released, the

functionality is guaranteed down to power-down reset threshold V

= 2.0 V (ADC and COMP) / 1.8 V (DAC) / 2.4 V (VREFBUF) to 3.6 V

DDA

V

is the analog power supply for the A/D converter, D/A converter, voltage

DDA

reference buffer and comparators. V
provided externally through VDD/VDDA pin.

= V

DDIO1

V

DDIO1

DD

is the power supply for the I/Os. V

as it is provided externally through VDD/VDDA pin.

= 1.55 V to 3.6 V

BAT

V

is the power supply (through a power switch) for RTC, TAMP, low-speed external

BAT

32.768 kHz oscillator and backup registers when V

PDR(MIN)

voltage level is identical to VDD voltage as it is

DDA

voltage level is identical to VDD voltage

DDIO1

is not present. V

DD

.

is provided

BAT

16/137 DS12231 Rev 2

STM32G081xB Functional overview

MSv39736V2

V

DDA

domain

RTC domain

D/A converter

A/D converter

Standby circuitry

(Wakeup, IWDG)

Voltage

regulator

Core

SRAM

Digital

peripherals

Low-voltage

detector

LSE crystal 32.768 kHz osc

BKP registers

RCC BDCR register

RTC and TAMP

2 x comparator

Voltage reference buffer

I/O ring

V

CORE

domain

Temp. sensor

Reset block

PLL, HSI

Flash memory

V

DDIO1

VREF+

V

DD

domain

V

CORE

VSS/VSSA

VDD/VDDA

VBAT

V

DDA

V

REF+

V

SSA

V

SS

V

DD

V

DDIO1

domain

externally through VBAT pin. When this pin is not available on the package, VBAT
bonding pad is internally bonded to the VDD/VDDA pin.

• V

is the input reference voltage for the ADC and DAC, or the output of the internal

REF+

voltage reference buffer (when enabled). When V
V

. When V

DDA

DDA

≥ 2 V, V

must be between 2 V and V

REF+

DDA

< 2 V, V

must be equal to

REF+

. It can be grounded

DDA

when the ADC and DAC are not active.

The internal voltage reference buffer supports two output voltages, which is configured
with VRS bit of the VREFBUF_CSR register:

–V

–V

V

REF+

internally connected with V

around 2.048 V (requiring V

REF+

around 2.5 V (requiring V

REF+

equal to or higher than 2.4 V)

DDA

equal to or higher than 2.8 V)

DDA

is delivered through VREF+ pin. On packages without VREF+ pin, V

, and the internal voltage reference buffer must be kept

DD

REF+

is

disabled (refer to datasheets for package pinout description).

• V

CORE

An embedded linear voltage regulator is used to supply the V
power. V
The Flash memory is also supplied with V

is the power supply for digital peripherals, SRAM and Flash memory.

CORE

DD

.

internal digital

CORE

Figure 2. Power supply overview

3.7.2 Power supply supervisor

The device has an integrated power-on/power-down (POR/PDR) reset active in all power
modes except Shutdown and ensuring proper operation upon power-on and power-down. It
maintains the device in reset when the supply voltage is below V
the need for an external reset circuit. Brownout reset (BOR) function allows extra flexibility. It

POR/PDR

threshold, without

DS12231 Rev 2 17/137

35

Functional overview STM32G081xB

can be enabled and configured through option bytes, by selecting one of four thresholds for
rising V

and other four for falling VDD.

DD

The device also features an embedded programmable voltage detector (PVD) that monitors
the V
when V

power supply and compares it to V

DD

level crosses the V

DD

threshold, selectively while falling, while rising, or while

PVD

threshold. It allows generating an interrupt

PVD

falling and rising. The interrupt service routine can then generate a warning message and/or
put the MCU into a safe state. The PVD is enabled by software.

3.7.3 Voltage regulator

Two embedded linear voltage regulators, main regulator (MR) and low-power regulator
(LPR), supply most of digital circuitry in the device.

The MR is used in Run and Sleep modes. The LPR is used in Low-power run, Low-power
sleep and Stop modes.

In Standby and Shutdown modes, both regulators are powered down and their outputs set in
high-impedance state, such as to bring their current consumption close to zero. However,
SRAM data retention is possible in Standby mode, in which case the LPR remains active
and it only supplies the SRAM.

3.7.4 Low-power modes

By default, the microcontroller is in Run mode after system or power reset. It is up to the
user to select one of the low-power modes described below:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.

• Low-power run mode

This mode is achieved with V

supplied by the low-power regulator to minimize the

CORE

regulator's operating current. The code can be executed from SRAM or from Flash,
and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can
be clocked by HSI16.

• Low-power sleep mode

This mode is entered from the low-power run mode. Only the CPU clock is stopped.
When wakeup is triggered by an event or an interrupt, the system reverts to the Low­power run mode.

• Stop 0 and Stop 1 modes

In Stop 0 and Stop 1 modes, the device achieves the lowest power consumption while
retaining the SRAM and register contents. All clocks in the V

domain are stopped.

CORE

The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are
disabled. The LSE or LSI keep running. The RTC can remain active (Stop mode with
RTC, Stop mode without RTC).

Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode,
so as to get clock for processing the wakeup event. The main regulator remains active
in Stop 0 mode while it is turned off in Stop 1 mode.

• Standby mode

The Standby mode is used to achieve the lowest power consumption, with POR/PDR
always active in this mode. The main regulator is switched off to power down V

CORE

domain. The low-power regulator is either switched off or kept active. In the latter case,

18/137 DS12231 Rev 2

STM32G081xB Functional overview

it only supplies SRAM to ensure data retention. The PLL, as well as the HSI16 RC
oscillator and the HSE crystal oscillator are also powered down. The RTC can remain
active (Standby mode with RTC, Standby mode without RTC).

For each I/O, the software can determine whether a pull-up, a pull-down or no resistor
shall be applied to that I/O during Standby mode.

Upon entering Standby mode, register contents are lost except for registers in the RTC
domain and standby circuitry. The SRAM contents can be retained through register
setting.

The device exits Standby mode upon external reset event (NRST pin), IWDG reset
event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event
(alarm, periodic wakeup, timestamp, tamper), or when a failure is detected on LSE
(CSS on LSE).

• Shutdown mode

The Shutdown mode allows to achieve the lowest power consumption. The internal
regulator is switched off to power down the V

domain. The PLL, as well as the

CORE

HSI16 and LSI RC-oscillators and HSE crystal oscillator are also powered down. The
RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).

The BOR is not available in Shutdown mode. No power voltage monitoring is possible
in this mode. Therefore, switching to RTC domain is not supported.

SRAM and register contents are lost except for registers in the RTC domain.

The device exits Shutdown mode upon external reset event (NRST pin), IWDG reset
event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event
(alarm, periodic wakeup, timestamp, tamper).

3.7.5 Reset mode

During and upon exiting reset, the schmitt triggers of I/Os are disabled so as to reduce
power consumption. In addition, when the reset source is internal, the built-in pull-up
resistor on NRST pin is deactivated.

3.7.6 VBAT operation

The V
backup registers.

In VBAT mode, the RTC domain is supplied from VBAT pin. The power source can be, for
example, an external battery or an external supercapacitor. Two anti-tamper detection pins
are available.

The RTC domain can also be supplied from VDD/VDDA pin.

By means of a built-in switch, an internal voltage supervisor allows automatic switching of
RTC domain powering between V
voltage of the RTC domain (V
are valid, the RTC domain is supplied from VDD/VDDA pin.

An internal circuit for charging the battery on VBAT pin can be activated if the V
within a valid range.

Note: External interrupts and RTC alarm/events cannot cause the microcontroller to exit the VBAT

mode, as in that mode the V

power domain, consuming very little energy, includes RTC, and LSE oscillator and

BAT

and voltage from VBAT pin to ensure that the supply

DD

) remains within valid operating conditions. If both voltages

BAT

voltage is

DD

is not within a valid range.

DD

DS12231 Rev 2 19/137

35

Functional overview STM32G081xB

3.8 Interconnect of peripherals

Several peripherals have direct connections between them. This allows autonomous
communication between peripherals, saving CPU resources thus power supply
consumption. In addition, these hardware connections allow fast and predictable latency.

Depending on peripherals, these interconnections can operate in Run, Sleep and Stop
modes.

Table 4. Interconnect of STM32G081xB peripherals

Interconnect source

TIMx

COMPx

ADCx TIM1 Timer triggered by analog watchdog Y Y -

RTC

All clocks sources (internal

and external)

CSS

RAM (parity error)

Flash memory (ECC error)

COMPx

PVD

Interconnect

destination

TIMx Timer synchronization or chaining Y Y -

ADCx
DACx

DMA Memory-to-memory transfer trigger Y Y -

COMPx Comparator output blanking Y Y -

TIM1,2,3

LPTIMERx

TIM16 Timer input channel from RTC events Y Y -

LPTIMERx

TIM14,16,17

TIM1,15,16,17 Timer break Y Y -

Conversion triggers Y Y -

Timer input channel, trigger, break
from analog signals comparison

Low-power timer triggered by analog
signals comparison

Low-power timer triggered by RTC
alarms or tampers

Clock source used as input channel for
RC measurement and trimming

Interconnect action

Run

YY -

YYY

YYY

YY -

Sleep

Low-power run

Low-power sleep

Stop

CPU (hard fault) TIM1,15,16,17 Timer break Y - -

TIMx External trigger Y Y -

GPIO

20/137 DS12231 Rev 2

LPTIMERx External trigger Y Y Y

ADC

DACx

Conversion external trigger Y Y -

STM32G081xB Functional overview

3.9 Clocks and startup

The clock controller distributes the clocks coming from different oscillators to the core and
the peripherals. It also manages clock gating for low-power modes and ensures clock
robustness. It features:

• Clock prescaler: to get the best trade-off between speed and current consumption,

the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler

• Safe clock switching: clock sources can be changed safely on the fly in run mode

through a configuration register.

• Clock management: to reduce power consumption, the clock controller can stop the

clock to the core, individual peripherals or memory.

• System clock source: three different sources can deliver SYSCLK system clock:

– 4-48 MHz high-speed oscillator with external crystal or ceramic resonator (HSE). It

can supply clock to system PLL. The HSE can also be configured in bypass mode
for an external clock.

– 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software. It can

supply clock to system PLL.

– System PLL with maximum output frequency of 64 MHz. It can be fed with HSE or

HSI16 clocks.

• Auxiliary clock source: two ultra-low-power clock sources for the real-time clock

(RTC):

– 32.768 kHz low-speed oscillator with external crystal (LSE), supporting four drive

capability modes. The LSE can also be configured in bypass mode for using an
external clock.

– 32 kHz low-speed internal RC oscillator (LSI) with ±5% accuracy, also used to

clock an independent watchdog.

• Peripheral clock sources: several peripherals (RNG, I2S, USARTs, I2Cs, LPTIMs,

ADC) have their own clock independent of the system clock.

• Clock security system (CSS): in the event of HSE clock failure, the system clock is

automatically switched to HSI16 and, if enabled, a software interrupt is generated. LSE
clock failure can also be detected and generate an interrupt. The CCS feature can be
enabled by software.

• Clock output:

– MCO (microcontroller clock output) provides one of the internal clocks for

external use by the application

– LSCO (low speed clock output) provides LSI or LSE in all low-power modes

(except in VBAT operation).

Several prescalers allow the application to configure AHB and APB domain clock
frequencies, 64 MHz at maximum.

3.10 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function (AF). Most of
the GPIO pins are shared with special digital or analog functions.

DS12231 Rev 2 21/137

35

Functional overview STM32G081xB

Through a specific sequence, this special function configuration of I/Os can be locked, such
as to avoid spurious writing to I/O control registers.

3.11 Direct memory access controller (DMA)

Direct memory access (DMA) controller transfers data from a source to a destination,
without making it transit through the CPU. DMA transfers are highly efficient; they save CPU
resources and facilitate time-critical processing.

The source and the destination of a DMA transfer can be a peripheral or a memory.

The DMA transfer source and destination data types can be programmed independently. If
different, the DMA controller performs data type conversion and adapts the addressing at
the source and at the destination to their respective data types.

DMA transfer size is the number of DMA transfer cycles to execute, programmable by
software. One cycle transfers one data item of selected data type from the DMA transfer
source to the DMA transfer destination. The DMA transfer starts at pre-programmed source
and destination base addresses. It ends at source and destination addresses that depend
on the DMA transfer size, source and destination data types, and on activation of address
auto-increment operation.

The DMA transfer starts upon a request from a peripheral or, in the specific case of memory­to-memory transfer, it starts when enabled by software.

The DMA controller executes one DMA transfer cycle per DMA transfer request from a
peripheral, until the total number of cycles reaches the pre-programmed DMA transfer size.
The circular mode of operation allows to repeat the DMA transfer infinitely, without software
intervention.

In the specific case of memory-to-memory transfer, the DMA controller executes, if enabled
by the software, the pre-programmed amount of cycles.

The DMA controller provides distinct DMA transfer channels. The channels can be
individually configured in term of source and destination location, DMA transfer size, data
type, priority level and operating mode. The DMA controller opens one channel at a time,
according to channel priorities.

Features of the DMA controller:

• 7 DMA transfer channels, independently configurable by software

• Per-channel DMA transfer trigger upon request from a peripheral

• Per-channel DMA transfer triggered by software (memory-to-memory mode)

• Programmable channel priority levels: very high, high, medium and low

• By-default (hardware) channel priority levels, to arbitrate concurrent requests from

channels with identical programmable priority levels

• Byte (8-bit unit), half-word (16-bit unit) and word (32-bit unit) DMA transfer data types,

programmable independently for the source and the destination

22/137 DS12231 Rev 2

STM32G081xB Functional overview

• Automatic alignment of DMA transfer source and destination addresses according to

their respective data types

• Circular operating mode support

• DMA Half Transfer, DMA Transfer Complete and DMA Transfer Error flags, logically

OR-ed together in a single interrupt request per channel

• Memory-to-memory, peripheral-to-memory, memory-to-peripheral and peripheral-to-

peripheral DMA transfer types

• DMA transfer size programmable up to 65535 DMA transfer cycles

• Access to Flash memory, SRAM, APB and AHB peripherals as source and destination

3.12 Interrupts and events

The device flexibly manages events causing interrupts of linear program execution, called
exceptions. The Cortex-M0+ processor core, a nested vectored interrupt controller (NVIC)
and an extended interrupt/event controller (EXTI) are the assets contributing to handling the
exceptions. Exceptions include core-internal events such as, for example, a division by zero
and, core-external events such as logical level changes on physical lines. Exceptions result
in interrupting the program flow, executing an interrupt service routine (ISR) then resuming
the original program flow.

The processor context (contents of program pointer and status registers) is stacked upon
program interrupt and unstacked upon program resume, by hardware. This avoids context
stacking and unstacking in the interrupt service routines (ISRs) by software, thus saving
time, code and power. The ability to abandon and restart load-multiple and store-multiple
operations significantly increases the device’s responsiveness in processing exceptions.

3.12.1 Nested vectored interrupt controller (NVIC)

The configurable nested vectored interrupt controller is tightly coupled with the core. It
handles physical line events associated with a non-maskable interrupt (NMI) and maskable
interrupts, and Cortex-M0+ exceptions. It provides flexible priority management.

The tight coupling of the processor core with NVIC significantly reduces the latency between
interrupt events and start of corresponding interrupt service routines (ISRs). The ISR
vectors are listed in a vector table, stored in the NVIC at a base address. The vector
address of an ISR to execute is hardware-built from the vector table base address and the
ISR order number used as offset.

If a higher-priority interrupt event happens while a lower-priority interrupt event occurring
just before is waiting for being served, the later-arriving higher-priority interrupt event is
served first. Another optimization is called tail-chaining. Upon a return from a higher-priority
ISR then start of a pending lower-priority ISR, the unnecessary processor context
unstacking and stacking is skipped. This reduces latency and contributes to power
efficiency.

DS12231 Rev 2 23/137

35

Functional overview STM32G081xB

Features of the NVIC:

• Low-latency interrupt processing

• 4 priority levels

• Handling of a non-maskable interrupt (NMI)

• Handling of 32 maskable interrupt lines

• Handling of 10 Cortex-M0+ exceptions

• Later-arriving higher-priority interrupt processed first

• Tail-chaining

• Interrupt vector retrieval by hardware

3.12.2 Extended interrupt/event controller (EXTI)

The extended interrupt/event controller adds flexibility in handling physical line events and
allows identifying wake-up events at processor wakeup from Stop mode.

The EXTI controller has 33 channels, of which 16 with rising, falling or rising and falling edge
detector capability. Any GPIO and a few peripheral signals can be connected to these
channels.

The channels can be independently masked.

The EXTI controller can capture pulses shorter than the internal clock period.

A register in the EXTI controller latches every event even in Stop mode, which allows the
software to identify the origin of the processor's wake-up from Stop mode or, to identify the
GPIO and the edge event having caused an interrupt.

3.13 Analog-to-digital converter (ADC)

A native 12-bit analog-to-digital converter is embedded into STM32G081xB devices. It can
be extended to 16-bit resolution through hardware oversampling. The ADC has up to 16
external channels and 3 internal channels (temperature sensor, voltage reference, V
monitoring). It performs conversions in single-shot or scan mode. In scan mode, automatic
conversion is performed on a selected group of analog inputs.

The ADC frequency is independent from the CPU frequency, allowing maximum sampling
rate of ~2 MSps even with a low CPU speed. An auto-shutdown function guarantees that
the ADC is powered off except during the active conversion phase.

The ADC can be served by the DMA controller. It can operate in the whole V
range.

The ADC features a hardware oversampler up to 256 samples, improving the resolution to
16 bits (refer to AN2668).

An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all scanned channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.

supply

DD

BAT

The events generated by the general-purpose timers (TIMx) can be internally connected to
the ADC start triggers, to allow the application to synchronize A/D conversions with timers.

24/137 DS12231 Rev 2

STM32G081xB Functional overview

3.13.1 Temperature sensor

The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature.

The temperature sensor is internally connected to an ADC input to convert the sensor
output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor may
vary from part to part due to process variation, the uncalibrated internal temperature sensor
is suitable only for relative temperature measurements.

To improve the accuracy of the temperature sensor, each part is individually factory­calibrated by ST. The resulting calibration data are stored in the part’s System memory,
accessible in read-only mode.

Calibration value name Description Memory address

TS_CAL1

TS_CAL2

Table 5. Temperature sensor calibration values

TS ADC raw data acquired at a
temperature of 30 °C (± 5 °C),
V

= V

DDA

TS ADC raw data acquired at a
temperature of 130 °C (± 5 °C),
V

= V

DDA

= 3.0 V (± 10 mV)

REF+

= 3.0 V (± 10 mV)

REF+

0x1FFF 75A8 - 0x1FFF 75A9

0x1FFF 75CA - 0x1FFF 75CB

3.13.2 Internal voltage reference (V

The internal voltage reference (V
ADC and comparators. V

REFINT

REFINT

is internally connected to an ADC input. The V

REFINT

)

) provides a stable (bandgap) voltage output for the

voltage is individually precisely measured for each part by ST during production test and
stored in the part’s System memory. It is accessible in read-only mode.

3.13.3 V

Calibration value name Description Memory address

battery voltage monitoring

BAT

Table 6. Internal voltage reference calibration values

Raw data acquired at a

VREFINT

temperature of 30 °C (± 5 °C),
V

DDA

= V

= 3.0 V (± 10 mV)

REF+

This embedded hardware feature allows the application to measure the V
using an internal ADC input. As the V

voltage may be higher than V

BAT

the ADC input range, the VBAT pin is internally connected to a bridge divider by 3. As a
consequence, the converted digital value is one third the V

3.14 Digital-to-analog converter (DAC)

REFINT

0x1FFF 75AA - 0x1FFF 75AB

battery voltage

BAT

and thus outside

DDA

voltage.

BAT

The 2-channel 12-bit buffered DAC converts a digital value into an analog voltage available
on the channel output. The architecture of either channel is based on integrated resistor
string and an inverting amplifier. The digital circuitry is common for both channels.

DS12231 Rev 2 25/137

35

Functional overview STM32G081xB

Features of the DAC:

• Two DAC output channels

• 8-bit or 12-bit output mode

• Buffer offset calibration (factory and user trimming)

• Left or right data alignment in 12-bit mode

• Synchronized update capability

• Noise-wave generation

• Triangular-wave generation

• Independent or simultaneous conversion for DAC channels

• DMA capability for either DAC channel

• Triggering with timer events, synchronized with DMA

• Triggering with external events

• Sample-and-hold low-power mode, with internal or external capacitor

3.15 Voltage reference buffer (VREFBUF)

When enabled, an embedded buffer provides the internal reference voltage to analog blocks
(for example ADC) and to VREF+ pin for external components.

The internal voltage reference buffer supports two voltages:

• 2.048 V

• 2.5 V

An external voltage reference can be provided through the VREF+ pin when the internal
voltage reference buffer is disabled.

On some packages, the VREF+ pad of the silicon die is double-bonded with supply pad to
common VDD/VDDA pin and so the internal voltage reference buffer cannot be used.

3.16 Comparators (COMP)

Two embedded rail-to-rail analog comparators have programmable reference voltage
(internal or external), hysteresis, speed (low for low-power) and output polarity.

The reference voltage can be one of the following:

• external, from an I/O

• internal, from DAC

• internal reference voltage (V

The comparators can wake up the device from Stop mode, generate interrupts, breaks or
triggers for the timers and can be also combined into a window comparator.

) or its submultiple (1/4, 1/2, 3/4)

REFINT

3.17 Random-number generator (RNG)

The embedded RNG delivers 32-bit random numbers generated by an integrated analog
circuit.

26/137 DS12231 Rev 2

STM32G081xB Functional overview

3.18 Advanced-encryption-standard (AES) hardware accelerator

The embedded AES hardware accelerator can encipher or decipher data, using AES
algorithm.

Features of AES:

• Encryption/decryption using AES Rijndael Block Cipher algorithm

• NIST-FIPS-197-compliant implementation of AES encryption/decryption algorithm

• 128-bit and 256-bit register for storing the encryption, decryption or derivation key (four

32-bit registers)

• Electronic codebook (ECB), cipher block chaining (CBC), counter (CTR), Galois

counter (GCM), Galois message authentication code (GMAC) and cipher message
authentication code (CMAC) modes supported

• Key scheduler

• Key derivation for decryption

• 128-bit data block processing

• 128-bit and 256-bit key length

• 32-bit input and output buffers

• Register access supporting 32-bit data width

• 128-bit register for the initialization vector when AES is configured in CBC mode or for

the 32-bit counter initialization when CTR mode is selected, GCM mode or CMAC
mode

• Automatic data flow control with support of direct memory access (DMA) using 2

channels, one for incoming data, the other for outcoming data

• Message processing suspend to process another message with higher priority

3.19 Timers and watchdogs

The device includes an advanced-control timer, six general-purpose timers, two basic
timers, two low-power timers, two watchdog timers and a SysTick timer. Table 7 compares
features of the advanced control, general purpose and basic timers.

Timer type Timer

Advanced-

control

TIM1 16-bit

Counter

resolution

Table 7. Timer feature comparison

Counter

type

Up, down,

up/down

Maximum
operating

frequency

128 MHz

Prescaler

factor

Integer from

1 to 2

16

DMA

request

generation

Yes 4 3

Capture/
compare

channels

Comple­mentary

outputs

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35

Functional overview STM32G081xB

Table 7. Timer feature comparison (continued)

Maximum
operating

frequency

64 MHz

64 MHz

Timer type Timer

TIM2 32-bit

TIM3 16-bit

General-

purpose

Basic

Low-power

TIM14 16-bit Up 64 MHz

TIM15 16-bit Up 128 MHz

TIM16
TIM17

TIM6
TIM7

LPTIM1
LPTIM2

Counter

resolution

16-bit Up 64 MHz

16-bit Up 64 MHz

16-bit Up 64 MHz

Counter

type

Up, down,

up/down

Up, down,

up/down

3.19.1 Advanced-control timer (TIM1)

The advanced-control timer can be seen as a three-phase PWM unit multiplexed on 6
channels. It has complementary PWM outputs with programmable inserted dead-times. It
can also be seen as a complete general-purpose timer. The 4 independent channels can be
used for:

• input capture

• output compare

• PWM output (edge or center-aligned modes) with full modulation capability (0-100%)

• one-pulse mode output

Prescaler

factor

Integer from

Integer from

Integer from

Integer from

Integer from

Integer from

1 to 2

1 to 2

1 to 2

1 to 2

1 to 2

1 to 2

n

where

2

n=0 to 7

16

16

16

16

16

16

DMA

request

generation

Yes 4 -

Yes 4 -

No 1 -

Yes 2 1

Yes 1 1

Yes - -

No N/A -

Capture/
compare

channels

Comple­mentary

outputs

In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled, so as to turn off any power switches driven by these outputs.

Many features are shared with those of the general-purpose TIMx timers (described in

Section 3.19.2) using the same architecture, so the advanced-control timers can work

together with the TIMx timers via the Timer Link feature for synchronization or event
chaining.

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STM32G081xB Functional overview

3.19.2 General-purpose timers (TIM2, TIM3, TIM14, TIM15, TIM16, TIM17)

There are six synchronizable general-purpose timers embedded in the device (refer to

Tab l e 7 for comparison). Each general-purpose timer can be used to generate PWM outputs

or act as a simple timebase.

• TIM2 and TIM3

These are full-featured general-purpose timers:

– TIM2 with 32-bit auto-reload up/downcounter and 16-bit prescaler

– TIM3 with 16-bit auto-reload up/downcounter and 16-bit prescaler

They have four independent channels for input capture/output compare, PWM or one­pulse mode output. They can operate together or in combination with other general­purpose timers via the Timer Link feature for synchronization or event chaining. They
can generate independent DMA request and support quadrature encoders. Their
counters can be frozen in debug mode.

• TIM14

This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. It has one
channel for input capture/output compare, PWM output or one-pulse mode output. Its
counter can be frozen in debug mode.

• TIM15, 16 and 17

These are general-purpose timers featuring:

– 16-bit auto-reload upcounter and 16-bit prescaler

– 2 channels and 1 complementary channel for TIM15

– 1 channel and 1 complementary channel for TIM16 and TIM17

All channels can be used for input capture/output compare, PWM or one-pulse mode
output. The timers can operate together via the Timer Link feature for synchronization
or event chaining. They can generate independent DMA request. Their counters can
be frozen in debug mode.

3.19.3 Basic timers (TIM6 and TIM7)

These timers are mainly used for triggering DAC conversions. They can also be used as
generic 16-bit timebases.

3.19.4 Low-power timers (LPTIM1 and LPTIM2)

These timers have an independent clock. When fed with LSE, LSI or external clock, they
keep running in Stop mode and they can wake up the system from it.

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35

Functional overview STM32G081xB

Features of LPTIM1 and LPTIM2:

• 16-bit up counter with 16-bit autoreload register

• 16-bit compare register

• Configurable output (pulse, PWM)

• Continuous/one-shot mode

• Selectable software/hardware input trigger

• Selectable clock source:

– Internal: LSE, LSI, HSI16 or APB clocks

– External: over LPTIM input (working even with no internal clock source running,

used by pulse counter application)

• Programmable digital glitch filter

• Encoder mode

3.19.5 Independent watchdog (IWDG)

The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with
user-defined refresh window. It is clocked from an independent 32 kHz internal RC (LSI).
Independent of the main clock, it can operate in Stop and Standby modes. It can be used
either as a watchdog to reset the device when a problem occurs, or as a free-running timer
for application timeout management. It is hardware- or software-configurable through the
option bytes. Its counter can be frozen in debug mode.

3.19.6 System window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked by the
system clock. It has an early-warning interrupt capability. Its counter can be frozen in debug
mode.

3.19.7 SysTick timer

This timer is dedicated to real-time operating systems, but it can also be used as a standard
down counter.

Features of SysTick timer:

• 24-bit down counter

• Autoreload capability

• Maskable system interrupt generation when the counter reaches 0

• Programmable clock source

3.20 Real-time clock (RTC), tamper (TAMP) and backup registers

The device embeds an RTC and five 32-bit backup registers, located in the RTC domain of
the silicon die.

The ways of powering the RTC domain are described in Section 3.7.6.

The RTC is an independent BCD timer/counter.

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