ST MICROELECTRONICS STM32G071CBU6 Datasheet

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STM32G071x8/xB

LQFP64

UFQFPN48

UFQFPN32

UFQFPN28

LQFP48

LQFP32

WLCSP25

2.3 × 2.5 mm

UFBGA64

5mm

10 mm

7mm

7 × 7 mm

5×5mm

4×4mm

Arm® Cortex®-M0+ 32-bit MCU, up to 128 KB Flash, 36 KB RAM,

4x USART, timers, ADC, DAC, comm. I/Fs, 1.7-3.6V

Datasheet - production data

Features

• Core: Arm® 32-bit Cortex®-M0+ CPU, frequency up to 64 MHz

• -40°C to 85°C/125°C operating temperature

• Memories

– Up to 128 Kbytes of Flash memory – 36 Kbytes of SRAM (32 Kbytes with HW

parity check)

• CRC calculation unit

• Reset and power management

– Voltage range: 1.7 V to 3.6 V – Power-on/Power-down reset (POR/PDR) – Programmable Brownout reset (BOR) – Programmable voltage detector (PVD) – Low-power modes:

Sleep, Stop, Standby, Shutdown

–V

supply for RTC and backup registers

BAT

• Clock management – 4 to 48 MHz crystal oscillator – 32 kHz crystal oscillator with calibration – Internal 16 MHz RC with PLL option (±1 %) – Internal 32 kHz RC oscillator (±5 %)

• Up to 60 fast I/Os – All mappable on external interrupt vectors – Multiple 5 V-tolerant I/Os

• 7-channel DMA controller with flexible mapping

• 12-bit, 0.4 µs ADC (up to 16 ext. channels)

– Up to 16-bit with hardware oversampling – Conversion range: 0 to 3.6V

• Two 12-bit DACs, low-power sample-and-hold

• Two fast low-power analog comparators, with

programmable input and output, rail-to-rail

• 14 timers (two 128 MHz capable): 16-bit for advanced motor control, one 32-bit and five 16bit general-purpose, two basic 16-bit, two lowpower 16-bit, two watchdogs, SysTick timer

• Calendar RTC with alarm and periodic wakeup from Stop/Standby/Shutdown

• Communication interfaces –Two I

C-bus interfaces supporting Fastmode Plus (1 Mbit/s) with extra current sink, one supporting SMBus/PMBus and wakeup from Stop mode

– Four USARTs with master/slave

synchronous SPI; two supporting ISO7816 interface, LIN, IrDA capability, auto baud rate detection and wakeup feature

– Low-power UART – Two SPIs (32 Mbit/s) with 4- to 16-bit

programmable bitframe, one multiplexed

with I

S interface

– HDMI CEC interface, wakeup on header

reception

• USB Type-C™ Power Delivery controller

• Development support: serial wire debug (SWD)

• 96-bit unique ID

• All packages ECOPACK

Reference Part number

STM32G071xB

STM32G071x8

Table 1. Device summary

STM32G071RB, STM32G071CB,

STM32G071KB, STM32G071GB,

STM32G071C8, STM32G071G8,

STM32G071K8, STM32G071R8

2 compliant

STM32G071EB

November 2018 DS12232 Rev 2 1/136

This is information on a product in full production.

www.st.com

Contents STM32G071x8/xB

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.1 Arm® Cortex®-M0+ core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.5 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.6 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 16

3.7 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.7.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.7.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.7.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.7.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.7.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.7.6 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.8 Interconnect of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.9 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.10 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.11 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.12 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.12.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 23

3.12.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 24

3.13 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.13.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.13.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.13.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.14 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.15 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.16 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

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3.17 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.17.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.17.2 General-purpose timers (TIM2, TIM3, TIM14, TIM15, TIM16, TIM17) . . 28

3.17.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.17.4 Low-power timers (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . 28

3.17.5 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.17.6 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.17.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.18 Real-time clock (RTC), tamper (TAMP) and backup registers . . . . . . . . . 29

3.19 Inter-integrated circuit interface (I

C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.20 Universal synchronous/asynchronous receiver transmitter (USART) . . . 31

3.21 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 32

3.22 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.23 USB Type-C™ Power Delivery controller . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.24 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.24.1 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4 Pinouts, pin description and alternate functions . . . . . . . . . . . . . . . . . 35

5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 57

5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 57

5.3.4 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

DS12232 Rev 2 3/136

Contents STM32G071x8/xB

5.3.6 Wakeup time from low-power modes and voltage scaling

transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

5.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

5.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

5.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

5.3.10 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

5.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

5.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

5.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

5.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

5.3.15 NRST input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

5.3.16 Analog switch booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

5.3.17 Analog-to-digital converter characteristics . . . . . . . . . . . . . . . . . . . . . . . 86

5.3.18 Digital-to-analog converter characteristics . . . . . . . . . . . . . . . . . . . . . . . 94

5.3.19 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . . 98

5.3.20 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

5.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

5.3.22 V

5.3.23 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

5.3.24 Characteristics of communication interfaces . . . . . . . . . . . . . . . . . . . . 102

5.3.25 UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

BAT

6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

6.1 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

6.2 UFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

6.3 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116

6.4 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

6.5 LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

6.6 UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

6.7 UFQFPN28 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

6.8 WLCSP25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

6.9 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

6.9.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

6.9.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 132

7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

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STM32G071x8/xB Contents

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

DS12232 Rev 2 5/136

List of tables STM32G071x8/xB

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. STM32G071x8/xB family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . 12

Table 3. Access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 15

Table 4. Interconnect of STM32G071x8/xB peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 5. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 6. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 7. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 8. I

Table 9. USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 10. SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 11. Terms and symbols used in Table 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 12. Pin assignment and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 13. Port A alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 14. Port B alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 15. Port C alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 16. Port D alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 17. Port F alternate function mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 18. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 19. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 20. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 21. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 22. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 23. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 24. Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 25. Current consumption in Run and Low-power run modes

Table 26. Typical current consumption in Run and Low-power run modes,

Table 27. Current consumption in Sleep and Low-power sleep modes . . . . . . . . . . . . . . . . . . . . . . . 63

Table 28. Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 29. Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 30. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 31. Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 32. Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 33. Current consumption of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 34. Low-power mode wakeup times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 35. Regulator mode transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 36. Wakeup time using LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 37. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 38. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 39. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 40. LSE oscillator characteristics (f

Table 41. HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 42. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 43. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 44. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 45. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 46. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

at different die temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

depending on code executed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

LSE

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Table 47. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 48. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 49. Electrical sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 50. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 51. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 52. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 53. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 54. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 55. Analog switch booster characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 56. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 57. Maximum ADC R

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

AIN

Table 58. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 59. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 60. DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 61. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 62. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 63. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 64. V Table 65. V

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

BAT

charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

BAT

Table 66. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Table 67. IWDG min/max timeout period at 32 kHz LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 68. Minimum I2CCLK frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 69. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 70. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 71. I

S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 72. USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 73. UCPD operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 74. LQFP64 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Table 75. UFBGA64 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 76. Recommended PCB design rules for UFBGA64 package . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 77. LQFP48 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Table 78. UFQFPN48 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Table 79. LQFP32 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 80. UFQFPN32 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Table 81. UFQFPN28 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Table 82. WLCSP25 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 83. Recommended PCB pad design rules for WLCSP25 package . . . . . . . . . . . . . . . . . . . . 130

Table 84. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Table 85. STM32G071x8/xB ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Table 86. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

DS12232 Rev 2 7/136

List of figures STM32G071x8/xB

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 2. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 3. STM32G071RxT LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 4. STM32G071RxH UFBGA64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 5. STM32G071CxT LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 6. STM32G071CxU UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 7. STM32G071KxT LQFP32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 8. STM32G071KxU UFQFPN32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 9. STM32G071GxU UFQFPN28 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 10. STM32G071Ex WLCSP25 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 11. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 12. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 13. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 14. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 15. VREFINT vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 16. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 17. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 18. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 19. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 20. HSI16 frequency vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 21. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 22. I/O AC characteristics definition

Figure 23. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 24. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 25. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 26. 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 27. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Figure 28. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 29. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 30. I Figure 31. I

Figure 32. LQFP64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Figure 33. Recommended footprint for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Figure 34. LQFP64 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 35. UFBGA64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 36. Recommended footprint for UFBGA64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figure 37. UFBGA64 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 38. LQFP48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 39. Recommended footprint for LQFP48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 40. LQFP48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 41. UFQFPN48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 42. Recommended footprint for UFQFPN48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 43. UFQFPN48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 44. LQFP32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Figure 45. Recommended footprint for LQFP32 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Figure 46. LQFP32 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 47. UFQFPN32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Figure 48. Recommended footprint for UFQFPN32 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

S master timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

8/136 DS12232 Rev 2

STM32G071x8/xB List of figures

Figure 49. UFQFPN32 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Figure 50. UFQFPN28 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Figure 51. Recommended footprint for UFQFPN28 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Figure 52. UFQFPN28 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Figure 53. WLCSP25 chip-scale package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Figure 54. Recommended PCB pad design for WLCSP25 package. . . . . . . . . . . . . . . . . . . . . . . . . 130

Figure 55. WLCSP25 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

DS12232 Rev 2 9/136

Introduction STM32G071x8/xB

1 Introduction

This document provides information on STM32G071x8/xB microcontrollers, such as description, functional overview, pin assignment and definition, electrical characteristics, packaging, and ordering codes.

Information on memory mapping and control registers is object of reference manual.

Information on Arm

®(a)

Cortex®-M0+ core is available from the www.arm.com website.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

10/136 DS12232 Rev 2

STM32G071x8/xB Description

2 Description

The STM32G071x8/xB mainstream microcontrollers are based on high-performance

Arm

Cortex®-M0+ 32-bit RISC core operating at up to 64 MHz frequency. Offering a high level of integration, they are suitable for a wide range of applications in consumer, industrial and appliance domains and ready for the Internet of Things (IoT) solutions.

The devices incorporate a memory protection unit (MPU), high-speed embedded memories (up to 128 Kbytes of Flash program memory and 36 Kbytes of SRAM), DMA and an extensive range of system functions, enhanced I/Os and peripherals. The devices offer standard communication interfaces (two I USARTs), one 12-bit ADC (2.5 MSps) with up to 19 channels, one 12-bit DAC with two channels, two fast comparators, an internal voltage reference buffer, a low-power RTC, an advanced control PWM timer running at up to double the CPU frequency, five generalpurpose 16-bit timers with one running at up to double the CPU frequency, a 32-bit generalpurpose timer, two basic and two low-power 16-bit timers, two watchdog timers, and a SysTick timer. The STM32G071x8/xB devices provide a fully integrated USB Type-C Power Delivery controller.

The devices operate within ambient temperatures from -40 to 125°C. They can operate with supply voltages from 1.7 V to 3.6 V. Optimized dynamic consumption combined with a comprehensive set of power-saving modes, low-power timers and low-power UART, allows the design of low-power applications.

Cs, two SPIs / one I2S, one HDMI CEC and four

VBAT direct battery input allows keeping RTC and backup registers powered.

The devices come in packages with 28 to 64 pins.

DS12232 Rev 2 11/136

Description STM32G071x8/xB

Table 2. STM32G071x8/xB family device features and peripheral counts

STM32G071_

Peripheral

_EB _G8 _GB

Flash memory (Kbyte) 128 64 128 64 128 64 128 64 128 64 128 64 128

SRAM (Kbyte) 32 (with parity) or 36 (without parity)

Advanced control 1 (16-bit) high frequency

General-purpose 4 (16-bit) + 1 (16-bit) high frequency + 1 (32-bit)

Basic 2 (16-bit)

Timers

Low-power 2 (16-bit)

SysTick 1

Watchdog 2

SPI [I2S]

(1)

USART 4

LPUART 1

Comm. interfaces

CEC 1

UCPD

(2)

RTC Yes

Tamper pins 2

Random number

generator

AES No

_G8 xxN

_GB

xxN

_K8 _KB

2 [1]

(2)

_K8 xxN

_KB

_C8 _CB _R8 _RB

xxN

GPIOs 23 26 30 44 60

Wakeup pins 4 3 4 3 4 5

12-bit ADC channels

10 ext. + 2 int.

9 ext.

+ 2 int.

11 ext. + 2 int.

10 ext. + 2 int.

14 ext. + 3 int.

12-bit DAC channels 2

Internal voltage reference

buffer

No Yes

Analog comparators 2

Max. CPU frequency 64 MHz

Operating voltage 1.7 to 3.6 V

Operating temperature

(3)

Ambient: -40 to 85 °C / -40 to 125 °C

Junction: -40 to 105 °C / -40 to 130 °C

Number of pins 25 28 32 48 64

1. The numbers in brackets denote the count of SPI interfaces configurable as I2S interface.

2. One port with only one CC line available (supporting limited number of use cases).

3. Depends on order code. Refer to Section 7: Ordering information for details.

12/136 DS12232 Rev 2

16 ext. + 3 int.

STM32G071x8/xB Description

MSv42182V2

UCPD

USART3/4

USART1/2

LPTIMER 1/2

TIMER 16/17

Power domain of analog blocks :

BAT

4 channels BKIN, BKIN2, ETR

System and

peripheral

clocks

PAx

PBx

PCx

PFx

MOSI/SD

MISO/MCK

SCK/CK

NSS/WS

SWCLK SWDIO

16x IN

OSC_IN OSC_OUT

VBAT

OSC32_IN OSC32_OUT

RTC_OUT RTC_REFIN RTC_TS

MOSI, MISO

SCK, NSS

HSI16

LSI

PLLPCLK

IR_OUT

1 channel BKIN

ETR, IN, OUT

1 channel

4 channels ETR

CPU

CORTEX-M0+

max

= 64 MHz

SWD

NVIC

EXTI

SPI1/I2S

SPI2

AHB-to-APB

RCC

Reset & clock control

I/F

XTAL OSC

4-48 MHz

IWDG

SRAM 36 KB

I/F

ADC

RTC, TAMP Backup regs

I/F

RC 16 MHz

RC 32 kHz

PLL

decoder

XTAL32 kHz

Bus matrix

I/F

2 channels BKIN

RX, TX CTS, RTS, CK

CEC

TIM6

TIM7

COMP1

COMP2

IN+, IN-,

OUT

Port D

Port C

Port B

Port A

DDA

SUPPLY

SUPERVISION

POWER

CORE

POR

Reset

Int

VDD/VDDA VSS/VSSA

NRST

PVD

POR/BOR

Voltage

regulator

USART3 & 4

USART1 & 2

LPTIM1 & 2

TIM16 & 17

TIM15

TIM14

TIM3

TIM2 (32-bit)

TIM1

GPIOs

IOPORT

HSE

PLLQCLK PLLRCLK

LSE

T sensor

RX, TX, CTS, RTS

LPUART

TAMP_IN

APB

AHB

CC, DBCC

FRSTX

UCPD1 & 2

HDMI-CEC

VREFBUF

DAC

I/F

DAC_OUT1

DAC_OUT2

CRC

VREF+

SCL, SDA

SCL, SDA SMBA, SMBUS

I2C1

I2C2

DBGMCU

WWDG

PWRCTRL

SYSCFG

DMA

DMAMUX

Port F

PDx

DDA

DDIO1

Low-voltage

detector

Parity

Flash memory

up to 128 KB

DDIO1

IRTIM

from peripherals

Figure 1. Block diagram

DS12232 Rev 2 13/136

Functional overview STM32G071x8/xB

3 Functional overview

3.1 Arm® Cortex®-M0+ core with MPU

The Cortex-M0+ is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:

• a simple architecture, easy to learn and program

• ultra-low power, energy-efficient operation

• excellent code density

• deterministic, high-performance interrupt handling

• upward compatibility with Cortex-M processor family

• platform security robustness, with integrated Memory Protection Unit (MPU).

The Cortex-M0+ processor is built on a highly area- and power-optimized 32-bit core, with a 2-stage pipeline Von Neumann architecture. The processor delivers exceptional energy efficiency through a small but powerful instruction set and extensively optimized design, providing high-end processing hardware including a single-cycle multiplier.

The Cortex-M0+ processor provides the exceptional performance expected of a modern 32-bit architecture, with a higher code density than other 8-bit and 16-bit microcontrollers.

Owing to embedded Arm core, the STM32G071x8/xB devices are compatible with Arm tools and software.

The Cortex-M0+ is tightly coupled with a nested vectored interrupt controller (NVIC) described in Section 3.12.1.

3.2 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task.

The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

3.3 Embedded Flash memory

STM32G071x8/xB devices feature up to 128 Kbytes of embedded Flash memory available for storing code and data.

14/136 DS12232 Rev 2

STM32G071x8/xB Functional overview

Flexible protections can be configured thanks to option bytes:

• Readout protection (RDP) to protect the whole memory. Three levels are available:

– Level 0: no readout protection

– Level 1: memory readout protection: the Flash memory cannot be read from or

written to if either debug features are connected, boot in RAM or bootloader is selected

– Level 2: chip readout protection: debug features (Cortex-M0+ serial wire), boot in

RAM and bootloader selection are disabled. This selection is irreversible.

Table 3. Access status versus readout protection level and execution modes

Area

User

memory

System

memory

Option

bytes

Backup

registers

1. Erased upon RDP change from Level 1 to Level 0.

Protection

level

1 Yes Yes Yes No No No

2 Yes Yes Yes N/A N/A N/A

1 Yes No No Yes No No

2 Yes No No N/A N/A N/A

1 Yes Yes Yes Yes Yes Yes

2 Yes No No N/A N/A N/A

1YesYesN/A

2 Yes Yes N/A N/A N/A N/A

User execution

Read Write Erase Read Write Erase

(1)

Debug, boot from RAM or boot

from system memory (loader)

No No N/A

• Write protection (WRP): the protected area is protected against erasing and

programming. Two areas per bank can be selected, with 2-Kbyte granularity.

• Proprietary code readout protection (PCROP): a part of the Flash memory can be

protected against read and write from third parties. The protected area is execute-only: it can only be reached by the STM32 CPU as instruction code, while all other accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited. An additional option bit (PCROP_RDP) determines whether the PCROP area is erased or not when the RDP protection is changed from Level 1 to Level 0.

(1)

The whole non-volatile memory embeds the error correction code (ECC) feature supporting:

• single error detection and correction

• double error detection

• readout of the ECC fail address from the ECC register

3.4 Embedded SRAM

STM32G071x8/xB devices have 32 Kbytes of embedded SRAM with parity. Hardware parity check allows memory data errors to be detected, which contributes to increasing functional safety of applications.

When the parity protection is not required because the application is not safety-critical, the parity memory bits can be used as additional SRAM, to increase its total size to 36 Kbytes.

The memory can be read/write-accessed at CPU clock speed, with 0 wait states.

DS12232 Rev 2 15/136

Functional overview STM32G071x8/xB

3.5 Boot modes

At startup, the boot pin and boot selector option bit are used to select one of the three boot options:

• boot from User Flash memory

• boot from System memory

• boot from embedded SRAM

The boot pin is shared with a standard GPIO and can be disabled through the boot selector option bit. The boot loader is located in System memory. It manages the Flash memory reprogramming through USART on pins PA9/PA10, PC10/PC11 or PA2/PA3, through I

Cbus on pins PB6/PB7 or PB10/PB11, or through SPI on pins PA4/PA5/PA6/PA7 or PB12/PB13/PB14/PB15.

3.6 Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link time and stored at a given memory location.

3.7 Power supply management

3.7.1 Power supply schemes

The STM32G071x8/xB devices require a 1.7 V to 3.6 V operating supply voltage (VDD). Several different power supplies are provided to specific peripherals:

• V

= 1.7 (2.0) to 3.6 V

is the external power supply for the internal regulator and the system analog such

as reset, power management and internal clocks. It is provided externally through VDD/VDDA pin.

The minimum voltage of 1.7 V corresponds to power-on reset release threshold V

POR(MAX)

. Once this threshold is crossed and power-on reset is released, the

functionality is guaranteed down to power-down reset threshold V

= 2.0 V (ADC and COMP) / 1.8 V (DAC) / 2.4 V (VREFBUF) to 3.6 V

DDA

is the analog power supply for the A/D converter, D/A converter, voltage

DDA

reference buffer and comparators. V provided externally through VDD/VDDA pin.

= V

DDIO1

is the power supply for the I/Os. V

as it is provided externally through VDD/VDDA pin.

= 1.55 V to 3.6 V

BAT

is the power supply (through a power switch) for RTC, TAMP, low-speed external

BAT

32.768 kHz oscillator and backup registers when V

PDR(MIN)

voltage level is identical to VDD voltage as it is

DDA

voltage level is identical to VDD voltage

DDIO1

is not present. V

is provided

BAT

16/136 DS12232 Rev 2

STM32G071x8/xB Functional overview

MSv39736V2

DDA

domain

RTC domain

D/A converter

A/D converter

Standby circuitry (Wakeup, IWDG)

Voltage

regulator

Core

SRAM

Digital

peripherals

Low-voltage

detector

LSE crystal 32.768 kHz osc

BKP registers

RCC BDCR register

RTC and TAMP

2 x comparator

Voltage reference buffer

I/O ring

CORE

domain

Temp. sensor

Reset block

PLL, HSI

Flash memory

DDIO1

VREF+

domain

CORE

VSS/VSSA

VDD/VDDA

VBAT

DDA

REF+

SSA

DDIO1

domain

externally through VBAT pin. When this pin is not available on the package, VBAT bonding pad is internally bonded to the VDD/VDDA pin.

• V

is the input reference voltage for the ADC and DAC, or the output of the internal

REF+

voltage reference buffer (when enabled). When V V

DDA

. When V

DDA

≥ 2 V, V

must be between 2 V and V

REF+

DDA

< 2 V, V

must be equal to

REF+

. It can be grounded

DDA

when the ADC and DAC are not active.

The internal voltage reference buffer supports two output voltages, which is configured with VRS bit of the VREFBUF_CSR register:

–V

REF+

internally connected with V

around 2.048 V (requiring V

REF+

around 2.5 V (requiring V

REF+

equal to or higher than 2.4 V)

DDA

equal to or higher than 2.8 V)

DDA

is delivered through VREF+ pin. On packages without VREF+ pin, V

, and the internal voltage reference buffer must be kept

REF+

disabled (refer to datasheets for package pinout description).

• V

CORE

An embedded linear voltage regulator is used to supply the V power. V The Flash memory is also supplied with V

is the power supply for digital peripherals, SRAM and Flash memory.

CORE

internal digital

CORE

Figure 2. Power supply overview

3.7.2 Power supply supervisor

The device has an integrated power-on/power-down (POR/PDR) reset active in all power modes except Shutdown and ensuring proper operation upon power-on and power-down. It maintains the device in reset when the supply voltage is below V the need for an external reset circuit. Brownout reset (BOR) function allows extra flexibility. It

POR/PDR

threshold, without

DS12232 Rev 2 17/136

Functional overview STM32G071x8/xB

can be enabled and configured through option bytes, by selecting one of four thresholds for rising V

and other four for falling VDD.

The device also features an embedded programmable voltage detector (PVD) that monitors the V when V

power supply and compares it to V

level crosses the V

threshold, selectively while falling, while rising, or while

PVD

threshold. It allows generating an interrupt

PVD

falling and rising. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

3.7.3 Voltage regulator

Two embedded linear voltage regulators, main regulator (MR) and low-power regulator (LPR), supply most of digital circuitry in the device.

The MR is used in Run and Sleep modes. The LPR is used in Low-power run, Low-power sleep and Stop modes.

In Standby and Shutdown modes, both regulators are powered down and their outputs set in high-impedance state, such as to bring their current consumption close to zero. However, SRAM data retention is possible in Standby mode, in which case the LPR remains active and it only supplies the SRAM.

3.7.4 Low-power modes

By default, the microcontroller is in Run mode after system or power reset. It is up to the user to select one of the low-power modes described below:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

• Low-power run mode

This mode is achieved with V

supplied by the low-power regulator to minimize the

CORE

regulator's operating current. The code can be executed from SRAM or from Flash, and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can be clocked by HSI16.

• Low-power sleep mode

This mode is entered from the low-power run mode. Only the CPU clock is stopped. When wakeup is triggered by an event or an interrupt, the system reverts to the Lowpower run mode.

• Stop 0 and Stop 1 modes

In Stop 0 and Stop 1 modes, the device achieves the lowest power consumption while retaining the SRAM and register contents. All clocks in the V

domain are stopped.

CORE

The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are disabled. The LSE or LSI keep running. The RTC can remain active (Stop mode with RTC, Stop mode without RTC).

Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode, so as to get clock for processing the wakeup event. The main regulator remains active in Stop 0 mode while it is turned off in Stop 1 mode.

• Standby mode

The Standby mode is used to achieve the lowest power consumption, with POR/PDR always active in this mode. The main regulator is switched off to power down V

CORE

domain. The low-power regulator is either switched off or kept active. In the latter case,

18/136 DS12232 Rev 2

STM32G071x8/xB Functional overview

it only supplies SRAM to ensure data retention. The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are also powered down. The RTC can remain active (Standby mode with RTC, Standby mode without RTC).

For each I/O, the software can determine whether a pull-up, a pull-down or no resistor shall be applied to that I/O during Standby mode.

Upon entering Standby mode, register contents are lost except for registers in the RTC domain and standby circuitry. The SRAM contents can be retained through register setting.

The device exits Standby mode upon external reset event (NRST pin), IWDG reset event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event (alarm, periodic wakeup, timestamp, tamper), or when a failure is detected on LSE (CSS on LSE).

• Shutdown mode

The Shutdown mode allows to achieve the lowest power consumption. The internal regulator is switched off to power down the V

domain. The PLL, as well as the

CORE

HSI16 and LSI RC-oscillators and HSE crystal oscillator are also powered down. The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).

The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode. Therefore, switching to RTC domain is not supported.

SRAM and register contents are lost except for registers in the RTC domain.

The device exits Shutdown mode upon external reset event (NRST pin), IWDG reset event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event (alarm, periodic wakeup, timestamp, tamper).

3.7.5 Reset mode

During and upon exiting reset, the schmitt triggers of I/Os are disabled so as to reduce power consumption. In addition, when the reset source is internal, the built-in pull-up resistor on NRST pin is deactivated.

3.7.6 VBAT operation

The V backup registers.

In VBAT mode, the RTC domain is supplied from VBAT pin. The power source can be, for example, an external battery or an external supercapacitor. Two anti-tamper detection pins are available.

The RTC domain can also be supplied from VDD/VDDA pin.

By means of a built-in switch, an internal voltage supervisor allows automatic switching of RTC domain powering between V voltage of the RTC domain (V are valid, the RTC domain is supplied from VDD/VDDA pin.

An internal circuit for charging the battery on VBAT pin can be activated if the V within a valid range.

Note: External interrupts and RTC alarm/events cannot cause the microcontroller to exit the VBAT

mode, as in that mode the V

power domain, consuming very little energy, includes RTC, and LSE oscillator and

BAT

and voltage from VBAT pin to ensure that the supply

) remains within valid operating conditions. If both voltages

BAT

voltage is

is not within a valid range.

DS12232 Rev 2 19/136

Functional overview STM32G071x8/xB

3.8 Interconnect of peripherals

Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections allow fast and predictable latency.

Depending on peripherals, these interconnections can operate in Run, Sleep and Stop modes.

Table 4. Interconnect of STM32G071x8/xB peripherals

Interconnect source

TIMx

COMPx

ADCx TIM1 Timer triggered by analog watchdog Y Y -

RTC

All clocks sources (internal

and external)

CSS

RAM (parity error)

Flash memory (ECC error)

COMPx

PVD

Interconnect

destination

TIMx Timer synchronization or chaining Y Y -

ADCx DACx

DMA Memory-to-memory transfer trigger Y Y -

COMPx Comparator output blanking Y Y -

TIM1,2,3

LPTIMERx

TIM16 Timer input channel from RTC events Y Y -

LPTIMERx

TIM14,16,17

TIM1,15,16,17 Timer break Y Y -

Conversion triggers Y Y -

Timer input channel, trigger, break from analog signals comparison

Low-power timer triggered by analog signals comparison

Low-power timer triggered by RTC alarms or tampers

Clock source used as input channel for RC measurement and trimming

Interconnect action

Run

YY -

YYY

YY -

Sleep

Low-power run

Low-power sleep

Stop

CPU (hard fault) TIM1,15,16,17 Timer break Y - -

TIMx External trigger Y Y -

GPIO

20/136 DS12232 Rev 2

LPTIMERx External trigger Y Y Y

ADC

DACx

Conversion external trigger Y Y -

STM32G071x8/xB Functional overview

3.9 Clocks and startup

The clock controller distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. It features:

• Clock prescaler: to get the best trade-off between speed and current consumption,

the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler

• Safe clock switching: clock sources can be changed safely on the fly in run mode

through a configuration register.

• Clock management: to reduce power consumption, the clock controller can stop the

clock to the core, individual peripherals or memory.

• System clock source: three different sources can deliver SYSCLK system clock:

– 4-48 MHz high-speed oscillator with external crystal or ceramic resonator (HSE). It

can supply clock to system PLL. The HSE can also be configured in bypass mode for an external clock.

– 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software. It can

supply clock to system PLL.

– System PLL with maximum output frequency of 64 MHz. It can be fed with HSE or

HSI16 clocks.

• Auxiliary clock source: two ultra-low-power clock sources for the real-time clock

(RTC):

– 32.768 kHz low-speed oscillator with external crystal (LSE), supporting four drive

capability modes. The LSE can also be configured in bypass mode for using an external clock.

– 32 kHz low-speed internal RC oscillator (LSI) with ±5% accuracy, also used to

clock an independent watchdog.

• Peripheral clock sources: several peripherals (I2S, USARTs, I2Cs, LPTIMs, ADC)

have their own clock independent of the system clock.

• Clock security system (CSS): in the event of HSE clock failure, the system clock is

automatically switched to HSI16 and, if enabled, a software interrupt is generated. LSE clock failure can also be detected and generate an interrupt. The CCS feature can be enabled by software.

• Clock output:

– MCO (microcontroller clock output) provides one of the internal clocks for

external use by the application

– LSCO (low speed clock output) provides LSI or LSE in all low-power modes

(except in VBAT operation).

Several prescalers allow the application to configure AHB and APB domain clock frequencies, 64 MHz at maximum.

3.10 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function (AF). Most of the GPIO pins are shared with special digital or analog functions.

DS12232 Rev 2 21/136

Functional overview STM32G071x8/xB

Through a specific sequence, this special function configuration of I/Os can be locked, such as to avoid spurious writing to I/O control registers.

3.11 Direct memory access controller (DMA)

Direct memory access (DMA) controller transfers data from a source to a destination, without making it transit through the CPU. DMA transfers are highly efficient; they save CPU resources and facilitate time-critical processing.

The source and the destination of a DMA transfer can be a peripheral or a memory.

The DMA transfer source and destination data types can be programmed independently. If different, the DMA controller performs data type conversion and adapts the addressing at the source and at the destination to their respective data types.

DMA transfer size is the number of DMA transfer cycles to execute, programmable by software. One cycle transfers one data item of selected data type from the DMA transfer source to the DMA transfer destination. The DMA transfer starts at pre-programmed source and destination base addresses. It ends at source and destination addresses that depend on the DMA transfer size, source and destination data types, and on activation of address auto-increment operation.

The DMA transfer starts upon a request from a peripheral or, in the specific case of memoryto-memory transfer, it starts when enabled by software.

The DMA controller executes one DMA transfer cycle per DMA transfer request from a peripheral, until the total number of cycles reaches the pre-programmed DMA transfer size. The circular mode of operation allows to repeat the DMA transfer infinitely, without software intervention.

In the specific case of memory-to-memory transfer, the DMA controller executes, if enabled by the software, the pre-programmed amount of cycles.

The DMA controller provides distinct DMA transfer channels. The channels can be individually configured in term of source and destination location, DMA transfer size, data type, priority level and operating mode. The DMA controller opens one channel at a time, according to channel priorities.

Features of the DMA controller:

• 7 DMA transfer channels, independently configurable by software

• Per-channel DMA transfer trigger upon request from a peripheral

• Per-channel DMA transfer triggered by software (memory-to-memory mode)

• Programmable channel priority levels: very high, high, medium and low

• By-default (hardware) channel priority levels, to arbitrate concurrent requests from

channels with identical programmable priority levels

• Byte (8-bit unit), half-word (16-bit unit) and word (32-bit unit) DMA transfer data types,

programmable independently for the source and the destination

22/136 DS12232 Rev 2

STM32G071x8/xB Functional overview

• Automatic alignment of DMA transfer source and destination addresses according to

their respective data types

• Circular operating mode support

• DMA Half Transfer, DMA Transfer Complete and DMA Transfer Error flags, logically

OR-ed together in a single interrupt request per channel

• Memory-to-memory, peripheral-to-memory, memory-to-peripheral and peripheral-to-

peripheral DMA transfer types

• DMA transfer size programmable up to 65535 DMA transfer cycles

• Access to Flash memory, SRAM, APB and AHB peripherals as source and destination

3.12 Interrupts and events

The device flexibly manages events causing interrupts of linear program execution, called exceptions. The Cortex-M0+ processor core, a nested vectored interrupt controller (NVIC) and an extended interrupt/event controller (EXTI) are the assets contributing to handling the exceptions. Exceptions include core-internal events such as, for example, a division by zero and, core-external events such as logical level changes on physical lines. Exceptions result in interrupting the program flow, executing an interrupt service routine (ISR) then resuming the original program flow.

The processor context (contents of program pointer and status registers) is stacked upon program interrupt and unstacked upon program resume, by hardware. This avoids context stacking and unstacking in the interrupt service routines (ISRs) by software, thus saving time, code and power. The ability to abandon and restart load-multiple and store-multiple operations significantly increases the device’s responsiveness in processing exceptions.

3.12.1 Nested vectored interrupt controller (NVIC)

The configurable nested vectored interrupt controller is tightly coupled with the core. It handles physical line events associated with a non-maskable interrupt (NMI) and maskable interrupts, and Cortex-M0+ exceptions. It provides flexible priority management.

The tight coupling of the processor core with NVIC significantly reduces the latency between interrupt events and start of corresponding interrupt service routines (ISRs). The ISR vectors are listed in a vector table, stored in the NVIC at a base address. The vector address of an ISR to execute is hardware-built from the vector table base address and the ISR order number used as offset.

If a higher-priority interrupt event happens while a lower-priority interrupt event occurring just before is waiting for being served, the later-arriving higher-priority interrupt event is served first. Another optimization is called tail-chaining. Upon a return from a higher-priority ISR then start of a pending lower-priority ISR, the unnecessary processor context unstacking and stacking is skipped. This reduces latency and contributes to power efficiency.

DS12232 Rev 2 23/136

Functional overview STM32G071x8/xB

Features of the NVIC:

• Low-latency interrupt processing

• 4 priority levels

• Handling of a non-maskable interrupt (NMI)

• Handling of 32 maskable interrupt lines

• Handling of 10 Cortex-M0+ exceptions

• Later-arriving higher-priority interrupt processed first

• Tail-chaining

• Interrupt vector retrieval by hardware

3.12.2 Extended interrupt/event controller (EXTI)

The extended interrupt/event controller adds flexibility in handling physical line events and allows identifying wake-up events at processor wakeup from Stop mode.

The EXTI controller has 33 channels, of which 16 with rising, falling or rising and falling edge detector capability. Any GPIO and a few peripheral signals can be connected to these channels.

The channels can be independently masked.

The EXTI controller can capture pulses shorter than the internal clock period.

A register in the EXTI controller latches every event even in Stop mode, which allows the software to identify the origin of the processor's wake-up from Stop mode or, to identify the GPIO and the edge event having caused an interrupt.

3.13 Analog-to-digital converter (ADC)

A native 12-bit analog-to-digital converter is embedded into STM32G071x8/xB devices. It can be extended to 16-bit resolution through hardware oversampling. The ADC has up to 16 external channels and 3 internal channels (temperature sensor, voltage reference, V monitoring). It performs conversions in single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs.

The ADC frequency is independent from the CPU frequency, allowing maximum sampling rate of ~2 MSps even with a low CPU speed. An auto-shutdown function guarantees that the ADC is powered off except during the active conversion phase.

The ADC can be served by the DMA controller. It can operate in the whole V range.

The ADC features a hardware oversampler up to 256 samples, improving the resolution to 16 bits (refer to AN2668).

An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all scanned channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

supply

BAT

The events generated by the general-purpose timers (TIMx) can be internally connected to the ADC start triggers, to allow the application to synchronize A/D conversions with timers.

24/136 DS12232 Rev 2

STM32G071x8/xB Functional overview

3.13.1 Temperature sensor

The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature.

The temperature sensor is internally connected to an ADC input to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor may vary from part to part due to process variation, the uncalibrated internal temperature sensor is suitable only for relative temperature measurements.

To improve the accuracy of the temperature sensor, each part is individually factorycalibrated by ST. The resulting calibration data are stored in the part’s System memory, accessible in read-only mode.

Calibration value name Description Memory address

TS_CAL1

TS_CAL2

Table 5. Temperature sensor calibration values

TS ADC raw data acquired at a temperature of 30 °C (± 5 °C), V

= V

DDA

TS ADC raw data acquired at a temperature of 130 °C (± 5 °C), V

= V

DDA

= 3.0 V (± 10 mV)

REF+

= 3.0 V (± 10 mV)

REF+

0x1FFF 75A8 - 0x1FFF 75A9

0x1FFF 75CA - 0x1FFF 75CB

3.13.2 Internal voltage reference (V

The internal voltage reference (V ADC and comparators. V

REFINT

is internally connected to an ADC input. The V

REFINT

)

) provides a stable (bandgap) voltage output for the

voltage is individually precisely measured for each part by ST during production test and stored in the part’s System memory. It is accessible in read-only mode.

3.13.3 V

Calibration value name Description Memory address

battery voltage monitoring

BAT

Table 6. Internal voltage reference calibration values

Raw data acquired at a

VREFINT

temperature of 30 °C (± 5 °C), V

DDA

= V

= 3.0 V (± 10 mV)

REF+

This embedded hardware feature allows the application to measure the V using an internal ADC input. As the V

voltage may be higher than V

BAT

the ADC input range, the VBAT pin is internally connected to a bridge divider by 3. As a consequence, the converted digital value is one third the V

3.14 Digital-to-analog converter (DAC)

REFINT

0x1FFF 75AA - 0x1FFF 75AB

battery voltage

BAT

and thus outside

DDA

voltage.

BAT

The 2-channel 12-bit buffered DAC converts a digital value into an analog voltage available on the channel output. The architecture of either channel is based on integrated resistor string and an inverting amplifier. The digital circuitry is common for both channels.

DS12232 Rev 2 25/136

Functional overview STM32G071x8/xB

Features of the DAC:

• Two DAC output channels

• 8-bit or 12-bit output mode

• Buffer offset calibration (factory and user trimming)

• Left or right data alignment in 12-bit mode

• Synchronized update capability

• Noise-wave generation

• Triangular-wave generation

• Independent or simultaneous conversion for DAC channels

• DMA capability for either DAC channel

• Triggering with timer events, synchronized with DMA

• Triggering with external events

• Sample-and-hold low-power mode, with internal or external capacitor

3.15 Voltage reference buffer (VREFBUF)

When enabled, an embedded buffer provides the internal reference voltage to analog blocks (for example ADC) and to VREF+ pin for external components.

The internal voltage reference buffer supports two voltages:

• 2.048 V

• 2.5 V

An external voltage reference can be provided through the VREF+ pin when the internal voltage reference buffer is disabled.

On some packages, the VREF+ pad of the silicon die is double-bonded with supply pad to common VDD/VDDA pin and so the internal voltage reference buffer cannot be used.

3.16 Comparators (COMP)

Two embedded rail-to-rail analog comparators have programmable reference voltage (internal or external), hysteresis, speed (low for low-power) and output polarity.

The reference voltage can be one of the following:

• external, from an I/O

• internal, from DAC

• internal reference voltage (V

The comparators can wake up the device from Stop mode, generate interrupts, breaks or triggers for the timers and can be also combined into a window comparator.

) or its submultiple (1/4, 1/2, 3/4)

REFINT

3.17 Timers and watchdogs

The device includes an advanced-control timer, six general-purpose timers, two basic timers, two low-power timers, two watchdog timers and a SysTick timer. Table 7 compares features of the advanced control, general purpose and basic timers.

26/136 DS12232 Rev 2

STM32G071x8/xB Functional overview

Timer type Timer

Advanced-

control

TIM1 16-bit

TIM2 32-bit

TIM3 16-bit

General-

purpose

TIM14 16-bit Up 64 MHz

TIM15 16-bit Up 128 MHz

TIM16 TIM17

Basic

Low-power

TIM6 TIM7

LPTIM1 LPTIM2

Table 7. Timer feature comparison

Counter

resolution

Counter

type

Up, down,

up/down

Up, down,

up/down

Up, down,

up/down

16-bit Up 64 MHz

Maximum operating

frequency

128 MHz

64 MHz

Prescaler

factor

Integer from

1 to 2

where

n=0 to 7

DMA

request

generation

Capture/ compare

channels

Yes 4 3

Yes 4 -

No 1 -

Yes 2 1

Yes 1 1

Yes - -

No N/A -

Complementary

outputs

3.17.1 Advanced-control timer (TIM1)

The advanced-control timer can be seen as a three-phase PWM unit multiplexed on 6 channels. It has complementary PWM outputs with programmable inserted dead-times. It can also be seen as a complete general-purpose timer. The 4 independent channels can be used for:

• input capture

• output compare

• PWM output (edge or center-aligned modes) with full modulation capability (0-100%)

• one-pulse mode output

In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled, so as to turn off any power switches driven by these outputs.

Many features are shared with those of the general-purpose TIMx timers (described in

Section 3.17.2) using the same architecture, so the advanced-control timers can work

together with the TIMx timers via the Timer Link feature for synchronization or event chaining.

DS12232 Rev 2 27/136

Functional overview STM32G071x8/xB

3.17.2 General-purpose timers (TIM2, TIM3, TIM14, TIM15, TIM16, TIM17)

There are six synchronizable general-purpose timers embedded in the device (refer to

Tab l e 7 for comparison). Each general-purpose timer can be used to generate PWM outputs

or act as a simple timebase.

• TIM2 and TIM3

These are full-featured general-purpose timers:

– TIM2 with 32-bit auto-reload up/downcounter and 16-bit prescaler

– TIM3 with 16-bit auto-reload up/downcounter and 16-bit prescaler

They have four independent channels for input capture/output compare, PWM or onepulse mode output. They can operate together or in combination with other generalpurpose timers via the Timer Link feature for synchronization or event chaining. They can generate independent DMA request and support quadrature encoders. Their counters can be frozen in debug mode.

• TIM14

This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. It has one channel for input capture/output compare, PWM output or one-pulse mode output. Its counter can be frozen in debug mode.

• TIM15, 16 and 17

These are general-purpose timers featuring:

– 16-bit auto-reload upcounter and 16-bit prescaler

– 2 channels and 1 complementary channel for TIM15

– 1 channel and 1 complementary channel for TIM16 and TIM17

All channels can be used for input capture/output compare, PWM or one-pulse mode output. The timers can operate together via the Timer Link feature for synchronization or event chaining. They can generate independent DMA request. Their counters can be frozen in debug mode.

3.17.3 Basic timers (TIM6 and TIM7)

These timers are mainly used for triggering DAC conversions. They can also be used as generic 16-bit timebases.

3.17.4 Low-power timers (LPTIM1 and LPTIM2)

These timers have an independent clock. When fed with LSE, LSI or external clock, they keep running in Stop mode and they can wake up the system from it.

28/136 DS12232 Rev 2

STM32G071x8/xB Functional overview

Features of LPTIM1 and LPTIM2:

• 16-bit up counter with 16-bit autoreload register

• 16-bit compare register

• Configurable output (pulse, PWM)

• Continuous/one-shot mode

• Selectable software/hardware input trigger

• Selectable clock source:

– Internal: LSE, LSI, HSI16 or APB clocks

– External: over LPTIM input (working even with no internal clock source running,

used by pulse counter application)

• Programmable digital glitch filter

• Encoder mode

3.17.5 Independent watchdog (IWDG)

The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with user-defined refresh window. It is clocked from an independent 32 kHz internal RC (LSI). Independent of the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. Its counter can be frozen in debug mode.

3.17.6 System window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked by the system clock. It has an early-warning interrupt capability. Its counter can be frozen in debug mode.

3.17.7 SysTick timer

This timer is dedicated to real-time operating systems, but it can also be used as a standard down counter.

Features of SysTick timer:

• 24-bit down counter

• Autoreload capability

• Maskable system interrupt generation when the counter reaches 0

• Programmable clock source

3.18 Real-time clock (RTC), tamper (TAMP) and backup registers

The device embeds an RTC and five 32-bit backup registers, located in the RTC domain of the silicon die.

The ways of powering the RTC domain are described in Section 3.7.6.

The RTC is an independent BCD timer/counter.

DS12232 Rev 2 29/136

Functional overview STM32G071x8/xB

Features of the RTC:

• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,

month, year, in BCD (binary-coded decimal) format

• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month

• Programmable alarm

• On-the-fly correction from 1 to 32767 RTC clock pulses, usable for synchronization with

a master clock

• Reference clock detection - a more precise second-source clock (50 or 60 Hz) can be

used to improve the calendar precision

• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal

inaccuracy

• Two anti-tamper detection pins with programmable filter

• Timestamp feature to save a calendar snapshot, triggered by an event on the

timestamp pin, a tamper event or by switching to VBAT mode

• 17-bit auto-reload wakeup timer (WUT) for periodic events, with programmable

resolution and period

• Multiple clock sources and references:

– A 32.768 kHz external crystal (LSE)

– An external resonator or oscillator (LSE)

– The internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)

– The high-speed external clock (HSE) divided by 32

When clocked by LSE, the RTC operates in VBAT mode and in all low-power modes. When clocked by LSI, the RTC does not operate in VBAT mode, but it does in low-power modes except for the Shutdown mode.

All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt and wake the device up from the low-power modes.

The backup registers allow keeping 20 bytes of user application data in the event of V failure, if a valid backup supply voltage is provided on VBAT pin. They are not affected by the system reset, power reset, and upon the device’s wakeup from Standby or Shutdown modes.

3.19 Inter-integrated circuit interface (I2C)

The device embeds two I2C-bus peripherals I2C1 and I2C2. Refer to Table 8 for the features.

The I

C-bus interface handles communication between the microcontroller and the serial

C-bus. It controls all I2C-bus-specific sequencing, protocol, arbitration and timing.

30/136 DS12232 Rev 2

STM32G071x8/xB Functional overview

Features of the I2C peripheral:

• I

C-bus specification and user manual rev. 5 compatibility:

– Slave and master modes, multimaster capability

– Standard-mode (Sm), with a bitrate up to 100 kbit/s

– Fast-mode (Fm), with a bitrate up to 400 kbit/s

– Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and extra output drive I/Os

– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses

– Programmable setup and hold times

– Clock stretching

• System management bus (SMBus) specification rev 2.0 compatibility:

– Hardware PEC (packet error checking) generation and verification with ACK

control

– Address resolution protocol (ARP) support

– SMBus alert

• Power system management protocol (PMBus™) specification rev 1.1 compatibility

• Independent clock: a choice of independent clock sources allowing the I2C

communication speed to be independent of the PCLK reprogramming

• Wakeup from Stop mode on address match

• Programmable analog and digital noise filters

• 1-byte buffer with DMA capability

Table 8. I

I2C features

C implementation

(1)

I2C1 I2C2

Standard mode (up to 100 kbit/s) X X

Fast mode (up to 400 kbit/s) X X

Fast Mode Plus (up to 1 Mbit/s) with extra output drive I/Os X X

Programmable analog and digital noise filters X X

SMBus/PMBus hardware support X -

Independent clock X -

Wakeup from Stop mode on address match X -

1. X: supported

3.20 Universal synchronous/asynchronous receiver transmitter (USART)

The device embeds universal synchronous/asynchronous receivers/transmitters (USART1, USART2, USART3, USART4) that communicate at speeds of up to 6 Mbit/s.

They provide hardware management of the CTS, RTS and RS485 DE signals, multiprocessor communication mode, master synchronous communication and single-wire half-duplex communication mode. Some can also support SmartCard communication (ISO

7816), IrDA SIR ENDEC, LIN Master/Slave capability and auto baud rate feature, and have

DS12232 Rev 2 31/136

Functional overview STM32G071x8/xB

a clock domain independent of the CPU clock, which allows them to wake up the MCU from Stop mode. The wakeup events from Stop mode are programmable and can be:

• start bit detection

• any received data frame

• a specific programmed data frame

All USART interfaces can be served by the DMA controller.

Table 9. USART implementation

USART modes/features

Hardware flow control for modem X X

Continuous communication using DMA X X

Multiprocessor communication X X

Synchronous mode X X

Smartcard mode X -

Single-wire half-duplex communication X X

IrDA SIR ENDEC block X -

LIN mode X -

Dual clock domain and wakeup from Stop mode X -

Receiver timeout interrupt X -

Modbus communication X -

Auto baud rate detection X -

Driver Enable X X

1. X: supported

(1)

USART1 USART2

USART3 USART4

3.21 Low-power universal asynchronous receiver transmitter (LPUART)

The device embeds one Low-Power UART. The LPUART supports asynchronous serial communication with minimum power consumption. It supports half duplex single wire communication and modem operations (CTS/RTS). It allows multiprocessor communication.

The LPUART has a clock domain independent from the CPU clock, and can wakeup the system from Stop mode. The wakeup events from Stop mode are programmable and can be:

• start bit detection

• any received data frame

• a specific programmed data frame

Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while having an extremely low energy consumption. Higher speed clock can be used to reach higher baudrates.

32/136 DS12232 Rev 2

STM32G071x8/xB Functional overview

The LPUART interface can be served by the DMA controller.

3.22 Serial peripheral interface (SPI)

Two SPI interfaces allow communication at up to 32 Mbits/s in master and slave modes. It supports half-duplex, full-duplex and simplex communications. A 3-bit prescaler gives 8 master mode frequencies. The frame size is configurable from 4 bits to 16 bits. The SPI interfaces support NSS pulse mode, TI mode and hardware CRC calculation.

The SPI interfaces can be served by the DMA controller.

One standard I can operate as master or slave, in half-duplex communication mode. It can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data resolution and synchronized by a specific signal. Audio sampling frequency from 8 kHz up to 192 kHz can be set by an 8-bit programmable linear prescaler. When operating in master mode, it can output a clock for an external audio component at 256 times the sampling frequency.

Hardware CRC calculation X X

Rx/Tx FIFO X X

S interface (multiplexed with SPI1) supporting four different audio standards

Table 10. SPI/I2S implementation

SPI features

(1)

SPI1 SPI2

NSS pulse mode X X

I2S mode X -

TI mode X X

1. X = supported.

3.23 USB Type-C™ Power Delivery controller

The device embeds two controllers (UCPD1 and UCPD2) compliant with USB Type-C Rev.

1.2 and USB Power Delivery Rev. 3.0 specifications.

The controllers use specific I/Os supporting the USB Type-C and USB Power Delivery requirements, featuring:

• USB Type-C pull-up (Rp, all values) and pull-down (Rd) resistors

• “Dead battery” support

• USB Power Delivery message transmission and reception

• FRS (fast role swap) support

DS12232 Rev 2 33/136

Functional overview STM32G071x8/xB

The digital controller handles notably:

• USB Type-C level detection with de-bounce, generating interrupts

• FRS detection, generating an interrupt

• byte-level interface for USB Power Delivery payload, generating interrupts (DMA

compatible)

• USB Power Delivery timing dividers (including a clock pre-scaler)

• CRC generation/checking

• 4b5b encode/decode

• ordered sets (with a programmable ordered set mask at receive)

• frequency recovery in receiver during preamble

The interface offers low-power operation compatible with Stop mode, maintaining the capacity to detect incoming USB Power Delivery messages and FRS signaling.

3.24 Development support

3.24.1 Serial wire debug port (SW-DP)

An Arm SW-DP interface is provided to allow a serial wire debugging tool to be connected to the MCU.

34/136 DS12232 Rev 2

STM32G071x8/xB Pinouts, pin description and alternate functions

MSv39710V3

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

PC4

PC5

PB0

PB1

PB2

PB10

PB11

PB12

PC11

PC12

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

VBAT

VREF+

VDD/VDDA

VSS/VSSA

PF2-NRST

PF0-OSC_IN

PF1-OSC_OUT

PC0

PC1

PC2

PC3

PC8

PA15

PA14-BOOT0

PA1 3

PA12 [PA10]

PA1 1 [ PA9]

PA10

PD9

PD8

PC7

PC6

PA9

PA8

PB15

PB14

PB13

PC9

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PB3

PB4

PB5

PB6

PB7

PB8

PB9

PC10

Top view

LQFP64

5352515049

646362

2829303132

171819

4 Pinouts, pin description and alternate functions

The devices housed in 64- and 48-pin packages provide 2-port USB-C Power Delivery. The devices housed in 28/32-pin packages come in two variants - “GP” with a single-port limited USB-C Power Delivery and “PD” with 2-port USB-C Power Delivery.

Figure 3. STM32G071RxT LQFP64 pinout

DS12232 Rev 2 35/136

Pinouts, pin description and alternate functions STM32G071x8/xB

MSv47971V1

VDD/

VDDA

VREF+

VBAT

PB5 PD3

VSS/

VSSA

PF2-

NRST

PC0

PA7 PC7

PF0-

OSC_I

PC1

PA3

PA6 PB0

PF1-

OSC_

OUT

PC2

PA2

PA5 PB1

PC3 PA0 PA 1 PA4 PC4

PC11 PC10 PB7 PB6 PD6

PC15-

OSC32

_OUT

PC12

PB8

PB3 PD5

PC14-

OSC32

_IN

PC13

PB9

PB4 PD4

PA10

PA13 PD9

PA9

PC6 PD8

PB14

PB15 PA 8

PB10

PB12 PB13

PC5 PB2 PB11

PD2 PD0 PC8

PD1

PC9

PA12

[PA10]

PA15

PA14-

BOOT0

PA11 [PA9]

12345678

MSv39711V3

PA2

PA3

PA4

PA5

PA6

PA7

PB0

PB1

PB2

PB10

PB11

PB12

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

VBAT

VREF+

VDD/VDDA

VSS/VSSA

PF2-NRST

PF0-OSC_IN

PF1-OSC_OUT

PA0 PA1

PA14-BOOT0 PA13 PA12 [PA10] PA11 [PA9] PA10 PC7 PC6 PA9 PA8 PB15 PB14 PB13

PA15

PD0

PD1

PD2

PD3

PB3

PB4

PB5

PB6

PB7

PB8

PB9

Top view

LQFP48

393740

484746

222421

131415

Figure 4. STM32G071RxH UFBGA64 ballout

Figure 5. STM32G071CxT LQFP48 pinout

36/136 DS12232 Rev 2

STM32G071x8/xB Pinouts, pin description and alternate functions

Exposed pad

MSv39714V3

Top view

UFQFPN48

393740

484746

222421

131415

VSS

PA2

PA3

PA4

PA5

PA6

PA7

PB0

PB1

PB2

PB10

PB11

PB12

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

VBAT

VREF+

VDD/VDDA

VSS/VSSA

PF2-NRST

PF0-OSC_IN

PF1-OSC_OUT

PA0 PA1

PA14-BOOT0 PA13 PA12 [PA10] PA11 [PA9] PA10 PC7 PC6 PA9 PA8 PB15 PB14 PB13

PA15

PD0

PD1

PD2

PD3

PB3

PB4

PB5

PB6

PB7

PB8

PB9

MSv42120V1

PA2

PA3

PA4

PA5

PA6

PA7

PB0

PB1

PB9

PC14-OSC32_IN

PC15-OSC32_OUT

VDD/VDDA

VSS/VSSA

PF2-NRST

PA0

PA1

PA13

PA12 [PA10]

PA11 [PA9]

PA10

PC6

PA9

PA8

PB15

PA14-BOOT0

PD0

PD1

PD2

PD3

PB6

PB7

PB8

Top view

LQFP32

323130

MSv39712V3

PA2

PA3

PA4

PA5

PA6

PA7

PB0

PB1

PB9

PC14-OSC32_IN

PC15-OSC32_OUT

VDD/VDDA

VSS/VSSA

PF2-NRST

PA0

PA1

PA13

PA12 [PA10]

PA11 [PA9]

PA10

PC6

PA9

PA8

PB2

PA14-BOOT0

PA15

PB3

PB4

PB5

PB6

PB7

PB8

Top view

LQFP32

323130

GP version

PD version

(STM32G071KxTxN)

(STM32G071KxT)

Figure 6. STM32G071CxU UFQFPN48 pinout

xposed pa

Figure 7. STM32G071KxT LQFP32 pinout

DS12232 Rev 2 37/136

Pinouts, pin description and alternate functions STM32G071x8/xB

MSv42121V1

PA2

PA3

PA4

PA5

PA6

PA7

PB0

PB1

PB9

PC14-OSC32_IN

PC15-OSC32_OUT

VDD/VDDA

VSS/VSSA

PF2-NRST

PA0 PA1

PA13 PA12 [PA10] PA11 [PA9] PA10 PC6 PA9 PA8 PB15

PA14-BOOT0

PD0

PD1

PD2

PD3

PB6

PB7

PB8

Top view

UFQFPN32

323130

VSS

MSv39715V3

PA2

PA3

PA4

PA5

PA6

PA7

PB0

PB1

PB9

PC14-OSC32_IN

PC15-OSC32_OUT

VDD/VDDA

VSS/VSSA

PF2-NRST

PA0 PA1

PA13 PA12 [PA10] PA11 [PA9] PA10 PC6 PA9 PA8 PB2

PA14-BOOT0

PA15

PB3

PB4

PB5

PB6

PB7

PB8

Top view

UFQFPN32

323130

VSS

GP version

PD version

(STM32G071KxUxN)

(STM32G071KxU)

Figure 8. STM32G071KxU UFQFPN32 pinout

38/136 DS12232 Rev 2

STM32G071x8/xB Pinouts, pin description and alternate functions

MSv42122V2

PA2

PA3

PA4

PA5

PA6

PA7

PB0

PC14-OSC32_IN

PC15-OSC32_OUT

VDD/VDDA

VSS/VSSA

PF2-NRST

PA0 PA1

PA14-BOOT0 PA13 PA12 [PA10] PA11 [ PA9] PC6 PA8 PB15

PD0

PD1

PD2

PD3

PB6

PB7

PB8

Top view

UFQFPN28

282726

MSv39713V4

PA2

PA3

PA4

PA5

PA6

PA7

PB0

PC14-OSC32_IN

PC15-OSC32_OUT

VDD/VDDA

VSS/VSSA

PF2-NRST

PA0 PA1

PA14-BOOT0 PA13 PA12 [PA10] PA11 [ PA9] PC6 PA8 PB1

PA15

PB3

PB4

PB5

PB6

PB7

PB8

Top view

UFQFPN28

282726

GP version

PD version

(STM32G071GxUxN)

(STM32G071GxU)

MSv47938V1

12345

PA15

PA14-

BOOT0

PB5 PB7

PC14-

OSC32

_IN

PA12

[PA10]

PA13 PB6 PB8

PC15-

OSC32

_OUT

PA11 [PA9]

PA6 PA 3 PA0 VDD

PA8 PA 7 PA4 PA 1 VSS

PB1 PB0 PA5 PA 2

PF2 NRST

Top view

Figure 9. STM32G071GxU UFQFPN28 pinout

Figure 10. STM32G071Ex WLCSP25 pinout

DS12232 Rev 2 39/136

Pinouts, pin description and alternate functions STM32G071x8/xB

Table 11. Terms and symbols used in Table 12

Column Symbol Definition

Pin name

Terminal name corresponds to its by-default function at reset, unless otherwise specified in parenthesis under the pin name.

S Supply pin

Pin type

I Input only pin

I/O Input / output pin

FT 5 V tolerant I/O

TT 3.6 V tolerant I/O

RST Bidirectional reset pin with embedded weak pull-up resistor

Options for TT or FT I/Os

I/O structure

_f I/O, Fm+ capable

_a I/O, with analog switch function

_c I/O, USB Type-C PD capable

_d I/O, USB Type-C PD Dead Battery function

Note Upon reset, all I/Os are set as analog inputs, unless otherwise specified.

functions

Alternate functions

Additional

functions

Functions selected through GPIOx_AFR registers

Functions directly selected/enabled through peripheral registers

Table 12. Pin assignment and description

Pin Number

Pin name

(function

Pin type

I/O structure

WLCSP25

UFQFPN28 - PD

UFQFPN28 - GP

LQFP64

UFBGA64

upon reset)

LQFP48 / UFQFPN48

LQFP32 / UFQFPN32 - PD

LQFP32 / UFQFPN32 - GP

- - - - - - A1 1 PC11 I/O FT -

- - - - - - B2 2 PC12 I/O FT -

- - - - - 1 C2 3 PC13 I/O FT

Alternate

Note

functions

USART3_RX,

USART4_RX, TIM1_CH4

LPTIM1_IN1,

UCPD1_FRSTX,

TIM14_CH1

(1)

(2)

TIM1_BKIN

Additional

functions

TAM P_I N1,R TC_TS, RTC_OUT1,WKUP2

40/136 DS12232 Rev 2

STM32G071x8/xB Pinouts, pin description and alternate functions

Table 12. Pin assignment and description (continued)

Pin Number

Pin name

LQFP64

WLCSP25

UFQFPN28 - PD

UFQFPN28 - GP

UFBGA64

LQFP48 / UFQFPN48

LQFP32 / UFQFPN32 - PD

LQFP32 / UFQFPN32 - GP

-----2C14

A51122---

B52 2 3 3 3B15

(function

upon reset)

PC14-

OSC32_IN

(PC14)

PC14-

OSC32_IN

(PC14)

PC15-

OSC32_OU

(PC15)

Pin type

I/O FT

Note

I/O structure

(1)(2

)

(1)(2

)

(1)(2

)

Alternate

functions

TIM1_BKIN2 OSC32_IN

TIM1_BKIN2 OSC32_IN,OSC_IN

OSC32_EN, OSC_EN,

TIM15_BKIN

Additional

functions

OSC32_OUT

- - - - - 4 D3 6 VBAT S - - - -

- - - - - 5 D2 7 VREF+ S - - - VREF_OUT

C5 3 3 4 4 6 D1 8 VDD/VDDA S - - - -

D5 4 4 5 5 7 E1 9 VSS/VSSA S - - - -

PF0-

-----8F110

OSC_IN

I/O FT - TIM14_CH1 OSC_IN

(PF0)

PF1-

-----9G111

OSC_OUT

I/O FT - OSC_EN, TIM15_CH1N OSC_OUT

(PF1)

E5 5 5 6 6 10 E2 12 PF2 - NRST I/O FT - MCO NRST

LPTIM1_IN1,

- - - - - - E3 13 PC0 I/O FT -

LPUART1_RX,

LPTIM2_IN1

LPTIM1_OUT,

- - - - - - F2 14 PC1 I/O FT -

LPUART1_TX,

TIM15_CH1

- - - - - - G2 15 PC2 I/O FT -

LPTIM1_IN2,

SPI2_MISO, TIM15_CH2

LPTIM1_ETR,

- - - - - - H1 16 PC3 I/O FT -

SPI2_MOSI,

LPTIM2_ETR

DS12232 Rev 2 41/136

Pinouts, pin description and alternate functions STM32G071x8/xB

Table 12. Pin assignment and description (continued)

Pin Number

Pin name

(function

upon reset)

LQFP64

WLCSP25

UFQFPN28 - PD

UFQFPN28 - GP

LQFP32 / UFQFPN32 - PD

LQFP32 / UFQFPN32 - GP

C4 6 6 7 7 11 H2 17 PA0 I/O FT_a -

D4 7 7 8 8 12 H3 18 PA1 I/O FT_a -

E4 8 8 9 9 13 G3 19 PA2 I/O FT_a -

C3 9 9 10 10 14 F3 20 PA3 I/O FT_a -

- - - - - 15H421 PA4 I/O TT_a -

D3 10 10 11 11 - - - PA4 I/O TT_a -

UFBGA64

LQFP48 / UFQFPN48

Pin type

I/O structure

Alternate

Note

functions

SPI2_SCK,

USART2_CTS,

TIM2_CH1_ETR,

USART4_TX,

LPTIM1_OUT,

UCPD2_FRSTX,

COMP1_OUT

SPI1_SCK/I2S1_CK,

USART2_RTS_DE_CK,

TIM2_CH2,

USART4_RX,

TIM15_CH1N,

I2C1_SMBA,

EVENTOUT

SPI1_MOSI/I2S1_SD,

USART2_TX, TIM2_CH3,

UCPD1_FRSTX,

TIM15_CH1,

LPUART1_TX,

COMP2_OUT

SPI2_MISO,

USART2_RX,

TIM2_CH4,

UCPD2_FRSTX,

TIM15_CH2,

LPUART1_RX,

EVENTOUT

SPI1_NSS/I2S1_WS,

SPI2_MOSI,

TIM14_CH1,

LPTIM2_OUT,

UCPD2_FRSTX,

EVENTOUT

SPI1_NSS/I2S1_WS,

SPI2_MOSI,

TIM14_CH1,

LPTIM2_OUT,

UCPD2_FRSTX,

EVENTOUT

Additional

functions

COMP1_INM,

ADC_IN0,

TAMP_IN2,WKUP1

COMP1_INP,

ADC_IN1

COMP2_INM,

ADC_IN2,

WKUP4,LSCO

COMP2_INP,

ADC_IN3

ADC_IN4,

DAC_OUT1,

RTC_OUT2

ADC_IN4,

DAC_OUT1, TAM P_I N1,R TC_TS, RTC_OUT1,WKUP2

42/136 DS12232 Rev 2

STM32G071x8/xB Pinouts, pin description and alternate functions

Table 12. Pin assignment and description (continued)

Pin Number

Pin name

(function

Pin type

I/O structure

WLCSP25

UFQFPN28 - PD

UFQFPN28 - GP

LQFP64

UFBGA64

upon reset)

LQFP48 / UFQFPN48

LQFP32 / UFQFPN32 - PD

LQFP32 / UFQFPN32 - GP

E3 11 11 12 12 16 G4 22 PA5 I/O TT_a -

C2 12 12 13 13 17 F4 23 PA6 I/O FT_a -

Alternate

Note

functions

SPI1_SCK/I2S1_CK,

CEC, TIM2_CH1_ETR,

USART3_TX,

LPTIM2_ETR,

UCPD1_FRSTX,

EVENTOUT

SPI1_MISO/I2S1_MCK, TIM3_CH1, TIM1_BKIN,

USART3_CTS,

TIM16_CH1,

LPUART1_CTS,

COMP1_OUT

Additional

functions

ADC_IN5,

DAC_OUT2

ADC_IN6

D2 13 13 14 14 18 E4 24 PA7 I/O FT_a -

- - - - - - H5 25 PC4 I/O FT_a -

- - - - - - H6 26 PC5 I/O FT_a -

E2 14 - 15 15 19 F5 27 PB0 I/O FT_a -

- - 14 - - - - - PB0 I/O FT_da -

SPI1_MOSI/I2S1_SD,

TIM3_CH2, TIM1_CH1N,

TIM14_CH1, TIM17_CH1,

UCPD1_FRSTX,

COMP2_OUT

USART3_TX, USART1_TX,

TIM2_CH1_ETR

USART3_RX,

USART1_RX, TIM2_CH2

SPI1_NSS/I2S1_WS,

TIM3_CH3, TIM1_CH2N,

USART3_RX,

LPTIM1_OUT,

UCPD1_FRSTX,

COMP1_OUT

SPI1_NSS/I2S1_WS,

TIM3_CH3, TIM1_CH2N,

USART3_RX,

LPTIM1_OUT,

UCPD1_FRSTX,

COMP1_OUT

ADC_IN7

COMP1_INM,

ADC_IN17

COMP1_INP,

ADC_IN18, WKUP5

ADC_IN8

UCPD1_DBCC2,

ADC_IN8

DS12232 Rev 2 43/136

Pinouts, pin description and alternate functions STM32G071x8/xB

Table 12. Pin assignment and description (continued)

Pin Number

Pin name

(function

upon reset)

LQFP64

WLCSP25

UFQFPN28 - PD

UFQFPN28 - GP

LQFP32 / UFQFPN32 - PD

LQFP32 / UFQFPN32 - GP

E1 15 - 16 16 20 G5 28 PB1 I/O FT_a -

- - - 17 - 21 H7 29 PB2 I/O FT_a -

- - - - - 22 G6 30 PB10 I/O FT_fa -

- - - - - 23H831 PB11 I/O FT_fa -

- - - - - 24 G7 32 PB12 I/O FT_a -

- - - - - 25 G8 33 PB13 I/O FT_f -

- - - - - 26 F6 34 PB14 I/O FT_f -

UFBGA64

LQFP48 / UFQFPN48

Pin type

I/O structure

Alternate

Note

functions

TIM14_CH1, TIM3_CH4,

TIM1_CH3N,

USART3_RTS_DE_CK,

LPTIM2_IN1,

LPUART1_RTS_DE,

EVENTOUT

SPI2_MISO,

USART3_TX,

LPTIM1_OUT,

EVENTOUT

CEC, LPUART1_RX,

TIM2_CH3, USART3_TX,

SPI2_SCK, I2C2_SCL,

COMP1_OUT

SPI2_MOSI,

LPUART1_TX,

TIM2_CH4,

USART3_RX, I2C2_SDA,

COMP2_OUT

SPI2_NSS,

LPUART1_RTS_DE,

TIM1_BKIN,

TIM15_BKIN,

UCPD2_FRSTX,

EVENTOUT

SPI2_SCK,

LPUART1_CTS,

TIM1_CH1N,

USART3_CTS,

TIM15_CH1N,

I2C2_SCL, EVENTOUT

SPI2_MISO,

UCPD1_FRSTX,

TIM1_CH2N,

USART3_RTS_DE_CK,

TIM15_CH1, I2C2_SDA,

EVENTOUT

Additional

functions

COMP1_INM,

ADC_IN9

COMP1_INP,

ADC_IN10

ADC_IN11

ADC_IN15

ADC_IN16

44/136 DS12232 Rev 2

STM32G071x8/xB Pinouts, pin description and alternate functions

Table 12. Pin assignment and description (continued)

Pin Number

Pin name

(function

Pin type

I/O structure

WLCSP25

UFQFPN28 - PD

UFQFPN28 - GP

LQFP64

UFBGA64

upon reset)

LQFP48 / UFQFPN48

LQFP32 / UFQFPN32 - PD

LQFP32 / UFQFPN32 - GP

- - 15 - 17 27 F7 35 PB15 I/O FT_c -

D1 16 16 18 18 28 F8 36 PA8 I/O FT_c -

- - - 1919 29E637 PA9 I/O FT_fd -

Alternate

Note

functions

SPI2_MOSI,

TIM1_CH3N,

TIM15_CH1N,

TIM15_CH2, EVENTOUT

MCO, SPI2_NSS,

TIM1_CH1,

LPTIM2_OUT,

EVENTOUT

MCO, USART1_TX,

TIM1_CH2, SPI2_MISO,

TIM15_BKIN, I2C1_SCL,

EVENTOUT

Additional

functions

UCPD1_CC2,

RTC_REFIN,

UCPD1_CC1

UCPD1_DBCC1

- 17 - 20 20 30 E7 38 PC6 I/O FT -

--17----- PC6 I/OFT_d -

- - - - - 31E539 PC7 I/O FT -

- - - - - - E8 40 PD8 I/O FT -

- - - - - - D8 41 PD9 I/O FT -

- - - 21 2132D642 PA10 I/O FT_fd -

C1 18 18 22 22 33 C8 43

B1 19 19 23 23 34 B8 44

PA11

[PA9]

PA1 2

[PA10]

I/O FT_f -

(3)

I/O FT_f -

(3)

UCPD1_FRSTX,

TIM3_CH1, TIM2_CH3

UCPD1_FRSTX,

TIM3_CH1, TIM2_CH3

UCPD2_FRSTX,

TIM3_CH2, TIM2_CH4

USART3_TX,

SPI1_SCK/I2S1_CK,

LPTIM1_OUT

USART3_RX,

SPI1_NSS/I2S1_WS,

TIM1_BKIN2

SPI2_MOSI,

USART1_RX,

TIM1_CH3, TIM17_BKIN,

I2C1_SDA, EVENTOUT

SPI1_MISO/I2S1_MCK,

USART1_CTS, TIM1_CH4, TIM1_BKIN2, I2C2_SCL, COMP1_OUT

SPI1_MOSI/I2S1_SD,

USART1_RTS_DE_CK,

TIM1_ETR, I2S_CKIN,

I2C2_SDA,

COMP2_OUT

UCPD1_DBCC1

UCPD1_DBCC2

DS12232 Rev 2 45/136

Pinouts, pin description and alternate functions STM32G071x8/xB

Table 12. Pin assignment and description (continued)

Pin Number

Pin name

(function

Pin type

I/O structure

WLCSP25

UFQFPN28 - PD

UFQFPN28 - GP

LQFP64

UFBGA64

upon reset)

LQFP48 / UFQFPN48

LQFP32 / UFQFPN32 - PD

LQFP32 / UFQFPN32 - GP

B2 20 20 24 24 35 D7 45 PA13 I/O FT

A2 21 21 25 25 36 C7 46

PA1 4-

BOOT0

I/O FT

A1 22 - 26 - 37 C6 47 PA15 I/O FT -

- - - - - - A8 48 PC8 I/O FT -

Alternate

Note

(4)

functions

SWDIO, IR_OUT,

EVENTOUT

SWCLK, USART2_TX,

(4)

EVENTOUT

SPI1_NSS/I2S1_WS,

USART2_RX,

TIM2_CH1_ETR, USART4_RTS_DE_CK, USART3_RTS_DE_CK,

EVENTOUT

UCPD2_FRSTX,

TIM3_CH3, TIM1_CH1

Additional

functions

BOOT0

- - - - - - B7 49 PC9 I/O FT -

- - 22 - 2638A750 PD0 I/O FT_c -

- - 23 - 2739B651 PD1 I/O FT_d -

- - 24 - 2840A652 PD2 I/O FT_c -

- - 25 - 29 41D553 PD3 I/O FT_d -

- - - - - - C5 54 PD4 I/O FT -

- - - - - - B5 55 PD5 I/O FT -

- - - - - - A5 56 PD6 I/O FT -

- 23 - 27 - 42B457 PB3 I/O FT_a -

I2S_CKIN, TIM3_CH4,

TIM1_CH2

EVENTOUT, SPI2_NSS,

TIM16_CH1

EVENTOUT, SPI2_SCK,

TIM17_CH1

USART3_RTS_DE_CK,

TIM3_ETR, TIM1_CH1N

USART2_CTS,

SPI2_MISO, TIM1_CH2N

USART2_RTS_DE_CK,

SPI2_MOSI, TIM1_CH3N

USART2_TX,

SPI1_MISO/I2S1_MCK,

TIM1_BKIN

USART2_RX,

SPI1_MOSI/I2S1_SD,

LPTIM2_OUT

SPI1_SCK/I2S1_CK,

TIM1_CH2, TIM2_CH2,

USART1_RTS_DE_CK,

EVENTOUT

UCPD2_CC1

UCPD2_DBCC1

UCPD2_CC2

UCPD2_DBCC2

COMP2_INM

46/136 DS12232 Rev 2

STM32G071x8/xB Pinouts, pin description and alternate functions

Table 12. Pin assignment and description (continued)

Pin Number

Pin name

(function

Pin type

I/O structure

WLCSP25

UFQFPN28 - PD

UFQFPN28 - GP

LQFP64

UFBGA64

upon reset)

LQFP48 / UFQFPN48

LQFP32 / UFQFPN32 - PD

LQFP32 / UFQFPN32 - GP

- 24 - 28 - 43C458 PB4 I/O FT_a -

A3 25 - 29 - 44 D4 59 PB5 I/O FT -

B3 26 26 30 30 45 A4 60 PB6 I/O FT_fa -

Alternate

Note

functions

SPI1_MISO/I2S1_MCK,

TIM3_CH1,

USART1_CTS,

TIM17_BKIN,

EVENTOUT

SPI1_MOSI/I2S1_SD,

TIM3_CH2, TIM16_BKIN,

LPTIM1_IN1, I2C1_SMBA,

COMP2_OUT

USART1_TX, TIM1_CH3,

TIM16_CH1N,

SPI2_MISO,

LPTIM1_ETR,

I2C1_SCL, EVENTOUT

Additional

functions

COMP2_INP

WKUP6

COMP2_INP

A4 27 27 31 31 46 A3 61 PB7 I/O FT_fa -

B4 28 28 32 32 47 B3 62 PB8 I/O FT_f -

- - - 1 1 48C363 PB9 I/O FT_f -

- - - - - - A2 64 PC10 I/O FT -

USART1_RX,

SPI2_MOSI,

TIM17_CH1N,

USART4_CTS,

LPTIM1_IN2, I2C1_SDA,

EVENTOUT

CEC, SPI2_SCK,

TIM16_CH1,

USART3_TX,

TIM15_BKIN, I2C1_SCL,

EVENTOUT

IR_OUT,

UCPD2_FRSTX,

TIM17_CH1,

USART3_RX,

SPI2_NSS, I2C1_SDA,

EVENTOUT

USART3_TX,

USART4_TX, TIM1_CH3

COMP2_INM,

PVD_IN

DS12232 Rev 2 47/136

Pinouts, pin description and alternate functions STM32G071x8/xB

1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:

- The speed should not exceed 2 MHz with a maximum load of 30 pF

- These GPIOs must not be used as current sources (for example to drive an LED).

2. After a RTC domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers. The RTC registers are not reset upon system reset. For details on how to manage these GPIOs, refer to the RTC domain and RTC register descriptions in the RM0444 reference manual.

3. Pin pair PA9/PA10 can be remapped in place of pin pair PA11/PA12 (default mapping), using SYSCFG_CFGR1 register.

4. Upon reset, these pins are configured as SW debug alternate functions, and the internal pull-up on PA13 pin and the internal pull-down on PA14 pin are activated.

48/136 DS12232 Rev 2

DS12232 Rev 2 49/136

Table 13. Port A alternate function mapping

Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

PA0 SPI2_SCK USART2_CTS TIM2_CH1_ETR - USART4_TX LPTIM1_OUT UCPD2_FRSTX COMP1_OUT

PA1

PA2

PA3 SPI2_MISO USART2_RX TIM2_CH4 - UCPD2_FRSTX TIM15_CH2 LPUART1_RX EVENTOUT

PA4

PA5

PA6

PA7

PA8 MCO SPI2_NSS TIM1_CH1 - - LPTIM2_OUT - EVENTOUT

PA9 MCO USART1_TX TIM1_CH2 - SPI2_MISO TIM15_BKIN I2C1_SCL EVENTOUT

PA10 SPI2_MOSI USART1_RX TIM1_CH3 - - TIM17_BKIN I2C1_SDA EVENTOUT

PA11

PA1 2

PA13 SWDIO IR_OUT - - - - - EVENTOUT

PA14 SWCLK USART2_TX - - - - - EVENTOUT

PA1 5

SPI1_SCK/

I2S1_CK

SPI1_MOSI/

I2S1_SD

SPI1_NSS/

I2S1_WS

SPI1_SCK/

I2S1_CK

SPI1_MISO/

I2S1_MCK

SPI1_MOSI/

I2S1_SD

SPI1_MISO/

I2S1_MCK

SPI1_MOSI/

I2S1_SD

SPI1_NSS/

I2S1_WS

USART2_RTS

_DE_CK

USART2_TX TIM2_CH3 - UCPD1_FRSTX TIM15_CH1 LPUART1_TX COMP2_OUT

SPI2_MOSI - - TIM14_CH1 LPTIM2_OUT UCPD2_FRSTX EVENTOUT

CEC TIM2_CH1_ETR - USART3_TX LPTIM2_ETR UCPD1_FRSTX EVENTOUT

TIM3_CH1 TIM1_BKIN - USART3_CTS TIM16_CH1 LPUART1_CTS COMP1_OUT

TIM3_CH2 TIM1_CH1N - TIM14_CH1 TIM17_CH1 UCPD1_FRSTX COMP2_OUT

USART1_CTS TIM1_CH4 - - TIM1_BKIN2 I2C2_SCL COMP1_OUT

USART1_RTS

_DE_CK

USART2_RX TIM2_CH1_ETR -

TIM2_CH2 - USART4_RX TIM15_CH1N I2C1_SMBA EVENTOUT

TIM1_ETR - - I2S_CKIN I2C2_SDA COMP2_OUT

USART4_RTS

_DE_CK

USART3_RTS

_DE_CK

-EVENTOUT

STM32G071x8/xB Pinouts, pin description and alternate functions

50/136 DS12232 Rev 2

Table 14. Port B alternate function mapping

Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

Pinouts, pin description and alternate functions STM32G071x8/xB

PB0

PB1 TIM14_CH1 TIM3_CH4 TIM1_CH3N -

SPI1_NSS/I2S1

_WS

TIM3_CH3 TIM1_CH2N - USART3_RX LPTIM1_OUT UCPD1_FRSTX COMP1_OUT

USART3_RTS

_DE_CK

LPTIM2_IN1

LPUART1_RTS

_DE

EVENTOUT

PB2 - SPI2_MISO - - USART3_TX LPTIM1_OUT - EVENTOUT

PB3

PB4

PB5

SPI1_SCK/I2S1

_CK

SPI1_MISO/I2S1

_MCK

SPI1_MOSI/I2S1

_SD

TIM1_CH2 TIM2_CH2 -

TIM3_CH1 - - USART1_CTS TIM17_BKIN - EVENTOUT

TIM3_CH2 TIM16_BKIN - - LPTIM1_IN1 I2C1_SMBA COMP2_OUT

USART1_RTS

_DE_CK

- - EVENTOUT

PB6 USART1_TX TIM1_CH3 TIM16_CH1N - SPI2_MISO LPTIM1_ETR I2C1_SCL EVENTOUT

PB7 USART1_RX SPI2_MOSI TIM17_CH1N - USART4_CTS LPTIM1_IN2 I2C1_SDA EVENTOUT

PB8 CEC SPI2_SCK TIM16_CH1 - USART3_TX TIM15_BKIN I2C1_SCL EVENTOUT

PB9 IR_OUT UCPD2_FRSTX TIM17_CH1 - USART3_RX SPI2_NSS I2C1_SDA EVENTOUT

PB10 CEC LPUART1_RX TIM2_CH3 - USART3_TX SPI2_SCK I2C2_SCL COMP1_OUT

PB11 SPI2_MOSI LPUART1_TX TIM2_CH4 - USART3_RX - I2C2_SDA COMP2_OUT

PB12 SPI2_NSS

LPUART1_RTS

_DE

TIM1_BKIN - - TIM15_BKIN UCPD2_FRSTX EVENTOUT

PB13 SPI2_SCK LPUART1_CTS TIM1_CH1N - USART3_CTS TIM15_CH1N I2C2_SCL EVENTOUT

PB14 SPI2_MISO UCPD1_FRSTX TIM1_CH2N -

USART3_RTS

_DE_CK

TIM15_CH1 I2C2_SDA EVENTOUT

PB15 SPI2_MOSI - TIM1_CH3N - TIM15_CH1N TIM15_CH2 - EVENTOUT

DS12232 Rev 2 51/136

Table 15. Port C alternate function mapping

STM32G071x8/xB Pinouts, pin description and alternate functions

Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

PC0LPTIM1_IN1LPUART1_RXLPTIM2_IN1-----

PC1LPTIM1_OUTLPUART1_TXTIM15_CH1-----

PC2LPTIM1_IN2SPI2_MISOTIM15_CH2-----

PC3LPTIM1_ETRSPI2_MOSILPTIM2_ETR-----

PC4USART3_TXUSART1_TXTIM2_CH1_ETR-----

PC5USART3_RXUSART1_RXTIM2_CH2-----

PC6UCPD1_FRSTXTIM3_CH1TIM2_CH3-----

PC7UCPD2_FRSTXTIM3_CH2TIM2_CH4-----

PC8UCPD2_FRSTXTIM3_CH3TIM1_CH1-----

PC9I2S_CKINTIM3_CH4TIM1_CH2-----

PC10USART3_TXUSART4_TXTIM1_CH3-----

PC11USART3_RXUSART4_RXTIM1_CH4-----

PC12LPTIM1_IN1UCPD1_FRSTXTIM14_CH1-----

PC13--TIM1_BKIN-----

PC14--TIM1_BKIN2-----

PC15 OSC32_EN OSC_EN TIM15_BKIN - ----

52/136 DS12232 Rev 2

Table 16. Port D alternate function mapping

Pinouts, pin description and alternate functions STM32G071x8/xB

Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

PD0EVENTOUTSPI2_NSSTIM16_CH1-----

PD1EVENTOUTSPI2_SCKTIM17_CH1-----

PD2

USART3_RTS

_DE_CK

TIM3_ETRTIM1_CH1N-----

PD3USART2_CTSSPI2_MISOTIM1_CH2N-----

PD4

PD5 USART2_TX

PD6 USART2_RX

PD8 USART3_TX

PD9 USART3_RX

USART2_RTS

_DE_CK

SPI2_MOSITIM1_CH3N-----

SPI1_MISO/I2S1

_MCK

SPI1_MOSI/I2S1

_SD

SPI1_SCK/I2S1

_CK

SPI1_NSS/I2S1

_WS

TIM1_BKIN-----

LPTIM2_OUT-----

LPTIM1_OUT-----

TIM1_BKIN2-----

Table 17. Port F alternate function mapping

Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

PF0--TIM14_CH1-----

PF1OSC_EN-TIM15_CH1N-----

PF2MCO-------

STM32G071x8/xB Electrical characteristics

MS19210V1

MCU pin

C = 50 pF

MS19211V1

MCU pin

5 Electrical characteristics

5.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

TBD indicates a value to be defined.

5.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at T the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3σ).

5.1.2 Typical values

= 25 °C and TA = TA(max) (given by

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = V are given only as design guidelines and are not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated

5.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

5.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 11.

5.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 12.

Figure 11. Pin loading conditions Figure 12. Pin input voltage

(mean ±2σ).

= 3 V. They

DDA

DS12232 Rev 2 53/136

109

Electrical characteristics STM32G071x8/xB

MSv47900V1

Backup circuitry

(LSE, RTC and

backup registers)

Kernel logic

(CPU, digital and

memories)

Level shifter

logic

OUT

Regulator

GPIOs

1.55 V to 3.6 V

1 x 100 nF

+ 1 x 4.7 μF

VDD/VDDA

VBAT

CORE

Power switch

DDIO1

ADC DAC

COMPs

VREFBUF

VREF+

VREF-

VSS/VSSA

REF

100 nF

1 μF

SSA

DDA

VREF+

MSv47901V1

DDVBAT

BAT

DDA

)

VBAT

VDD/VDDA

5.1.6 Power supply scheme

Figure 13. Power supply scheme

Caution: Power supply pin pair (VDD/VDDA and VSS/VSSA) must be decoupled with filtering

5.1.7 Current consumption measurement

54/136 DS12232 Rev 2

ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device.

Figure 14. Current consumption measurement scheme

STM32G071x8/xB Electrical characteristics

5.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 18, Table 19 and Table 20 may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Symbol Ratings Min Max Unit

- V

External supply voltage -0.3 4.0

- V

BAT

Input voltage on FT_xx pins except FT_c

(1)

Input voltage on FT_c pins

Input voltage on any other pin

1. Refer to Table 19 for the maximum allowed injected current values.

2. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.

Table 18. Voltage characteristics

- 0.3 VDD +

- 0.3

5.5

4.0

(2)

Table 19. Current characteristics

Symbol Ratings Max Unit

(1)

100

DD/VDDA

SS/VSSA

Current into VDD/VDDA power pin (source)

Current out of VSS/VSSA ground pin (sink)

Output current sunk by any I/O and control pin except FT_f 15

IO(PIN)

Output current sunk by any FT_f pin 20

Output current sourced by any I/O and control pin 15

(6)

(2)

INJ(PIN)

(4)

-5 / 0

must never be

∑I

Total output current sunk by sum of all I/Os and control pins

IO(PIN)

(3)

INJ(PIN)

∑|I

1. All main power (VDD/VDDA, VBAT) and ground (VSS/VSSA) pins must always be connected to the external power supplies, in the permitted range.

2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count packages.

3. A positive injection is induced by V exceeded. Refer also to Table 18: Voltage characteristics for the maximum allowed input voltage values.

4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.

5. On these I/Os, any current injection disturbs the analog performances of the device.

6. When several inputs are submitted to a current injection, the maximum ∑|I injected currents (instantaneous values).

INJ(PIN)

Total output current sourced by sum of all I/Os and control pins

Injected current on a FT_xx pin -5 / NA

Injected current on a TT_a pin

(5)

Total injected current (sum of all I/Os and control pins)

> V

while a negative injection is induced by VIN < VSS. I

DDIOx

is the absolute sum of the negative

INJ(PIN)

DS12232 Rev 2 55/136

109

Electrical characteristics STM32G071x8/xB

Table 20. Thermal characteristics

Symbol Ratings Value Unit

STG

Storage temperature range –65 to +150 °C

Maximum junction temperature 150 °C

5.3 Operating conditions

5.3.1 General operating conditions

Symbol Parameter Conditions Min Max Unit

HCLK

PCLK

Internal AHB clock frequency - 0 64

Internal APB clock frequency - 0 64

Standard operating voltage - 1.7

Analog supply voltage

DDA

Table 21. General operating conditions

(1)

For ADC and COMP operation

For DAC operation 1.8 3.6

For VREFBUF operation 2.4 3.6

1.62 3.6

MHz

3.6 V

Backup operating voltage - 1.55 3.6 V

BAT

All except TT_xx and FT_c -0.3 Min(V

I/O input voltage

FT_c -0.3 5.0

(4)

Ambient temperature

Junction temperature

1. When RESET is released functionality is guaranteed down to V

2. For operation with voltage higher than V

3. The T

4. Temperature range digit in the order code. See Section 7: Ordering information.

(max) applies to PD(max). At PD < PD(max) the ambient temperature is allowed to go higher than TA(max) provided

that the junction temperature TJ does not exceed TJ(max). Refer to Section 6.9: Thermal characteristics.

(3)

Suffix 6

(4)

Suffix 3

(4)

Suffix 6

(4)

Suffix 3

min.

PDR

+0.3 V, the internal pull-up and pull-down resistors must be disabled.

-40 85

-40 125

-40 105

-40 130

+ 3.6, 5.5)

(2)

VTT_xx -0.3 VDD + 0.3

°C

56/136 DS12232 Rev 2

STM32G071x8/xB Electrical characteristics

5.3.2 Operating conditions at power-up / power-down

The parameters given in Table 22 are derived from tests performed under the ambient temperature condition summarized in Table 21.

Symbol Parameter Conditions Min Max Unit

VDD slew rate

VDD

Table 22. Operating conditions at power-up / power-down

rising - ∞

falling; ULPEN = 0 10 ∞

falling; ULPEN = 1 100 ∞ ms/V

µs/V

5.3.3 Embedded reset and power control block characteristics

The parameters given in Table 23 are derived from tests performed under the ambient temperature conditions summarized in Table 21: General operating conditions.

Table 23. Embedded reset and power control block characteristics

Symbol Parameter Conditions

POR temporization when VDD crosses

POR

PDR

BOR1

BOR2

BOR3

BOR4

PVD0

PVD1

PVD2

PVD3

PVD4

(2)

POR

rising - 250 400 μs

Power-on reset threshold - 1.62 1.66 1.70 V

Power-down reset threshold - 1.60 1.64 1.69 V

rising 2.05 2.10 2.18

Brownout reset threshold 1

Brownout reset threshold 2

Brownout reset threshold 3

Brownout reset threshold 4

Programmable voltage detector threshold 0

PVD threshold 1

PVD threshold 2

PVD threshold 3

PVD threshold 4

falling 1.95 2.00 2.08

rising 2.20 2.31 2.38

falling 2.10 2.21 2.28

rising 2.50 2.62 2.68

falling 2.40 2.52 2.58

rising 2.80 2.91 3.00

falling 2.70 2.81 2.90

rising 2.05 2.15 2.22

falling 1.95 2.05 2.12

rising 2.20 2.30 2.37

falling 2.10 2.20 2.27

rising 2.35 2.46 2.54

falling 2.25 2.36 2.44

rising 2.50 2.62 2.70

falling 2.40 2.52 2.60

rising 2.65 2.74 2.87

falling 2.55 2.64 2.77

RSTTEMPO

(1)

Min Typ Max Unit

DS12232 Rev 2 57/136

109

Electrical characteristics STM32G071x8/xB

Table 23. Embedded reset and power control block characteristics (continued)

Symbol Parameter Conditions

rising 2.80 2.91 3.03

PVD5

PVD6

PVD threshold 5

PVD threshold 6

falling 2.70 2.81 2.93

rising 2.90 3.01 3.14

falling 2.80 2.91 3.04

Hysteresis in continuous mode

hyst_POR_PDR

Hysteresis of V

POR

and V

PDR

Hysteresis in other mode

hyst_BOR_PVD

DD(BOR_PVD)

1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.

2. Guaranteed by design.

Hysteresis of V

(2)

BOR and PVD consumption - - 1.1 1.6 µA

BORx

and V

PVDx

(1)

Min Typ Max Unit

-20-

-30-

- - 100 - mV

58/136 DS12232 Rev 2

STM32G071x8/xB Electrical characteristics

MSv40169V1

1.185

1.19

1.195

1.2

1.205

1.21

1.215

1.22

1.225

1.23

1.235

-40 -20 0 20 40 60 80 100 120

°C

Mean Min Max

5.3.4 Embedded voltage reference

The parameters given in Table 24 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 21: General operating

conditions.

Symbol Parameter Conditions Min Typ Max Unit

Table 24. Embedded internal voltage reference

REFINT

S_vrefint

start_vrefint

DD(VREFINTBUF)

∆V

REFINT

Coeff_vrefint

Coeff

DDCoeff

REFINT_DIV1

REFINT_DIV2

REFINT_DIV3

1. The shortest sampling time can be determined in the application by multiple iterations.

2. Guaranteed by design.

Internal reference voltage -40°C < TJ < 130°C 1.182 1.212 1.232 V

ADC sampling time when reading

(1)

the internal reference voltage

Start time of reference voltage buffer when ADC is enable

buffer consumption from

REFINT

VDD when converted by ADC

Internal reference voltage spread over the temperature range

-4

--812

- - 12.5 20

= 3 V - 5 7.5

Temperature coefficient - - 30 50

Long term stability 1000 hours, T = 25 °C - 300 1000

Voltage coefficient 3.0 V < VDD < 3.6 V - 250 1200

1/4 reference voltage

1/2 reference voltage 49 50 51

3/4 reference voltage 74 75 76

Figure 15. V

vs. temperature

REFINT

(2)

--µs

24 25 26

(2)

µs

µA

ppm/°C

ppm

ppm/V

REFINT

DS12232 Rev 2 59/136

109

Electrical characteristics STM32G071x8/xB

5.3.5 Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.

The current consumption is measured as described in Figure 14: Current consumption

measurement scheme.

Typical and maximum current consumption

The MCU is placed under the following conditions:

• All I/O pins are in analog input mode

• All peripherals are disabled except when explicitly mentioned

• The Flash memory access time is adjusted with the minimum wait states number,

depending on the f to CPU clock (HCLK) frequency” available in the RM0444 reference manual).

• When the peripherals are enabled f

• For Flash memory and shared peripherals f

Unless otherwise stated, values given in Table 25 through Table 31 are derived from tests performed under ambient temperature and supply voltage conditions summarized in

Table 21: General operating conditions.

frequency (refer to the table “Number of wait states according

HCLK

= f

PCLK

HCLK

PCLK

= f

HCLK

= f

HCLKS

60/136 DS12232 Rev 2

STM32G071x8/xB Electrical characteristics

Table 25. Current consumption in Run and Low-power run modes

at different die temperatures

(1)

Unit

Symbol Parameter

Supply

DD(Run)

current in

Run mode

General f

Range 1; PLL enabled;

= f

HCLK

HSE_bypass

(≤16 MHz),

= f

HCLK

(>16 MHz);

(3)

PLLRCLK

Range 2; PLL enabled;

= f

HCLK

HSE_bypass

(≤16 MHz),

= f

HCLK

(>16 MHz);

(3)

PLLRCLK

Conditions Typ Max

HCLK

64 MHz

Fetch

from

25°C85°C125°C25°C85°C130°

(2)

6.3 6.4 6.8 6.7 7.0 7.7

56 MHz 5.5 5.7 5.9 5.9 6.3 6.8

48 MHz 5.0 5.1 5.4 5.2 5.7 6.3

32 MHz 3.5 3.6 3.8 4.0 4.3 4.7

Flash

memory

24 MHz 2.8 2.9 3.1 3.1 3.6 4.0

16 MHz 1.8 1.9 2.1 2.1 2.5 3.0

64 MHz

6.0 6.2 6.4 6.3 6.6 7.0

56 MHz 5.3 5.5 5.7 5.6 5.8 6.2

48 MHz 4.7 4.8 5.0 5.0 5.2 5.6

SRAM

32 MHz 3.3 3.4 3.5 3.5 3.8 4.1

24 MHz 2.6 2.7 2.9 2.8 3.1 3.4

16 MHz 1.7 1.7 1.9 1.9 2.1 2.7

16 MHz

8 MHz 0.8 0.9 1.0 1.2 1.3 1.8

2 MHz 0.3 0.3 0.5 0.5 0.8 1.4

Flash

memory

16 MHz

8 MHz 0.7 0.8 1.0 1.1 1.2 1.6

1.4 1.5 1.7 1.7 2.0 2.6

1.4 1.4 1.6 1.6 1.8 2.2

SRAM

4 MHz 0.4 0.5 0.6 0.7 0.9 1.5

2 MHz 0.3 0.3 0.5 0.5 0.8 1.2

2 MHz

220 255 420 530 795 1255

1 MHz 105 155 320 505 770 1200

Flash

memory

199 231 380 485 700 1220

SRAM

DD(LPRun)

Supply

current in

Low-power

run mode

PLL disabled; f

= f

HCLK

HSE

bypass (> 32 kHz),

= f

HCLK

bypass (= 32 kHz);

(3)

LSE

500 kHz 67 105 265 465 700 1110

125 kHz 26 66 230 450 520 1045

32 kHz 17 56 220 375 475 1035

2 MHz

1 MHz 95 140 290 430 660 1140

500 kHz 61 95 240 365 625 1100

125 kHz 24 59 225 335 440 970

32 kHz 15 55 220 325 355 940

1. Based on characterization results, not tested in production.

2. Prefetch and cache enabled when fetching from Flash

= 3.0 V for values in Typ columns and 3.6 V for values in Max columns, all peripherals disabled, cache enabled,

3. V

prefetch disabled for code and data fetch from Flash and enabled from SRAM

DS12232 Rev 2 61/136

µA

109

Electrical characteristics STM32G071x8/xB

Table 26. Typical current consumption in Run and Low-power run modes,

depending on code executed

Symbol Parameter

Supply

DD(Run)

current in

Run mode

General Code

Range 1; f

= f

HCLK

64 MHz;

(2)

PLLRCLK

Range 2; f

HCLK

= f

HSI16

= 16 MHz, PLL disabled,

(2)

Conditions Typ

Unit

6.4

Reduced code

(3)

Fetch

from

25 °C 25 °C

(1)

Coremark 6.2 97

Dhrystone 2.1 5.9 92

Flash

memory

Fibonacci 4.6 71

While(1) loop 4.6 71

Reduced code

(3)

6.2 96

Coremark 6.2 97

Dhrystone 2.1 6.0 93

SRAM

Fibonacci 6.2 96

While(1) loop 4.8 75

Reduced code

(3)

1.5 94

Coremark 1.5 94

Dhrystone 2.1 1.5 91

Flash

memory

Fibonacci 1.1 69

While(1) loop 1.1 69

Reduced code

(3)

1.5 91

Coremark 1.4 88

Dhrystone 2.1 1.4 84

SRAM

Typ

Unit

100

uA/MHz

Fibonacci 1.5 91

While(1) loop 1.1 69

Reduced code

(3)

380

Coremark 395 198

Dhrystone 2.1 405 203

Flash

memory

Fibonacci 385 193

DD(LPRun)

Supply

current in

Low-power

run mode

= f

HCLK

HSI16

2 MHz; PLL disabled,

(2)

/8 =

While(1) loop 400 200

Reduced code

(3)

250 125

Coremark 245 123

Dhrystone 2.1 240 120

SRAM

Fibonacci 250 125

While(1) loop 230 115

1. Prefetch and cache enabled when fetching from Flash

VDD = 3.3 V, all peripherals disabled, cache enabled, prefetch disabled for execution in Flash and enabled in SRAM

3. Reduced code used for characterization results provided in Table 25.

62/136 DS12232 Rev 2

190

uA/MHz

STM32G071x8/xB Electrical characteristics

Table 27. Current consumption in Sleep and Low-power sleep modes

Conditions Typ Max

Symbol Parameter

General

Voltage

scaling

Flash memory enabled;

= f

DD(Sleep)

Supply

current in

Sleep mode

HCLK

(≤16 MHz; PLL disabled), f

HCLK

(>16 MHz; PLL

= f

bypass

HSE

PLLRCLK

Range 1

enabled); All peripherals disabled

Range 2

Supply

DD(LPSleep)

current in

Low-power

sleep mode

1. Based on characterization results, not tested in production.

Flash memory disabled; PLL disabled;

= f

HCLK

bypass (> 32 kHz),

HSE

= f

bypass (= 32 kHz);

LSE

All peripherals disabled

HCLK

25°C85°C125°C25°C85°C130°

64 MHz 1.8 1.9 2.1 1.8 2.1 2.9

56 MHz 1.6 1.7 1.9 1.7 1.9 2.8

48 MHz 1.4 1.5 1.7 1.6 1.7 2.7

32 MHz 1.0 1.1 1.3 1.2 1.3 2.3

24 MHz 0.8 0.9 1.1 1.0 1.1 1.9

16 MHz 0.5 0.6 0.8 0.6 0.7 1.7

16 MHz 0.4 0.5 0.7 0.5 0.6 1.4

8 MHz 0.3 0.3 0.5 0.3 0.5 1.2

2 MHz 0.1 0.2 0.4 0.2 0.4 1.1

2 MHz 60 99 265 150 360 1110

1 MHz 33 75 240 130 330 1010

500 kHz 25 64 230 125 250 870

125 kHz 16 55 220 110 235 715

32 kHz 14 53 215 110 225 645

(1)

Unit

µA

Table 28. Current consumption in Stop 0 mode

Conditions Typ Max

Symbol Parameter

HSI kernel V

1.8 V 275 305 430 330 425 750

2.4 V 280 310 435 330 450 850

Enabled

3 V 280 315 435 350 490 950

DD(Stop 0)

Supply

current in

Stop 0

3.6 V 285 315 440 375 500 1020

1.8 V 95 140 270 120 180 490

mode

2.4 V 100 145 275 125 220 610

Disabled

3 V 100 145 280 125 240 720

3.6 V 105 150 285 130 250 840

1. Based on characterization results, not tested in production.

(1)

Unit

25°C 85°C 125°C 25°C 85°C 130°C

µA

DS12232 Rev 2 63/136

109

Electrical characteristics STM32G071x8/xB

Table 29. Current consumption in Stop 1 mode

Conditions Typ Max

Symbol Parameter

Flash

memory

RTC

(2)

1.8 V 3.2 32 150 8 100 480

2.4 V 3.3 32 150 10 120 535

Disabled

3.6 V 3.8 33 155 18 140 705

1.8 V 3.4 32 150 9 100 480

2.4 V 3.7 32 155 11 120 540

DD(Stop 1)

Supply

current in

Stop 1

Not

powered

Enabled

mode

3.6 V 4.4 34 160 20 145 720

1.8 V 6.9 36 155 12 100 575

2.4 V 7.3 36 160 14 110 600

Powered Disabled

3.6 V 7.8 38 160 23 135 665

1. Based on characterization results, not tested in production.

2. Clocked by LSI

(1)

25°C 85°C 125°C 25°C 85°C 130°C

3 V 3.4 33 155 15 135 620

3 V 4.0 33 155 16 140 630

3 V 7.3 37 160 18 120 645

Unit

µA

Symbol Parameter

Supply current

DD(Standby)

in Standby

mode

Table 30. Current consumption in Standby mode

Conditions Typ Max

(2)

General V

RTC disabled

RTC enabled,

clocked by LSI;

IWDG enabled,

clocked by LSI

ULPEN = 0

1.8 V 0.07 1.7 6.7 0.7 9 34

2.4 V 0.13 2.1 8.1 0.8 12 38

3.0 V 0.20 2.5 10.0 0.9 14 46

3.6 V 0.34 3.0 12.0 1.0 16 55

1.8 V 0.35 2.0 7.0 0.8 10 35

2.4 V 0.49 2.4 8.4 1.0 12 40

3.0 V 0.66 2.9 10.5 1.3 15 47

3.6 V 0.90 3.5 12.5 2.2 18 56

1.8 V 0.26 1.9 6.8 0.8 10 34

2.4 V 0.37 2.3 8.3 1.0 12 39

3.0 V 0.49 2.7 10.3 1.4 15 45

3.6 V 0.69 3.3 12.3 2.1 18 52

1.8 V 0.70 1.6 6.6 - - -

2.4 V 0.89 2.0 8.0 - - -

3.0 V 1.10 2.4 9.8 - - -

3.6 V 1.30 2.9 11.8 - - -

25°C 85°C 125°C 25°C 85°C 130°C

(1)

Unit

µA

64/136 DS12232 Rev 2

STM32G071x8/xB Electrical characteristics

Table 30. Current consumption in Standby mode (continued)

Symbol Parameter

Conditions Typ Max

General V

Extra supply

∆I

DD(SRAM)

1. Based on characterization results, not tested in production.

2. Without SRAM retention and with ULPEN bit set

3. To be added to I

current to retain SRAM

(3)

content

DD(Standby)

SRAM retention

enabled

as appropriate

Table 31. Current consumption in Shutdown mode

1.8 V 0.49 3.0 14.8 0.6 16 58

2.4 V 0.57 3.1 14.9 1.1 17 63

3.0 V 0.67 3.2 15.0 1.5 17 67

3.6 V 0.77 3.3 15.0 1.9 18 71

Conditions Typ Max

Symbol Parameter

RTC V

1.8 V 17 515 4500 250 3000 32600

2.4 V 23 600 5150 450 3500 33600

3.0 V 33 730 6450 1075 4250 37400

3.6 V 53 940 7700 1250 5300 43600

1.8 V 205 710 4700 900 4500 27300

2.4 V 300 890 5500 1550 5500 34800

3.0 V 420 1150 6800 2475 6000 40900

DD(Shutdown)

Supply current

in Shutdown

mode

Disabled

Enabled, clocked

by LSE bypass at

32.768 kHz

3.6 V 565 1450 8100 3250 7000 48500

1. Based on characterization results, not tested in production.

Table 32. Current consumption in VBAT mode

Conditions Typ Max

Symbol Parameter

DD(VBAT)

Supply

current in

VBAT mode

RTC V

Enabled,

clocked by LSE

bypass at

32.768 kHz

Enabled,

clocked by LSE

crystal at

32.768 kHz

1.8 V 165 170 620 - - -

2.4 V 260 355 970 - - -

3.0 V 365 475 1200 - - -

3.6 V 505 655 2070 - - -

1.8 V 290 390 960 - - -

2.4 V 370 480 1150 - - -

3.0 V 470 600 1650 - - -

3.6 V 600 815 2250 - - -

1.8 V 1 80 660 - - -

Disabled

2.4 V 2 90 750 - - -

3.0 V 2 105 1200 - - -

3.6 V 6 200 1700 - - -

25°C 85°C 125°C 25°C 85°C 130°C

(1)

Unit

µA

(1)

Unit

(1)

Unit

1. Based on characterization results, not tested in production.

DS12232 Rev 2 65/136

109

Electrical characteristics STM32G071x8/xB

DDIO1fSW

C××=

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 51: I/O static characteristics.

For the output pins, any external pull-down or external load must also be considered to estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs.

Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,

as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption measured previously (see

Table 33: Current consumption of peripherals, the I/Os used by an application also

contribute to the current consumption. When an I/O pin switches, it uses the current from the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin:

where

is the current sunk by a switching I/O to charge/discharge the capacitive load

C is the total capacitance seen by the I/O pin: C = C

is the I/O supply voltage

DDIO1

is the I/O switching frequency

INT

+ C

EXT + CS

CS is the PCB board capacitance including the pad pin.

The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.

66/136 DS12232 Rev 2

STM32G071x8/xB Electrical characteristics

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in Table 33. The MCU is placed under the following conditions:

• All I/O pins are in Analog mode

• The given value is calculated by measuring the difference of the current consumptions:

– when the peripheral is clocked on

– when the peripheral is clocked off

• Ambient operating temperature and supply voltage conditions summarized in Table 18:

Voltage characteristics

• The power consumption of the digital part of the on-chip peripherals is given in

Table 33. The power consumption of the analog part of the peripherals (where

applicable) is indicated in each related section of the datasheet.

Table 33. Current consumption of peripherals

IOPORT

AHB

APB

Peripheral Range 1 Range 2

IOPORT Bus 1.0 0.7 0.5

GPIOA 3.4 2.8 3.0

GPIOB 3.1 2.6 2.5

GPIOC 2.9 2.5 3.0

GPIOD 1.8 1.5 1.5

GPIOF 0.7 0.6 1.0

Bus matrix 3.2 2.2 2.8

All AHB Peripherals 15.0 12.5 14.0

DMA1/DMAMUX 4.7 3.8 4.5

CRC 0.5 0.4 0.5

FLASH 4.1 3.5 4.0

All APB peripherals 46.5 47.5 48.0

AHB to APB bridge

PWR 0.4 0.3 0.5

SYSCFG/VREFBUF/COMP 0.4 0.4 0.3

WWDG 0.4 0.3 0.5

(1)

0.2 0.2 0.1

Low-power

run and sleep

Unit

µA/MHz

TIM1 7.3 6.1 6.5

TIM2 4.7 3.8 5.0

TIM3 3.6 3.0 2.5

TIM6 0.7 0.6 0.5

DS12232 Rev 2 67/136

109

Electrical characteristics STM32G071x8/xB

Table 33. Current consumption of peripherals (continued)

APB

Peripheral Range 1 Range 2

Low-power

run and sleep

TIM7 0.7 0.7 1.0

TIM14 1.5 1.2 1.5

TIM15 4.0 3.3 3.0

TIM16 2.3 2.0 2.0

TIM17 0.7 0.7 0.5

LPTIM1 3.2 2.7 3.0

LPTIM2 3.1 2.5 3.0

I2C1 3.8 3.1 3.5

I2C2 0.7 0.6 1.0

SPI2 1.5 1.2 1.0

USART1 7.2 6.0 6.5

USART2 7.2 6.0 6.0

USART3 2.0 1.7 2.0

USART4 2.0 1.7 2.0

LPUART1 4.3 3.5 4.0

CEC 0.4 0.3 0.5

UCPD1 4.0 7.7 NA

UCPD2 4.0 7.7 NA

ADC 2.0 1.7 2.0

DAC 2.2 1.8 2.0

Unit

µA/MHz

(2)

1. The AHB to APB Bridge is automatically active when at least one peripheral is ON on the APB.

2. UCPDx are always clocked by HSI16.

5.3.6 Wakeup time from low-power modes and voltage scaling transition times

The wakeup times given in Table 34 are the latency between the event and the execution of the first user instruction.

Table 34. Low-power mode wakeup times

Symbol Parameter Conditions Typ Max Unit

Wakeup time from

WUSLEEP

Sleep to Run

-1111

mode

Transiting to Low-power-run-mode execution in Flash memory not powered in Low-power sleep mode;

HCLK = HSI16 / 8 = 2 MHz

WULPSLEEP

Wakeup time from Low-power sleep mode

68/136 DS12232 Rev 2

(1)

11 1 4

CPU

cycles

STM32G071x8/xB Electrical characteristics

Table 34. Low-power mode wakeup times

(1)

(continued)

Symbol Parameter Conditions Typ Max Unit

Transiting to Run-mode execution in Flash memory not

WUSTOP0

Wakeup time from Stop 0

powered in Stop 0 mode; HCLK = HSI16 = 16 MHz; Regulator in Range 1 or Range 2

Transiting to Run-mode execution in SRAM or in Flash memory powered in Stop 0 mode;

HCLK = HSI16 = 16 MHz;

5.6 6

µs

22.4

Regulator in Range 1 or Range 2

Transiting to Run-mode execution in Flash memory not powered in Stop 1 mode;

HCLK = HSI16 = 16 MHz;

9.0 11.2

Regulator in Range 1 or Range 2

Transiting to Run-mode execution in SRAM or in Flash

WUSTOP1

Wakeup time from Stop 1

memory powered in Stop 1 mode; HCLK = HSI16 = 16 MHz; Regulator in Range 1 or Range 2

Transiting to Low-power-run-mode execution in Flash memory not powered in Stop 1 mode;

HCLK = HSI16/8 = 2 MHz;

57.5

µs

22 25.3

Regulator in low-power mode (LPR = 1 in PWR_CR1)

Transiting to Low-power-run-mode execution in SRAM or in Flash memory powered in Stop 1 mode;

HCLK = HSI16 / 8 = 2 MHz;

18 23.5

Regulator in low-power mode (LPR = 1 in PWR_CR1)

WUSTBY

WUSHDN

Wakeup time from Standby mode

Wakeup time from Shutdown mode

Wakeup time from

WULPRUN

1. Based on characterization results, not tested in production.

2. Time until REGLPF flag is cleared in PWR_SR2.

Low-power run

(2)

mode

Transiting to Run mode; HCLK = HSI16 = 16 MHz; Regulator in Range 1

Transiting to Run mode; HSISYS = HSI16/8 = 2 MHz

Table 35. Regulator mode transition times

(1)

14.5 30 µs

258 340 µs

57µs

Symbol Parameter Conditions Typ Max Unit

VOST

1. Based on characterization results, not tested in production.

2. Time until VOSF flag is cleared in PWR_SR2.

Transition times between regulator Range 1 and Range 2

(2)

HSISYS = HSI16 20 40 µs

DS12232 Rev 2 69/136

109

Electrical characteristics STM32G071x8/xB

MS19214V2

HSEH

f(HSE)

90%

10%

HSE

r(HSE)

HSEL

w(HSEH)

w(HSEL)

Table 36. Wakeup time using LPUART

(1)

Symbol Parameter Conditions Typ Max Unit

Wakeup time needed to calculate the maximum

WULPUART

LPUART baud rate allowing to wakeup up from Stop mode when LPUART clock source is HSI16

1. Guaranteed by design.

Stop mode 0 - 1.7

Stop mode 1 - 8.5

5.3.7 External clock source characteristics

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 5.3.14. See

Figure 16 for recommended clock input waveform.

Table 37. High-speed external user clock characteristics

Symbol Parameter Conditions Min Typ Max Unit

HSE_ext

HSEH

HSEL

w(HSEH)

w(HSEL)

1. Guaranteed by design.

User external clock source frequency

OSC_IN input pin high level voltage - 0.7 V

OSC_IN input pin low level voltage - V

OSC_IN high or low time

Voltage scaling Range 1

Voltage scaling Range 2

Voltage scaling Range 1

Voltage scaling Range 2

-848

-826

DDIO1

7- -

18 - -

(1)

-V

-0.3 V

DDIO1

µs

MHz

Figure 16. High-speed external clock source AC timing diagram

70/136 DS12232 Rev 2

STM32G071x8/xB Electrical characteristics

MS19215V2

LSEH

f(LSE)

90%

10%

LSE

r(LSE)

LSEL

w(LSEH)

w(LSEL)

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 5.3.14. See

Figure 17 for recommended clock input waveform.

Table 38. Low-speed external user clock characteristics

Symbol Parameter Conditions Min Typ Max Unit

(1)

LSE_ext

LSEH

LSEL

w(LSEH)

w(LSEL)

1. Guaranteed by design.

User external clock source frequency - - 32.768 1000 kHz

OSC32_IN input pin high level voltage - 0.7 V

OSC32_IN input pin low level voltage - V

OSC32_IN high or low time - 250 - - ns

DDIO1

-V

- 0.3 V

DDIO1

Figure 17. Low-speed external clock source AC timing diagram

DS12232 Rev 2 71/136

109

Electrical characteristics STM32G071x8/xB

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 39. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Table 39. HSE oscillator characteristics

Symbol Parameter Conditions

(2)

(1)

Min Typ Max Unit

OSC_IN

Oscillator frequency - 4 8 48 MHz

Feedback resistor - - 200 - kΩ

During startup

= 3 V,

Rm = 30 Ω,

(3)

--5.5

-0.44-

CL = 10 pF@8 MHz

= 3 V,

Rm = 45 Ω,

-0.45-

CL = 10 pF@8 MHz

= 3 V,

DD(HSE)

HSE current consumption

Rm = 30 Ω,

-0.68-

CL = 5 pF@48 MHz

= 3 V,

Rm = 30 Ω,

-0.94-

CL = 10 pF@48 MHz

= 3 V,

Rm = 30 Ω,

-1.77-

CL = 20 pF@48 MHz

SU(HSE)

1. Guaranteed by design.

2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

3. This consumption level occurs during the first 2/3 of the t

4. t

SU(HSE)

oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer

Maximum critical crystal

transconductance

(4)

Startup time VDD is stabilized - 2 - ms

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz

Startup - - 1.5 mA/V

startup time

SU(HSE)

For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 18). C same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C

and CL2. PCB and MCU pin capacitance must be included (10 pF

can be used as a rough estimate of the combined pin and board capacitance) when sizing C

and CL2.

72/136 DS12232 Rev 2

and C

are usually the

STM32G071x8/xB Electrical characteristics

MS19876V1

(1)

OSC_IN

OSC_OUT

Bias

controlled

gain

HSE

EXT

8 MHz

resonator

Resonator with integrated capacitors

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator

design guide for ST microcontrollers” available from the ST website www.st.com.

Figure 18. Typical application with an 8 MHz crystal

1. R

value depends on the crystal characteristics.

EXT

Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 40. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Symbol Parameter Conditions

DD(LSE)

critmax

LSE current consumption

Maximum critical crystal gm

Table 40. LSE oscillator characteristics (f

LSEDRV[1:0] = 00 Low drive capability

LSEDRV[1:0] = 01 Medium low drive capability

LSEDRV[1:0] = 10 Medium high drive capability

LSEDRV[1:0] = 11 High drive capability

LSEDRV[1:0] = 00 Low drive capability

LSEDRV[1:0] = 01 Medium low drive capability

LSEDRV[1:0] = 10 Medium high drive capability

LSE

(2)

= 32.768 kHz)

Min Typ Max Unit

-250 -

-315 -

-500 -

-630 -

--0.5

- - 0.75

--1.7

(1)

µA/V

SU(LSE)

LSEDRV[1:0] = 11 High drive capability

(3)

Startup time VDD is stabilized - 2 - s

DS12232 Rev 2 73/136

--2.7

109

Electrical characteristics STM32G071x8/xB

MS30253V2

OSC32_IN

OSC32_OUT

Drive

programmable

amplifier

LSE

32.768 kHz resonator

Resonator with integrated capacitors

1. Guaranteed by design.

2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST microcontrollers”.

3. t

is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is

SU(LSE)

reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator

design guide for ST microcontrollers” available from the ST website www.st.com.

Figure 19. Typical application with a 32.768 kHz crystal

Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden

5.3.8 Internal clock source characteristics

Symbol Parameter Conditions Min Typ Max Unit

HSI16

TRIM HSI16 frequency user trimming step

HSI16

∆

Temp(HSI16)

to add one.

The parameters given in Table 41 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 21: General operating

conditions. The provided curves are characterization results, not tested in production.

High-speed internal (HSI16) RC oscillator

Table 41. HSI16 oscillator characteristics

HSI16 Frequency VDD=3.0 V, TA=30 °C 15.88 - 16.08 MHz

From code 127 to 128 -8 -6 -4

From code 63 to 64 From code 191 to 192

For all other code increments

(2)

Duty Cycle - 45 - 55 %

= 0 to 85 °C -1 - 1 %

HSI16 oscillator frequency drift over temperature

= -40 to 125 °C -2 - 1.5

(1)

-5.8 -3.8 -1.8

0.2 0.3 0.4

74/136 DS12232 Rev 2

STM32G071x8/xB Electrical characteristics

MSv39299V1

15.6

15.7

15.8

15.9

16.1

16.2

16.3

16.4

MHz

min mean max

+1%

-1%

+2%

-2%

+1.5%

-1.5%

-40 -20 0 20 40 60 80 100 120 °C

Table 41. HSI16 oscillator characteristics

(1)

(continued)

Symbol Parameter Conditions Min Typ Max Unit

∆

VDD(HSI16)

su(HSI16)

stab(HSI16)

DD(HSI16)

1. Based on characterization results, not tested in production.

2. Guaranteed by design.

HSI16 oscillator frequency drift over V

(2)

HSI16 oscillator start-up time - - 0.8 1.2 μs

(2)

HSI16 oscillator stabilization time - - 3 5 μs

(2)

HSI16 oscillator power consumption - - 155 190 μA

VDD=1.62 V to 3.6 V -0.1 - 0.05 %

Figure 20. HSI16 frequency vs. temperature

Low-speed internal (LSI) RC oscillator

Symbol Parameter Conditions Min Typ Max Unit

LSI

SU(LSI)

STAB(LSI)

DD(LSI)

1. Based on characterization results, not tested in production.

LSI frequency

(2)

LSI oscillator start-up time - - 80 130 μs

(2)

LSI oscillator stabilization time 5% of final frequency - 125 180 μs

LSI oscillator power

(2)

consumption

Table 42. LSI oscillator characteristics

= 3.0 V, TA = 30 °C 31.04 - 32.96

= 1.62 V to 3.6 V, TA = -40 to

125 °C

- - 110 180 nA

DS12232 Rev 2 75/136

(1)

29.5 - 34

kHz

109

Electrical characteristics STM32G071x8/xB

2. Guaranteed by design.

5.3.9 PLL characteristics

The parameters given in Table 43 are derived from tests performed under temperature and V

supply voltage conditions summarized in Table 21: General operating conditions.

Table 43. PLL characteristics

Symbol Parameter Conditions Min Typ Max Unit

PLL_IN

PLL input clock frequency

PLL input clock duty cycle - 45 - 55 %

(2)

Voltage scaling Range 1 3.09 - 122

PLL_P_OUT

PLL multiplier output clock P

Voltage scaling Range 2 3.09 - 40

Voltage scaling Range 1 12 - 128

PLL_Q_OUT

PLL multiplier output clock Q

Voltage scaling Range 2 12 - 33

Voltage scaling Range 1 12 - 64

PLL_R_OUT

PLL multiplier output clock R

Voltage scaling Range 2 12 - 16

(1)

-2.66-16MHz

MHz

VCO_OUT

LOCK

Jitter

PLL VCO output

Voltage scaling Range 2 96 - 128

PLL lock time - - 15 40 μs

RMS cycle-to-cycle jitter

-50-

System clock 56 MHz

RMS period jitter - 40 -

VCO freq = 96 MHz - 200 260

Voltage scaling Range 1 96 - 344

DD(PLL)

PLL power consumption

(1)

on V

VCO freq = 344 MHz - 520 650

1. Guaranteed by design.

2. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between the two PLLs.

5.3.10 Flash memory characteristics

Table 44. Flash memory characteristics

Symbol Parameter Conditions Typ Max Unit

prog

prog_row

64-bit programming time - 85 125 µs

Row (32 double word) programming time

Normal programming 2.7 4.6

Fast programming 1.7 2.8

(1)

MHz

±ps

μAVCO freq = 192 MHz - 300 380

prog_page

ERASE

Page (2 Kbyte) programming time

Page (2 Kbyte) erase time - 22.0 40.0

76/136 DS12232 Rev 2

Normal programming 21.8 36.6

Fast programming 13.7 22.4

STM32G071x8/xB Electrical characteristics

Table 44. Flash memory characteristics

(1)

(continued)

Symbol Parameter Conditions Typ Max Unit

prog_bank

Bank (128 Kbyte

(2)

) programming

time

Mass erase time - 22.1 40.1 ms

Normal programming 1.4 2.4

Fast programming 0.9 1.4

Programming 3 -

DD(FlashA)

Average consumption from V

Mass erase 3 -

Programming, 2 µs peak duration

DD(FlashP)

Maximum current (peak)

Erase, 41 µs peak duration

1. Guaranteed by design.

2. Values provided also apply to devices with less Flash memory than one 128 Kbyte bank

Table 45. Flash memory endurance and data retention

Symbol Parameter Conditions Min

END

RET

1. Guaranteed by characterization results.

2. Cycling performed over the whole temperature range.

Endurance TA = -40 to +105 °C 10 kcycles

1 kcycle

Data retention

10 kcycles

(2)

at TA = 85 °C

(2)

at TA = 105 °C 15

(2)

at TA = 125 °C 7

(2)

at TA = 55 °C 30

(2)

at TA = 85 °C 15

(2)

at TA = 105 °C 10

(1)

Unit

Yea rs

mAPage erase 3 -

5.3.11 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until

a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

• FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V

through a 100 pF capacitor, until a functional disturbance occurs. This test is

compliant with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed.

and

DS12232 Rev 2 77/136

109

Electrical characteristics STM32G071x8/xB

The test results are given in Table 46. They are based on the EMS levels and classes defined in application note AN1709.

Table 46. EMS characteristics

Symbol Parameter Conditions

= 3.3 V, TA = +25 °C,

FESD

Voltage limits to be applied on any I/O pin to induce a functional disturbance

Fast transient voltage burst limits to be applied through 100 pF on VDD and V

EFTB

pins to induce a functional disturbance

= 64 MHz, LQFP64,

HCLK

conforming to IEC 61000-4-2

VDD = 3.3 V, TA = +25 °C, f

= 64 MHz, LQFP64,

HCLK

conforming to IEC 61000-4-4

Level/

Class

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• corrupted program counter

• unexpected reset

• critical data corruption (for example control registers)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading.

78/136 DS12232 Rev 2

STM32G071x8/xB Electrical characteristics

Table 47. EMI characteristics

Symbol Parameter Conditions

VDD = 3.6 V, TA = 25 °C,

EMI

Peak level

LQFP64 package compliant with IEC 61967-2

5.3.12 Electrical sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the ANSI/JEDEC standard.

Table 48. ESD absolute maximum ratings

Max vs.

Monitored

frequency band

HSE/fHCLK

]

Unit

8 MHz / 64 MHz

0.1 MHz to 30 MHz 7

30 MHz to 130 MHz -1

dBµV

130 MHz to 1 GHz 8

1 GHz to 2 GHz 7

EMI level 2.5 -

Symbol Ratings Conditions Class

= +25 °C, conforming

ESD(HBM)

Electrostatic discharge voltage (human body model)

Electrostatic discharge

ESD(CDM)

voltage (charge device model)

1. Based on characterization results, not tested in production.

to ANSI/ESDA/JEDEC JS-001

TA = +25 °C, conforming to ANSI/ESDA/JEDEC JS-002

2 2000

C2a 500

Maximum

(1)

value

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up performance:

• A supply overvoltage is applied to each power supply pin.

• A current is injected to each input, output and configurable I/O pin.

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Symbol Parameter Conditions Class

LU Static latch-up class T

Table 49. Electrical sensitivity

= +125 °C conforming to JESD78 II

Unit

DS12232 Rev 2 79/136

109

Electrical characteristics STM32G071x8/xB

5.3.13 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or above V product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out-of-range parameter: ADC error above a certain limit (higher than 5 LSB TUE), induced leakage current on adjacent pins out of conventional limits (-5 µA/+0 µA range) or other functional failure (for example reset occurrence or oscillator frequency deviation).

The characterization results are given in Table 50.

Negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection.

(for standard, 3.3 V-capable I/O pins) should be avoided during normal

DDIO1

Table 50. I/O current injection susceptibility

(1)

Symbol Description

All except PA4, PA5, PA6,

INJ

1. Based on characterization results, not tested in production.

Injected current on pin

PB0, PB3, and PC0

PA4 , PA 5 - 5 0 m A

PA6, PB0, PB3, and PC0 0 N/A mA

Functional susceptibility

Negative injection

-5 N/A mA

Positive

injection

Unit

80/136 DS12232 Rev 2

STM32G071x8/xB Electrical characteristics

5.3.14 I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 51 are derived from tests performed under the conditions summarized in Table 21: General operating conditions. All I/Os are designed as CMOS- and TTL-compliant.

Symbol Parameter Conditions Min Typ Max Unit

I/O input low level

(1)

voltage

I/O input high level

(1)

voltage

(3)

I/O input hysteresis

hys

Table 51. I/O static characteristics

All except

1.62 V < V

FT_c

2 V < V

DDIO1

1.62 V < V

All except

1.62 V < V

FT_c

FT_c 1.62 V < V

TT_xx, FT_xx,

1.62 V < V

NRST

< 3.6 V - -

DDIO1

< 2.7 V - - 0.3 x V

< 2.7 V - - 0.25 x V

DDIO1

< 3.6 V

DDIO1

< 3.6 V 0.7 x V

DDIO1

< 3.6 V - 200 - mV

DDIO1

0.7 x V

+ 0.26

DDIO1

(3)

0.3 x V

0.39 x V

- 0.06

(

-5

DDIO1

(2)

DDIO1

(3)

DDIO1

V0.49 x V

FT_xx except FT_c and FT_d

lkg

Input leakage

(3)

current

FT_c

FT_d

TT_a

Weak pull-up

1. Refer to Figure 21: I/O input characteristics.

2. Tested in production.

3. Guaranteed by design.

equivalent resistor

(5)

Weak pull-down

equivalent resistor

I/O pin capacitance - - 5 - pF

(5)

VIN = V

DDIO1

≤ V

0 < V

DDIO1

≤ VIN ≤ V

DDIO1

+1 V < VIN ≤

DDIO1

(3)

5.5 V

0 < V

≤ V

DDIO1

< VIN ≤ 5 V - - 3000

DDIO1

0 < VIN ≤ V

DDIO1

0 < V

DDIO1

< VIN ≤ 5.5 V - - 9000

≤ V

DDIO1

< VIN ≤ + 0.3 V

+1 V - - 600

DDIO1

--±70

- - 150

- - 2000

- - 4500

--±150

- - 2000

25 40 55 kΩ

(4)

DS12232 Rev 2 81/136

109

Electrical characteristics STM32G071x8/xB

MSv47925V1

1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6

0.5

1.5

2.5

Minimum required

logic level 1 zone

Minimum required

logic level 0 zone

IHmin

= 0.7 V

DDIO

(CMOS standard requirement)

ILmax

= 0.3 V

DDIO

(CMOS standard requirement)

Undefined input range

IHmin

= 0.49 V

DDIO

+ 0.26

ILmax

= 0.39 V

DDIO

- 0.06

(V)

DDIO

(V)

TTL standard requirement

Device characteristics

Test thresholds

4. This value represents the pad leakage of the I/O itself. The total product pad leakage is provided by this formula: I

Total_Ileak_max

5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimal (~10% order).

= 10 µA + [number of I/Os where VIN is applied on the pad] ₓ I

lkg

(Max).

All I/Os are CMOS- and TTL-compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters, as shown in Figure 21.

Figure 21. I/O input characteristics

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ±20 mA (with a relaxed V

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2:

OL/VOH

• The sum of the currents sourced by all the I/Os on V consumption of the MCU sourced on V I

VDD

• The sum of the currents sunk by all the I/Os on V the MCU sunk on V

(see Table 18: Voltage characteristics).

, cannot exceed the absolute maximum rating I

Voltage characteristics).

82/136 DS12232 Rev 2

Output voltage levels

Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in

plus the maximum

cannot exceed the absolute maximum rating

DD,

DDIO1,

, plus the maximum consumption of

(see Table 18:

VSS

STM32G071x8/xB Electrical characteristics

Table 21: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT OR TT

unless otherwise specified).

Table 52. Output voltage characteristics

Symbol Parameter Conditions Min Max Unit

Output low level voltage for an I/O pin CMOS port

Output high level voltage for an I/O pin V

(3)

Output low level voltage for an I/O pin TTL port

IO|

= 6 mA for other I/Os V

DDIO1

(2)

= 2 mA for FT_c I/Os

≥ 2.7 V

(2)

|IIO| = 2 mA for FT_c I/Os

(3)

Output high level voltage for an I/O pin 2.4 -

(3)

Output low level voltage for an I/O pin All I/Os except FT_c

(3)

Output high level voltage for an I/O pin V

(3)

Output low level voltage for an I/O pin |IIO| = 1 mA for FT_c I/Os

(3)

Output high level voltage for an I/O pin V

= 6 mA for other I/Os

≥ 2.7 V

DDIO1

|IIO| = 18 mA

≥ 2.7 V

DDIO1

= 3 mA for other I/Os

≥ 1.62 V

DDIO1

|IIO| = 20 mA

≥ 2.7 V

OLFM+

1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 18:

Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always

respect the absolute maximum ratings ΣIIO.

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

3. Guaranteed by design.

Output low level voltage for an FT I/O

(3)

pin in FM+ mode (FT I/O with _f option)

DDIO1

IO|

DDIO1

= 9 mA

≥ 1.62 V

(1)

-0.4

- 0.4 -

DDIO1

-0.4

-1.3

- 1.3 -

DDIO1

-0.4

- 0.45 -

DDIO1

-0.4

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in Figure 22 and

Table 53, respectively.

Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 21: General

operating conditions.

Table 53. I/O AC characteristics

Speed Symbol Parameter Conditions Min Max Unit

C=50 pF, 2.7 V ≤ V

Fmax Maximum frequency

C=50 pF, 1.6 V ≤ V

C=10 pF, 2.7 V ≤ V

C=10 pF, 1.6 V ≤ V

C=50 pF, 2.7 V ≤ V

Tr/Tf Output rise and fall time

C=50 pF, 1.6 V ≤ V

C=10 pF, 2.7 V ≤ V

C=10 pF, 1.6 V ≤ V

DS12232 Rev 2 83/136

(1)(2)

≤ 3.6 V - 2

DDIO1

≤ 2.7 V - 0.35

DDIO1

≤ 3.6 V - 3

DDIO1

≤ 2.7 V - 0.45

DDIO1

≤ 3.6 V - 100

DDIO1

≤ 2.7 V - 225

DDIO1

≤ 3.6 V - 75

DDIO1

≤ 2.7 V - 150

DDIO1

MHz

109

Electrical characteristics STM32G071x8/xB

Table 53. I/O AC characteristics

(1)(2)

(continued)

Speed Symbol Parameter Conditions Min Max Unit

C=50 pF, 2.7 V ≤ V

Fmax Maximum frequency

C=50 pF, 1.6 V ≤ V

C=10 pF, 2.7 V ≤ V

C=10 pF, 1.6 V ≤ V

C=50 pF, 2.7 V ≤ V

Tr/Tf Output rise and fall time

C=50 pF, 1.6 V ≤ V

C=10 pF, 2.7 V ≤ V

C=10 pF, 1.6 V ≤ V

C=50 pF, 2.7 V ≤ V

Fmax Maximum frequency

C=50 pF, 1.6 V ≤ V

C=10 pF, 2.7 V ≤ V

C=10 pF, 1.6 V ≤ V

C=50 pF, 2.7 V ≤ V

Tr/Tf Output rise and fall time

C=50 pF, 1.6 V ≤ V

C=10 pF, 2.7 V ≤ V

C=10 pF, 1.6 V ≤ V

C=30 pF, 2.7 V ≤ V

Fmax Maximum frequency

C=30 pF, 1.6 V ≤ V

C=10 pF, 2.7 V ≤ V

C=10 pF, 1.6 V ≤ V

C=30 pF, 2.7 V ≤ V

Tr/Tf Output rise and fall time

C=30 pF, 1.6 V ≤ V

C=10 pF, 2.7 V ≤ V

C=10 pF, 1.6 V ≤ V

Fm+

1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the SYSCFG_CFGR1 register. Refer to the RM0444 reference manual for a description of GPIO Port configuration register.

2. Guaranteed by design.

3. This value represents the I/O capability but the maximum system frequency is limited to 64 MHz.

4. The fall time is defined between 70% and 30% of the output waveform, according to I

Fmax Maximum frequency

Tf Output fall time

(4)

C=50 pF, 1.6 V ≤ V

≤ 3.6 V - 10

DDIO1

≤ 2.7 V - 2

DDIO1

≤ 3.6 V - 15

DDIO1

≤ 2.7 V - 2.5

DDIO1

≤ 3.6 V - 30

DDIO1

≤ 2.7 V - 60

DDIO1

≤ 3.6 V - 15

DDIO1

≤ 2.7 V - 30

DDIO1

≤ 3.6 V - 30

DDIO1

≤ 2.7 V - 15

DDIO1

≤ 3.6 V - 60

DDIO1

≤ 2.7 V - 30

DDIO1

≤ 3.6 V - 11

DDIO1

≤ 2.7 V - 22

DDIO1

≤ 3.6 V - 4

DDIO1

≤ 2.7 V - 8

DDIO1

≤ 3.6 V - 60

DDIO1

≤ 2.7 V - 30

DDIO1

≤ 3.6 V - 80

DDIO1

≤ 2.7 V - 40

DDIO1

≤ 3.6 V - 5.5

DDIO1

≤ 2.7 V - 11

DDIO1

≤ 3.6 V - 2.5

DDIO1

≤ 2.7 V - 5

DDIO1

≤ 3.6 V

DDIO1

C specification.

MHz

(3)

-1MHz

-5ns

84/136 DS12232 Rev 2

STM32G071x8/xB Electrical characteristics

MS32132V2

10%

50%

90%

10%

50%

90%

Maximum frequency is achieved if (t + t (≤ 2/3)T and if the duty cycle is (45-55%)

when loaded by the specified capacitance.

r(IO)out

f(IO)out

Figure 22. I/O AC characteristics definition

1. Refer to Table 53: I/O AC characteristics.

5.3.15 NRST input characteristics

The NRST input driver uses CMOS technology. It is connected to a permanent pull-up resistor, R

Unless otherwise specified, the parameters given in the following table are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 21: General operating conditions.

Table 54. NRST pin characteristics

(1)

Symbol Parameter Conditions Min Typ Max Unit

IL(NRST)

IH(NRST)

hys(NRST)

F(NRST)

NF(NRST)

1. Guaranteed by design.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimal (~10% order)

NRST input low level voltage

NRST input high level voltage

NRST Schmitt trigger voltage hysteresis

Weak pull-up equivalent resistor

NRST input filtered pulse

NRST input not filtered pulse

(2)

VIN = V

1.7 V ≤ V

- - - 0.3 x V

- 0.7 x V

DDIO1

--200-mV

25 40 55 kΩ

---70ns

≤ 3.6 V 350 - - ns

DS12232 Rev 2 85/136

109

Electrical characteristics STM32G071x8/xB

MS19878V3

Internal reset

External

reset circuit

(1)

NRST

(2)

Filter

0.1 μF

Figure 23. Recommended NRST pin protection

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the V

Table 54: NRST pin characteristics. Otherwise the reset will not be taken into account by the device.

3. The external capacitor on NRST must be placed as close as possible to the device.

max level specified in

IL(NRST)

5.3.16 Analog switch booster

Table 55. Analog switch booster characteristics

Symbol Parameter Min Typ Max Unit

SU(BOOST)

DD(BOOST)

1. Guaranteed by design.

Supply voltage 1.62 V - 3.6 V

Booster startup time - - 240 µs

Booster consumption for

1.62 V ≤ V

≤ 2.0 V

Booster consumption for

2.0 V ≤ V

≤ 2.7 V

Booster consumption for

2.7 V ≤ V

≤ 3.6 V

--250

--500

--900

5.3.17 Analog-to-digital converter characteristics

Unless otherwise specified, the parameters given in Table 56 are preliminary values derived from tests performed under ambient temperature, f conditions summarized in Table 21: General operating conditions.

Note: It is recommended to perform a calibration after each power-up.

Symbol Parameter Conditions

Table 56. ADC characteristics

(2)

frequency and V

PCLK

(1)

Min Typ Max Unit

(1)

supply voltage

DDA

µA

DDA

REF+

86/136 DS12232 Rev 2

Analog supply voltage - 1.62 - 3.6 V

Positive reference

voltage

< 2 V V

DDA

≥ 2 V 2 - V

DDA

STM32G071x8/xB Electrical characteristics

Table 56. ADC characteristics

Symbol Parameter Conditions

Range 1 0.14 - 35

Range 2 0.14 - 16

12 bits; V

10 bits; V

8 bits; V

6 bits; V

ADC

DDA

≤ 2 V - - 2.18

DDA

≤ 2 V - - 2.50

DDA

≤ 2 V - - 2.92

DDA

≤ 2 V - - 3.50

DDA

= 35 MHz; 12 bits;

> 2 V

DDA

= 35 MHz;

≤ 2 V

DDA

12 bits; V

DDA

≤ 2 V - - f

DDA

-V

ADC

TRIG

AIN

ADC clock frequency

Sampling rate

12 bits; V

10 bits; V

8 bits; V

6 bits; V

External trigger frequency

ADC

12 bits; V

(3)

Conversion voltage range

(1)

(continued)

(2)

Min Typ Max Unit

> 2 V - - 2.50

> 2 V - - 2.92

> 2 V - - 3.50

> 2 V - - 4.38

- - 2.35

- - 2.18

> 2 V - - f

SSA

-V

ADC

REF+

MHz

MSps

MHz

/15

/16

AIN

ADC

STAB

CAL

LATR

ADCVREG_STUP

External input impedance

Internal sample and hold capacitor

---50kΩ

--5-pF

ADC power-up time - 2

= 35 MHz 2.35 µs

Calibration time

ADC

-821/f

Trigger conversion latency;

CKMODE = 00 2 - 3

CKMODE = 01 - - 2.75

Regular and injected channels without conversion abort

Sampling time

CKMODE = 10 - - 2.63

CKMODE = 11 - - 3

= 35 MHz 0.043 - 4.59 µs

ADC

-1.5-160.51/f

ADC voltage regulator start-up time

---20

Conversion

cycle

ADC

1/f

ADC

µs

DS12232 Rev 2 87/136

109

Electrical characteristics STM32G071x8/xB

(2)

(1)

(continued)

Min Typ Max Unit

0.40 - 4.95 µs

+ 12.5 cycles for successive

approximation

Table 56. ADC characteristics

Symbol Parameter Conditions

= 35 MHz

ADC

Resolution = 12 bits

CONV

Total conversion time (including sampling time)

= 14 to 173

Laps of time allowed

IDLE

between two conversions without

- - - 100 µs

rearm

fs = 2.5 MSps - 410 -

DDA(ADC)

ADC consumption from V

DDA

= 1 MSps - 164 -

= 10 kSps - 17 -

fs = 2.5 MSps - 65 -

DDV(ADC)

1. Guaranteed by design

2. I/O analog switch voltage booster must be enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when V disabled when V

is internally connected to V

REF+

functions for further details.

ADC consumption from V

REF+

≥ 2.4 V.

DDA

= 1 MSps - 26 -

= 10 kSps - 0.26 -

on some packages.Refer to Section 4: Pinouts, pin description and alternate

< 2.4 V and

DDA

1/f

ADC

µAf

Resolution

12 bits

Table 57. Maximum ADC R

Sampling cycle at

35 MHz

(3)

1.5

Sampling time at

35 MHz

AIN

[ns]

43 50

3.5 100 680

7.5 214 2200

12.5 357 4700

19.5 557 8200

39.5 1129 15000

79.5 2271 33000

160.5 4586 50000

Max. R

(Ω)

AIN

(1)(2)

88/136 DS12232 Rev 2

STM32G071x8/xB Electrical characteristics

Resolution

10 bits

8 bits

Table 57. Maximum ADC R

Sampling cycle at

35 MHz

(3)

1.5

3.5 100 820

7.5 214 3300

12.5 357 5600

19.5 557 10000

39.5 1129 22000

79.5 2271 39000

160.5 4586 50000

(3)

1.5

3.5 100 1500

7.5 214 3900

12.5 357 6800

19.5 557 12000

39.5 1129 27000

79.5 2271 50000

160.5 4586 50000

(3)

1.5

3.5 100 2200

7.5 214 5600

Sampling time at

. (continued)

AIN

35 MHz

[ns]

43 68

43 82

43 390

Max. R

(Ω)

AIN

(1)(2)

6 bits

12.5 357 10000

19.5 557 15000

39.5 1129 33000

79.5 2271 50000

160.5 4586 50000

1. Guaranteed by design.

2. I/O analog switch voltage booster must be enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when V

2.4 V and disabled when V

3. Only allowed with V

DDA

> 2 V

≥ 2.4 V.

DS12232 Rev 2 89/136

DDA

109

Electrical characteristics STM32G071x8/xB

Table 58. ADC accuracy

Symbol Parameter Conditions

= V

DDA

= 35 MHz; fs ≤ 2.5 MSps;

ADC

REF+

= 3 V;

TA = 25 °C

< 3.6 V;

To ta l

unadjusted

error

2 V < V f

DDA=VREF+

= 35 MHz; fs ≤ 2.5 MSps;

ADC

TA = entire range

1.65 V < V

DDA=VREF+

TA = entire range

EO Offset error

Range 1: f Range 2: f

= V

DDA

= 35 MHz; fs ≤ 2.5 MSps;

ADC

= 25 °C

2 V < V

= 35 MHz; fs ≤ 2.5 MSps;

ADC

TA = entire range

1.65 V < V = entire range

Range 1: f Range 2: f

= V

DDA

= 35 MHz; fs ≤ 2.5 MSps;

ADC

= 35 MHz; fs ≤ 2.2 MSps;

ADC

= 16 MHz; fs ≤ 1.1 MSps;

ADC

= 3 V;

REF+

DDA=VREF+

ADC

REF+

< 3.6 V;

= 35 MHz; fs ≤ 2.2 MSps; = 16 MHz; fs ≤ 1.1 MSps;

= 3 V;

TA = 25 °C

(4)

< 3.6 V;

(1)(2)(3)

Min Typ Max Unit

-34

-36.5

-37.5

-1.52

-1.54.5

-1.55.5

-33.5

LSB

EG Gain error

Differential

linearity error

2 V < V f

DDA=VREF+

= 35 MHz; fs ≤ 2.5 MSps;

ADC

< 3.6 V;

TA = entire range

1.65 V < V

DDA=VREF+

TA = entire range Range 1: f Range 2: f

= V

DDA

= 35 MHz; fs ≤ 2.5 MSps;

ADC

= 25 °C

2 V < V

= 35 MHz; fs ≤ 2.5 MSps;

ADC

= entire range

1.65 V < V

= 35 MHz; fs ≤ 2.2 MSps;

ADC

= 16 MHz; fs ≤ 1.1 MSps;

ADC

= 3 V;

REF+

DDA=VREF+

< 3.6 V;

TA = entire range Range 1: f Range 2: f

= 35 MHz; fs ≤ 2.2 MSps;

ADC

= 16 MHz; fs ≤ 1.1 MSps;

ADC

< 3.6 V;

-35 LSB

-36.5

-1.21.5

-1.21.5 LSB

-1.21.5

90/136 DS12232 Rev 2

STM32G071x8/xB Electrical characteristics

Table 58. ADC accuracy

Symbol Parameter Conditions

ENOB

SINAD

SNR

Integral

linearity error

Effective

number of

bits

Signal-to-

noise and

distortion

ratio

Signal-to-

noise ratio

= V

DDA

= 35 MHz; fs ≤ 2.5 MSps;

ADC

TA = 25 °C

2 V < V

= 35 MHz; fs ≤ 2.5 MSps;

ADC

TA = entire range

1.65 V < V = entire range

Range 1: f Range 2: f

= V

DDA

= 35 MHz; fs ≤ 2.5 MSps;

ADC

TA = 25 °C

2 V < V f

= 35 MHz; fs ≤ 2.5 MSps;

ADC

= entire range

1.65 V < V

TA = entire range Range 1: f Range 2: f

= V

DDA

= 35 MHz; fs ≤ 2.5 MSps;

ADC

TA = 25 °C

2 V < V

= 35 MHz; fs ≤ 2.5 MSps;

ADC

TA = entire range

1.65 V < V = entire range

Range 1: f Range 2: f

= V

DDA

= 35 MHz; fs ≤ 2.5 MSps;

ADC

= 25 °C

2 V < V f

= 35 MHz; fs ≤ 2.5 MSps;

ADC

= entire range

1.65 V < V

TA = entire range Range 1: f Range 2: f

= 3 V;

REF+

DDA=VREF+

ADC

REF+

DDA=VREF+

ADC

REF+

DDA=VREF+

ADC

REF+

DDA=VREF+

ADC

< 3.6 V;

= 35 MHz; fs ≤ 2.2 MSps; = 16 MHz; fs ≤ 1.1 MSps;

= 3 V;

< 3.6 V;

= 35 MHz; fs ≤ 2.2 MSps; = 16 MHz; fs ≤ 1.1 MSps;

= 3 V;

< 3.6 V;

= 35 MHz; fs ≤ 2.2 MSps; = 16 MHz; fs ≤ 1.1 MSps;

= 3 V;

< 3.6 V;

= 35 MHz; fs ≤ 2.2 MSps; = 16 MHz; fs ≤ 1.1 MSps;

(1)(2)(3)

(4)

(continued)

Min Typ Max Unit

-2.53

-2.53 LSB

-2.53.5

10.1 10.2 -

9.6 10.2 bit

9.5 10.2 -

62.5 63 -

59.5 63 dB

59 63 -

63 64 -

60 64 -

DS12232 Rev 2 91/136

109

Electrical characteristics STM32G071x8/xB

MSv19880V3

(1) Example of an actual transfer curve

(2) Ideal transfer curve

(3) End point correlation line

4095

4094

4093

2 345 6

1 7 4093 4094 4095

1 LSB

ideal

(1)

(3)

(2)

Code

AIN

/ V

REF+

)*4095

total unadjusted error: maximum deviation

between the actual and ideal transfer curves.

gain error: deviation between the last ideal

transition and the last actual one.

differential linearity error: maximum deviation

between actual steps and the ideal ones.

integral linearity error: maximum deviation between

any actual transition and the end point correlation line.

offset error: maximum deviation between the

first actual transition and the first ideal one.

Table 58. ADC accuracy

Symbol Parameter Conditions

= V

DDA

= 35 MHz; fs ≤ 2.5 MSps;

ADC

REF+

= 3 V;

(1)(2)(3)

(4)

(continued)

Min Typ Max Unit

--74-73

TA = 25 °C

< 3.6 V;

= 35 MHz; fs ≤ 2.2 MSps; = 16 MHz; fs ≤ 1.1 MSps;

--74-70

< 2.4 V

DDA

THD

To ta l

harmonic

distortion

2 V < V f TA = entire range

1.65 V < V T Range 1: f Range 2: f

DDA=VREF+

= 35 MHz; fs ≤ 2.5 MSps;

ADC

DDA=VREF+

= entire range

ADC

1. Based on characterization results, not tested in production.

2. ADC DC accuracy values are measured after internal calibration.

3. Injecting negative current on any analog input pin significantly reduces the accuracy of A-to-D conversion of signal on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins susceptible to receive negative current.

4. I/O analog switch voltage booster enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when V and disabled when V

DDA

≥ 2.4 V.

Figure 24. ADC accuracy characteristics

92/136 DS12232 Rev 2

STM32G071x8/xB Electrical characteristics

MS33900V5

Sample and hold ADC converter

12-bit

converter

parasitic

(2)

lkg

(3)

ADC

DDA

AIN

(1)

AIN

AINx

ADC

Figure 25. Typical connection diagram using the ADC

1. Refer to Table 56: ADC characteristics for the values of R

2. C

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

parasitic

pad capacitance (refer to Table 51: I/O static characteristics for the value of the pad capacitance). A high C

value will downgrade conversion accuracy. To remedy this, f

parasitic

AIN

and C

ADC

should be reduced.

ADC

3. Refer to Table 51: I/O static characteristics for the values of Ilkg.

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 13: Power supply

scheme. The 100 nF capacitor should be ceramic (good quality) and it should be placed as

close as possible to the chip.

DS12232 Rev 2 93/136

109

Electrical characteristics STM32G071x8/xB

5.3.18 Digital-to-analog converter characteristics

Table 59. DAC characteristics

(1)

Symbol Parameter Conditions Min Typ Max Unit

DAC output buffer OFF, DAC_OUT

DDA

Analog supply voltage for DAC ON

pin not connected (internal connection only)

1.71 -

3.6 V

Other modes 1.80 -

DAC output buffer OFF, DAC_OUT

REF+

Positive reference voltage

pin not connected (internal connection only)

1.71 V

DDA

Other modes 1.80 -

BON

BOFF

DAC_OUT

Resistive load

DAC output buffer ON

connected to V

SSA

DDA

Output Impedance DAC output buffer OFF 9.6 11.7 13.8 kΩ

Output impedance sample

VDD = 2.7 V - - 2

and hold mode, output

= 2.0 V - - 3.5

buffer ON

Output impedance sample

VDD = 2.7 V - - 16.5

and hold mode, output

= 2.0 V - - 18.0

DAC output buffer ON - - 50 pF

buffer OFF

Capacitive load

Sample and hold mode - 0.1 1 µF

Voltage on DAC_OUT

DAC output buffer ON 0.2 -

output

DAC output buffer OFF 0 - V

5- -

25 - -

REF+

– 0.2

REF+

±0.5 LSB - 1.7 3

Normal mode DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ

±1 LSB - 1.6 2.9

±2 LSB - 1.55 2.85

±4 LSB - 1.48 2.8

±8 LSB - 1.4 2.75

Normal mode DAC output buffer OFF, ±1LSB, CL = 10 pF

Normal mode DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ

Normal mode DAC output buffer OFF, CL ≤ 10 pF

-2 2.5

-4.2 7.5

-2 5

SETTLING

WAKEUP

Settling time (full scale: for a 12-bit code transition between the lowest and the highest input codes when DAC_OUT reaches final value ±0.5LSB, ±1 LSB, ±2 LSB, ±4 LSB, ±8 LSB)

Wakeup time from off state (setting the ENx bit in the

(2)

DAC Control register) until final value ±1 LSB

kΩ

µs

PSRR V

supply rejection ratio

DDA

Normal mode DAC output buffer ON CL ≤ 50 pF, RL = 5 kΩ, DC

94/136 DS12232 Rev 2

--80 -28dB

STM32G071x8/xB Electrical characteristics

Table 59. DAC characteristics

(1)

(continued)

Symbol Parameter Conditions Min Typ Max Unit

W_to_W

SAMP

Minimum time between two consecutive writes into the DAC_DORx register to guarantee a correct DAC_OUT for a small variation of the input code (1 LSB)

Sampling time in sample and hold mode (code transition between the lowest input code and the highest input code when DACOUT reaches final value ±1LSB)

DAC_MCR:MODEx[2:0] = 000 or 001 CL ≤ 50 pF; RL ≥ 5 kΩ

DAC_MCR:MODEx[2:0] = 010 or 011 CL ≤ 10 pF

DAC output buffer

DAC_OUT pin connected

ON, C

DAC output buffer OFF, C

= 100 nF

DAC_OUT pin not connected (internal

DAC output buffer OFF

1- -

1.4 - -

-0.7 3.5

-10.5 18

-2 3.5µs

connection only)

leak

int

TRIM

offset

DDA(DAC)

Output leakage current

Internal sample and hold capacitor

Sample and hold mode, DAC_OUT pin connected

- 5.2 7 8.8 pF

-- -

Middle code offset trim time DAC output buffer ON 50 - - µs

= 3.6 V - 1500 -

Middle code offset for 1 trim code step

REF+

= 1.8 V - 750 -

REF+

DAC output buffer ON

No load, middle code (0x800)

No load, worst code (0xF1C)

- 315 500

- 450 670

DAC consumption from V

DDA

DAC output buffer OFF

Sample and hold mode, C 100 nF

No load, middle code (0x800)

-- 0.2

315 ₓ

/(Ton+

(4)

)

off

(3)

670 ₓ

/(Ton+

)

off

µV

µA

(4)

µs

DS12232 Rev 2 95/136

109

Electrical characteristics STM32G071x8/xB

MSv47959V1

12-bit

digital-to-analog

converter

Buffered / non-buffered DAC

DAC_OUTx

LOAD

Buffer

(1)

Table 59. DAC characteristics

(1)

(continued)

Symbol Parameter Conditions Min Typ Max Unit

No load, middle

DAC output buffer ON

code (0x800)

No load, worst code (0xF1C)

DDV(DAC)

DAC consumption from V

REF+

DAC output buffer OFF

No load, middle code (0x800)

Sample and hold mode, buffer ON,

= 100 nF, worst case

Sample and hold mode, buffer OFF, CSH = 100 nF, worst case

1. Guaranteed by design.

2. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).

3. Refer to Table 51: I/O static characteristics.

is the Refresh phase duration. T

4. T

is the Hold phase duration. Refer to RM0444 reference manual for more details.

off

- 185 240

- 340 400

- 155 205

185 ₓ

/(Ton+

)

off

155 ₓ

/(Ton+

)

off

(4)

400 ₓ

/(Ton+

off

205 ₓ

/(Ton+

off

(4)

)

(4)

)

Figure 26. 12-bit buffered / non-buffered DAC

µA

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register.

96/136 DS12232 Rev 2

STM32G071x8/xB Electrical characteristics

Table 60. DAC accuracy

(1)

Symbol Parameter Conditions Min Typ Max Unit

DNL

Differential non linearity

(2)

DAC output buffer ON - - ±2

DAC output buffer OFF - - ±2

- monotonicity 10 bits guaranteed

INL

Offset

Offset1

OffsetCal

Integral non linearity

Offset error at code 0x800

Offset error at code 0x001

(3)

(4)

Offset Error at code 0x800 after calibration

DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ

DAC output buffer OFF CL ≤ 50 pF, no RL

DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ

DAC output buffer OFF CL ≤ 50 pF, no RL

DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ

= 3.6 V - - ±12

REF+

= 1.8 V - - ±25

REF+

= 3.6 V - - ±5

REF+

= 1.8 V - - ±7

REF+

--±4

LSB

--±8

--±5

Gain Gain error

To ta l

TUE

unadjusted error

To ta l

TUECal

unadjusted error after calibration

SNR

THD

Signal-to-noise ratio

Total harmonic distortion

DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ

(5)

DAC output buffer OFF CL ≤ 50 pF, no RL

DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ

DAC output buffer OFF CL ≤ 50 pF, no RL

DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ

DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ 1 kHz, BW 500 kHz

DAC output buffer OFF CL ≤ 50 pF, no RL, 1 kHz BW 500 kHz

DAC output buffer ON CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz

DAC output buffer OFF CL ≤ 50 pF, no RL, 1 kHz

--±0.5

--±30

LSB

--±12

--±23LSB

-71.2-

-71.6-

--78-

--79-

DS12232 Rev 2 97/136

109

Electrical characteristics STM32G071x8/xB

Table 60. DAC accuracy

(1)

(continued)

Symbol Parameter Conditions Min Typ Max Unit

DAC output buffer ON

SINAD

Signal-to-noise and distortion ratio

CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz

DAC output buffer OFF CL ≤ 50 pF, no RL, 1 kHz

DAC output buffer ON

ENOB

Effective number of bits

CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz

DAC output buffer OFF CL ≤ 50 pF, no RL, 1 kHz

1. Guaranteed by design.

2. Difference between two consecutive codes - 1 LSB.

3. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095.

4. Difference between the value measured at Code (0x001) and the ideal value.

5. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when

buffer is OFF, and from code giving 0.2 V and (V

– 0.2) V when buffer is ON.

REF+

-70.4-

-71-

-11.4-

bits

-11.5-

5.3.19 Voltage reference buffer characteristics

Table 61. VREFBUF characteristics

Symbol Parameter Conditions Min Typ Max Unit

(1)

= 0 2.4 - 3.6

= 1 2.8 - 3.6

= 0 1.65 - 2.4

= 1 1.65 - 2.8

= 0 2.046

= 1 2.498

= 0 V

= 1 V

(3)

-150 mV - V

DDA

-150 mV - V

DDA

2.048 2.049

2.5 2.502

(3)

DDA

REFBUF_

OUT

TRIM

Analog supply voltage

Voltage reference output

Trim step resolution

Normal mode

Degraded mode

Normal mode

Degraded mode

- - - ±0.05 ±0.1 %

(2)

CL Load capacitor - - 0.5 1 1.5 µF

Equivalent

esr

load

line_reg

load_reg

Serial Resistor of C

load

Static load current

Line regulation 2.8 V ≤ V

Load regulation 500 μA ≤ I

----2Ω

----4mA

= 500 µA - 200 1000

≤ 3.6 V

DDA

≤4 mA Normal mode - 50 500 ppm/mA

load

= 4 mA - 100 500

load

ppm/V

98/136 DS12232 Rev 2

STM32G071x8/xB Electrical characteristics

Table 61. VREFBUF characteristics

(1)

(continued)

Symbol Parameter Conditions Min Typ Max Unit

Temperature

Coeff_vrefbuf

PSRR

START

coefficient of VREFBUF

Power supply rejection

Start-up time

-40 °C < TJ < +125 °C - - 50 ppm/ °C

(4)

DC 40 60 -

100 kHz 25 40 -

CL = 0.5 µF

CL = 1.5 µF

(5)

-300350

-500650

-650800

Control of maximum DC

INRUSH

DDA(VREFB

UF)

1. Guaranteed by design.

2. In degraded mode, the voltage reference buffer can not maintain accurately the output voltage which will follow (V drop voltage).

3. Guaranteed by test in production.

4. The temperature coefficient at VREF+ output is the sum of T

5. The capacitive load must include a 100 nF capacitor in order to cut-off the high frequency noise.

6. To correctly control the VREFBUF inrush current during start-up phase and scaling change, the V the range [2.4 V to 3.6 V] and [2.8 V to 3.6 V] respectively for VRS = 0 and VRS = 1.

current drive on VREFBUF_OUT during start-up

(6)

phase

VREFBUF consumption

DDA

from V

--8-mA

= 0 µA - 16 25

load

= 500 µA - 18 30

load

= 4 mA - 35 50

load

Coeff_vrefint

and T

Coeff_vrefbuf

DDA

voltage should be in

µsCL = 1.1 µF

µAI

5.3.20 Comparator characteristics

Table 62. COMP characteristics

Symbol Parameter Conditions Min Typ Max Unit

DDA

(2)

DDA(SCALER)

START_SCALER

Analog supply voltage

Comparator input voltage range

Scaler input voltage - V

Scaler offset voltage - - ±5 ±10 mV

Scaler static

BRG_EN=0 (bridge disable) - 200 300 nA consumption from V

DDA

BRG_EN=1 (bridge enable) - 0.8 1 µA

Scaler startup time - - 100 200 µs

-1.62-3.6V

-0-V

DS12232 Rev 2 99/136

(1)

REFINT

DDA

109

Electrical characteristics STM32G071x8/xB

Table 62. COMP characteristics

(1)

(continued)

Symbol Parameter Conditions Min Typ Max Unit

START

Comparator startup time to reach propagation delay specification

High-speed mode - - 5

Medium-speed mode - - 15

200 mV step;

High-speed mode - 30 50 ns

100 mV

Propagation delay

>200 mV step;

overdrive

Medium-speed mode - 0.3 0.6 µs

High-speed mode - - 70 ns

100 mV

Medium-speed mode - - 1.2 µs

offset

Comparator offset error

overdrive

Full common mode range - ±5 ±20 mV

No hysteresis - 0 -

hys

Comparator hysteresis

Low hysteresis - 10 -

Medium hysteresis - 20 -

High hysteresis - 30 -

Static - 5 7.5

With 50 kHz and ±100 mV overdrive square signal

-6-

Static - 7 10

With 50 kHz and ±100 mV overdrive square signal

-8-

DDA(COMP)

Comparator consumption from V

DDA

Medium-speed

mode;

No deglitcher

Medium-speed

mode;

With deglitcher

Static - 250 400

High-speed

mode

With 50 kHz and ±100 mV overdrive square signal

-250-

µs

µA

1. Guaranteed by design.

2. Refer to Table 24: Embedded internal voltage reference.

5.3.21 Temperature sensor characteristics

Symbol Parameter Min Typ Max Unit

(1)

Avg_Slope

START(TS_BUF)

(1)

START

VTS linearity with temperature - ±1 ±2 °C

(2)

Average slope 2.3 2.5 2.7 mV/°C

Voltage at 30°C (±5 °C)

(1)

Sensor Buffer Start-up time in continuous mode

Start-up time when entering in continuous mode

100/136 DS12232 Rev 2

Table 63. TS characteristics

(3)

(4)

0.742 0.76 0.785 V

-815µs

- 70 120 µs

ST MICROELECTRONICS STM32G071CBU6 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Table 1. Device summary

1 Introduction

2 Description

Table 2. STM32G071x8/xB family device features and peripheral counts

Figure 1. Block diagram

3 Functional overview

3.1 Arm® Cortex®-M0+ core with MPU

3.2 Memory protection unit

3.3 Embedded Flash memory

Table 3. Access status versus readout protection level and execution modes

3.4 Embedded SRAM

3.5 Boot modes

3.6 Cyclic redundancy check calculation unit (CRC)

3.7 Power supply management

3.7.1 Power supply schemes

Figure 2. Power supply overview

3.7.2 Power supply supervisor

3.7.3 Voltage regulator

3.7.4 Low-power modes

3.7.5 Reset mode

3.7.6 VBAT operation

3.8 Interconnect of peripherals

Table 4. Interconnect of STM32G071x8/xB peripherals

3.9 Clocks and startup

3.10 General-purpose inputs/outputs (GPIOs)

3.11 Direct memory access controller (DMA)

3.12 Interrupts and events

3.12.1 Nested vectored interrupt controller (NVIC)

3.12.2 Extended interrupt/event controller (EXTI)

3.13 Analog-to-digital converter (ADC)

3.13.1 Temperature sensor

Table 5. Temperature sensor calibration values

Table 6. Internal voltage reference calibration values

3.14 Digital-to-analog converter (DAC)

3.15 Voltage reference buffer (VREFBUF)

3.16 Comparators (COMP)

3.17 Timers and watchdogs

Table 7. Timer feature comparison

3.17.1 Advanced-control timer (TIM1)

3.17.2 General-purpose timers (TIM2, TIM3, TIM14, TIM15, TIM16, TIM17)

3.17.3 Basic timers (TIM6 and TIM7)

3.17.4 Low-power timers (LPTIM1 and LPTIM2)

3.17.5 Independent watchdog (IWDG)

3.17.6 System window watchdog (WWDG)

3.17.7 SysTick timer

3.18 Real-time clock (RTC), tamper (TAMP) and backup registers

3.19 Inter-integrated circuit interface (I2C)

3.20 Universal synchronous/asynchronous receiver transmitter (USART)

Table 9. USART implementation

3.21 Low-power universal asynchronous receiver transmitter (LPUART)

3.22 Serial peripheral interface (SPI)

Table 10. SPI/I2S implementation

3.23 USB Type-C™ Power Delivery controller

3.24 Development support

3.24.1 Serial wire debug port (SW-DP)

4 Pinouts, pin description and alternate functions

Figure 3. STM32G071RxT LQFP64 pinout

Figure 4. STM32G071RxH UFBGA64 ballout

Figure 5. STM32G071CxT LQFP48 pinout

Figure 6. STM32G071CxU UFQFPN48 pinout

Figure 7. STM32G071KxT LQFP32 pinout

Figure 8. STM32G071KxU UFQFPN32 pinout

Figure 9. STM32G071GxU UFQFPN28 pinout

Figure 10. STM32G071Ex WLCSP25 pinout

Table 11. Terms and symbols used in Table 12

Table 12. Pin assignment and description

Table 13. Port A alternate function mapping

Table 14. Port B alternate function mapping

Table 15. Port C alternate function mapping

Table 16. Port D alternate function mapping

Table 17. Port F alternate function mapping

5 Electrical characteristics

5.1 Parameter conditions

5.1.1 Minimum and maximum values

5.1.2 Typical values

5.1.3 Typical curves