STMicroelectronics STM32G031C4, STM32G031K4, STM32G031F4, STM32G031G4, STM32G031J4 Datasheet
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STM32G031x4/x6/x8
Errata sheet
STM32G031x4/x6/x8 device errata
Applicability
This document applies to the part numbers of STM32G031x4/x6/x8 devices and the device variants as stated in this page.
It gives a summary and a description of the device errata, with respect to the device datasheet and reference manual RM0444.
Deviation of the real device behavior from the intended device behavior is considered to be a device limitation. Deviation of the description in the reference manual or the datasheet from the intended device behavior is considered to be a documentation erratum. The term “errata” applies both to limitations and documentation errata.
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Table 1. Device summary |
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Reference |
Part numbers |
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STM32G031x4 |
STM32G031C4, STM32G031K4, STM32G031F4, STM32G031G4, STM32G031J4 |
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STM32G031x6 |
STM32G031C6, STM32G031K6, STM32G031F6, STM32G031G6, STM32G031J6 |
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STM32G031x8 |
STM32G031C8, STM32G031K8, STM32G031F8, STM32G031G8, STM32G031Y8 |
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Table 2. Device variants
Reference |
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Silicon revision codes |
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Device marking(1) |
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REV_ID(2) |
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STM32G031xx |
Z |
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0x1001 |
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1.Refer to the device datasheet for how to identify this code on different types of package.
2.REV_ID[15:0] bitfield of DBGMCU_IDCODE register.
ES0487 - Rev 3 - February 2021 |
www.st.com |
For further information contact your local STMicroelectronics sales office. |
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STM32G031x4/x6/x8
Summary of device errata
1Summary of device errata
The following table gives a quick reference to the STM32G031x4/x6/x8 device limitations and their status: A = workaround available
N = no workaround available
P = partial workaround available
Applicability of a workaround may depend on specific conditions of target application. Adoption of a workaround may cause restrictions to target application. Workaround for a limitation is deemed partial if it only reduces the rate of occurrence and/or consequences of the limitation, or if it is fully effective for only a subset of instances on the device or in only a subset of operating modes, of the function concerned.
Table 3. Summary of device limitations
Function |
Section |
Limitation |
Status |
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Rev. Z |
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2.1.1 |
Unstable LSI when it clocks RTC or CSS on LSE |
P |
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2.1.2 |
WUFx wakeup flag wrongly set during configuration |
A |
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2.1.3 |
Under Level 1 read protection, booting from Main Flash memory selected |
N |
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through PA14 BOOT0 pin is not functional |
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System |
2.1.4 |
DMAMUX cannot be synchronized or triggered by EXTI |
N |
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2.1.5 |
Overwriting with all zeros a Flash memory location previously programmed with |
N |
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all ones fails |
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2.1.6 |
Wakeup from Stop not effective under certain conditions |
N |
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2.1.7 |
Flash memory PCROP area weakness |
N |
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2.1.8 |
PC13 signal transitions disturb LSE |
N |
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DMA |
2.2.1 |
DMA disable failure and error flag omission upon simultaneous transfer error |
A |
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and global flag clear |
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2.3.1 |
SOFx not asserted when writing into DMAMUX_CFR register |
N |
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2.3.2 |
OFx not asserted for trigger event coinciding with last DMAMUX request |
N |
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DMAMUX |
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2.3.3 |
OFx not asserted when writing into DMAMUX_RGCFR register |
N |
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2.3.4 |
Wrong input DMA request routed upon specific DMAMUX_CxCR register write |
A |
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coinciding with synchronization event |
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2.4.1 |
Overrun flag is not set if EOC reset coincides with new conversion end |
P |
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ADC |
2.4.2 |
Writing ADC_CFGR1 register while ADEN bit is set resets RES[1:0] bitfield |
A |
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2.4.3 |
Out-of-threshold value is not detected in AWD1 Single mode |
A |
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2.4.4 |
ADC sampling time might be one cycle longer |
N |
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2.5.1 |
One-pulse mode trigger not detected in master-slave reset + trigger |
P |
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configuration |
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2.5.2 |
Consecutive compare event missed in specific conditions |
N |
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TIM |
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2.5.3 |
Output compare clear not working with external counter reset |
P |
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2.5.4 |
TIM1 synchronization trigger might be missed |
N |
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2.5.5 |
TIM16 and TIM17 are unduly clocked by SYSCLK |
N |
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LPTIM |
2.6.1 |
Device may remain stuck in LPTIM interrupt when entering Stop mode |
A |
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2.6.2 |
Device may remain stuck in LPTIM interrupt when clearing event flag |
P |
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RTC and TAMP |
2.7.1 |
Calendar initialization may fail in case of consecutive INIT mode entry |
A |
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ES0487 - Rev 3 |
page 2/18 |
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STM32G031x4/x6/x8 |
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Summary of device errata |
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Function |
Section |
Limitation |
Status |
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Rev. Z |
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2.8.1 |
Wrong data sampling when data setup time (tSU;DAT) is shorter than one I2C |
P |
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kernel clock period |
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I2C |
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2.8.2 |
Spurious bus error detection in master mode |
A |
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2.8.3 |
Spurious master transfer upon own slave address match |
P |
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USART |
2.9.1 |
Data corruption due to noisy receive line |
N |
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SPI |
2.10.1 |
BSY bit may stay high when SPI is disabled |
A |
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2.10.2 |
BSY bit may stay high at the end of data transfer in slave mode |
A |
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The following table gives a quick reference to the documentation errata.
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Table 4. Summary of device documentation errata |
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Function |
Section |
Documentation erratum |
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ADC |
2.4.5 |
ADC trigger latency parameter |
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USART |
2.9.2 |
USART prescaler feature missing in USART implementation section |
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ES0487 - Rev 3 |
page 3/18 |
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STM32G031x4/x6/x8
Description of device errata
2Description of device errata
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The following sections describe limitations of the applicable devices with Arm® core and provide workarounds if |
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available. They are grouped by device functions. |
Note: |
Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. |
2.1System
2.1.1Unstable LSI when it clocks RTC or CSS on LSE
Description
The LSI clock can become unstable (duty cycle different from 50 %) and its maximum frequency can become significantly higher than 32 kHz, when:
•LSI clocks the RTC, or it clocks the clock security system (CSS) on LSE (which holds when the LSECSSON bit set), and
•the VDD power domain is reset while the backup domain is not reset, which happens:
–upon exiting Shutdown mode
–if VBAT is separate from VDD and VDD goes off then on
–if VBAT is tied to VDD (internally in the package for products not featuring the VBAT pin, or externally) and a short (< 1 ms) VDD drop under VDD(min) occurs
Workaround
Apply one of the following measures:
•Clock the RTC with LSE or HSE/32, without using the CSS on LSE
•If LSI clocks the RTC or when the LSECSSON bit is set, reset the backup domain upon each VDD power up (when the BORRSTF flag is set). If VBAT is separate from VDD, also restore the RTC configuration, backup registers and anti-tampering configuration.
2.1.2WUFx wakeup flag wrongly set during configuration
Description
Upon configuring a wakeup pin (WKUPx), the corresponding wakeup flag (WUFx) might spuriously go high depending on the state and configuration of the wakeup pin.
Workaround
After configuring a wakeup pin, clear its corresponding WUFx flag.
2.1.3Under Level 1 read protection, booting from Main Flash memory selected through PA14 BOOT0 pin is not functional
Description
With the Flash memory read protection set to Level 1 and the boot mode selected through the PA14-BOOT0 pin (BOOT0 function of the pin), an attempt to boot from Main Flash memory can wrongly be interpreted by the read protection mechanism as an unauthorized access, preventing the user code execution. Booting from Main Flash memory operates correctly if selected through option bits (nBOOT_SEL and nBOOT0 both set).
ES0487 - Rev 3 |
page 4/18 |
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STM32G031x4/x6/x8
System
Workaround
None.
2.1.4DMAMUX cannot be synchronized or triggered by EXTI
Description
The EXTI-related DMAMUX synchronization and trigger inputs are wrongly routed to the it_exti_per(y) output instead of being routed to the exti[15:0] output lines.
The it_exti_per(y) signals are not usable for synchronizing and triggering DMAMUX.
Workaround
None.
2.1.5Overwriting with all zeros a Flash memory location previously programmed with all ones fails
Description
Any attempt to re-program with all zeros (0x0000 0000 0000 0000) a Flash memory location previously programmed with 0xFFFF FFFF FFFF FFFF fails and the PROGERR flag of the FLASH_SR register is set.
Workaround
None.
2.1.6Wakeup from Stop not effective under certain conditions
Description
With the HSI clock divider bitfield HSIDIV[2:0] set to a value different from 000, the device fails to enter Stop mode when SYSCLK is set to HSE clock.
With the HSI clock divider bitfield HSIDIV[2:0] set to a value different from 000, peripherals with clock request capability fail to wake the device up from Stop modes.
Workaround
None.
2.1.7Flash memory PCROP area weakness
Description
When the CPU accesses PCROP-protected Flash memory areas:
•Fetch requests are allowed and are responded to normally.
•Read access are properly discarded. However, the bus holds and returns the value read during previous successful access.
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Workaround |
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None. |
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Note: |
We recommend to use the PCROP protection in the following RDP and PCROP_RDP configurations: |
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RDP = Level 1 and PCROP_RDP = 1 |
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RDP = Level 2 |
ES0487 - Rev 3 |
page 5/18 |
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STM32G031x4/x6/x8
DMA
2.1.8PC13 signal transitions disturb LSE
Description
The PC13 port toggling disturbs the LSE clock.
Workaround
None.
2.2DMA
2.2.1DMA disable failure and error flag omission upon simultaneous transfer error and global flag clear
Description
Upon a data transfer error in a DMA channel x, both the specific TEIFx and the global GIFx flags are raised and the channel x is normally automatically disabled. However, if in the same clock cycle the software clears the GIFx flag (by setting the CGIFx bit of the DMA_IFCR register), the automatic channel disable fails and the TEIFx flag is not raised.
This issue does not occur with ST's HAL software that does not use and clear the GIFx flag when the channel is active.
Workaround
Do not clear GIFx flags when the channel is active. Instead, use HTIFx, TCIFx, and TEIFx specific event flags and their corresponding clear bits.
2.3DMAMUX
2.3.1SOFx not asserted when writing into DMAMUX_CFR register
Description
The SOFx flag of the DMAMUX_CSR status register is not asserted if overrun from another DMAMUX channel occurs when the software writes into the DMAMUX_CFR register.
This can happen when multiple DMA channels operate in synchronization mode, and when overrun can occur from more than one channel. As the SOFx flag clear requires a write into the DMAMUX_CFR register (to set the corresponding CSOFx bit), overrun occurring from another DMAMUX channel operating during that write operation fails to raise its corresponding SOFx flag.
Workaround
None. Avoid the use of synchronization mode for concurrent DMAMUX channels, if at least two of them potentially generate synchronization overrun.
2.3.2OFx not asserted for trigger event coinciding with last DMAMUX request
Description
In the DMAMUX request generator, a trigger event detected in a critical instant of the last-generated DMAMUX request being served by the DMA controller does not assert the corresponding trigger overrun flag OFx. The critical instant is the clock cycle at the very end of the trigger overrun condition.
Additionally, upon the following trigger event, one single DMA request is issued by the DMAMUX request generator, regardless of the programmed number of DMA requests to generate.
The failure only occurs if the number of requests to generate is set to more than two (GNBREQ[4:0] > 00001).
ES0487 - Rev 3 |
page 6/18 |
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