STM32F722xx STM32F723xx
Arm® Cortex®-M7 32b MCU+FPU, 462DMIPS, up to 512KB Flash /256+16+4KB RAM, USB OTG HS/FS, 18 TIMs, 3 ADCs, 21 com IF
Datasheet - production data
Features
•Core: Arm® 32-bit Cortex®-M7 CPU with FPU, adaptive real-time accelerator (ART Accelerator) and L1-cache: 8 Kbytes of data cache and 8 Kbytes of instruction cache, allowing 0-wait state execution from embedded Flash memory and external memories, frequency up to 216 MHz, MPU,
462 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1) and DSP instructions.
•Memories
–Up to 512 Kbytes of Flash memory with protection mechanisms (read and write protections, proprietary code readout protection (PCROP))
–528 bytes of OTP memory
–SRAM: 256 Kbytes (including 64 Kbytes of data TCM RAM for critical real-time data) + 16 Kbytes of instruction TCM RAM (for critical real-time routines) + 4 Kbytes of backup SRAM (available in the lowest power modes)
–Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories
•Dual mode Quad-SPI
•Clock, reset and supply management
–1.7 V to 3.6 V application supply and I/Os
–POR, PDR, PVD and BOR
–Dedicated USB power
–4-to-26 MHz crystal oscillator
–Internal 16 MHz factory-trimmed RC (1% accuracy)
–32 kHz oscillator for RTC with calibration
–Internal 32 kHz RC with calibration
•Low-power
–Sleep, Stop and Standby modes
LQFP64 (10 × 10 mm) |
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UFBGA144 (7 x 7 mm) |
WLCSP100 |
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LQFP100 (14 × 14 mm) |
UFBGA176 (10 x 10 mm) |
(0.4 mm pitch) |
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LQFP144 (20 × 20 mm) |
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LQFP176 (24 x 24 mm) |
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–VBAT supply for RTC, 32×32 bit backup registers + 4 Kbytes of backup SRAM
•3×12-bit, 2.4 MSPS ADC: up to 24 channels and 7.2 MSPS in triple interleaved mode
•2×12-bit D/A converters
•Up to 18 timers: up to thirteen 16-bit (1x lowpower 16-bit timer available in Stop mode) and two 32-bit timers, each with up to 4 IC/OC/PWMs or pulse counter and quadrature (incremental) encoder inputs. All 15 timers running up to 216 MHz. 2x watchdogs, SysTick timer
•General-purpose DMA: 16-stream DMA controller with FIFOs and burst support
•Debug mode
–SWD and JTAG interfaces
–Cortex®-M7 Trace Macrocell™
•Up to 140 I/O ports with interrupt capability
–Up to 136 fast I/Os up to 108 MHz
–Up to 138 5 V-tolerant I/Os
•Up to 21 communication interfaces
–Up to 3× I2C interfaces (SMBus/PMBus)
–Up to 4 USARTs/4 UARTs (27 Mbit/s, ISO7816 interface, LIN, IrDA, modem control)
–Up to 5 SPIs (up to 54 Mbit/s), 3 with muxed simplex I2Ss for audio class accuracy via internal audio PLL or external clock
–2 x SAIs (serial audio interface)
November 2020 |
DS11853 Rev 7 |
1/230 |
This is information on a product in full production. |
www.st.com |
STM32F722xx STM32F723xx
–1 x CAN (2.0B active)
–2 x SDMMCs
•Advanced connectivity
–USB 2.0 full-speed device/host/OTG controller with on-chip PHY
–USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and on-chip Hi-speed PHY or ULPI depending on the part number
•CRC calculation unit
•RTC: subsecond accuracy, hardware calendar
•96-bit unique ID
• True random number generator
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Table 1. Device summary |
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Reference |
Part number |
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STM32F722xx |
STM32F722IC, STM32F722IE, STM32F722RC, STM32F722RE, STM32F722VC, |
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STM32F722VE, STM32F722ZC, STM32F722ZE |
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STM32F723xx |
STM32F723IC, STM32F723IE, STM32F723VC, STM32F723VE, STM32F723ZC, |
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STM32F723ZE |
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2/230 |
DS11853 Rev 7 |
STM32F722xx STM32F723xx |
Contents |
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Contents
1 |
Introduction |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
13 |
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2 |
Description . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
14 |
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2.1 |
Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . |
17 |
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2.2 |
STM32F723xx versus STM32F722xx LQFP100/ LQFP144/ |
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LQFP176 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
19 |
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3 |
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
22 |
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3.1 |
Arm® Cortex®-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
22 |
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3.2 |
Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
22 |
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3.3 |
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
23 |
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3.4 |
CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . |
23 |
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3.5 |
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
23 |
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3.6 |
AXI-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
24 |
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3.7 |
DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
25 |
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3.8 |
Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
26 |
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3.9 |
Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . |
26 |
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3.10 |
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . |
27 |
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3.11 |
External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . |
27 |
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3.12 |
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
27 |
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3.13 |
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
28 |
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3.14 |
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
28 |
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3.15 |
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
30 |
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3.15.1 |
Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
30 |
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3.15.2 |
Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
30 |
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3.16 |
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
32 |
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3.16.1 |
Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
32 |
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3.16.2 |
Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
33 |
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3.16.3 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . |
36 |
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3.17 |
Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . |
36 |
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3.18 |
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
37 |
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3.19 |
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
38 |
DS11853 Rev 7 |
3/230 |
Contents |
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STM32F722xx STM32F723xx |
3.20 Timers and watchdogs . . . . . . . . . . . . . . . . . . . |
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3.20.1 Advanced-control timers (TIM1, TIM8) . . . |
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3.20.2 |
General-purpose timers (TIMx) . . . . . . . . . |
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3.20.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . |
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3.20.4 |
Low-power timer (LPTIM1) . . . . . . . . . . . . |
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3.20.5 |
Independent watchdog . . . . . . . . . . . . . . . |
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3.20.6 |
Window watchdog . . . . . . . . . . . . . . . . . . . |
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3.20.7 |
SysTick timer . . . . . . . . . . . . . . . . . . . . . . . |
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3.21 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.22Universal synchronous/asynchronous receiver transmitters (USART) . . 43
3.23Serial peripheral interface (SPI)/interintegrated sound interfaces (I2S) . 44
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3.24 |
Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 44 |
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3.25 |
Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 45 |
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3.26 |
Audio PLL (PLLSAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 45 |
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3.27 |
SD/SDIO/MMC card host interface (SDMMC) . . . . . . . . . . . . . . . . . . . . . |
45 |
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3.28 |
Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
45 |
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3.29 |
Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . |
46 |
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3.30 |
Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . |
46 |
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3.31 |
Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
47 |
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3.32 |
General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . |
47 |
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3.33 |
Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
47 |
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3.34 |
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
48 |
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3.35 |
Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
48 |
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3.36 |
Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . |
48 |
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3.37 |
Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
49 |
4 |
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
50 |
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5 |
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
100 |
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6 |
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
101 |
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4/230 |
DS11853 Rev 7 |
STM32F722xx STM32F723xx |
Contents |
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6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 6.3.2 VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 6.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . 110
6.3.4Operating conditions at power-up / power-down (regulator OFF) . . . . 110
6.3.5 |
Reset and power control block characteristics . . . . . . . . . . . . . . . . . . |
110 |
6.3.6 |
Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . |
112 |
6.3.7 |
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
112 |
6.3.8 |
Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . |
130 |
6.3.9 |
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . |
131 |
6.3.10 |
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . |
136 |
6.3.11 |
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
137 |
6.3.12PLL spread spectrum clock generation (SSCG) characteristics . . . . . 140
6.3.13USB OTG HS PHY PLLs characteristics (on STM32F723xx devices) 142
6.3.14 USB OTG HS PHY regulator characteristics . . . . . . . . . . . . . . . . . . . |
142 |
6.3.15USB HS PHY external resistor characteristics
(on STM32F723xx devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 6.3.16 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 6.3.17 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 6.3.18 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 146 6.3.19 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 6.3.20 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 6.3.21 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 6.3.22 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 6.3.23 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 6.3.24 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 6.3.25 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
6.3.26 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 6.3.27 Reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
6.3.28 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 6.3.29 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 6.3.30 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
DS11853 Rev 7 |
5/230 |
Contents |
STM32F722xx STM32F723xx |
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6.3.31 Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 6.3.32 SD/SDIO MMC card host interface (SDMMC) characteristics . . . . . . . 199
7 |
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . 202 |
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7.1 |
LQFP64 – 10 x 10 mm, low-profile quad flat package information |
. . . . . 202 |
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7.2 |
LQFP100, 14 x 14 mm low-profile quad flat package information |
. . . . . 205 |
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7.3 |
LQFP144, 20 x 20 mm low-profile quad flat package information |
. . . . . 208 |
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7.4 |
LQFP176 24 x 24 mm low-profile quad flat package information . |
. . . . . .211 |
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7.5 |
UFBGA144 package information . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . 215 |
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7.6 |
UFBGA176+25, 10 x 10, 0.65 mm ultra thin-pitch ball grid |
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array package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . 218 |
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7.7 |
WLCSP100 - 0.4 mm pitch wafer level chip scale package information 221 |
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7.8 |
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . 225 |
8 |
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . 226 |
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Appendix A Recommendations when using internal reset OFF . . . . . . . |
. . . . 227 |
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A.1 |
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . 227 |
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
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DS11853 Rev 7 |
STM32F722xx STM32F723xx |
List of tables |
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List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Table 2. STM32F722xx and STM32F723xx features and peripheral counts . . . . . . . . . . . . . . . . . . 15 Table 3. Voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 33 Table 4. Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 5. Voltage regulator modes in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 6. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 7. I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 8. USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 9. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 10. STM32F722xx and STM32F723xx pin and ball definition . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 11. FMC pin definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 12. STM32F722xx and STM32F723xx alternate function mapping. . . . . . . . . . . . . . . . . . . . . 89 Table 13. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Table 14. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 15. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table 16. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table 17. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 108 Table 18. VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 19. VCAP1 operating conditions in the LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 20. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . 110 Table 21. Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . 110 Table 22. reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Table 23. Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Table 24. Typical and maximum current consumption in Run mode, code with data processing
running from ITCM RAM, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Table 25. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART ON except prefetch / L1-cache ON)
or SRAM on AXI (L1-cache ON), regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 26. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory or SRAM on AXI (L1-cache disabled), regulator ON . . . . . 115 Table 27. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory on ITCM interface (ART disabled), regulator ON . . . . . . . . 116 Table 28. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART ON except prefetch / L1-cache ON)
or SRAM on AXI (L1-cache ON), regulator OFF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Table 29. Typical and maximum current consumption in Sleep mode, regulator ON. . . . . . . . . . . . 118 Table 30. Typical and maximum current consumption in Sleep mode, regulator OFF. . . . . . . . . . . 118 Table 31. Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . 119 Table 32. Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . 120
Table 33. Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . 121 Table 34. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 35. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Table 36. USB OTG HS and USB OTG PHY HS current consumption . . . . . . . . . . . . . . . . . . . . . . 130 Table 37. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Table 38. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Table 39. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Table 40. HSE 4-26 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Table 41. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
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Table 42. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Table 43. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Table 44. Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Table 45. PLLI2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Table 46. PLLISAI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Table 47. SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Table 48. USB OTG HS PLL1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Table 49. USB OTG HS PLL2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Table 50. USB OTG HS PHY regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Table 51. USB HS PHY external resistor characteristics (on STM32F723xx devices). . . . . . . . . . . 143 Table 52. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Table 53. Flash memory programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Table 54. Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Table 55. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Table 56. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Table 57. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Table 58. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Table 59. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Table 60. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Table 61. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Table 62. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Table 63. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Table 64. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Table 65. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Table 66. RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Table 67. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 68. ADC static accuracy at fADC = 18 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Table 69. ADC static accuracy at fADC = 30 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Table 70. ADC static accuracy at fADC = 36 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Table 71. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 158 Table 72. ADC dynamic accuracy at fADC = 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 158 Table 73. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 74. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 75. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Table 76. internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 77. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Table 78. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Table 79. Minimum I2CCLK frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Table 80. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 81. SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Table 82. I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 83. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Table 84. USB OTG full speed startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Table 85. USB OTG full speed DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Table 86. USB OTG full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Table 87. USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Table 88. USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Table 89. Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Table 90. USB OTG high speed DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Table 91. USB OTG high speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Table 92. USB FS PHY BCD electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Table 93. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 179
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Table 94. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings . . . . . . . . . . 179 Table 95. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 180 Table 96. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings. . . . . . . . . . 181 Table 97. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Table 98. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 182 Table 99. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Table 100. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 184 Table 101. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Table 102. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Table 103. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 189 Table 104. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Table 105. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Table 106. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Table 107. SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Table 108. LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Table 109. SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Table 110. LPSDR SDRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Table 111. Quad-SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Table 112. Quad-SPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Table 113. Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V . . . . . . . . . . . . . 200 Table 114. Dynamic characteristics: eMMC characteristics, VDD=1.71V to 1.9V . . . . . . . . . . . . . . . 201 Table 115. LQFP64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Table 116. LQPF100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Table 117. LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Table 118. LQFP176 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Table 119. UFBGA144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Table 120. UFBGA144 recommended PCB design rules (0.50 mm pitch BGA) . . . . . . . . . . . . . . . . 216 Table 121. UFBGA176+25 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Table 122. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 219 Table 123. WLCSP100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Table 124. WLCSP100 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . 223 Table 125. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Table 126. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Table 127. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 227 Table 128. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
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Figure 1. |
Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 17 |
Figure 2. |
Compatible board design for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 18 |
Figure 3. |
Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 19 |
Figure 4. |
Compatible board design for LQFP144 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 19 |
Figure 5. |
Compatible board design for LQFP176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 20 |
Figure 6. |
STM32F722xx and STM32F723xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 21 |
Figure 7. |
STM32F722xx and STM32F723xx AXI-AHB bus matrix architecture(1) . . . . . . . . . . . . . |
. 24 |
Figure 8. VDDUSB connected to VDD power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 29 |
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Figure 9. VDDUSB connected to external power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 29 |
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Figure 10. |
Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . |
. 31 |
Figure 11. |
PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 31 |
Figure 12. |
Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
34 |
Figure 13. |
Startup in regulator OFF: slow VDD slope |
|
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- power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . |
35 |
Figure 14. |
Startup in regulator OFF mode: fast VDD slope |
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- power-down reset risen before VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . |
35 |
Figure 15. STM32F722xx LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
50 |
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Figure 16. STM32F722xx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
51 |
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Figure 17. STM32F723xx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
52 |
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Figure 18. |
STM32F723xx WLCSP100 ballout (with OTG PHY HS) . . . . . . . . . . . . . . . . . . . . . . . . . . |
53 |
Figure 19. STM32F722xx LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
54 |
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Figure 20. STM32F723xx LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
55 |
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Figure 21. |
STM32F723xx UFBGA144 ballout (with OTG PHY HS). . . . . . . . . . . . . . . . . . . . . . . . . . . |
56 |
Figure 22. STM32F722xx LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
57 |
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Figure 23. STM32F723xx LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
58 |
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Figure 24. STM32F723xx UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
59 |
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Figure 25. |
STM32F723xx UFBGA176 ballout (with OTG PHY HS). . . . . . . . . . . . . . . . . . . . . . . . . . . |
60 |
Figure 26. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
101 |
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Figure 27. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
101 |
|
Figure 28. STM32F722xx power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
102 |
|
Figure 29. STM32F723xx power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
103 |
|
Figure 30. |
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
104 |
Figure 31. |
External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
109 |
Figure 32. |
Typical VBAT current consumption (RTC ON/BKP SRAM OFF and |
|
|
LSE in low drive mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
122 |
Figure 33. |
Typical VBAT current consumption (RTC ON/BKP SRAM OFF and |
|
|
LSE in medium low drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
122 |
Figure 34. |
Typical VBAT current consumption (RTC ON/BKP SRAM OFF and |
|
|
LSE in medium high drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
123 |
Figure 35. |
Typical VBAT current consumption (RTC ON/BKP SRAM OFF and |
|
|
LSE in high drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
123 |
Figure 36. |
Typical VBAT current consumption (RTC ON/BKP SRAM OFF and |
|
|
LSE in high medium drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
124 |
Figure 37. |
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . |
132 |
Figure 38. |
Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . |
133 |
Figure 39. |
Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
134 |
Figure 40. |
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
135 |
Figure 41. |
ACCHSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
136 |
10/230 |
DS11853 Rev 7 |
STM32F722xx STM32F723xx |
List of figures |
|
Figure 42. LSI deviation versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . 137 |
|
Figure 43. PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . 141 |
|
Figure 44. PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 141 |
|
Figure 45. FT I/O input characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 150 |
|
Figure 46. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 153 |
|
Figure 47. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 154 |
|
Figure 48. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 159 |
|
Figure 49. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 159 |
|
Figure 50. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . |
. . . . . . . . 160 |
|
Figure 51. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . |
. . . . . . . . 160 |
|
Figure 52. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 164 |
|
Figure 53. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 167 |
|
Figure 54. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 168 |
|
Figure 55. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 168 |
|
Figure 56. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 170 |
|
Figure 57. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 170 |
|
Figure 58. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 172 |
|
Figure 59. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 172 |
|
Figure 60. USB OTG full speed timings: definition of data signal rise and fall time. . . . . . |
. . . . . . . . 174 |
|
Figure 61. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 175 |
|
Figure 62. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . |
. . . . . . . . 178 |
|
Figure 63. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . |
. . . . . . . . 180 |
|
Figure 64. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . |
. . . . . . . . 181 |
|
Figure 65. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . |
. . . . . . . . 183 |
|
Figure 66. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 185 |
|
Figure 67. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 187 |
|
Figure 68. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . |
. . . . . . . . 189 |
|
Figure 69. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 190 |
|
Figure 70. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 192 |
|
Figure 71. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 192 |
|
Figure 72. NAND controller waveforms for common memory read access . . . . . . . . . . . . |
. . . . . . . . 192 |
|
Figure 73. NAND controller waveforms for common memory write access. . . . . . . . . . . . |
. . . . . . . . 193 |
|
Figure 74. SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 194 |
|
Figure 75. SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 196 |
|
Figure 76. Quad-SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 199 |
|
Figure 77. Quad-SPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 199 |
|
Figure 78. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 200 |
|
Figure 79. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 200 |
|
Figure 80. |
LQFP64 outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 202 |
Figure 81. LQFP64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 203 |
|
Figure 82. LQFP64 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 204 |
|
Figure 83. |
LQFP100 outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 205 |
Figure 84. LQFP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 206 |
|
Figure 85. LQFP100 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 207 |
|
Figure 86. |
LQFP144 outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 208 |
Figure 87. LQFP144 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 209 |
|
Figure 88. LQFP144 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 210 |
|
Figure 89. |
LQFP176 outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 211 |
Figure 90. LQFP176 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 213 |
|
Figure 91. LQFP176 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 214 |
|
Figure 92. |
UFBGA144 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 215 |
Figure 93. |
UFBGA144 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 216 |
DS11853 Rev 7 |
11/230 |
List of figures |
STM32F722xx STM32F723xx |
|
Figure 94. |
UFBGA144 top view example . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . 217 |
Figure 95. |
UFBGA176 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . 218 |
Figure 96. |
UFBGA176+25 recommended footprint . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . 219 |
Figure 97. |
UFBGA176 top view example. . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . 220 |
Figure 98. |
WLCSP100 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . 221 |
Figure 99. |
WLCSP100 recommended footprint . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . 222 |
Figure 100. |
WLCSP100 top view example . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . 224 |
12/230 |
DS11853 Rev 7 |
STM32F722xx STM32F723xx |
Introduction |
|
|
This datasheet provides the ordering information and mechanical device characteristics of the STM32F722xx and STM32F723xx microcontrollers.
This document should be ready in conjunction with the STM32F72xxx and STM32F73xxx advanced Arm®-based 32-bit MCUs reference manual (RM0431). The reference manual is available from the STMicroelectronics website www.st.com.
For information on the Arm®(a) Cortex®-M7 core, refer to the Cortex®-M7 technical reference manual available from the http://www.arm.com website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
DS11853 Rev 7 |
13/230 |
Description |
STM32F722xx STM32F723xx |
|
|
The STM32F722xx and STM32F723xx devices are based on the high-performance Arm® Cortex®-M7 32-bit RISC core operating at up to 216 MHz frequency. The Cortex®-M7 core features a single floating point unit (SFPU) precision which supports Arm® single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances the application security.
The STM32F722xx and STM32F723xx devices incorporate high-speed embedded memories with a Flash memory up to 512 Kbytes, 256 Kbytes of SRAM (including
64 Kbytes of data TCM RAM for critical real-time data), 16 Kbytes of instruction TCM RAM (for critical real-time routines), 4 Kbytes of backup SRAM available in the lowest power modes, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses, a 32-bit multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external memories access.
All the devices offer three 12-bit ADCs, two DACs, a low-power RTC, thirteen generalpurpose 16-bit timers including two PWM timers for motor control, two general-purpose 32bit timers, a true random number generator (RNG). They also feature standard and advanced communication interfaces.
•Up to three I2Cs
•Five SPIs, three I2Ss in half duplex mode. To achieve the audio class accuracy, the I2S peripherals can be clocked via a dedicated internal audio PLL or via an external clock to allow synchronization.
•Four USARTs plus four UARTs
•An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the ULPI or with the integrated HS PHY depending on the part number)
•One CAN
•Two SAI serial audio interfaces
•Two SDMMC host interfaces
Advanced peripherals include two SDMMC interfaces, a flexible memory control (FMC) interface, a Quad-SPI Flash memory interface.
The STM32F722xx and STM32F723xx devices operate in the –40 to +105 °C temperature range from a 1.7 to 3.6 V power supply. Dedicated supply inputs for the USB (OTG_FS and OTG_HS) and the SDMMC2 (clock, command and 4-bit data) are available on all the packages except LQFP100 and LQFP64 for a greater power supply choice.
The supply voltage can drop to 1.7 V with the use of an external power supply supervisor. A comprehensive set of power-saving mode allows the design of low-power applications.
The STM32F722xx and STM32F723xx devices offer devices in 7 packages ranging from 64 pins to 176 pins. The set of included peripherals changes with the device chosen.
14/230 |
DS11853 Rev 7 |
STM32F722xx STM32F723xx |
Description |
|
|
These features make the STM32F722xx and STM32F723xx microcontrollers suitable for a wide range of applications:
•Motor drive and application control,
•Medical equipment,
•Industrial applications: PLC, inverters, circuit breakers,
•Printers, and scanners,
•Alarm systems, video intercom, and HVAC,
•Home audio appliances,
•Mobile applications, Internet of Things,
•Wearable devices: smartwatches.
The following table lists the peripherals available on each part number.
Peripherals |
STM32F72xRx |
|
STM32F72xVx |
|
STM32F72xZx |
|
STM32F72xIx |
|||||||
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Flash memory in Kbytes |
|
256 |
|
512 |
|
256 |
512 |
|
256 |
|
512 |
|
256 |
512 |
|
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|
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System |
|
|
|
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256(176+16+64) |
|
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|
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||
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|
|
|
|
|
SRAM in Kbytes |
Instruction |
|
|
|
|
|
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16 |
|
|
|
|
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Backup |
|
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|
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|
4 |
|
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FMC memory controller |
|
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No |
|
|
|
|
Yes(1) |
|
|
|
|
||
Quad-SPI |
|
|
|
|
|
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Yes |
|
|
|
|
||
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General-purpose |
|
|
|
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10(2) |
|
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|
|
|
||
Timers |
Advanced-control |
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2 |
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Basic |
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2 |
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Low-power |
|
No |
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1 |
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|||
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Random number generator |
|
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Yes |
|
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|
|||
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|
|
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||
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SPI / I2S |
3/3 (simplex)(3) |
|
4/3 (simplex)(3) |
|
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5/3 (simplex)(3) |
|
|||||
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I2C |
|
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3 |
|
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USART/UART |
|
4/2 |
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4/4 |
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USB OTG FS |
|
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Yes |
|
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||
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Communication |
USB OTG HS(4) |
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Yes |
|
|
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|
||
interfaces |
USB OTG PHY HS |
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No |
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Yes(10) |
|
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||
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controller (USBPHYC) |
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CAN |
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1 |
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SAI |
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2 |
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SDMMC1 |
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Yes |
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SDMMC2 |
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No |
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Yes(5)(6) |
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GPIOs |
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50 |
|
82 in STM32F722xx |
|
114 in STM32F722xx |
|
140 in STM32F722xx |
|||||
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79 in STM32F723xx |
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112 in STM32F723xx |
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138 in STM32F723xx |
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12-bit ADC |
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3 |
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Number of channels |
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16 |
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24 |
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12-bit DAC |
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Yes |
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Number of channels |
|
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2 |
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Maximum CPU frequency |
|
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216 MHz(7) |
|
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|
DS11853 Rev 7 |
15/230 |
Description |
STM32F722xx STM32F723xx |
|
|
Table 2. STM32F722xx and STM32F723xx features and peripheral counts (continued)
Peripherals |
STM32F72xRx |
|
STM32F72xVx |
STM32F72xZx |
|
STM32F72xIx |
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Operating voltage |
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1.7 to 3.6 V(8) |
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||
Operating temperatures |
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Ambient temperatures: –40 to +85 °C /–40 to +105 °C |
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Junction temperature: –40 to + 125 °C |
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(9) |
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LQFP100(10) |
LQFP144 |
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UFBGA176 |
Package |
LQFP64 |
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WLCSP100 |
UFBGA144(10) |
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LQFP176 |
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1.For the LQFP100 package, only FMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select.
2.On the STM32F723xx device packages, except the 176-pin ones, the TIM12 is not available, so there are 9 generalpurpose timers.
3.The SPI1, SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode.
4.USB OTG HS with the ULPI on the STM32F722xx devices and with integrated HS PHY on the STM32F723xx devices.
5.The SDMMC2 supports a dedicated power rail for clock, command and data 0..4 lines, feature available starting from 144 pin package.
6.The SDMMC2 is not available on the STM32F723Vx devices.
7.216 MHz maximum frequency for - 40°C to + 85°C ambient temperature range (200 MHz maximum frequency for - 40°C to + 105°C ambient temperature range).
8.VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to Section 3.15.2: Internal reset OFF).
9.Available only on the STM32F722xx devices.
10.Available only on the STM32F723xx devices.
16/230 |
DS11853 Rev 7 |
STM32F722xx STM32F723xx |
Description |
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|
The STM32F722xx devices are fully pin-to-pin, compatible with the STM32F7x5xx, STM32F7x6xx, STM32F7x7xx devices.
The STM32F722xx devices are partially pin-to-pin, compatible with the STM32F4xxxx devices, allowing the user to try different peripherals, and reaching higher performances (higher frequency) for a greater degree of freedom during the development cycle.
Figure 1 and Figure 2 give compatible board designs between the STM32F722xx, with LQFP64 and LQFP100 packages, and STM32F4xx families.
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STM32F427xx / STM32F437xx |
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STM32F429xx / STM32F439xx |
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PC3 |
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18 |
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STM32F415xx / STM32F417xx |
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STM32F405xx / STM32F407xx |
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VDD |
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19 |
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VSSA |
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20 |
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VREF+ |
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21 |
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VDDA |
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22 |
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|||
PA0-WKUP |
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23 |
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PA1 |
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24 |
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PA2 |
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25 |
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26 |
27 |
28 |
29 |
30 |
31 |
32 |
33 |
34 |
35 |
36 |
37 |
38 |
39 |
40 |
41 |
42 |
43 |
44 |
45 |
46 |
47 |
48 |
49 |
50 |
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<![if ! IE]> <![endif]>PA3 |
|
<![if ! IE]> <![endif]>VSS |
<![if ! IE]> <![endif]>VDD |
|
<![if ! IE]> <![endif]>PA4 |
|
<![if ! IE]> <![endif]>PA5 |
<![if ! IE]> <![endif]>PA6 |
<![if ! IE]> <![endif]>PA7 |
<![if ! IE]> <![endif]>PC4 |
<![if ! IE]> <![endif]>PC5 |
|
<![if ! IE]> <![endif]>PB0 |
|
<![if ! IE]> <![endif]>PB1 |
|
<![if ! IE]> <![endif]>PB2 |
|
<![if ! IE]> <![endif]>PE7 |
|
<![if ! IE]> <![endif]>PE8 |
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<![if ! IE]> <![endif]>PE9 |
|
<![if ! IE]> <![endif]>PE10 |
|
<![if ! IE]> <![endif]>PE11 |
<![if ! IE]> <![endif]>PE12 |
<![if ! IE]> <![endif]>PE13 |
<![if ! IE]> <![endif]>PE14 |
|
<![if ! IE]> <![endif]>PE15 |
|
<![if ! IE]> <![endif]>PB10 |
<![if ! IE]> <![endif]>PB11 |
<![if ! IE]> <![endif]>VCAP1 |
|
<![if ! IE]> <![endif]>VDD |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||
PC3 |
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STM32F72xxx |
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18 |
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||||||||||||||||||
VSSA |
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19 |
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VREF+ |
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20 |
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VDDA |
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21 |
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PA0-WKUP |
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22 |
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PA1 |
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23 |
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Pins 19 to 49 are not compatible |
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PA2 |
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24 |
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PA3 |
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25 |
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26 |
27 |
28 |
29 |
30 |
31 |
32 |
33 |
34 |
35 |
36 |
37 |
38 |
39 |
40 |
41 |
42 |
43 |
44 |
45 |
46 |
47 |
48 |
49 |
50 |
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<![if ! IE]> <![endif]>VSS |
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<![if ! IE]> <![endif]>VDD |
|
<![if ! IE]> <![endif]>PA4 |
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<![if ! IE]> <![endif]>PA5 |
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<![if ! IE]> <![endif]>PA6 |
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<![if ! IE]> <![endif]>PA7 |
<![if ! IE]> <![endif]>PC4 |
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<![if ! IE]> <![endif]>PC5 |
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<![if ! IE]> <![endif]>PB0 |
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<![if ! IE]> <![endif]>PB1 |
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<![if ! IE]> <![endif]>PB2 |
|
<![if ! IE]> <![endif]>PE7 |
<![if ! IE]> <![endif]>PE8 |
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<![if ! IE]> <![endif]>PE9 |
<![if ! IE]> <![endif]>PE10 |
<![if ! IE]> <![endif]>PE11 |
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<![if ! IE]> <![endif]>PE12 |
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<![if ! IE]> <![endif]>PE13 |
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<![if ! IE]> <![endif]>PE14 |
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<![if ! IE]> <![endif]>PE15 |
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<![if ! IE]> <![endif]>PB10 |
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<![if ! IE]> <![endif]>PB11 |
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<![if ! IE]> <![endif]>VCAP1 |
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<![if ! IE]> <![endif]>VSS |
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<![if ! IE]> <![endif]>VDD |
MSv41001V2
DS11853 Rev 7 |
17/230 |
Description |
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STM32F722xx STM32F723xx |
||||||||||||
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|||||||||||
|
Figure 2. Compatible board design for LQFP64 package |
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||||||||||||||||||||||||
|
<![if ! IE]> <![endif]>PC12 |
<![if ! IE]> <![endif]>PC11 |
|
<![if ! IE]> <![endif]>PC10 |
|
<![if ! IE]> <![endif]>PA15 |
<![if ! IE]> <![endif]>PA14 |
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<![if ! IE]> <![endif]>PC12 |
<![if ! IE]> <![endif]>PC11 |
<![if ! IE]> <![endif]>PC10 |
<![if ! IE]> <![endif]>PA15 |
<![if ! IE]> <![endif]>PA14 |
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53 52 51 50 49 |
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53 52 51 50 49 |
VDD |
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||||||||||||||
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48 |
VDD |
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VDD |
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48 |
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VDD |
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47 |
VCAP_2 |
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47 |
VSS |
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46 |
PA13 |
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46 |
PA13 |
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45 |
PA12 |
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45 |
PA12 |
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44 |
PA11 |
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44 |
PA11 |
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43 |
PA10 |
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43 |
PA10 |
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42 |
PA9 |
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42 |
PA9 |
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VSS |
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VSS |
|||||||||||||||
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STM32F405/ |
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41 |
PA8 |
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41 |
PA8 |
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STM32F4x1 |
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||||||||||
|
STM32F415 line |
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40 |
PC9 |
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40 |
PC9 |
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39 |
PC8 |
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39 |
PC8 |
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38 |
PC7 |
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38 |
PC7 |
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37 |
PC6 |
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PB11 not available anymore |
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37 |
PC6 |
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|||||
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36 |
PB15 |
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36 |
PB15 |
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||||||
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Replaced by VCAP_1 |
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35 |
PB14 |
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35 |
PB14 |
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34 |
PB13 |
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34 |
PB13 |
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33 |
PB12 |
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33 |
PB12 |
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||||
28 29 |
30 |
3132 |
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28 29 30 31 32 |
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||||||||||||
|
<![if ! IE]> <![endif]>PB2 |
<![if ! IE]> <![endif]>PB10 |
|
<![if ! IE]> <![endif]>PB11 |
<![if ! IE]> <![endif]>VCAP 1 |
<![if ! IE]> <![endif]>VDD |
|
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|
<![if ! IE]> <![endif]>PB2 |
<![if ! IE]> <![endif]>PB10 |
<![if ! IE]> <![endif]>VCAP 1 |
<![if ! IE]> <![endif]>VSS |
<![if ! IE]> <![endif]>VDD |
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VCAP increased to 4.7 μf
ESR 1 ohm or below 1 ohm
|
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VSS |
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VDD |
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<![if ! IE]> <![endif]>PB5 PB4 PB3 PD2 |
<![if ! IE]> <![endif]>PC12 |
<![if ! IE]> <![endif]>PC 11 |
|
<![if ! IE]> <![endif]>PC10 PA15 |
|
<![if ! IE]> <![endif]>PA14 |
|
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||||||||||||||
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57 56 55 54 53 52 51 50 49 |
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VDD |
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48 |
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VSS |
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47 |
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46 |
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PA13 |
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45 |
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PA12 |
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44 |
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PA11 |
|||
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43 |
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PA10 |
|||
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STM32F722xx |
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42 |
|
PA9 |
||||||||||||||
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PC7 |
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PC5 not available anymore |
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37 |
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PC6 |
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36 |
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PB15 |
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Replaced by VCAP_1 |
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35 |
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PB14 |
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34 |
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PB13 |
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33 |
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PB12 |
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17 18 19 20 21 22 23 24 |
25 26 27 28 29 |
30 31 |
32 |
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<![if ! IE]> <![endif]>PA3 |
|
<![if ! IE]> <![endif]>VSS VDD |
<![if ! IE]> <![endif]>PA4 PA5 PA6 PA7 PC4 PB0 PB1 PB2 |
<![if ! IE]> <![endif]>PB10 |
<![if ! IE]> <![endif]>PB11 |
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<![if ! IE]> <![endif]>VCAP 1 |
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<![if ! IE]> <![endif]>VSS |
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<![if ! IE]> <![endif]>VDD |
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VCAP increased to 4.7 μf
ESR between 0.1 ohm and 0.2 ohm
VSS VDD
VDD
VSS
Not compatible STM32F722xx pins with either STM32F4x1 or STM32F405/F415 or both
VSS VDD
MSv41007V3
The STM32F722xx LQFP144, UFBGA176 and LQFP176 packages are fully pin to pin compatible with the STM32F4xx devices.
18/230 |
DS11853 Rev 7 |
STM32F722xx STM32F723xx |
Description |
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58 |
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PD11 |
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58 |
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PD11 |
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STM32F722xx |
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STM32F723xx |
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57 |
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PB15 |
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57 |
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PD10 |
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56 |
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PB14 |
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56 |
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PD9 |
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55 |
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VDD12OTGHS |
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55 |
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PD8 |
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54 |
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VDDPHYHS |
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54 |
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PB15 |
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53 |
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OTG_HS_REXT |
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53 |
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PB14 |
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52 |
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PB13 |
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52 |
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PB13 |
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51 |
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PB12 |
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51 |
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PB12 |
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50 |
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50 |
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<![if ! IE]> <![endif]>VDD |
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<![if ! IE]> <![endif]>VDD |
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Not compatible pins |
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MSv63473V1 |
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||||||||||||||||
|
Figure 4. Compatible board design for LQFP144 package |
|||||||||||||||||||||||||||
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93 |
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93 |
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PG8 |
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PG8 |
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92 |
|
PG5 |
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92 |
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PG7 |
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91 |
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PG4 |
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91 |
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PG6 |
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90 |
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PG3 |
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90 |
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PG5 |
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89 |
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PG2 |
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89 |
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PG4 |
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88 |
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PD15 |
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88 |
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PG3 |
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87 |
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PD14 |
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87 |
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PG2 |
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86 |
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VDD |
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86 |
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PD15 |
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85 |
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VSS |
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85 |
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PD14 |
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84 |
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PD13 |
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84 |
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VDD |
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83 |
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PD12 |
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83 |
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VSS |
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82 |
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PD11 |
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82 |
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PD13 |
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81 |
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PD10 |
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81 |
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PD12 |
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80 |
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PD9 |
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|||||||||
STM32F722xx |
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80 |
|
PD11 |
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STM32F723xx |
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79 |
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PD8 |
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79 |
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PD10 |
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78 |
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PB15 |
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78 |
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PD9 |
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77 |
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PB14 |
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||||||
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77 |
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PD8 |
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76 |
|
VDD12OTGHS |
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76 |
|
PB15 |
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75 |
|
OTG_HS_REXT |
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||||||||||||
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75 |
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PB14 |
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74 |
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PB13 |
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||||||||
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74 |
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PB13 |
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73 |
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PB12 |
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73 |
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PB12 |
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72 |
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72 |
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<![if ! IE]> <![endif]>VDD |
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<![if ! IE]> <![endif]>VDD |
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PG6, PG7 removed on the STM32F723xx |
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Not compatible pins
MSv41098V1
DS11853 Rev 7 |
19/230 |
Description |
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STM32F722xx STM32F723xx |
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Figure 5. Compatible board design for LQFP176 package |
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112 |
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PG8 |
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112 |
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PG8 |
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111 |
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PG7 |
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111 |
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PG5 |
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110 |
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PG6 |
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110 |
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PG4 |
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109 |
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PG5 |
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109 |
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PG3 |
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108 |
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PG4 |
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108 |
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PG2 |
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107 |
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PG3 |
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107 |
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PD15 |
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106 |
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PG2 |
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106 |
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PD14 |
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105 |
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PD15 |
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105 |
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VDD |
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104 |
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PD14 |
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104 |
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VSS |
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103 |
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VDD |
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103 |
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PD13 |
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102 |
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VSS |
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102 |
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PD12 |
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101 |
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PD13 |
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101 |
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PD11 |
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100 |
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PD12 |
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100 |
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PD10 |
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99 |
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PD11 |
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99 |
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PD9 |
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98 |
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PD10 |
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98 |
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PD8 |
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97 |
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PD9 |
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97 |
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PB15 |
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STM32F722xx |
96 |
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PD8 |
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96 |
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PB14 |
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STM32F723xx |
95 |
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95 |
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PB15 |
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VDD12OTGHS |
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94 |
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PB14 |
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94 |
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OTG_HS_REXT |
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93 |
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93 |
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PB13 |
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PB13 |
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92 |
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PB12 |
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92 |
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PB12 |
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91 |
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VDD |
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91 |
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VDD |
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90 |
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VSS |
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90 |
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VSS |
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89 |
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PH12 |
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89 |
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PH12 |
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88 |
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88 |
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<![if ! IE]> <![endif]>PH11 |
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<![if ! IE]> <![endif]>PH11 |
PG6, PG7 removed on the STM32F723xx |
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Not compatible pins |
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MSv41099V1 |
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Figure 6 shows the general block diagram of the device family.
20/230 |
DS11853 Rev 7 |
STM32F722xx STM32F723xx |
Description |
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JTRST, JTDI, |
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JTAG & SW |
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MPU FPU |
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JTCK/SWCLK |
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ETM |
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NVIC |
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JTDO/SWD, JTDO |
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DTCM |
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TRACECK |
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Arm CPU |
ICTM |
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TRACED[3:0] |
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Cortex-M7 |
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8KB |
AXIM |
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<![if ! IE]> <![endif]>AHB2AXI |
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I-Cache |
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216MHz |
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D-Cache |
AHBP |
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8KB |
AHBS |
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(2) |
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LDO |
PLL1 |
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USB HS |
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PHY |
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BGR |
PLL2 |
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<![if ! IE]> <![endif]>PHY |
DP, DM |
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ULPI:CK, D[7:0], DIR, STP, NXT |
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<![if ! IE]> <![endif]>FS |
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SCL/SDA, INT, ID, VBUS |
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PA[15:0] |
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PB[15:0] |
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PC[15:0] |
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PD[15:0] |
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PE[15:0] |
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PF[15:0] |
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PG[15:0] |
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PH[15:0] |
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PI[11:0] |
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USB OTG HS |
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DMA/ |
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PLL |
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LDO |
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FIFO |
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GP-DMA2 |
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8 Streams |
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FIFO |
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GP-DMA1 |
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8 Streams |
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FIFO |
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GPIO PORT A
GPIO PORT B
GPIO PORT C
GPIO PORT D
GPIO PORT E
GPIO PORT F
GPIO PORT G
GPIO PORT H
GPIO PORT I
168 AF |
EXT IT. WKUP |
<![endif]>AHB BUS-MATRIX 11S8M
DTCM RAM 64KB
ITCM RAM 16KB
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FLASH 512KB |
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RNG |
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<![if ! IE]> <![endif]>FIFO |
USB |
<![if ! IE]> <![endif]>PHY |
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DP |
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DM |
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OTG FS |
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SCL, SDA, INT, ID, VBUS |
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CLK, NE [3:0], A[23:0], |
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AHB2 216 MHz |
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D[31:0], NOEN, NWEN, |
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EXT MEM CTL (FMC) |
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NBL[3:0], SDCLKE[1:0] |
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SDNE[1:0], SDNWE, NL |
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SRAM, SDRAM, NOR-Flash, |
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NRAS, NCAS, NADV |
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NAND-Flash, SDRAM |
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NWAIT, INTN |
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Quad-SPI |
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@VDDA |
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AHB1 216 MHz |
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POR |
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SUPPLY |
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reset |
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SUPERVISION |
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Int |
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POR/PDR |
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BOR |
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@VDDA |
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PVD |
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RC HS |
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VDD12 |
@VDD33 |
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RC LS |
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BBgen + POWER MNGT |
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PLL1+PLL2+PLL3 |
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<![if ! IE]> <![endif]>PWRCTRL |
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VOLT. REG |
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3.3V TO 1.2V |
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@VDD33 |
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XTAL OSC |
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4- 16MHz |
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& controlGT |
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WDG32K |
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Standby |
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interface |
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<![if ! IE]> <![endif]>FCLK HCLK APBP2CLK APBP1CLK AHB2PCLK AHB1PCLK |
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@VSW |
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<![if ! IE]> <![endif]>LS |
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RTC |
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XTAL 32 kHz |
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AWU |
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<![if ! IE]> <![endif]>LS |
|
Backup register |
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||||||||
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CRC |
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4 KB BKPRAM |
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CLK, CS,D[7:0]
VDDA, VSSA
NRESET
WKUP[4:0]
(3)
VDDPHYHS = 3.0 to 3.6V VDDMMC33 = 3.0 to 3.6V VDDUSB33 = 3.0 to 3.6 V VDD = 1.8 to 3.6 V
VSS
VCAP1
OSC_IN
OSC_OUT
VBAT = 1.8 to 3.6 V
OSC32_IN
OSC32_OUT
RTC_TS
RTC_TAMPx
RTC_OUT
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D[7:0] |
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SDMMC1 |
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CMD, CK as AF |
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D[7:0] |
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SDMMC2 |
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CMD, CK as AF |
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4 compl. chan. (TIM1_CH1[1:4]N), |
TIM1 / PWM |
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4 chan. (TIM1_CH1[1:4]ETR, BKIN as AF |
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4 compl. chan.(TIM8_CH1[1:4]N), |
TIM8 / PWM |
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4 chan. (TIM8_CH1[1:4], ETR, BKIN as AF |
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2 channels as AF |
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TIM9 |
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1 channel as AF |
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TIM10 |
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1 channel as AF |
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TIM11 |
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RX, TX, SCK, |
smcard |
USART1 |
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CTS, RTS as AF |
irDA |
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RX, TX, SCK, |
smcard |
USART6 |
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CTS, RTS as AF |
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irDA |
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MOSI, MISO, |
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SPI1/I2S1 |
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SCK, NSS as AF |
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MOSI, MISO, |
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SPI4 |
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SCK, NSS as AF |
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MOSI, MISO, |
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SPI5 |
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SCK, NSS as AF |
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SAI1 |
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SD, SCK, FS, MCLK as AF |
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SD, SCK, FS, MCLK as AF |
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SAI2 |
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<![endif]>FIFOFIFO
16b
16b
16b
16b
16b (max) MHz108
<![if ! IE]><![endif]>FIFO FIFOAPB2
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OTG HS PHY(2) |
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ULPI:CK, D[7:0], DIR, STP, NXT |
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SCL, SDA, INT, ID, VBUS |
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CONTROLLER |
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@VDDA |
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AHB/APB2
AHB/
APB1
WWDG
LPTIM1
TIM6
TIM7
SYSCFG
GPDMA1
16b |
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<![if ! IE]> <![endif]>0MHz3 |
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<![if ! IE]> <![endif]>(max) |
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16b |
<![if ! IE]> <![endif]>APB1 |
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<![if ! IE]> <![endif]>MHz |
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16b |
<![if ! IE]> <![endif]>54 |
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<![if ! IE]> <![endif]>APB1 |
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TIM2 |
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32b |
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4 channels, ETR as AF |
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TIM3 |
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16b |
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4 channels, ETR as AF |
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TIM4 |
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16b |
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4 channels, ETR as AF |
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TIM5 |
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32b |
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4 channels |
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TIM12 |
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16b |
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2 channels as AF |
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TIM13 |
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16b |
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1 channel as AF |
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TIM14 |
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16b |
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1 channel as AF |
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USART2 |
smcard |
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RX, TX, SCK |
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irDA |
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CTS, RTS as AF |
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USART3 |
smcard |
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RX, TX, SCK |
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irDA |
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CTS, RTS as AF |
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UART4 |
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RX, TX as AF |
UART5 |
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RX, TX as AF |
UART7 |
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RX, TX as AF |
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UART8 |
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RX, TX as AF |
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SPI2/I2S2 |
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MOSI, MISO, SCK |
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NSS as AF |
SPI3/I2S3 |
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MOSI, MISO, SCK |
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NSS as AF |
I2C1/SMBUS |
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<![if ! IE]> <![endif]>filter |
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SCL, SDA, SMBAL as AF |
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<![if ! IE]> <![endif]>Digital |
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I2C2/SMBUS |
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SCL, SDA, SMBAL as AF |
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SCL, SDA, SMBAL as AF |
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I2C3/SMBUS |
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VDDREF_ADC |
U S AR T 2M Bps |
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bxCAN1 |
8 analog inputs common |
Temperature sensor |
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ADC1 |
@VDDA |
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to the 3 ADCs |
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8 analog inputs common |
ADC2 |
DAC1 |
ITF |
to the ADC1 & 2 |
IF |
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8 analog inputs for ADC3 |
ADC3 |
DAC2 |
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<![endif]>FIFO
TX, RX
DAC1 |
DAC2 |
MSv41012V4 |
as AF |
as AF |
1.The timers connected to APB2 are clocked from TIMxCLK up to 216 MHz, while the timers connected to APB1 are clocked from TIMxCLK either up to 108 MHz or 216 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register.
2.Available only on the STM32F723xx devices.
3.Available only on the STM32F723xx LQFP100 package.
DS11853 Rev 7 |
21/230 |
Functional overview |
STM32F722xx STM32F723xx |
|
|
3.1Arm® Cortex®-M7 with FPU
The Arm® Cortex®-M7 with FPU processor is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and low interrupt latency.
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The Cortex®-M7 processor is a highly efficient high-performance featuring: |
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– Six-stage dual-issue pipeline |
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– |
Dynamic branch prediction |
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– Harvard caches (8 Kbytes of I-cache and 8 Kbytes of D-cache) |
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– |
64-bit AXI4 interface |
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– 64-bit ITCM interface |
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– 2x32-bit DTCM interfaces |
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The processor supports the following memory interfaces: |
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• Tightly Coupled Memory (TCM) interface. |
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• Harvard instruction and data caches and AXI master (AXIM) interface. |
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• Dedicated low-latency AHB-Lite peripheral (AHBP) interface. |
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The processor supports a set of DSP instructions which allow efficient signal processing and |
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complex algorithm execution. |
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It supports single precision FPU (floating point unit), speeds up software development by |
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using metalanguage development tools, while avoiding saturation. |
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Figure 6 shows the general block diagram of the STM32F722xx and STM32F723xx family. |
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Note: |
Cortex®-M7 with FPU core is binary compatible with the Cortex®-M4 core. |
The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
22/230 |
DS11853 Rev 7 |
STM32F722xx STM32F723xx |
Functional overview |
|
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The STM32F722xx and STM32F723xx devices embed a Flash memory of up to 512 Kbytes available for storing programs and data.
The flexible protections can be configured thanks to option bytes:
•Readout protection (RDP) to protect the whole memory. Three levels are available:
–Level 0: no readout protection
–Level 1: No access (read, erase, program) to the Flash memory or backup SRAM can be performed while the debug feature is connected or while booting from RAM or system memory bootloader
–Level 2: debug/chip read protection disabled.
•Write protection (WRP): the protected area is protected against erasing and programming.
•Proprietary code readout protection (PCROP): Flash memory user sectors (0 to 7) can be protected against D-bus read accesses by using the proprietary readout protection (PCROP). The protected area is execute-only.
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
All the devices feature:
•System SRAM up to 256 Kbytes:
–SRAM1 on AHB bus Matrix: 176 Kbytes
–SRAM2 on AHB bus Matrix: 16 Kbytes
–DTCM-RAM on TCM interface (Tighly Coupled Memory interface): 64 Kbytes for critical real-time data.
•Instruction RAM (ITCM-RAM) 16 Kbytes:
–It is mapped on TCM interface and reserved only for CPU Execution/Instruction useful for critical real-time routines.
The Data TCM RAM is accessible by the GP-DMAs and peripheral DMAs through the specific AHB slave of the CPU.The instruction TCM RAM is reserved only for CPU. It is accessed at CPU clock speed with 0 wait states.
•4 Kbytes of backup SRAM
This area is accessible only from the CPU. Its content is protected against possible unwanted write accesses, and is retained in Standby or VBAT mode.
DS11853 Rev 7 |
23/230 |
Functional overview |
STM32F722xx STM32F723xx |
|
|
3.6AXI-AHB bus matrix
The STM32F722xx and STM32F723xx system architecture is based on 2 sub-systems:
•An AXI to multi AHB bridge converting AXI4 protocol to AHB-Lite protocol:
–3x AXI to 32-bit AHB bridges connected to AHB bus matrix
–1x AXI to 64-bit AHB bridge connected to the embedded Flash memory
•A multi-AHB Bus-Matrix
–The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, USB HS) and the slaves (Flash memory, RAM, FMC, Quad-SPI, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously.
<![if ! IE]> <![endif]>DTCM |
<![if ! IE]> <![endif]>ITCM |
<![if ! IE]> <![endif]>AHBS |
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GP |
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Arm Cortex-M7 |
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GP |
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USB OTG |
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DMA1 |
DMA2 |
HS |
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<![if ! IE]> <![endif]>AXIM |
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<![if ! IE]> <![endif]>AHBP |
<![if ! IE]> <![endif]>DMA PI |
<![if ! IE]> <![endif]>DMAMEM1 |
<![if ! IE]> <![endif]>DMAMEM2 |
<![if ! IE]> <![endif]>DMA P2 |
<![if ! IE]> <![endif]>USBHS M |
DTCM RAM |
8KB |
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I/D Cache |
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64KB |
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ITCM RAM |
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16KB |
AXI to |
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multi-AHB |
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ITCM |
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<![if ! IE]> <![endif]>ART |
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FLASH |
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64-bit AHB |
512KB |
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64-bit BuS Matrix |
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SRAM1 |
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176KB |
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SRAM2 |
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16KB |
AHB
Periph1 APB1
AHB |
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periph2 |
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FMC external |
APB2 |
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MemCtl |
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Quad-SPI |
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32-bit Bus Matrix - S |
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MSv41005V1 |
1. The above figure has large wires for 64-bits bus and thin wires for 32-bits bus.
24/230 |
DS11853 Rev 7 |
STM32F722xx STM32F723xx |
Functional overview |
|
|
The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB).
The two DMA controllers support a circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code.
Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. The configuration is made by software and transfer sizes between source and destination are independent.
The DMA can be used with the main peripherals:
•SPI and I2S
•I2C
•USART
•General-purpose, basic and advanced-control timers TIMx
•DAC
•SDMMC
•ADC
•SAI
•Quad-SPI
DS11853 Rev 7 |
25/230 |
Functional overview |
STM32F722xx STM32F723xx |
|
|
The Flexible memory controller (FMC) includes three memory controllers:
•The NOR/PSRAM memory controller
•The NAND/memory controller
•The Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller The main features of the FMC controller are the following:
•Interface with static-memory mapped devices including:
–Static random access memory (SRAM)
–NOR Flash memory/OneNAND Flash memory
–PSRAM (4 memory banks)
–NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
•Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
•8-, 16-, 32-bit data bus width
•Independent Chip Select control for each memory bank
•Independent configuration for each memory bank
•Write FIFO
•Read FIFO for SDRAM controller
•The maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is HCLK/2
LCD parallel interface
The FMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration.
3.9Quad-SPI memory interface (QUADSPI)
All the devices embed a Quad-SPI memory interface, which is a specialized communication interface targetting Single, Dual or Quad-SPI Flash memories. It can work in:
•Direct mode through registers
•External Flash status register polling mode
•Memory mapped mode.
Up to 256 Mbytes of external Flash are memory mapped, supporting 8, 16 and 32-bit access. The code execution is supported.
The opcode and the frame format are fully programmable. The communication can be either in Single Data Rate or Dual Data Rate.
26/230 |
DS11853 Rev 7 |
STM32F722xx STM32F723xx |
Functional overview |
|
|
The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 110 maskable interrupt channels plus the 16 interrupt lines of the Cortex®- M7 with FPU core.
•Closely coupled NVIC gives low-latency interrupt processing
•Interrupt entry vector table address passed directly to the core
•Allows early processing of interrupts
•Processing of late arriving, higher-priority interrupts
•Support tail chaining
•Processor state automatically saved
•Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with a minimum interrupt latency.
The external interrupt/event controller consists of 24 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 140 GPIOs in the STM32F722xx devices (138 GPIOs in the STM32F723xx devices) can be connected to the 16 external interrupt lines.
On reset the 16 MHz internal HSI RC oscillator is selected as the default CPU clock. The 16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing to increase the frequency up to 216 MHz. Similarly, a full interrupt management of the PLL clock entry is available when necessary (for example if an indirectly used external oscillator fails).
Several prescalers allow the configuration of the two AHB buses, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB buses is 216 MHz while the maximum frequency of the high-speed APB domains is
108 MHz. The maximum allowed frequency of the low-speed APB domain is 54 MHz.
The devices embed two dedicated PLLs (PLLI2S and PLLSAI) which allow to achieve audio class performance. In this case, the I2S and SAI master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz.
The STM32F723xx devices embed two PLLs inside the PHY HS controller: PLL1 and PLL2. The PLL1 allows to output 60 MHz used as an input for PLL2 which itself allows to generate the 480 Mbps in the USB OTG High Speed mode.
The PLL1 has as input HSE clock.
DS11853 Rev 7 |
27/230 |
Functional overview |
STM32F722xx STM32F723xx |
|
|
At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF which includes:
•All Flash address space mapped on ITCM or AXIM interface
•All RAM address space: ITCM, DTCM RAMs and SRAMs mapped on AXIM interface
•The System memory bootloader
The boot loader is located in system memory. It is used to reprogram the Flash memory through a serial interface.
•VDD = 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when enabled), provided externally through VDD pins.
•VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
•VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present.
Note: |
The VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to |
|
Section 3.15.2: Internal reset OFF). Refer to Table 3: Voltage regulator configuration mode |
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versus device operating mode to identify the packages supporting this option. |
|
• The VDDSDMMC can be connected either to VDD or an external independent power |
|
supply (1.8 to 3.6V) for the SDMMC2 pins (clock, command, and 4-bit data). For |
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example, when the device is powered at 1.8V, an independent power supply 2.7V can |
|
be connected to VDDSDMMC.When the VDDSDMMC is connected to a separated power |
|
supply, it is independent from VDD or VDDA but it must be the last supply to be provided |
|
and the first to disappear. The following conditions VDDSDMMC must be respected: |
|
– During the power-on phase (VDD < VDD_MIN), VDDSDMMC should be always lower |
|
than VDD |
|
– During the power-down phase (VDD < VDD_MIN), VDDSDMMC should be always |
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lower than VDD |
|
– The VDDSDMMC rising and falling time rate specifications must be respected |
|
– In the operating mode phase, VDDSDMMC could be lower or higher than VDD: |
|
All associated GPIOs powered by VDDSDMMC are operating between |
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VDDSDMMC_MIN and VDDSDMMC_MAX. |
|
• The VDDUSB can be connected either to VDD or an external independent power supply |
|
(3.0 to 3.6V) for USB transceivers (refer to Figure 8 and Figure 9). For example, when |
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the device is powered at 1.8V, an independent power supply 3.3V can be connected to |
|
the VDDUSB. When the VDDUSB is connected to a separated power supply, it is |
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independent from VDD or VDDA but it must be the last supply to be provided and the first |
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to disappear. The following conditions VDDUSB must be respected: |
|
– During the power-on phase (VDD < VDD_MIN), VDDUSB should be always lower |
|
than VDD |
|
– During the power-down phase (VDD < VDD_MIN), VDDUSB should be always lower |
|
than VDD |
28/230 |
DS11853 Rev 7 |
STM32F722xx STM32F723xx |
Functional overview |
|
|
–The VDDUSB rising and falling time rate specifications must be respected
–In the operating mode phase, VDDUSB could be lower or higher than VDD:
-If the USB (USB OTG_HS/OTG_FS) is used, the associated GPIOs powered by VDDUSB are operating between VDDUSB_MIN and VDDUSB_MAX.
-The VDDUSB supplies both USB transceiver (USB OTG_HS and USB OTG_FS). If only one USB transceiver is used in the application, the GPIOs associated to the
other USB transceiver are still supplied by VDDUSB.
- If the USB (USB OTG_HS/OTG_FS) is not used, the associated GPIOs powered by VDDUSB are operating between VDD_MIN and VDD_MAX.
VDD |
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VDD_MAX |
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VDD= VDDA = VDDUSB |
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VDD_MIN |
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Power-on |
Operating mode |
Power-down |
time |
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MS37591V1 |
VDDUSB_MAX |
USB functional area |
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VDDUSB |
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VDDUSB_MIN |
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USB non |
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non |
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functional |
VDD = VDDA |
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area |
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VDD_MIN |
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Power-on |
Operating mode |
Power-down |
time |
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MS37590V1 |
|
DS11853 Rev 7 |
|
29/230 |
Functional overview |
STM32F722xx STM32F723xx |
|
|
On the STM32F7x3xx devices, the USB OTG HS sub-system uses one or two additional power supply pins depending on the package:
•The VDD12OTGHS pin is the output of PHY HS regulator (1.2V). An external capacitor of 2.2 µF must be connected on the VDD12OTGHS pin.
•On the LQFP100 only, a second power pin VDDPHYHS is used to supply the USB OTG PHY HS and associated GPIOs.The VDDPHYHS follows the same rules provided for the VDDUSB power pin.
On packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high. On the other packages, the power supply supervisor is always enabled.
The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is reached, the option byte loading process starts, either to confirm or modify default BOR thresholds, or to disable BOR permanently. Three BOR thresholds are available through option bytes. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for an external reset circuit.
The device also features an embedded programmable voltage detector (PVD) that monitors
the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is
higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
This feature is available only on packages featuring the PDR_ON pin. The internal power-on reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin.
An external power supply supervisor should monitor VDD and NRST and should maintain the device in reset mode as long as VDD is below a specified threshold. PDR_ON should be connected to VSS. Refer to Figure 10: Power supply supervisor interconnection with internal reset OFF.
30/230 |
DS11853 Rev 7 |