STMicroelectronics STM32F479AI, STM32F479AG, STM32F479BI, STM32F479BG, STM32F479II Datasheet

STM32F479xx

Arm®Cortex®-M4 32b MCU+FPU, 225DMIPS, up to 2MB Flash/384+4KB RAM, USB OTG HS/FS, Ethernet, FMC, dual Quad-SPI, Crypto, Graphical accelerator, Camera IF, LCD-TFT & MIPI DSI

Datasheet - production data

Features

Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 180 MHz, MPU, 225 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions

Memories

–Up to 2 MB of Flash memory organized into two banks allowing read-while-write

–Up to 384+4 KB of SRAM including 64 KB of CCM (core coupled memory) data RAM

–Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR, SDRAM, Flash NOR/NAND memories

–Dual-flash mode Quad-SPI interface

Graphics:

–Chrom-ART Accelerator™ (DMA2D), graphical hardware accelerator enabling enhanced graphical user interface with minimum CPU load

–LCD parallel interface, 8080/6800 modes

–LCD TFT controller supporting up to XGA resolution

–MIPI® DSI host controller supporting up to 720p 30Hz resolution

Clock, reset and supply management

–1.7 V to 3.6 V application supply and I/Os

–POR, PDR, PVD and BOR

–4-to-26 MHz crystal oscillator

–Internal 16 MHz factory-trimmed RC (1% accuracy)

–32 kHz oscillator for RTC with calibration

–Internal 32 kHz RC with calibration

Low power

–Sleep, Stop and Standby modes

–VBAT supply for RTC, 20×32 bit backup registers + optional 4 KB backup SRAM

3×12-bit, 2.4 MSPS ADC: up to 24 channels and 7.2 MSPS in triple interleaved mode

2×12-bit D/A converters

General-purpose DMA: 16-stream DMA controller with FIFOs and burst support

Up to 17 timers: up to twelve 16-bit and two 32bit timers up to 180 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input. 2x watchdogs and SysTick timer

	LQFP100 (14 × 14 mm)
							UFBGA169 (7 × 7 mm)
	LQFP144 (20 × 20 mm)
		WLCSP168					UFBGA176 (10 x 10 mm)
	LQFP176 (24 × 24 mm)
							TFBGA216 (13 x 13 mm)
	LQFP208 (28 × 28 mm)

Debug mode

–SWD & JTAG interfaces

–Cortex®-M4 Trace Macrocell™

Up to 161 I/O ports with interrupt capability

–Up to 157 fast I/Os up to 90 MHz

–Up to 159 5 V-tolerant I/Os

Up to 21 communication interfaces

–Up to 3 × I2C interfaces (SMBus/PMBus)

–Up to 4 USARTs and 4 UARTs (11.25 Mbit/s, ISO7816 interface, LIN, IrDA, modem control)

–Up to 6 SPIs (45 Mbits/s), 2 with muxed fullduplex I2S for audio class accuracy via internal audio PLL or external clock

–1 x SAI (serial audio interface)

–2 × CAN (2.0B Active)

–SDIO interface

Advanced connectivity

–USB 2.0 full-speed device/host/OTG controller with on-chip PHY

–USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI

–Dedicated USB power rail enabling on-chip PHYs operation throughout the entire MCU power supply range

–10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII

8- to 14-bit parallel camera interface up to 54 Mbytes/s

Cryptographic accelerator

–HW accelerator for AES 128, 192, 256, Triple DES, HASH (MD5, SHA-1, SHA-2) and HMAC

True random number generator

CRC calculation unit

RTC: subsecond accuracy, hardware calendar

96-bit unique ID

Table 1. Device summary

	Reference	Part numbers
		STM32F479AI, STM32F479AG, STM32F479BI,
	STM32F479xx	STM32F479BG, STM32F479II, STM32F479IG,
		STM32F479NI, STM32F479NG, STM32479VG,
		STM32479VI, STM32479ZG, STM32479ZI

January 2021

DS11118 Rev 6

1/220

This is information on a product in full production.

www.st.com

Contents	STM32F479xx

Contents

1	Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		12
	1.1	Compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15

1.1.1 LQFP176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.1.2 LQFP208 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.1.3 UFBGA176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.1.4 TFBGA216 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2	Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			21
	2.1	Arm® Cortex®-M4 with FPU and embedded Flash and SRAM . . . . . . . .		21
	2.2	Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . .		21
	2.3	Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		21
	2.4	Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		22
	2.5	CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . .		22
	2.6	Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		22
	2.7	Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		22
	2.8	DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		23
	2.9	Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		24
	2.10	Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . .		25
	2.11	LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		25
	2.12	DSI Host (DSIHOST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		25
	2.13	Chrom-ART Accelerator™ (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . .		27
	2.14	Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . .		27
	2.15	External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . .		27
	2.16	Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		28
	2.17	Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		28
	2.18	Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		28
	2.19	Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		30
		2.19.1	Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	30
		2.19.2	Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	30
	2.20	Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		31

2.20.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.20.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2/220

DS11118 Rev 6

STM32F479xx	Contents

2.20.3 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 35

2.21 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 35 2.22 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2.23 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.24 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2.24.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . .		38
2.24.2	General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	39
2.24.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		39
2.24.4	Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	39
2.24.5	Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	39
2.24.6	SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	40

2.25 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

2.26Universal synchronous/asynchronous receiver transmitters (USART) . . 40

2.27 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.28 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.29 Serial Audio interface (SAI1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.30 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.31 Audio and LCD PLL(PLLSAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.32 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . . . 42 2.33 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . . . 43 2.34 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.35 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 44 2.36 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 44 2.37 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.38 Cryptographic accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.39 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.40 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.41 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.42 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.43 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.44 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.45 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3

Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

48

DS11118 Rev 6

3/220

Contents STM32F479xx

4	Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			84
5	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			89
	5.1	Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		89
		5.1.1	Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	89
		5.1.2	Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	89
		5.1.3	Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	89
		5.1.4	Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	89
		5.1.5	Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	89
		5.1.6	Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	90
		5.1.7	Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . .	91

5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 5.3.2 VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . . 96

5.3.4Operating conditions at power-up / power-down (regulator OFF) . . . . . 96

5.3.5	Reset and power control block characteristics . . . . . . . . . . . . . . . . . .	. 96
5.3.6	Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .	. 98
5.3.7	Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	98
5.3.8	Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . .	114
5.3.9	External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .	115
5.3.10	Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .	119
5.3.11	PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	120

5.3.12PLL spread spectrum clock generation (SSCG) characteristics . . . . . 123

5.3.13 MIPI D-PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 5.3.14 MIPI D-PHY PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 5.3.15 MIPI D-PHY regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 128 5.3.16 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 5.3.17 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 5.3.18 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 132 5.3.19 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 5.3.20 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 5.3.21 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 5.3.22 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 5.3.23 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 5.3.24 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

4/220

DS11118 Rev 6

STM32F479xx	Contents

5.3.25 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

5.3.26 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 5.3.27 Reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

5.3.28 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 5.3.29 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 5.3.30 Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 5.3.31 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 186 5.3.32 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 187 5.3.33 SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 189 5.3.34 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

6	Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		192
	6.1	LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	192
	6.2	LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	195
	6.3	WLCSP168 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	198
	6.4	UFBGA169 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	200
	6.5	LQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	203
	6.6	UFBGA(176+25) package information . . . . . . . . . . . . . . . . . . . . . . . . . .	207
	6.7	LQFP208 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	208
	6.8	TFBGA216 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	212
	6.9	Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	215
7	Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		216
Appendix A Recommendations when using internal reset OFF . . . . . . . . . . .			217
	A.1	Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	217

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

DS11118 Rev 6

5/220

List of tables	STM32F479xx

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. STM32F479xx features and peripheral counts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 3. Voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 32 Table 4. Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 5. Voltage regulator modes in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 6. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 7. Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 8. USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 9. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 10. STM32F479xx pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 11. FMC pin definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 12. Alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 13. STM32F479xx register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 14. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 15. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table 16. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table 17. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 18. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 95 Table 19. VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 20. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 96 Table 21. Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 96 Table 22. Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Table 23. Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 24. Typical and maximum current consumption in Run mode, code with data processing

running from Flash memory (ART accelerator enabled except prefetch) or RAM,

regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table 25. Typical and maximum current consumption in Run mode, code with data processing

running from Flash memory (ART accelerator disabled), regulator ON . . . . . . . . . . . . . . 101 Table 26. Typical and maximum current consumption in Run mode, code with data

processing running from Flash memory (ART accelerator enabled except prefetch), regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 27. Typical and maximum current consumption in Sleep mode, regulator ON. . . . . . . . . . . . 103 Table 28. Typical and maximum current consumption in Sleep mode, regulator OFF. . . . . . . . . . . 104 Table 29. Typical and maximum current consumption in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 30. Typical and maximum current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . 106

Table 31. Typical and maximum current consumption in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . . 107 Table 32. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 33. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Table 34. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 35. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 36. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 37. HSE 4-26 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 38. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Table 39. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Table 40. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Table 41. Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Table 42. PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 43. PLLSAI (audio and LCD-TFT PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

6/220

DS11118 Rev 6

STM32F479xx	List of tables

Table 44. SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Table 45. MIPI D-PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Table 46. MIPI D-PHY AC characteristics LP mode and HS/LP transitions . . . . . . . . . . . . . . . . . . . 126 Table 47. DSI-PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Table 48. DSI regulator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Table 49. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Table 50. Flash memory programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 51. Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Table 52. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Table 53. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Table 54. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Table 55. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Table 56. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Table 57. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Table 58. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Table 59. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Table 60. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Table 61. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Table 62. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Table 63. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Table 64. SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Table 65. I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Table 66. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Table 67. USB OTG full speed startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Table 68. USB OTG full speed DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Table 69. USB OTG full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Table 70. USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Table 71. USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Table 72. Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Table 73. Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 154 Table 74. Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 155 Table 75. Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 155 Table 76. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Table 77. ADC static accuracy at fADC = 18 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Table 78. ADC static accuracy at fADC = 30 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Table 79. ADC static accuracy at fADC = 36 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Table 80. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 159 Table 81. ADC dynamic accuracy at fADC = 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 159 Table 82. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Table 83. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Table 84. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Table 85. internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Table 86. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Table 87. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Table 88. Asynchronous non-multiplexed SRAM/PSRAM/NOR - read timings . . . . . . . . . . . . . . . . 167 Table 89. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings . . . . . . . . . . 167 Table 90. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 168 Table 91. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings. . . . . . . . . . 169 Table 92. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Table 93. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 170 Table 94. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Table 95. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 172

DS11118 Rev 6

7/220

List of tables	STM32F479xx

Table 96. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Table 97. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Table 98. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 177 Table 99. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Table 100. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Table 101. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Table 102. SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Table 103. LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Table 104. SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Table 105. LPSDR SDRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Table 106. Quad-SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Table 107. Quad-SPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Table 108. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Table 109. LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Table 110. Dynamic characteristics: SD / MMC characteristics, VDD = 2.7 to 3.6 V . . . . . . . . . . . . . 190 Table 111. Dynamic characteristics: SD / MMC characteristics, VDD = 1.71 to 1.9 V . . . . . . . . . . . . 191 Table 112. RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Table 113. LQFP100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Table 114. LQFP144 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Table 115. WLCSP168 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Table 116. UFBGA169 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Table 117. UFBGA169 - Recommended PCB design rules (0.5 mm pitch BGA). . . . . . . . . . . . . . . . 201 Table 118. LQFP176 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Table 119. UFBGA(176+25) - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Table 120. UFBGA(176+25) - Recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . 208 Table 121. LQFP208 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Table 122. TFBGA216 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Table 123. TFBGA216 - Recommended PCB design rules (0.8 mm pitch) . . . . . . . . . . . . . . . . . . . . 213 Table 124. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Table 125. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Table 126. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 217 Table 127. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

8/220

DS11118 Rev 6

STM32F479xx	List of figures

List of figures

Figure 1.	Incompatible board design for LQFP176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 16
Figure 2.	Incompatible board design for LQFP208 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 17
Figure 3.	UFBGA176 port-to-terminal assignment differences . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 18
Figure 4.	TFBGA216 port-to-terminal assignment differences. . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 19
Figure 5. STM32F479xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 20
Figure 6. STM32F479xx Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 23
Figure 7.	VDDUSB connected to an external independent power supply . . . . . . . . . . . . . . . . . . . .	. 29
Figure 8.	Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . .	30
Figure 9.	PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	31
Figure 10.	Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	33
Figure 11.	Startup in regulator OFF: slow VDD slope
	- power-down reset risen after VCAP_1 , VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . .	34
Figure 12.	Startup in regulator OFF mode: fast VDD slope
	- power-down reset risen before VCAP_1 , VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . .	35
Figure 13. STM32F47x LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		48
Figure 14. STM32F47x LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		49
Figure 15. STM32F47x WLCSP168 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		50
Figure 16.	STM32F47x UFBGA169 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	51
Figure 17.	STM32F47x UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	52
Figure 18. STM32F47x LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		53
Figure 19. STM32F47x LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		54
Figure 20. STM32F47x TFBGA216 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		55
Figure 21.	Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	84
Figure 22. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		89
Figure 23. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		89
Figure 24. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		90
Figure 25.	Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	91
Figure 26.	External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	95
Figure 27.	Typical VBAT current consumption
	(RTC ON / backup SRAM ON and LSE in Low drive mode) . . . . . . . . . . . . . . . . . . . . . .	107
Figure 28.	Typical VBAT current consumption
	(RTC ON / backup SRAM ON and LSE in High drive mode) . . . . . . . . . . . . . . . . . . . . . .	108
Figure 29.	High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .	116
Figure 30.	Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . .	116
Figure 31.	Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	117
Figure 32.	Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	118
Figure 33. ACCHSI vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		119
Figure 34.	ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	120
Figure 35.	PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .	124
Figure 36.	PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	124
Figure 37.	MIPI D-PHY HS/LP clock lane transition timing diagram . . . . . . . . . . . . . . . . . . . . . . . . .	127
Figure 38.	MIPI D-PHY HS/LP data lane transition timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . .	127
Figure 39.	FT I/O input characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	136
Figure 40.	I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	139
Figure 41.	Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	140
Figure 42.	SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	144
Figure 43.	SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	144
Figure 44.	SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	145

DS11118 Rev 6

9/220

List of figures	STM32F479xx

Figure 45. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Figure 46. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Figure 47. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Figure 48. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Figure 49. USB OTG full speed timings: definition of data signal rise and fall time. . . . . . . . . . . . . . 151 Figure 50. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Figure 51. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Figure 52. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Figure 53. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Figure 54. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Figure 55. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Figure 56. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 161 Figure 57. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 161 Figure 58. 12-bit buffered/non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Figure 59. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 166 Figure 60. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 168 Figure 61. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 169 Figure 62. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 171 Figure 63. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Figure 64. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Figure 65. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 177 Figure 66. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Figure 67. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Figure 68. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Figure 69. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 180 Figure 70. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 181 Figure 71. SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Figure 72. SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Figure 73. Quad-SPI SDR timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Figure 74. Quad-SPI DDR timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Figure 75. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Figure 76. LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Figure 77. LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Figure 78. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Figure 79. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Figure 80. LQFP100 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Figure 81. LQFP100 - Recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Figure 82. LQFP100 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Figure 83. LQFP144 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Figure 84. LQFP144 - Recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Figure 85. LQFP144 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Figure 86. WLCSP168 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Figure 87. UFBGA169 - Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Figure 88. UFBGA169 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Figure 89. UFBGA169 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Figure 90. LQFP176 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Figure 91. LQFP176 - Recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Figure 92. LQFP176 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Figure 93. UFBGA(176+25) - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Figure 94. UFBGA(176+25) - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Figure 95. LQFP208 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Figure 96. LQFP208 - Recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

10/220

DS11118 Rev 6

STM32F479xx	List of figures

Figure 97. LQFP208 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Figure 98. TFBGA216 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Figure 99. TFBGA216 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Figure 100. TFBGA216 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

DS11118 Rev 6

11/220

Description	STM32F479xx

1 Description

The STM32F479xx devices are based on the high-performance Arm®(a) Cortex®-M4 32-bit RISC core operating at a frequency of up to 180 MHz. The Cortex®-M4 core features a Floating point unit (FPU) single precision which supports all Arm® single-precision dataprocessing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security.

The STM32F479xx devices incorporate high-speed embedded memories (Flash memory up to 2 Mbytes, up to 384 Kbytes of SRAM), up to 4 Kbytes of backup SRAM, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.

All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose 16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers, a true random number generator (RNG), and a cryptographic acceleration cell. They also feature standard and advanced communication interfaces:

Up to three I2Cs

Six SPIs, two I2Ss full duplex. To achieve audio class accuracy, the I2S peripherals can be clocked via a dedicated internal audio PLL or via an external clock to allow synchronization.

Four USARTs plus four UARTs

An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the ULPI)

Two CANs

One SAI serial audio interface

An SDMMC host interface

Ethernet and camera interface

LCD-TFT display controller

Chrom-ART Accelerator™

DSI Host.

Advanced peripherals include an SDMMC interface, a flexible memory control (FMC) interface, a Quad-SPI Flash memory, camera interface for CMOS sensors and a cryptographic acceleration cell. Refer to Table 2 for the list of peripherals available on each part number.

The STM32F479xx devices operate in the –40 to +105 °C temperature range from a 1.7 to 3.6 V power supply. A dedicated supply input for USB (OTG_FS and OTG_HS) only in full speed mode, is available on all packages.

The supply voltage can drop to 1.7 V (refer to Section 2.19.2). A comprehensive set of power-saving mode allows the design of low-power applications.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

12/220

DS11118 Rev 6

STM32F479xx	Description

The STM32F479xx devices are offered in eight packages, ranging from 100 to 216 pins. The set of included peripherals changes with the device chosen, according to Table 2.

These features make the STM32F479xx microcontrollers suitable for a wide range of applications:

Motor drive and application control

Medical equipment

Industrial applications: PLC, inverters, circuit breakers

Printers, and scanners

Alarm systems, video intercom, and HVAC

Home audio appliances

Figure 5 shows the general block diagram of the device family.

Table 2. STM32F479xx features and peripheral counts

Peripherals

<![if ! IE]> <![endif]>STM32F479Vx

<![if ! IE]> <![endif]>STM32F479Zx

<![if ! IE]> <![endif]>STM32F479Ax

<![if ! IE]> <![endif]>STM32F479Ix

<![if ! IE]> <![endif]>STM32F479Bx

<![if ! IE]> <![endif]>STM32F479Nx

Flash memory in Kbytes

1024

2048

1024

2048

1024

2048

1024

2048

1024

2048

1024

2048

SRAM in

System

384(160+32+128+64)

Kbytes

Backup

4

FMC memory controller

Yes

Quad-SPI

Yes

Ethernet

Yes

General-

10

purpose

Timers

Advanced-

2

control

Basic

2

Random number generator

Yes

SPI / I2S

4/2(full duplex)(1)

6/2(full duplex)(1)

I2C

3

USART/UART

4/3

4/4

Communication

USB OTG FS

Yes

interfaces

USB OTG HS

Yes

CAN

2

SAI

1

SDIO

Yes

Camera interface

Yes

DS11118 Rev 6

13/220

Description							STM32F479xx
Table 2. STM32F479xx features and peripheral counts (continued)
Peripherals	<![if ! IE]> <![endif]>STM32F479Vx	<![if ! IE]> <![endif]>STM32F479Zx	<![if ! IE]> <![endif]>STM32F479Ax		<![if ! IE]> <![endif]>STM32F479Ix		<![if ! IE]> <![endif]>STM32F479Bx	<![if ! IE]> <![endif]>STM32F479Nx
MIPI-DSI Host			Yes
LCD-TFT			Yes
Chrom-ART Accelerator™			Yes
(DMA2D)
Cryptography			Yes
GPIOs	71	131	114		131		161	161
12-bit ADC				3
Number of channels	14	20		24
12-bit DAC			Yes
Number of channels				2
Maximum CPU frequency			180 MHz
Operating voltage			1.7 to 3.6V(2)
Operating temperatures	Ambient operating temperature: −40 to 85 °C / −40 to 105 °C
		Junction temperature: −40 to 105 °C / −40 to 125 °C
Package	LQFP100	LQFP144	UFBGA169		LQFP176		LQFP208	TFBGA216
			WLCSP168		UFBGA176

1.The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode.

2.VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to Section 2.19.2).

14/220

DS11118 Rev 6

STM32F479xx	Description

1.1Compatibility throughout the family

STM32F479xx devices are not compatible with other STM32F4xx devices.

Figure 1 and Figure 2 show incompatible board designs, respectively, for LQFP176 and LQFP208 packages (highlighted pins).

The UFBGA176 and TFBGA216 ballouts are compatible with other STM32F4xx devices, only few IO port pins are substituted, as shown in Figure 3 and Figure 4.

The LQFP100, LQFP144 and UFBGA169 packages are incompatible with other STM32F4xx devices.

DS11118 Rev 6

15/220

Description	STM32F479xx

1.1.1LQFP176 package

Figure 1. Incompatible board design for LQFP176 package

									<![if ! IE]> <![endif]>VSS				<![if ! IE]> <![endif]>PI3				<![if ! IE]> <![endif]>PI1
							135 134									133						PI0
																				132
																				131		VDD
																				130		VSS
																				129		VCAP2
																				128		PA13
																				127		PA12
																				126		PA11
																				125		PA10
																				124		PA9
																				123		PA8
																				122		PC9
																				121		PC8
																				120		PC7
																				119		PC6
																				118		VDDUSB
																				117		VSS
STM32F469xx/479xx																				116		PG8
																				115		PG7
		LQFP176																		114		PG6
																				113		PG5
																				112		PG4
																				111		PG3
																				110		PG2
																				109		VSSDSI
																				108		DSIHOST_D1N
																				107		DSIHOST_D1P
																				106		VDD12DSI
																				105		DSIHOST_CKN
																				104		DSIHOST_CKP
																				103		VSSDSI
																				102		DSIHOST_D0N
																				101		DSIHOST_D0P
																				100		VCAPDSI
																				99		VDDSI
																				98		PD15
																				97		PD14
																				96		VDD
																				95		VSS
																				94		PD13
																				93		PD12
																				92		PD11
																				91		PD10
																				90		PD9
																				89		PD8
84				85			86				87					88
		<![if ! IE]> <![endif]>PH7			<![if ! IE]> <![endif]>PB12			<![if ! IE]> <![endif]>PB13				<![if ! IE]> <![endif]>PB14					<![if ! IE]> <![endif]>PB15

1. Pins from 85 to 133 are not compatible.

							<![if ! IE]> <![endif]>VSS			<![if ! IE]> <![endif]>PI3		<![if ! IE]> <![endif]>PI2
					135 134 133
												132			PI1
												131			PI0
												130			PH15
												129			PH14
												128			PH13
												127			VDD
												126			VSS
												125			VCAP2
												124			PA13
												123			PA12
												122			PA11
												121			PA10
												120			PA9
												119			PA8
												118			PC9
												117			PC8
	STM32F4xx											116			PC7
												115			PC6
	LQFP176											114			VDD
												113			VSS
												112			PG8
												111			PG7
												110			PG6
												109			PG5
												108			PG4
												107			PG3
												106			PG2
												105			PD15
												104			PD14
												103			VDD
												102			VSS
												101			PD13
												100			PD12
												99			PD11
												98			PD10
												97			PD9
												96			PD8
												95			PB15
												94			PB14
												93			PB13
												92			PB12
												91			VDD
												90			VSS
												89			PH12
84			85		86				87			88
	<![if ! IE]> <![endif]>PH7			<![if ! IE]> <![endif]>PH8		<![if ! IE]> <![endif]>PH9				<![if ! IE]> <![endif]>PH10		<![if ! IE]> <![endif]>PH11			MS38294V2

16/220

DS11118 Rev 6

STM32F479xx	Description

1.1.2LQFP208 package

Figure 2. Incompatible board design for LQFP208 package

	138		PC6		138		PC6
	137		VDDUSB		137		VDD
	136		VSS		136		VSS
	135		PG8		135		PG8
	134		PG7		134		PG7
	133		PG6		133		PG6
	132		PG5		132		PG5
STM32F469xx/479xx	131		PG4	STM32F42x/STM32F43x	131		PG4
	130		PG3		130		PG3
LQFP208	129		PG2	LQFP208	129		PG2
	128		VSSDSI		128		PK2
	127		DSIHOST_D1N		127		PK1
	126		DSIHOST_D1P		126		PK0
	125		VDD12DSI		125		VSS
	124		DSIHOST_CKN		124		VDD
	123		DSIHOST_CKP		123		PJ11
	122		VSSDSI		122		PJ10
	121		DSIHOST_D0N		121		PJ9
	120		DSIHOST_D0P		120		PJ8
	119		VCAPDSI		119		PJ7
	118		VDDDSI		118		PJ6
	117		PD15		117		PD15
	116		PD14		116		PD14

MS38295V1

1. Pins from 118 to 128 and pin 137 are not compatible

DS11118 Rev 6

17/220

Description	STM32F479xx

1.1.3UFBGA176 package

Figure 3. UFBGA176 port-to-terminal assignment differences

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

A

PE3

PE2

PE1

PE0

PB8

PB5

PG14

PG13

PB4

PB3

PD7

PC12

PA15

PA14

PA13

B

PE4

PE5

PE6

PB9

PB7

PB6

PG15

PG12

PG11

PG10

PD6

PD0

PC11

PC10

PA12

C

VBAT

PI7

PI6

PI5

VDD

PDR

VDD

VDD

VDD

PG9

PD5

PD1

PI3

PA11

_ON

D

PC13

PI8

PI9

PI4

VSS

BOOT0

VSS

VSS

VSS

PD4

PD3

PD2

PI1

PA10

E

PC14

PF0

PI10

PI11

PI0

PA 9

F

PC15

VSS

VDD

PH2

VSS

VSS

VSS

VSS

VSS

VSS

VCAP2

PC9

PA 8

G

PH0

VSS

VDD

PH3

VSS

VSS

VSS

VSS

VSS

VSS

VDD

PC8

PC7

H

PH1

PF2

PF1

PH4

VSS

VSS

VSS

VSS

VSS

PG8

PC6

J

NRST

PF3

PF4

PH5

VSS

VSS

VSS

VSS

VSS

VDD

PG7

PG6

K

PF7

PF6

PF5

VDD

VSS

VSS

VSS

VSS

VSS

PG5

PG4

PG3

L

PF10

PF9

PF8

BYPASS

PD15

PG2

_REG

M

VSSA

PC0

PC1

PC2

PC3

PB2

PG1

VSS

VSS

VCAP

PH6

PD14

PD13

_1

N

VREF-

PA1

PA0

PA4

PC4

PF13

PG0

VDD

VDD

VDD

PE13

PH7

PD12

PD11

PD10

P

VREF+

PA2

PA6

PA5

PC5

PF12

PF15

PE8

PE9

PE11

PE14

PB12

PB13

PD9

PD8

R

VDDA

PA3

PA7

PB1

PB0

PF11

PF14

PE7

PF10

PE12

PE15

PB10

PB11

PB14

PB15

	STM32F42xx/3xx			STM32F469xx
	STM32F40xx/41xx			STM32F479xx
	PD1	PI3	PI2	PD1	PI3	NC
	PD2	PH15	PI1	PD2	VDD12	PI1
					DSI
			PI0	DSI	DSI	PI0
	PH13	PH14		HOST_	HOST_
				D1P	D1N
	VSS	VCAP2	PC9	VSS	VCAP2	PC9
	VSS	VDD	PC8	VSS	VDD	PC8
	VSS	VDD	PG8	VSS	VDD_	PG8
				DSI	USB
	VDD	VDD	PG7	VDD	VDD	PG7
				DSI
	PH12	PG5	PG4	VCAP	PG5	PG4
				DSI
	PH11	PH10	PD15	DSI	DSI	PD15
				HOST_	HOST_
				CKP	CKN
	PH8	PH9	PD14	DSI	DSI	PD14
				HOST_	HOST_
				D0P	D0N

MS39403V1

1. The highlighted pins are substituted with dedicated DSI IO pins on STM32F469xx/479xx devices.

18/220

DS11118 Rev 6

STM32F479xx	Description

1.1.4TFBGA216 package

Figure 4. TFBGA216 port-to-terminal assignment differences

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

A

PE4

PE3

PE2

PG14

PE1

PE0

PB8

PB5

PB4

PB3

PD7

PC12

PA15

PA14

PA13

B

PE5

PE6

PG13

PB9

PB7

PB6

PG15

PG11

PJ13

PJ12

PD6

PD0

PC11

PC10

PA12

C

VBAT

PI8

PI4

PK7

PK6

PK5

PG12

PG10

PJ14

PD5

PD3

PD1

PI3

PI2

PA11

D

PC13

PF0

PI5

PI7

PI10

PI6

PK4

PK3

PG9

PJ15

PD4

PD2

PH15

PI1

PA10

E	PC14	PF1	PI12	PI9	PDR	BOOT0
					ON
F	PC15	VSS	PI11	VDD	VDD	VSS

VDD	VDD	VDD	VDD	VCAP2 PH13	PH14	PI0	PA9
VSS	VSS	VSS	VSS	VDD		PC9	PA8

G	PH0	PF2	PI13	PI15
H	PH1	PF3	PI14	PH4
J	NRST	PF4	PH5	PH3

VDD	VSS	VSS		PC8	PC7
VDD	VSS	VSS		PG8	PC6
VDD	VSS	VSS	VDD	PG7	PG6

K

PF7

PF6

PF5

PH2

VDD

VSS

VSS

VSS

VSS

VSS

VDD

PD15

PB13

PD10

L

PF10

PF9

PF8

PC3

BYPASS

VSS

VDD

VDD

VDD

VDD

VCAP1

PD14

PB12

PD9

PD8

-REG

M

VSSA

PC0

PC1

PC2

PB2

PF12

PG1

PF15

PJ4

PD12

PD13

PG3

PG2

PJ5

PH12

N

VREF-

PA1

PA0

PA4

PC4

PF13

PG0

PJ3

PE8

PD11

PG5

PG4

PH7

PH9

PH11

P

VREF+

PA2

PA6

PA5

PC5

PF14

PJ2

PF11

PE9

PE11

PE14

PB10

PH6

PH8

PH10

R VDDA PA3 PA7 PB1 PB0 PJ0	PJ1 PE7 PE10 PE12 PE15 PE13 PB11 PB14 PB15
STM32F42xx/3xx	STM32F469xx
STM32F40xx/41xx	STM32F479xx

VDD PK1 PL2

VDD PJ11 PK0

VDD PJ8 PJ10

VDD PJ7 PJ9

VDD PJ6 PD15

	VDD	DSI	DSI
		HOST_	HOST_
		D1P	D1N
	VDDD	VSS	VDD12
	USB	DSI	DSI
	VDD	DSI	DSI
		HOST_	HOST_
	DSI
		CKP	CKN
	VDD	DSI	DSI
		HOST_	HOST_
		D0P	D0N
	VDD	VCAP	PD15
		DSI

MSv39404V1

1. The highlighted pins are substituted with dedicated DSI IO pins on STM32F469xx/479xx devices.

DS11118 Rev 6

19/220

Description	STM32F479xx

Figure 5. STM32F479xx block diagram

JTRST, JTDI,

JTCK/SWCLK

JTDO/SWD, JTDO

TRACECK

TRACED(3:0)

D+, D- VDDUSB = 3.0 to 3.6 V ULPI : CLK, D(7:0), DIR, STP, NXT SCL/SDA, INT, ID, VBUS

CCM data RAM 64 KB

JTAG & SW MPUFPU

ETM NVIC

	ARM
	Cortex M4
	180 MHz
<![if ! IE]> <![endif]>PHY	OTG HS
	USB
	GP-DMA2
	GP-DMA1

D-BUS
I-BUS
S-BUS	<![if ! IE]> <![endif]>MATRIX
DMA/
FIFO	<![if ! IE]> <![endif]>BUS
8 Streams
FIFO	<![if ! IE]> <![endif]>AHB
8 Streams

FIFO

LCD-TFT FIFO

			CLK, NE[3:0], A[23:0], D[31:0],
EXT MEM CTRL (FMC)			NOE, NWEN, NBL[3:0],
			SDCLKE[1:0], SDNE[1:0],
SRAM, PSRAM, NOR Flash
			NRAS, NCAS, NADV,
NAND Flash, SDRAM
			NWAIT, INTR

QuadSPI

<![if ! IE]> <![endif]>ACCEL/ CACHE	Flash 1MB
	Flash 1MB

SRAM1 160KB

SRAM2 32KB SRAM3 128KB

AHB2180MHz MHz

						CLK,
						BK1_NCS, BK2_NCS,
						D[7:0]
<![if ! IE]> <![endif]>FIFO		AES256
		3DES,
<![if ! IE]> <![endif]>FIFO		HASH
		RNG					HSYNC, VSYNC
<![if ! IE]> <![endif]>FIFO		ITF
		CAMERA					PIXCK, D(13:0)
<![if ! IE]> <![endif]>FIFO		USB		<![if ! IE]> <![endif]>PHY		D+, D-,
		OTG FS				VDDUSB = 3.0 to 3.6 V,
						SCL, SDA, INT, ID, VBUS

	DMA-2D	FIFO	AHB1 180 MHz
PA[15:0]	USARTGPIO PORT2MBpsA			@VDDA
						POR	SUPPLY
PB[15:0]	USARTGPIO PORT2MBpsB			RC HS
				RC LS	Reset		SUPERVISION
PC[15:0]						Int	POR/PDR/
	USARTGPIO PORT2MBpsC			PLL1,2,3			BOR
							PVD
PD[15:0]	USARTGPIO PORT2MBpsD
							@VDDA @VDD
PE[15:0]
	USARTGPIO PORT2MBpsE		RESET&				XTAL OSC
PF[15:0]			CLOCK				4-26MHz
	USARTGPIO PORT2MBpsF		MANAGT
			CTRL				IWDG
PG[15:0]	USARTGPIO PORT2MBpsG		<![if ! IE]> <![endif]>PCLKx	<![if ! IE]> <![endif]>HCLKx	<![if ! IE]> <![endif]>LS	Standbyinterface
PH[15:0]	USARTGPIO PORT2MBpsH						@VBAT
							XTAL 32kHz
PI[15:0]	USARTGPIO 2MBpsPORTI		CRC				RTC
PJ[15:0]							AWU
	USARTGPIO PORT2MBpsJ				<![if ! IE]> <![endif]>LS	Backup Register
PK[7:0]						4KB BKPRAM
	USARTGPIO PORT2MBpsK

DSIHOST_D0 P/N

TIM2

32b

DSIHOST_D1 P/N

DSIHOST_CK P/N

<![if ! IE]> <![endif]>DSI PHI

DSI Host

TIM3

16b

VDD12DSI, VDDSI, VSSDSI

VCAPDSI

DSIHOST_TE

USARTEXT IT2MBps. WKUP

DMA2

DMA1

TIM4

16b

168 AF

VDDA, VSSA,

NRST

OSCIN

OSCOUT

VBAT = 1.8 to 3.6 V

OSC32_IN

OSC32_OUT

RTC_TAMP1

RTC_TAMP2

RTC_OUT

RTC_REFIN

RTC_TS

4 Channels, ETR as AF

4 Channels, ETR as AF

4 Channels, ETR as AF

D[7:0]

CMD, CK as AF

4 compl. chan. (TIM1_CH1[1:4]N),

4 chan. (TIM8_CH1[1:4]ETR), BKIN as AF 4 compl. chan. (TIM1_CH1[1:4]N),

4 chan. (TIM8_CH1[1:4]ETR), BKIN as AF

2 channels as AF

1 channel as AF

1 channel as AF

RX, TX, SCK,

CTS, RTS as AF

RX, TX, SCK,

CTS, RTS as AF

MOSI, MISO, SCK,

NSS as AF

MOSI, MISO, SCK,

NSS as AF

MOSI, MISO, SCK,

NSS as AF

MOSI, MISO, SCK,

NSS as AF

SD, SCK, FS

MCLK as AF

SDIO / MMC	<![if ! IE]> <![endif]>FIFO
USARTTIMER12MBps/ PWM	16b
USARTTIMER82MBps/ PWM 16b
TIMEUSART92MBps16b
	16b
TIMER10USA2MBps
	16b
TIMER11USART 2MBps		<![if ! IE]> <![endif]>MHz
irDA
smcard
USART USART2MBps 1
smcard		<![if ! IE]> <![endif]>90
USART USART2MBps 6		<![if ! IE]> <![endif]>APB2
irDA
USARTSPI1/I2S2MBps
USARTSPI2MBps4
USARTSPI52MBps		<![if ! IE]> <![endif]>Hz
USARTSPI62MBps		<![if ! IE]> <![endif]>60M
		<![if ! IE]> <![endif]>APB2
USART 2MBps	<![if ! IE]> <![endif]>FIFO
SAI 1
@VDDA

V DDREF_ADC				USARTTEMP SENSOR2MBps

AHB/APB2 AHB/APB1

WWDG

<![if ! IE]>

<![endif]>APB1 45 MHz

TIMER6 16b

TIMER7 16b

@VDDA

	TIM5	32b		4 Channels
	TIM12	16b		2 Channels as AF
	TIM13		16b	1 Channels as AF
	TIM14		16b	1 CH as AF
	USART2	smcard		RX, TX, SCK,
			irDA	CTS, RTS as AF
	USART3smcard			RX, TX, SCK
			irDA	CTS, RTS as AF
	UART4			RX, TX as AF
	UART5			RX, TX as AF
	UART7			RX, TX as AF
	UART8			RX, TX as AF
	SPI2/I2S			MOSI, MISO, SCK
				NSS/WS, MCK as AF
	SPI3/I2S			MOSI, MISO, SCK
				NSS/WS, MCK as AF
	I2C1/SMBUS			SCL, SDA, SMBA as AF
			<![if ! IE]> <![endif]>Filter
	I2C2/SMBUS			SCL, SDA, SMBA as AF
			<![if ! IE]> <![endif]>Dig.
	I2C3/SMBUS			SCL, SDA, SMBA as AF

8 analog inputs common

ADC1

DAC1

ITF

to the 3 ADCs

bxCAN1

8 analog inputs common

ADC2

IF

DAC2

to the ADC1 & 2

bxCAN2

ADC 3

8 analog inputs to ADC3

<![if ! IE]>

<![endif]>FIFO

TX, RX

TX, RX

DAC1 as AF	DAC2 as AF	MS38297V1

1.The timers connected to APB2 are clocked from TIMxCLK up to 180 MHz, while the timers connected to APB1 are clocked from TIMxCLK either up to 90 MHz or 180 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register.

20/220

DS11118 Rev 6

STM32F479xx	Functional overview

2 Functional overview

2.1Arm® Cortex®-M4 with FPU and embedded Flash and SRAM

The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm® processors for embedded systems, developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.

The Arm® Cortex®-M4 with FPU core is a 32-bit RISC processor that features exceptional code-efficiency, delivering the high-performance expected from an Arm® core in the memory size usually associated with 8- and 16-bit devices.

	The processor supports a set of DSP instructions that allow efficient signal processing and
	complex algorithm execution. Its single precision FPU (floating point unit) speeds up
	software development by using metalanguage development tools, while avoiding saturation.
	The STM32F47x line is compatible with all Arm® tools and software.
	Figure 5 shows the general block diagram of the STM32F47x line.
Note:	Cortex®-M4 with FPU core is binary compatible with the Cortex®-M3 core.

2.2Adaptive real-time memory accelerator (ART Accelerator™)

The ART Accelerator™ is a memory accelerator optimized for STM32 industry-standard Arm® Cortex®-M4 with FPU processors. It balances the inherent performance advantage of the Arm® Cortex®-M4 with FPU over Flash memory technologies, which normally require the processor to wait for the Flash memory at higher frequencies.

To release the processor full 225 DMIPS performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 128-bit Flash memory. Based on CoreMark® benchmark, the performance achieved thanks to the ART Accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 180 MHz.

2.3Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 Gbytes of addressable memory.

The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

DS11118 Rev 6

21/220

Functional overview	STM32F479xx

2.4Embedded Flash memory

The devices embed a Flash memory of up to 2 Mbytes available for storing programs and data.

2.5CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location.

2.6Embedded SRAM

All devices embed:

Up to 384Kbytes of system SRAM including 64 Kbytes of CCM (core coupled memory) data RAM

RAM is accessed (read/write) at CPU clock speed with 0 wait states.

4 Kbytes of backup SRAM

This area is accessible only from the CPU. Its content is protected against possible unwanted write accesses, and is retained in Standby or VBAT mode.

2.7Multi-AHB bus matrix

The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB HS, LCD-TFT, and DMA2D) and the slaves (Flash memory, RAM, FMC, QUADSPI, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously.

22/220

DS11118 Rev 6

STM32F479xx

Functional overview

Figure 6. STM32F479xx Multi-AHB matrix

64-Kbyte

ARM

GP

GP

MAC

USB OTG

LCD-TFT

Chrom ART

CCM data RAM

Cortex-M4

DMA1

DMA2

Ethernet

HS

Accelerator(DMA2D)

<![if ! IE]> <![endif]>I-bus

<![if ! IE]> <![endif]>D-bus

<![if ! IE]> <![endif]>S-bus

<![if ! IE]> <![endif]>DMA PI

<![if ! IE]> <![endif]>DMA MEM1

<![if ! IE]> <![endif]>DMA MEM2

<![if ! IE]> <![endif]>DMA P2

<![if ! IE]> <![endif]>ETHERNET M

<![if ! IE]> <![endif]>USB HS M

<![if ! IE]> <![endif]>LCD-TFT M

<![if ! IE]> <![endif]>DMA2D

ICODE

Flash

<![if ! IE]> <![endif]>ACCEL

DCODE

memory

SRAM1

160 Kbyte

SRAM2

32 Kbyte

SRAM3

128 Kbyte

AHB2

APB1

peripherals

AHB1

peripherals

APB2

FMC external

MemCtl

QuadSPI

Bus matrix-S

MS33862V1

2.8DMA controller (DMA)

The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB).

The two DMA controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code.

Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. Configuration is made by software and transfer sizes between source and destination are independent.

DS11118 Rev 6

23/220

Functional overview	STM32F479xx

The DMA can be used with the main peripherals:

SPI and I2S

I2C

USART

General-purpose, basic and advanced-control timers TIMx

DAC

SDIO

Camera interface (DCMI)

ADC

SAI1

QUADSPI.

2.9Flexible memory controller (FMC)

The Flexible memory controller (FMC) includes three memory controllers:

The NOR/PSRAM memory controller

The NAND/memory controller

The Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller

The main features of the FMC controller are the following:

Interface with static-memory mapped devices including:

–Static random access memory (SRAM)

–NOR Flash memory/OneNAND Flash memory

–PSRAM

–NAND Flash memory with ECC hardware to check up to 8 Kbytes of data

Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories

8-,16-,32-bit data bus width

Independent Chip Select control for each memory bank

Independent configuration for each memory bank

Write FIFO

Read FIFO for SDRAM controller

The Maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is HCLK/2.

LCD parallel interface

The FMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to

specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost effective graphic applications using LCD modules with embedded controllers or high

performance solutions using external controllers with dedicated acceleration.

24/220

DS11118 Rev 6

STM32F479xx	Functional overview

2.10Quad-SPI memory interface (QUADSPI)

All STM32F479xx devices embed a Quad-SPI memory interface, which is a specialized communication interface targeting Single, Dual, Quad or Dual-flash SPI memories. It can work in direct mode through registers, external flash status register polling mode and memory mapped mode. Up to 256 Mbytes external Flash memory are mapped, supporting 8, 16 and 32-bit access. Code execution is supported.

The opcode and the frame format are fully programmable. Communication can be either in Single Data Rate or Dual Data Rate.

2.11LCD-TFT controller

The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue) and delivers all signals to interface directly to a broad range of LCD and TFT panels up to XGA (1024x768) resolution with the following features:

2 displays layers with dedicated FIFO (64x32-bit)

Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer

Up to 8 Input color formats selectable per layer

Flexible blending between two layers using alpha value (per pixel or constant)

Flexible programmable parameters for each layer

Color keying (transparency color)

Up to 4 programmable interrupt events.

2.12DSI Host (DSIHOST)

The DSI Host is a dedicated peripheral for interfacing with MIPI DSI compliant displays. It includes a dedicated video interface internally connected to the LTDC and a generic APB interface that can be used to transmit information to the display.

These interfaces are as follows:

LTDC interface:

–Used to transmit information in Video Mode, in which the transfers from the host processor to the peripheral take the form of a real-time pixel stream (DPI).

–Through a customized for mode, this interface can be used to transmit information in full bandwidth in the Adapted Command Mode (DBI).

APB slave interface:

–Allows the transmission of generic information in Command mode, and follows a proprietary register interface.

–Can operate concurrently with either LTDC interface in either Video Mode or Adapted Command Mode.

Video mode pattern generator:

–Allows the transmission of horizontal/vertical color bar and D-PHY BER testing pattern without any kind of stimuli.

DS11118 Rev 6

25/220

Functional overview	STM32F479xx

The DSI Host main features:

Compliant with MIPI Alliance standards

Interface with MIPI D-PHY

Supports all commands defined in the MIPI Alliance specification for DCS:

–Transmission of all Command mode packets through the APB interface

–Transmission of commands in low-power and high-speed during Video Mode

Supports up to two D-PHY data lanes

Bidirectional communication and escape mode support through data lane 0

Supports non-continuous clock in D-PHY clock lane for additional power saving

Supports Ultra Low-Power mode with PLL disabled

ECC and Checksum capabilities

Support for End of Transmission Packet (EoTp)

Fault recovery schemes

3D transmission support

Configurable selection of system interfaces:

–AMBA APB for control and optional support for Generic and DCS commands

–Video Mode interface through LTDC

–Adapted Command Mode interface through LTDC

Independently programmable Virtual Channel ID in

–Video Mode

–Adapted Command Mode

–APB Slave

Video Mode interfaces features

LTDC interface color coding mappings into 24-bit interface:

–16-bit RGB, configurations 1, 2, and 3

–18-bit RGB, configurations 1 and 2

–24-bit RGB

Programmable polarity of all LTDC interface signals

Maximum resolution is limited by available DSI physical link bandwidth:

–Number of lanes: 2

–Maximum speed per lane: 500 Mbps

Adapted interface features

Support for sending large amounts of data through the memory_write_start (WMS) and memory_write_continue (WMC) DCS commands

LTDC interface color coding mappings into 24-bit interface:

–16-bit RGB, configurations 1, 2, and 3

–18-bit RGB, configurations 1 and 2

–24-bit RGB

26/220

DS11118 Rev 6

STM32F479xx	Functional overview

Video mode pattern generator

Vertical and horizontal color bar generation without LTDC stimuli

BER pattern without LTDC stimuli

2.13Chrom-ART Accelerator™ (DMA2D)

The Chrom-Art Accelerator™ (DMA2D) is a graphic accelerator which offers advanced bit blitting, row data copy and pixel format conversion. It supports the following functions:

Rectangle filling with a fixed color

Rectangle copy

Rectangle copy with pixel format conversion

Rectangle composition with blending and pixel format conversion.

Various image format coding are supported, from indirect 4bpp color mode up to 32bpp direct color. It embeds dedicated memory to store color lookup tables.

An interrupt can be generated when an operation is complete or at a programmed watermark.

All the operations are fully automatized and are running independently from the CPU or the DMAs.

2.14Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 93 maskable interrupt channels plus the 16 interrupt lines of the Cortex®- M4 with FPU core.

Closely coupled NVIC gives low-latency interrupt processing

Interrupt entry vector table address passed directly to the core

Allows early processing of interrupts

Processing of late arriving, higher-priority interrupts

Support tail chaining

Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction overhead

This hardware block provides flexible interrupt management features with minimum interrupt latency.

2.15External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 23 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 159 GPIOs can be connected to the 16 external interrupt lines.

DS11118 Rev 6

27/220

Functional overview	STM32F479xx

2.16Clocks and startup

On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The 16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy over the full

temperature range. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing to increase the frequency up to 180 MHz. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example if an indirectly used external oscillator fails).

Several prescalers allow the configuration of the two AHB buses, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB buses is 180 MHz while the maximum frequency of the high-speed APB domains is

90 MHz. The maximum allowed frequency of the low-speed APB domain is 45 MHz.

The devices embed a dedicated PLL (PLLI2S) and PLLSAI which allows to achieve audio class performance. In this case, the I2S master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz.

2.17Boot modes

At startup, boot pins are used to select one out of three boot options:

Boot from user Flash

Boot from system memory

Boot from embedded SRAM

The boot loader is located in system memory. It is used to reprogram the Flash memory through a serial interface. Refer to application note AN2606 for details.

2.18Power supply schemes

VDD = 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when enabled), provided externally through VDD pins.

VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.

Note:	VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to
	Section 2.19.2). Refer to Table 3 to identify the packages supporting this option.
	VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
	backup registers (through power switch) when VDD is not present.
	VDDUSB can be connected either to VDD or an external independent power supply (3.0
	to 3.6 V) for USB transceivers.
	For example, when device is powered at 1.8V, an independent power supply 3.3 V can
	be connected to VDDUSB. When the VDDUSB is connected to a separated power supply,
	it is independent from VDD or VDDA but it must be the last supply to be provided and the
	first to disappear.

28/220

DS11118 Rev 6

STM32F479xx	Functional overview

The following conditions must be respected:

–During power-on phase (VDD < VDD_MIN), VDDUSB should be always lower than VDD

–During power-down phase (VDD < VDD_MIN), VDDUSB should be always lower than VDD

–VDDUSB rising and falling time rate specifications must be respected.

–In operating mode phase, VDDUSB could be lower or higher than VDD:

–If USB (USB OTG_HS/OTG_FS) is used, the associated GPIOs powered by

VDDUSB are operating between VDDUSB_MIN and VDDUSB_MAX.The VDDUSB supplies both USB transceivers (USB OTG_HS and USB OTG_FS).

–If only one USB transceiver is used in the application, the GPIOs associated to the other USB transceiver are still supplied by VDDUSB.

–If USB (USB OTG_HS/OTG_FS) is not used, the associated GPIOs powered by VDDUSB are operating between VDD_MIN and VDD_MAX.

–If USB (USB OTG_HS/OTG_FS) is not used and the associated GPIOs

powered by VDDUSB are not used, then VDDUSB should be tied to VSS or VDD (VDDUSB must not be floating).

Figure 7. VDDUSB connected to an external independent power supply

VDDUSB_MAX	USB functional area
	VDDUSB
VDDUSB_MIN
USB non		non
functional	VDD = VDDA
area
VDD_MIN
Power-on	Operating mode	Power-down	time
			MS37590V1

The DSI (Display Serial Interface) sub-system uses several power supply pins that are independent from the other supply pins:

VDDDSI is an independent DSI power supply dedicated for DSI Regulator and MIPI D-PHY. This supply must be connected to global VDD.

VCAPDSI pin is the output of DSI Regulator (1.2 V), which must be connected externally to VDD12DSI.

VDD12DSI pin is used to supply the MIPI D-PHY, and to supply clock and data lanes pins. An external capacitor of 2.2 µF must be connected on VDD12DSI pin.

VSSDSI pin is an isolated supply ground used for DSI sub-system.

If DSI functionality is not used at all, then:

– VDDDSI pin must be connected to global VDD.

DS11118 Rev 6

29/220

Functional overview	STM32F479xx

–VCAPDSI pin must be connected externally to VDD12DSI but the external capacitor is no more needed.

–VSSDSI pin must be grounded.

2.19Power supply supervisor

2.19.1Internal reset ON

On packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high. On other packages the power supply supervisor is always enabled.

The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is reached, the option byte loading process starts, either to confirm or modify default BOR thresholds, or to disable BOR permanently. Three BOR thresholds are available through option bytes. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for an external reset circuit.

The device also features an embedded programmable voltage detector (PVD) that monitors

the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is

higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

2.19.2Internal reset OFF

This feature is available only on packages featuring the PDR_ON pin. The internal power-on reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin.

An external power supply supervisor should monitor VDD and NRST and should maintain the device in reset mode as long as VDD is below a specified threshold. PDR_ON must be connected to VSS, as shown in Figure 8.

Figure 8. Power supply supervisor interconnection with internal reset OFF

VDD
				STM32F479xx						Application reset
				VBAT						signal (optional)
				PDR_ON

VSS

PDR not active : 1.7 V < VDD < 3.6 V

MSv36589V1

30/220

DS11118 Rev 6