Adaptive real-time accelerator (ART
Accelerator™) allowing 0-wait state execution
from Flash memory, frequency up to 180 MHz,
MPU, 225 DMIPS/1.25 DMIPS/MHz(Dhrystone
2.1), and DSP instructions
Memories
– Up to 2 MB of Flash memory organized into
two banks allowing read-while-write
– Up to 384+4 KB of SRAM including 64 KB of
CCM (core coupled memory) data RAM
– Flexible external memory controller with up
to 32-bit data bus: SRAM, PSRAM,
SDRAM/LPSDR, SDRAM, Flash
NOR/NAND memories
– Dual-flash mode Quad-SPI interface
Graphics:
– Chrom-ART Accelerator™ (DMA2D),
graphical hardware accelerator enabling
enhanced graphical user interface with
minimum CPU load
– LCD parallel interface, 8080/6800 modes
– LCD TFT controller supporting up to XGA
resolution
–MIPI
®
DSI host controller supporting up to
720p 30Hz resolution
Clock, reset and supply management
– 1.7 V to 3.6 V application supply and I/Os
– POR, PDR, PVD and BOR
– 4-to-26 MHz crystal oscillator
– Internal 16 MHz factory-trimmed RC (1%
accuracy)
– 32 kHz oscillator for RTC with calibration
– Internal 32 kHz RC with calibration
Table 77.ADC static accuracy at f
Table 78.ADC static accuracy at f
Table 79.ADC static accuracy at f
Table 80.ADC dynamic accuracy at f
Table 81.ADC dynamic accuracy at f
The STM32F479xx devices are based on the high-performance Arm
RISC core operating at a frequency of up to 180 MHz. The Cortex
Floating point unit (FPU) single precision which supports all Arm
®(a)
Cortex®-M4 32-bit
®
-M4 core features a
®
single-precision dataprocessing instructions and data types. It also implements a full set of DSP instructions and
a memory protection unit (MPU) which enhances application security.
The STM32F479xx devices incorporate high-speed embedded memories (Flash memory
up to 2 Mbytes, up to 384 Kbytes of SRAM), up to 4 Kbytes of backup SRAM, and an
extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB
buses and a 32-bit multi-AHB bus matrix.
All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose
16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers,
a true random number generator (RNG), and a cryptographic acceleration cell. They also
feature standard and advanced communication interfaces:
Up to three I
Six SPIs, two I
2
Cs
2
Ss full duplex. To achieve audio class accuracy, the I2S peripherals can
be clocked via a dedicated internal audio PLL or via an external clock to allow
synchronization.
Four USARTs plus four UARTs
An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the
ULPI)
Two CANs
One SAI serial audio interface
An SDMMC host interface
Ethernet and camera interface
LCD-TFT display controller
Chrom-ART Accelerator™
DSI Host.
Advanced peripherals include an SDMMC interface, a flexible memory control (FMC)
interface, a Quad-SPI Flash memory, camera interface for CMOS sensors and a
cryptographic acceleration cell. Refer to Ta bl e 2 for the list of peripherals available on each
part number.
The STM32F479xx devices operate in the –40 to +105 °C temperature range from a 1.7 to
3.6 V power supply. A dedicated supply input for USB (OTG_FS and OTG_HS) only in full
speed mode, is available on all packages.
The supply voltage can drop to 1.7 V (refer to Section 2.19.2). A comprehensive set of
power-saving mode allows the design of low-power applications.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
12 /22 0DS 1111 8 Rev 6
STM32F479xxDescription
The STM32F479xx devices are offered in eight packages, ranging from 100 to 216 pins.
The set of included peripherals changes with the device chosen, according to Tab le 2.
These features make the STM32F479xx microcontrollers suitable for a wide range of
applications:
Table 2. STM32F479xx features and peripheral counts (continued)
Peripherals
STM32F479Vx
STM32F479Zx
STM32F479Ax
STM32F479Ix
STM32F479Bx
STM32F479Nx
MIPI-DSI HostYes
LCD-TFT Yes
Chrom-ART Accelerator™
(DMA2D)
Yes
CryptographyYes
GPIOs71131114131161161
12-bit ADC
Number of channels
12-bit DAC
Number of channels
142024
3
Yes
2
Maximum CPU frequency180 MHz
Operating voltage1.7 to 3.6V
Operating temperatures
PackageLQFP100LQFP144
1. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode.
2. VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to Section 2.19.2).
Ambient operating temperature: −40 to 85 °C / −40 to 105 °C
Junction temperature: −40 to 105 °C / −40 to 125 °C
UFBGA169
WLCSP168
(2)
LQFP176
UFBGA176
LQFP208TFBGA216
14 /22 0DS 1111 8 Rev 6
STM32F479xxDescription
1.1 Compatibility throughout the family
STM32F479xx devices are not compatible with other STM32F4xx devices.
Figure 1 and Figure 2 show incompatible board designs, respectively, for LQFP176 and
LQFP208 packages (highlighted pins).
The UFBGA176 and TFBGA216 ballouts are compatible with other STM32F4xx devices,
only few IO port pins are substituted, as shown in Figure 3 and Figure 4.
The LQFP100, LQFP144 and UFBGA169 packages are incompatible with other
STM32F4xx devices.
DS 1111 8 Rev 615/ 2 2 0
47
DescriptionSTM32F479xx
MS38294V2
VSS
PI3
PI1
135 134 133
132
PI0
131
VDD
130
VSS
129
VCAP2
128
PA13
127
PA12
126
PA11
125
PA10
124
PA9
123
PA8
122
PC9
121
PC8
120
PC7
119
PC6
VDDUSB
117
VSS
116
PG8
115
PG7
114
PG6
113
PG5
112
PG4
111
PG3
110
PG2
109
VSSDSI
108
DSIHOST_D1N
107
DSIHOST_D1P
106
VDD12DSI
105
DSIHOST_CKN
104
DSIHOST_CKP
103
VSSDSI
102
DSIHOST_D0N
101
DSIHOST_D0P
100
VCAPDSI
99
VDDSI
98
PD15
97
PD14
96
VDD
95
VSS
94
PD13
93
PD12
92
PD11
91
PD10
90
PD9
89
PD8
84 85
86 87
88
STM32F469xx/479xx
LQFP176
PH7
PB12
PB13
PB14
PB15
118
VSS
PI3
PI2
135 134
133
132
PI1
131PI0
130
PH15
129
PH14
128
PH13
127
VDD
126
VSS
125
VCAP2
124
PA13
123
PA12
122
PA11
121
PA10
120
PA9
119
PA8
118
PC9
117
PC8
116
PC7
115
PC6
114
VDD
113
VSS
112
PG8
111
PG7
110
PG6
109
PG5
108
PG4
107
PG3
106
PG2
105
PD15
104
PD14
103
VDD
102
VSS
101
PD13
100
PD12
99
PD11
98
PD10
97
PD9
96
PD8
95
PB15
94
PB14
93
PB13
92
PB12
91
VDD
90
VSS
89
PH12
84
85
86
87
88
PH8
PH9
PH10
PH11
STM32F4xx
LQFP176
PH7
1.1.1 LQFP176 package
Figure 1. Incompatible board design for LQFP176 package
16 /22 0DS 1111 8 Rev 6
1. Pins from 85 to 133 are not compatible.
STM32F479xxDescription
MS38295V1
138
PC6
PC6
137VDDUSB
VDD
136
VSS
VSS
135
PG8
PG8
134
PG7
PG7
133
PG6
PG6
132
PG5
PG5
131
PG4
PG4
130
PG3
PG3
129
PG2
PG2
128
VSSDSI
PK2
127
DSIHOST_D1N
PK1
126
DSIHOST_D1P
PK0
125
VDD12DSI
VSS
124
DSIHOST_CKN
VDD
123
DSIHOST_CKP
PJ11
122
VSSDSI
PJ10
121
DSIHOST_D0N
PJ9
120
DSIHOST_D0P
PJ8
119
VCAPDSI
PJ7
118
VDDDSI
PJ6
117
PD15
PD15
116
PD14
PD14
STM32F42x/STM32F43x
LQFP208
STM32F469xx/479xx
LQFP208
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
1.1.2 LQFP208 package
Figure 2. Incompatible board design for LQFP208 package
1. Pins from 118 to 128 and pin 137 are not compatible
1. The timers connected to APB2 are clocked from TIMxCLK up to 180 MHz, while the timers connected to
APB1 are clocked from TIMxCLK either up to 90 MHz or 180 MHz depending on TIMPRE bit configuration
in the RCC_DCKCFGR register.
STM32F479xxFunctional overview
2 Functional overview
2.1 Arm® Cortex®-M4 with FPU and embedded Flash and SRAM
The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm® processors for
embedded systems, developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced response to interrupts.
The Arm
code-efficiency, delivering the high-performance expected from an Arm
memory size usually associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions that allow efficient signal processing and
complex algorithm execution. Its single precision FPU (floating point unit) speeds up
software development by using metalanguage development tools, while avoiding saturation.
The STM32F47x line is compatible with all Arm
Figure 5 shows the general block diagram of the STM32F47x line.
Note:Cortex
®
Cortex®-M4 with FPU core is a 32-bit RISC processor that features exceptional
®
tools and software.
®
-M4 with FPU core is binary compatible with the Cortex®-M3 core.
The ART Accelerator™ is a memory accelerator optimized for STM32 industry-standard
®
Arm
Cortex®-M4 with FPU processors. It balances the inherent performance advantage of
the Arm
the processor to wait for the Flash memory at higher frequencies.
To release the processor full 225 DMIPS performance at this frequency, the accelerator
implements an instruction prefetch queue and branch cache, which increases program
execution speed from the 128-bit Flash memory. Based on CoreMark
performance achieved thanks to the ART Accelerator is equivalent to 0 wait state program
execution from Flash memory at a CPU frequency up to 180 MHz.
®
Cortex®-M4 with FPU over Flash memory technologies, which normally require
®
benchmark, the
2.3 Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 Gbytes
of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
DS 1111 8 Rev 621/ 2 2 0
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Functional overviewSTM32F479xx
2.4 Embedded Flash memory
The devices embed a Flash memory of up to 2 Mbytes available for storing programs and
data.
2.5 CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a software
signature during runtime, to be compared with a reference signature generated at link-time
and stored at a given memory location.
2.6 Embedded SRAM
All devices embed:
Up to 384Kbytes of system SRAM including 64 Kbytes of CCM (core coupled memory)
data RAM
RAM is accessed (read/write) at CPU clock speed with 0 wait states.
4 Kbytes of backup SRAM
This area is accessible only from the CPU. Its content is protected against possible
unwanted write accesses, and is retained in Standby or V
BAT mode.
2.7 Multi-AHB bus matrix
The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB
HS, LCD-TFT, and DMA2D) and the slaves (Flash memory, RAM, FMC, QUADSPI, AHB
and APB peripherals) and ensures a seamless and efficient operation even when several
high-speed peripherals work simultaneously.
22 /22 0DS 1111 8 Rev 6
STM32F479xxFunctional overview
ARM
Cortex-M4
GP
DMA1
GP
DMA2
MAC
Ethernet
USB OTG
HS
Bus matrix-S
ICODE
DCODE
ACCEL
Flash
memory
SRAM1
160 Kbyte
SRAM2
32 Kbyte
AHB2
peripherals
AHB1
peripherals
FMC external
MemCtl
I-bus
D-bus
S-bus
DMA_PI
DMA_MEM1
DMA_MEM2
DMA_P2
ETHERNET_M
USB_HS_M
MS33862V1
CCM data RAM
64-Kbyte
APB1
APB2
SRAM3
128 Kbyte
LCD-TFT
Chrom ART
Accelerator(DMA2D)
LCD-TFT_M
DMA2D
QuadSPI
Figure 6. STM32F479xx Multi-AHB matrix
2.8 DMA controller (DMA)
The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8
streams each. They are able to manage memory-to-memory, peripheral-to-memory and
memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,
support burst transfer and are designed to provide the maximum peripheral bandwidth
(AHB/APB).
The two DMA controllers support circular buffer management, so that no specific code is
needed when the controller reaches the end of the buffer. The two DMA controllers also
have a double buffering feature, which automates the use and switching of two memory
buffers without requiring any special code.
Each stream is connected to dedicated hardware DMA requests, with support for software
trigger on each stream. Configuration is made by software and transfer sizes between
source and destination are independent.
DS 1111 8 Rev 623/ 2 2 0
47
Functional overviewSTM32F479xx
The DMA can be used with the main peripherals:
SPI and I
2
I
C
USART
General-purpose, basic and advanced-control timers TIMx
DAC
SDIO
Camera interface (DCMI)
ADC
SAI1
QUADSPI.
2
S
2.9 Flexible memory controller (FMC)
The Flexible memory controller (FMC) includes three memory controllers:
The NOR/PSRAM memory controller
The NAND/memory controller
The Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller
The main features of the FMC controller are the following:
Interface with static-memory mapped devices including:
–Static random access memory (SRAM)
–NOR Flash memory/OneNAND Flash memory
–PSRAM
–NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
8-,16-,32-bit data bus width
Independent Chip Select control for each memory bank
Independent configuration for each memory bank
Write FIFO
Read FIFO for SDRAM controller
The Maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is
HCLK/2.
LCD parallel interface
The FMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost
effective graphic applications using LCD modules with embedded controllers or high
performance solutions using external controllers with dedicated acceleration.
24 /22 0DS 1111 8 Rev 6
STM32F479xxFunctional overview
2.10 Quad-SPI memory interface (QUADSPI)
All STM32F479xx devices embed a Quad-SPI memory interface, which is a specialized
communication interface targeting Single, Dual, Quad or Dual-flash SPI memories. It can
work in direct mode through registers, external flash status register polling mode and
memory mapped mode. Up to 256 Mbytes external Flash memory are mapped, supporting
8, 16 and 32-bit access. Code execution is supported.
The opcode and the frame format are fully programmable. Communication can be either in
Single Data Rate or Dual Data Rate.
2.11 LCD-TFT controller
The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue)
and delivers all signals to interface directly to a broad range of LCD and TFT panels up to
XGA (1024x768) resolution with the following features:
2 displays layers with dedicated FIFO (64x32-bit)
Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer
Up to 8 Input color formats selectable per layer
Flexible blending between two layers using alpha value (per pixel or constant)
Flexible programmable parameters for each layer
Color keying (transparency color)
Up to 4 programmable interrupt events.
2.12 DSI Host (DSIHOST)
The DSI Host is a dedicated peripheral for interfacing with MIPI DSI compliant displays. It
includes a dedicated video interface internally connected to the LTDC and a generic APB
interface that can be used to transmit information to the display.
These interfaces are as follows:
LTDC interface:
–Used to transmit information in Video Mode, in which the transfers from the host
processor to the peripheral take the form of a real-time pixel stream (DPI).
–Through a customized for mode, this interface can be used to transmit information
in full bandwidth in the Adapted Command Mode (DBI).
APB slave interface:
–Allows the transmission of generic information in Command mode, and follows a
proprietary register interface.
–Can operate concurrently with either LTDC interface in either Video Mode or
Adapted Command Mode.
Video mode pattern generator:
–Allows the transmission of horizontal/vertical color bar and D-PHY BER testing
pattern without any kind of stimuli.
DS 1111 8 Rev 625/ 2 2 0
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Functional overviewSTM32F479xx
The DSI Host main features:
Compliant with MIPI
Interface with MIPI
Supports all commands defined in the MIPI
–Transmission of all Command mode packets through the APB interface
–Transmission of commands in low-power and high-speed during Video Mode
Supports up to two D-PHY data lanes
Bidirectional communication and escape mode support through data lane 0
Supports non-continuous clock in D-PHY clock lane for additional power saving
Supports Ultra Low-Power mode with PLL disabled
ECC and Checksum capabilities
Support for End of Transmission Packet (EoTp)
Fault recovery schemes
3D transmission support
Configurable selection of system interfaces:
–AMBA APB for control and optional support for Generic and DCS commands
–Video Mode interface through LTDC
–Adapted Command Mode interface through LTDC
Independently programmable Virtual Channel ID in
–Video Mode
–Adapted Command Mode
–APB Slave
Alliance standards
D-PHY
Alliance specification for DCS:
Video Mode interfaces features
LTDC interface color coding mappings into 24-bit interface:
–16-bit RGB, configurations 1, 2, and 3
–18-bit RGB, configurations 1 and 2
–24-bit RGB
Programmable polarity of all LTDC interface signals
Maximum resolution is limited by available DSI physical link bandwidth:
–Number of lanes: 2
–Maximum speed per lane: 500 Mbps
Adapted interface features
Support for sending large amounts of data through the memory_write_start (WMS) and
memory_write_continue (WMC) DCS commands
LTDC interface color coding mappings into 24-bit interface:
–16-bit RGB, configurations 1, 2, and 3
–18-bit RGB, configurations 1 and 2
–24-bit RGB
26 /22 0DS 1111 8 Rev 6
STM32F479xxFunctional overview
Video mode pattern generator
Vertical and horizontal color bar generation without LTDC stimuli
BER pattern without LTDC stimuli
2.13 Chrom-ART Accelerator™ (DMA2D)
The Chrom-Art Accelerator™ (DMA2D) is a graphic accelerator which offers advanced bit
blitting, row data copy and pixel format conversion. It supports the following functions:
Rectangle filling with a fixed color
Rectangle copy
Rectangle copy with pixel format conversion
Rectangle composition with blending and pixel format conversion.
Various image format coding are supported, from indirect 4bpp color mode up to 32bpp
direct color. It embeds dedicated memory to store color lookup tables.
An interrupt can be generated when an operation is complete or at a programmed
watermark.
All the operations are fully automatized and are running independently from the CPU or the
DMAs.
2.14 Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
and handle up to 93 maskable interrupt channels plus the 16 interrupt lines of the Cortex
M4 with FPU core.
Interrupt entry vector table address passed directly to the core
Allows early processing of interrupts
Processing of late arriving, higher-priority interrupts
Support tail chaining
Processor state automatically saved on interrupt entry, and restored on interrupt exit,
with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
2.15 External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 23 edge-detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 159 GPIOs can be connected
to the 16 external interrupt lines.
®
-
DS 1111 8 Rev 627/ 2 2 0
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Functional overviewSTM32F479xx
2.16 Clocks and startup
On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The
16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy over the full
temperature range. The application can then select as system clock either the RC oscillator
or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is
detected, the system automatically switches back to the internal RC oscillator and a
software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing
to increase the frequency up to 180 MHz. Similarly, full interrupt management of the PLL
clock entry is available when necessary (for example if an indirectly used external oscillator
fails).
Several prescalers allow the configuration of the two AHB buses, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB
buses is 180 MHz while the maximum frequency of the high-speed APB domains is
90 MHz. The maximum allowed frequency of the low-speed APB domain is 45 MHz.
The devices embed a dedicated PLL (PLLI2S) and PLLSAI which allows to achieve audio
class performance. In this case, the I
frequencies from 8 kHz to 192 kHz.
2.17 Boot modes
At startup, boot pins are used to select one out of three boot options:
Boot from user Flash
Boot from system memory
Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory
through a serial interface. Refer to application note AN2606 for details.
2.18 Power supply schemes
VDD = 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when
enabled), provided externally through V
Note:V
V
DD/VDDA
Section 2.19.2). Refer to Ta bl e 3 to identify the packages supporting this option.
V
V
, V
SSA
blocks, RCs and PLL. V
BAT
= 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset
DDA
minimum value of 1.7 V is obtained when the internal reset is OFF (refer to
DDA
and V
= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when V
can be connected either to VDD or an external independent power supply (3.0
DDUSB
to 3.6 V) for USB transceivers.
For example, when device is powered at 1.8V, an independent power supply 3.3 V can
be connected to V
it is independent from V
DDUSB
. When the V
or V
DD
first to disappear.
2
S master clock can generate all standard sampling
pins.
DD
must be connected to VDD and VSS, respectively.
SSA
is not present.
DD
is connected to a separated power supply,
DDUSB
but it must be the last supply to be provided and the
DDA
28 /22 0DS 1111 8 Rev 6
STM32F479xxFunctional overview
MS37590V1
V
DDUSB_MIN
V
DD_MIN
time
V
DDUSB_MAX
USB functional area
VDD=V
DDA
USB non
functional
area
V
DDUSB
Power-on
Power-down
Operating mode
USB non
functional
area
The following conditions must be respected:
–During power-on phase (V
V
DD
–During power-down phase (VDD < V
V
DD
–V
rising and falling time rate specifications must be respected.
DDUSB
–In operating mode phase, V
< V
DD
DDUSB
DD_MIN
DD_MIN
), V
), V
should be always lower than
DDUSB
should be always lower than
DDUSB
could be lower or higher than VDD:
– If USB (USB OTG_HS/OTG_FS) is used, the associated GPIOs powered by
V
are operating between V
DDUSB
DDUSB_MIN
and V
DDUSB_MAX
.The V
DDUSB
supplies both USB transceivers (USB OTG_HS and USB OTG_FS).
– If only one USB transceiver is used in the application, the GPIOs associated to
the other USB transceiver are still supplied by V
DDUSB
.
– If USB (USB OTG_HS/OTG_FS) is not used, the associated GPIOs powered
by V
are operating between V
DDUSB
DD_MIN
and V
DD_MAX
.
– If USB (USB OTG_HS/OTG_FS) is not used and the associated GPIOs
powered by V
(V
must not be floating).
DDUSB
are not used, then V
DDUSB
should be tied to VSS or VDD
DDUSB
Figure 7. V
connected to an external independent power supply
DDUSB
The DSI (Display Serial Interface) sub-system uses several power supply pins that are
independent from the other supply pins:
VDDDSI is an independent DSI power supply dedicated for DSI Regulator and MIPI
D-PHY. This supply must be connected to global VDD.
VCAPDSI pin is the output of DSI Regulator (1.2 V), which must be connected
externally to VDD12DSI.
VDD12DSI pin is used to supply the MIPI D-PHY, and to supply clock and data lanes
pins. An external capacitor of 2.2 µF must be connected on VDD12DSI pin.
VSSDSI pin is an isolated supply ground used for DSI sub-system.
If DSI functionality is not used at all, then:
–VDDDSI pin must be connected to global VDD.
DS 1111 8 Rev 629/ 2 2 0
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Functional overviewSTM32F479xx
PDR_ON
STM32F479xx
VSS
PDR not active : 1.7 V < VDD < 3.6 V
VBAT
VDD
Application reset
signal (optional)
MSv36589V1
–VCAPDSI pin must be connected externally to VDD12DSI but the external
capacitor is no more needed.
–VSSDSI pin must be grounded.
2.19 Power supply supervisor
2.19.1 Internal reset ON
On packages embedding the PDR_ON pin, the power supply supervisor is enabled by
holding PDR_ON high. On other packages the power supply supervisor is always enabled.
The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and
ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is
reached, the option byte loading process starts, either to confirm or modify default BOR
thresholds, or to disable BOR permanently. Three BOR thresholds are available through
option bytes. The device remains in reset mode when V
V
POR/PDR
or V
, without the need for an external reset circuit.
BOR
The device also features an embedded programmable voltage detector (PVD) that monitors
the V
DD/VDDA
generated when V
higher than the V
power supply and compares it to the V
DD/VDDA
PVD
drops below the V
threshold. The interrupt service routine can then generate a warning
threshold and/or when VDD/V
PVD
message and/or put the MCU into a safe state. The PVD is enabled by software.
is below a specified threshold,
DD
threshold. An interrupt can be
PVD
DDA
is
2.19.2 Internal reset OFF
This feature is available only on packages featuring the PDR_ON pin. The internal power-on
reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin.
An external power supply supervisor should monitor V
the device in reset mode as long as V
connected to VSS, as shown in Figure 8.
Figure 8. Power supply supervisor interconnection with internal reset OFF
is below a specified threshold. PDR_ON must be
DD
and NRST and should maintain
DD
30 /22 0DS 1111 8 Rev 6
STM32F479xxFunctional overview
MS19009V7
V
DD
time
PDR = 1.7 V
time
NRST
PDR_ON
PDR_ON
Reset by other source than
power supply supervisor
The VDD specified threshold, below which the device must be maintained under reset, is
1.7 V (see Figure 9).
A comprehensive set of power-saving mode allows to design low-power applications.
When the internal reset is OFF, the following integrated features are no more supported:
The brownout reset (BOR) circuitry must be disabled
The embedded programmable voltage detector (PVD) is disabled
V
functionality is no more available and V
BAT
pin should be connected to VDD.
BAT
All packages allow to disable the internal reset through the PDR_ON signal when connected
to V
.
SS
Figure 9. PDR_ON control with internal reset OFF
1. PDR_ON signal to be kept always low.
2.20 Voltage regulator
The regulator has four operating modes:
Regulator ON
–Main regulator mode (MR)
–Low power regulator (LPR)
–Power-down
Regulator OFF
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Functional overviewSTM32F479xx
2.20.1 Regulator ON
On packages embedding the BYPASS_REG pin, the regulator is enabled by holding
BYPASS_REG low. On all other packages, the regulator is always enabled.
There are three power modes configured by software when the regulator is ON:
MR mode used in Run/sleep modes or in Stop modes
–In Run/Sleep mode
The MR mode is used either in the normal mode (default mode) or the over-drive
mode (enabled by software). Different voltages scaling are provided to reach the
best compromise between maximum frequency and dynamic power consumption.
The over-drive mode allows operating at a higher frequency than the normal mode
for a given voltage scaling.
–In Stop modes
The MR can be configured in two ways during stop mode:
MR operates in normal mode (default mode of MR in stop mode)
MR operates in under-drive mode (reduced leakage mode).
LPR is used in the Stop modes:
The LP regulator mode is configured by software when entering Stop mode.
Like the MR mode, the LPR can be configured in two ways during stop mode:
–LPR operates in normal mode (default mode when LPR is ON)
–LPR operates in under-drive mode (reduced leakage mode).
Power-down is used in Standby mode.
The Power-down mode is activated only when entering in Standby mode. The regulator
output is in high impedance and the kernel circuitry is powered down, inducing zero
consumption. The contents of the registers and SRAM are lost.
Refer to Tab le 3 for a summary of voltage regulator modes versus device operating modes.
Two external ceramic capacitors should be connected on V
CAP_1
and V
CAP_2
Section 2.18 and Table 126.
All packages have the regulator ON feature.
Table 3. Voltage regulator configuration mode versus device operating mode
Voltage regulator
configuration
Normal modeMRMRMR or LPR-
Over-drive mode
Under-drive mode--MR or LPR-
Power-down mode---Yes
1. ‘-’ means that the corresponding configuration is not available.
2. The over-drive mode is not available when V
(2)
Run modeSleep modeStop modeStandby mode
MRMR--
= 1.7 to 2.1 V.
DD
pin. Refer to
(1)
32 /22 0DS 1111 8 Rev 6
STM32F479xxFunctional overview
ai18498V3
BYPASS_REG
V
CAP_1
V
CAP_2
PA0
V12
V
DD
NRST
V
DD
Application reset
signal (optional)
External V
CAP_1/2
power
supply supervisor
Ext. reset controller active
when V
CAP_1/2
< Min V
12
V12
2.20.2 Regulator OFF
This feature is available only on packages featuring the BYPASS_REG pin. The regulator is
disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply
externally a V
Since the internal voltage scaling is not managed internally, the external voltage value must
be aligned with the targeted maximum frequency. Refer to Operating conditions.The two
2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors. Refer
to Section 2.18.
voltage source through V
12
CAP_1
and V
CAP_2
pins.
When the regulator is OFF, there is no more internal monitoring on V
supply supervisor should be used to monitor the V
of the logic power domain. PA0 pin
12
should be used for this purpose, and act as power-on reset on V
. An external power
12
power domain.
12
In regulator OFF mode, the following features are no more supported:
PA0 cannot be used as a GPIO pin since it allows to reset a part of the V
logic power
12
domain which is not reset by the NRST pin.
As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As
a consequence, PA0 and NRST pins must be managed separately if the debug
connection under reset or pre-reset is required.
The over-drive and under-drive modes are not available.
The Standby mode is not available.
Figure 10. Regulator OFF
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Functional overviewSTM32F479xx
ai18491g
V
DD
time
Min V
12
PDR = 1.7 or 1.8 V
V
CAP_1
,
V
CAP_2
V
12
NRST
time
PA0
The following conditions must be respected:
V
must always be higher than V
DD
CAP_1
and V
to avoid current injection between
CAP_2
power domains.
If the time for V
V
to reach 1.7 V, then PA0 must be kept low to cover both conditions: until V
DD
and V
CAP_2
reach V
Otherwise, if the time for V
than the time for V
and V
CAP_1
minimum value and until V
12
CAP_1
to reach 1.7 V, then PA0 can be asserted low externally (see
DD
CAP_2
to reach V
and V
CAP_2
minimum value is faster than the time for
12
reaches 1.7 V (see Figure 11).
DD
to reach V
minimum value is slower
12
CAP_1
Figure 12).
If V
CAP_1
and V
CAP_2
go below V
minimum value and VDD is higher than 1.7 V, then a
12
reset must be asserted on PA0 pin.
Note:The minimum value of V
(see Operating conditions).
Figure 11. Startup in regulator OFF: slow V
- power-down reset risen after V
1. This figure is valid whatever the internal reset mode (ON or OFF).
depends on the maximum frequency targeted in the application
12
slope
CAP_1
, V
CAP_2
DD
stabilization
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STM32F479xxFunctional overview
V
DD
time
Min V
12
V
CAP_1
, V
CAP_2
V
12
PA0
NRST
time
ai18492f
PDR = 1.7 or 1.8 V
(2)
Figure 12. Startup in regulator OFF mode: fast VDD slope
- power-down reset risen before V
1. This figure is valid whatever the internal reset mode (ON or OFF).
CAP_1
, V
CAP_2
stabilization
2.20.3 Regulator ON/OFF and internal reset ON/OFF availability
Table 4. Regulator ON/OFF and internal reset ON/OFF availability
PackageRegulator ONRegulator OFFInternal reset ONInternal reset OFF
WLCSP168
UFBGA169
LQFP208
LQFP176
UFBGA176
TFBGA216
YesNo
Yes
BYPASS_REG set
to V
SS
Yes
BYPASS_REG set
to V
DD
Yes
PDR_ON set to V
PDR_ON set to V
DD
Yes
2.21 Real-time clock (RTC), backup SRAM and backup registers
The backup domain includes:
The real-time clock (RTC)
4 Kbytes of backup SRAM
20 backup registers
The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain
the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binarycoded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are
performed automatically. The RTC provides a programmable alarm and programmable
periodic interrupts with wakeup from Stop and Standby modes. The sub-seconds value is
also available in binary format.
SS
It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power
RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC
has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz
output to compensate for any natural quartz deviation.
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Two alarm registers are used to generate an alarm at a specific time and calendar fields can
be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit
programmable binary auto-reload downcounter with programmable resolution is available
and allows automatic wakeup and periodic alarms from every 120 µs to every 36 hours.
A 20-bit prescaler is used for the time base clock. It is by default configured to generate a
time base of 1 second from a clock at 32.768 kHz.
The 4-Kbyte backup SRAM is an EEPROM-like memory area. It can be used to store data
which need to be retained in VBAT and standby mode. This memory area is disabled by
default to minimize power consumption (see Section 2.22). It can be enabled by software.
The backup registers are 32-bit registers used to store 80 bytes of user application data
when V
power is not present. Backup registers are not reset by a system, a power reset,
DD
or when the device wakes up from the Standby mode (see Section 2.22).
Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes,
hours, day, and date.
Like backup SRAM, the RTC and backup registers are supplied through a switch that is
powered either from the V
supply when present or from the V
DD
BAT
pin.
2.22 Low-power modes
The devices support three low-power modes to achieve the best compromise between low
power consumption, short startup time and available wakeup sources:
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
Stop mode
The Stop mode achieves the lowest power consumption while retaining the contents of
SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled.
The voltage regulator can be put either in main regulator mode (MR) or in low-power
mode (LPR). Both modes can be configured as follows (see Tab le 5):
–Normal mode (default mode when MR or LPR is enabled)
–Under-drive mode.
The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup /
tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup).
Voltage regulator
configuration
Normal modeMR ON LPR ON
Table 5. Voltage regulator modes in stop mode
Main regulator (MR)Low-power regulator (LPR)
Under-drive modeMR in under-drive modeLPR in under-drive mode
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.2 V domain is powered off. The
36 /22 0DS 1111 8 Rev 6
STM32F479xxFunctional overview
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, the SRAM and register contents are lost except for registers in the
backup domain and the backup SRAM when selected.
The device exits the Standby mode when an external reset (NRST pin), an IWDG reset,
a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event
occurs.
The standby mode is not supported when the embedded voltage regulator is bypassed
and the 1.2 V domain is controlled by an external power.
2.23 V
The V
supercapacitor, or from V
operation
BAT
pin allows to power the device V
BAT
when no external battery neither an external supercapacitor are
DD
present.
V
operation is activated when VDD is not present.
BAT
The V
pin supplies the RTC, the backup registers and the backup SRAM.
BAT
Note:When the microcontroller is supplied from V
do not exit it from V
When PDR_ON pin is connected to V
more available and V
operation.
BAT
(Internal Reset OFF), the V
pin should be connected to VDD.
BAT
SS
2.24 Timers and watchdogs
The devices include two advanced-control timers, eight general-purpose timers, two basic
timers and two watchdog timers.
All timer counters can be frozen in debug mode.
Tab le 6 compares the features of the advanced-control, general-purpose and basic timers.
domain from an external battery, an external
BAT
, external interrupts and RTC alarm/events
BAT
functionality is no
BAT
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Functional overviewSTM32F479xx
Timer
type
Advanced
control
General
purpose
Basic
,
,
Counter
resolution
16-bit
32-bit
16-bit
16-bitUp
16-bitUp
16-bitUp
Timer
TIM1,
TIM8
TIM2,
TIM5
TIM3,
TIM4
TIM916-bitUp
TIM10
TIM11
TIM1216-bitUp
TIM13
TIM14
TIM6,
TIM7
Counter
type
Up,
Down,
Up/down
Up,
Down,
Up/down
Up,
Down,
Up/down
Table 6. Timer feature comparison
Prescaler
factor
Any integer
between 1
and 65536
Any integer
between 1
and 65536
Any integer
between 1
and 65536
Any integer
between 1
and 65536
Any integer
between 1
and 65536
Any integer
between 1
and 65536
Any integer
between 1
and 65536
Any integer
between 1
and 65536
DMA
request
generation
Yes4Yes90180
Yes4No4590/180
Yes4No4590/180
No2No90180
No1No90180
No2No4590/180
No1No4590/180
Yes0No4590/180
Capture/
compare
channels
Complementary
output
Max
interface
clock
(MHz)
Max
timer
clock
(MHz)
(1)
1. The maximum timer clock is either 90 or 180 MHz depending on TIMPRE bit configuration in the
RCC_DCKCFGR register.
2.24.1 Advanced-control timers (TIM1, TIM8)
The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators
multiplexed on 6 channels. They have complementary PWM outputs with programmable
inserted dead times. They can also be considered as complete general-purpose timers.
Their 4 independent channels can be used for:
Input capture
Output compare
PWM generation (edge- or center-aligned modes)
One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0100%).
The advanced-control timer can work together with the TIMx timers via the Timer Link
feature for synchronization or event chaining.
TIM1 and TIM8 support independent DMA request generation.
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STM32F479xxFunctional overview
2.24.2 General-purpose timers (TIMx)
There are ten synchronizable general-purpose timers embedded in the STM32F47x devices
(see Tab l e 6 for differences).
TIM2, TIM3, TIM4, TIM5
The STM32F47x include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3,
and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload up/down
counter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16-bit autoreload up/down counter and a 16-bit prescaler. They all feature 4 independent
channels for input capture/output compare, PWM or one-pulse mode output. This gives
up to 16 input capture/output compare/PWMs on the largest packages.
The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the
other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the
Timer Link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are
capable of handling quadrature (incremental) encoder signals and the digital outputs
from 1 to 4 hall-effect sensors.
TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9
and TIM12 have two independent channels for input capture/output compare, PWM or
one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5
full-featured general-purpose timers. They can also be used as simple time bases.
2.24.3 Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger and waveform generation. They can also be
used as a generic 16-bit time base.
TIM6 and TIM7 support independent DMA request generation.
2.24.4 Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes.
2.24.5 Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
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Functional overviewSTM32F479xx
2.24.6 SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
downcounter. It features:
a 24-bit downcounter
autoreload capability
maskable system interrupt generation when the counter reaches 0
programmable clock source.
2.25 Inter-integrated circuit interface (I2C)
Up to three I²C bus interfaces can operate in multimaster and slave modes. They can
support the standard (up to 100 KHz), and fast (up to 400 KHz) modes. They support the
7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). A hardware CRC
generation/verification is embedded.
The I²C bus interfaces can be served by DMA and support SMBus 2.0/PMBus.
The devices also include programmable analog and digital noise filters (see Tabl e 7).
Table 7. Comparison of I2C analog and digital filters
FilterAnalogDigital
Pulse width of suppressed spikes 50 nsProgrammable length, from one to fifteen I2C peripheral clocks
The devices embed four universal synchronous/asynchronous receiver transmitters
(USART1, USART2, USART3 and USART6) and four universal asynchronous receiver
transmitters (UART4, UART5, UART7, and UART8).
These six interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to
communicate at speeds of up to 11.25 Mbit/s. The other available interfaces communicate
at up to 5.62 bit/s.
USART1, USART2, USART3 and USART6 also provide hardware management of the CTS
and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication
capability. All interfaces can be served by the DMA controller.
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STM32F479xxFunctional overview
Name
USART1XXXXXX5.6211.25
USART2XXXXXX2.815.62
USART3XXXXXX2.815.62
UART4X-X-X-2.815.62
UART5X-X-X-2.815.62
USART6XXXXXX5.6211.25
UART7X-X-X-2.815.62
UART8X-X-X-2.815.62
1. X = feature supported.
Standard
features
Modem
(RTS/CTS)
Table 8. USART feature comparison
LIN
SPI
master
irDA
Smartcard
(ISO 7816)
(1)
Max. baud rate in Mbit/s
Oversampling
by 16
Oversampling
by 8
APB
mapping
APB2
(max.
90 MHz)
APB1
(max.
45 MHz)
APB1
(max.
45 MHz)
APB1
(max.
45 MHz)
APB1
(max.
45 MHz)
APB2
(max.
90 MHz)
APB1
(max.
45 MHz)
APB1
(max.
45 MHz)
2.27 Serial peripheral interface (SPI)
The devices feature up to six SPIs in slave and master modes in full-duplex and simplex
communication modes. SPI1, SPI4, SPI5, and SPI6 can communicate at up to 45 Mbits/s,
SPI2 and SPI3 can communicate at up to 22.5 Mbit/s. The 3-bit prescaler gives 8 master
mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the
DMA controller.
The SPI interface can be configured to operate in TI mode for communications in master
mode and slave mode.
2.28 Inter-integrated sound (I2S)
Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can be
operated in master or slave mode, in full duplex and simplex communication modes, and
can be configured to operate with a 16-/32-bit resolution as an input or output channel.
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Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of
2
the I
S interfaces is/are configured in master mode, the master clock can be output to the
external DAC/CODEC at 256 times the sampling frequency.
All I2Sx can be served by the DMA controller.
Note:For I2S2 full-duplex mode, I2S2_CK and I2S2_WS signals can be used only on GPIO Port
B and GPIO Port D.
2.29 Serial Audio interface (SAI1)
The serial audio interface (SAI1) is based on two independent audio sub-blocks which can
operate as transmitter or receiver with their FIFO. Many audio protocols are supported by
each block: I2S standards, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF
output, supporting audio sampling frequencies from 8 kHz up to 192 kHz. Both sub-blocks
can be configured in master or in slave mode.
In master mode, the master clock can be output to the external DAC/CODEC at 256 times of
the sampling frequency.
The two sub-blocks can be configured in synchronous mode when full-duplex mode is
required.
SAI1 can be served by the DMA controller.
2.30 Audio PLL (PLLI2S)
The devices feature an additional dedicated PLL for audio I2S and SAI applications. It allows
to achieve error-free I
performance, while using USB peripherals.
The PLLI2S configuration can be modified to manage an I
without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.
The audio PLL can be programmed with very low error to obtain sampling rates ranging
from 8 KHz to 192 KHz.
In addition to the audio PLL, a master clock input pin can be used to synchronize the
2
I
S/SAI flow with an external PLL (or Codec output).
2
S sampling clock accuracy without compromising on the CPU
2
S/SAI sample rate change
2.31 Audio and LCD PLL(PLLSAI)
An additional PLL dedicated to audio and LCD-TFT is used for SAI1 peripheral in case the
PLLI2S is programmed to achieve another audio sampling frequency (49.152 MHz or
11.2896 MHz) and the audio application requires both sampling frequencies simultaneously.
The PLLSAI is also used to generate the LCD-TFT clock.
2.32 Secure digital input/output interface (SDIO)
An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System
Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.
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STM32F479xxFunctional overview
The interface allows data transfer at up to 48 MHz, and is compliant with the SD Memory
Card Specification Version 2.0.
The SDIO Card Specification Version 2.0 is also supported with two different databus
modes: 1-bit (default) and 4-bit.
The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack
of MMC4.1 or previous.
In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital
protocol Rev1.1.
2.33 Ethernet MAC interface with dedicated DMA and IEEE 1588
support
The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for
ethernet LAN communications through an industry-standard medium-independent interface
(MII) or a reduced medium-independent interface (RMII). The microcontroller requires an
external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair,
fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals
for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller.
The devices include the following features:
Supports 10 and 100 Mbit/s rates
Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM
and the descriptors (see the STM32F4xx reference manual for details)
Tagged MAC frame support (VLAN support)
Half-duplex (CSMA/CD) and full-duplex operation
MAC control sublayer (control frames) support
32-bit CRC generation and removal
Several address filtering modes for physical and multicast address (multicast and
group addresses)
32-bit status code for each transmitted or received frame
Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the
receive FIFO are both 2 Kbytes.
Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008
(PTP V2) with the time stamp comparator connected to the TIM2 input
Triggers interrupt when system time becomes greater than target time
2.34 Controller area network (bxCAN)
The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1
Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive
FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one
CAN is used). 256 bytes of SRAM are allocated for each CAN.
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2.35 Universal serial bus on-the-go full-speed (OTG_FS)
The device embeds an USB OTG full-speed device/host/OTG peripheral with integrated
transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and
with the OTG 2.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
The main features are:
Combined Rx and Tx FIFO size of 1.28 KB with dynamic FIFO sizing
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
1 bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints
12 host channels with periodic OUT support
Software configurable to OTG1.3 and OTG2.0 modes of operation
USB 2.0 LPM (Link Power Management) support
Internal FS OTG PHY support
HNP/SNP/IP inside (no need for any external resistor)
For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
2.36 Universal serial bus on-the-go high-speed (OTG_HS)
The device embeds a USB OTG high-speed (up to 480 Mb/s) device/host/OTG peripheral.
The USB OTG HS supports both full-speed and high-speed operations. It integrates the
transceivers for full-speed operation (12 MB/s) and features a UTMI low-pin interface (ULPI)
for high-speed operation (480 MB/s). When using the USB OTG HS in HS mode, an
external PHY device connected to the ULPI is required.
The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG
2.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
The main features are:
Combined Rx and Tx FIFO size of 4 KB with dynamic FIFO sizing
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
8 bidirectional endpoints
16 host channels with periodic OUT support
Software configurable to OTG1.3 and OTG2.0 modes of operation
USB 2.0 LPM (Link Power Management) support
Internal FS OTG PHY support
External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is
connected to the microcontroller ULPI port through 12 signals. It can be clocked using
the 60 MHz output.
Internal USB DMA
HNP/SNP/IP inside (no need for any external resistor)
for OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
44 /22 0DS 1111 8 Rev 6
STM32F479xxFunctional overview
2.37 Digital camera interface (DCMI)
The devices embed a camera interface that can connect with camera modules and CMOS
sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera
interface can sustain a data transfer rate up to 54 Mbyte/s at 54 MHz. It features:
Programmable polarity for the input pixel clock and synchronization signals
Parallel data communication can be 8-, 10-, 12- or 14-bit
Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
Supports continuous mode or snapshot (a single frame) mode
Capability to automatically crop the image black & white.
2.38 Cryptographic accelerator
The devices embed a cryptographic accelerator. This cryptographic accelerator provides a
set of hardware acceleration for the advanced cryptographic algorithms usually needed to
provide confidentiality, authentication, data integrity and non repudiation when exchanging
messages with a peer.
These algorithms consists of:
Encryption/Decryption
–DES/TDES (data encryption standard/triple data encryption standard): ECB
(electronic codebook) and CBC (cipher block chaining) chaining algorithms, 64,128- or 192-bit key
mode) chaining algorithms, 128, 192 or 256-bit key
Universal hash
–SHA-1 and SHA-2 (secure hash algorithms)
–MD5
–HMAC
The cryptographic accelerator supports DMA request generation.
2.39 Random number generator (RNG)
All devices embed an RNG that delivers 32-bit random numbers generated by an integrated
analog circuit.
2.40 General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
DS 1111 8 Rev 645/ 2 2 0
47
Functional overviewSTM32F479xx
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
Fast I/O handling allowing maximum I/O toggling up to 90 MHz.
2.41 Analog-to-digital converters (ADCs)
Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16
external channels, performing conversions in the single-shot or scan mode. In scan mode,
automatic conversion is performed on a selected group of analog inputs.
Additional logic functions embedded in the ADC interface allow:
Simultaneous sample and hold
Interleaved sample and hold
The ADC can be served by the DMA controller. An analog watchdog feature allows very
precise monitoring of the converted voltage of one, some or all selected channels. An
interrupt is generated when the converted voltage is outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,
TIM2, TIM3, TIM4, TIM5, or TIM8 timer.
2.42 Temperature sensor
The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally
connected to the same input channel as V
sensor output voltage into a digital value. When the temperature sensor and V
conversion are enabled at the same time, only V
As the offset of the temperature sensor varies from chip to chip due to process variation, the
internal temperature sensor is mainly suitable for applications that detect temperature
changes instead of absolute temperatures. If an accurate temperature reading is needed,
then an external temperature sensor part should be used.
, ADC1_IN18, which is used to convert the
BAT
2.43 Digital-to-analog converter (DAC)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs.
conversion is performed.
BAT
BAT
46 /22 0DS 1111 8 Rev 6
STM32F479xxFunctional overview
This dual digital Interface supports the following features:
two DAC converters: one for each output channel
8-bit or 10-bit monotonic output
left or right data alignment in 12-bit mode
synchronized update capability
noise-wave generation
triangular-wave generation
dual DAC channel independent or simultaneous conversions
DMA capability for each channel
external triggers for conversion
input voltage reference V
Eight DAC trigger inputs are used in the device. The DAC channels are triggered through
the timer update outputs that are also connected to different DMA streams.
REF+
2.44 Serial wire JTAG debug port (SWJ-DP)
The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could
be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
2.45 Embedded Trace Macrocell™
The Arm Embedded Trace Macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F47x through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or
any other high-speed channel. Real-time instruction and data flow activity can be recorded
and then formatted for display on the host computer that runs the debugger software. TPA
hardware is commercially available from common development tool vendors.
The Embedded Trace Macrocell operates with third party debugger software tools.
DS 1111 8 Rev 647/ 2 2 0
47
Pinouts and pin descriptionSTM32F479xx
MS40560V1
LQFP100
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
9
11
4
6
8
1
2
3
5
7
PH1
PC0
PC1
PC2
PC3
VSSA
VREF+
VDDA
PA0
PA1
PA2
PA3
VSS
VDD
PA4
PH0
NRST
PC13
PC15
VDD
PE2
VSS
VBAT
PC14
VSS
66
64
63
62
61
60
59
58
57
56
55
54
53
52
51
67
65
72
70
68
75
74
73
71
69
91
89888786858483828180797877
76
92
90
97
95
93
100
99
98
96
94
35
37383940414243444546474849
50
34
36
29
31
33
262728
30
32
PA5
PA6
PB1
PE8
PE12
PA7
PB0
PE9
PE14
PB11
PB2
PE7
PE15
VCAP1
PB12
PE10
PE11
VSS
PB13
PB15
PE13
PB10
VDD
PB14
PD8
PC6
DSIHOST_D1N
DSIHOST_D1P
VDD12DSI
DSIHOST_CKN
DSIHOST_CKP
VSSDSI
DSIHOST_D0N
DSIHOST_D0P
VCAPDSI
VDDDSI
PD15
PD14
PD10
PD9
PC7
VDDUSB
PA10
PA8
PC8
PA13
PA12
PA11
PA9
PC9
VDD
PB9
PB7
PB4
PD5
PB8
BOOT0
PB3
PD3
PD0
PB6
PB5
PD2
PC12
PA15
PD7
PD6
PC11
PA14
VDD
PD4
PD1
PC10
VSS
VCAP2
3 Pinouts and pin description
Figure 13. STM32F47x LQFP100 pinout
1. The above figure shows the package top view.
48 /22 0DS 1111 8 Rev 6
STM32F479xxPinouts and pin description
MS40561V2
LQFP144
21
23
24
25
26
27
28
29
30
31
32
33
34
35
36
20
22
15
17
19
13
14
16
18
PC0
PC2
PC3
VDD
VSSA
VREF+
VDDA
PA0
PA1
PA2
PA3
VSS
VDD
PA4
PA5
NRST
PC1
VSS
PF10
PH1
PF4
PF5
VDD
PH0
88
86
85
84
83
82
81
80
79
78
77
76
75
74
73
89
87
94
92
90
97
96
95
93
91
135
133
132
131
130
129
128
127
126
125
124
123
122
121
136
134
141
139
137
144
143
142
140
138
47
49505152535455565758596061
72
46
48
41
43
45
383940
42
44
PA7
PC4
PB1
PF12
PF15
PC5
PB0
VDD
PG1
PE9
PB2
PF11
PE7
VSS
PE11
PF13
PF14
VDD
PE12
PE14
PG0
PE8
PE10
PE13
PD9
DSIHOST_D1P
DSIHOST_CKN
DSIHOST_CKP
VSSDSI
DSIHOST_D0N
DSIHOST_D0P
VCAPDSI
VDDDSI
PD15
PD14
VDD
VSS
PD12
PD11
PD10
DSIHOST_D1N
VDD12DSI
PG6
PG4
PG2
VDDUSB
PG8
PG7
PG5
PG3
PE2
VDD
PE0
BOOT0
PB4
PDR_ON
PE1
PB7
PG15
PG12
PB9
PB8
VDD
PG11
PD6
PB6
PB5
PG10
VDD
PD5
PB3
VSS
PG9
VSS
120PD4
119PD3
118PD2
117PD1
116PD0
115PC12
114PC11
113PC10
112PA15
111PA14
110VDD
109VSS
108VCAP2
104
107
106
105
103
PA10
PA13
PA12
PA11
PA9
9998PC7
PC6
101
100
PC9
PC8
102PA8
686970
71
PB13
PB14
PD8
PB15
646566
67
PB11
VCAP1
PB12
VDD
62
63
PE15
PB10
37
PA6
12
11
6
8
10
4
5
7
9
PF3
PF2
PC13
PC15
PF1
PE6
VBAT
PC14
PF0
3PE5
2PE4
1PE3
Figure 14. STM32F47x LQFP144 pinout
1. The above figure shows the package top view.
DS 1111 8 Rev 649/ 2 2 0
83
Pinouts and pin descriptionSTM32F479xx
MSv35729V2
121110987654321
PI7VDDPE0PB7PB3VDDPG12PD7VSSPD1PA15PI2
PE5
A
B
C
D
E
F
G
H
J
K
L
M
N
P
PI6
VSS
PB8
PB5
VSS
PG11
VDD
PD4
PC11
PI3
PH13
VBAT
PE4
PI5
PE1
PB4
PG10
PD5
PD2
PC12
PI1
VDD
VSS
PC13
PE6
PI4
PDR_
ON
PG15
PG9
PD3
PC10
PA14
PH14
VCAP2
PA13
PC15
PC14
PE3
PB9
PG13
PD6
PD0
PI0
PH15
PA10
PA9
PA8
VSS
PI11
PI10
PE2
BOOT0
PA11
PA12
PC9
PC8
PC6
VSS
VDD
USB
PF2
VDD
PF0
PI9
PB6
PC7
PG8
PG2
PG3
PG6
PG4
PG5
PF5
PF3
PF1
NRST
PF15
VSS
PG7
PB12
PD13
DSI
HOST
_D1P
DSI
HOST
_D1N
VSS
DSI
VDD
VSS
PF4
PC0
PA7
PF13
PG0
PE14
PD11
DSI
HOST
_D0N
DSI
HOST
_CKN
DSI
HOST
_CKP
PH1
PH0
PF10
PA1
PH5
PF11
PE9
PB11
PB13
DSI
HOST
_D0P
VDD12
DSI
VCAP
DSI
PC1
VSSA
PA0
PA2
PA5
PF14
PE13
PH9
PD8
PD14
PD15
VDD
DSI
VDDA
PH2
PH4
PA4
PF12
PE8
PE12
PH8
PH10
PD10
PD12
VSS
PH3
VSS
PA3
PB1
VSS
PE7
PE11
VCAP1
PH11
PB15
PD9
PB10
VDD
PA6
PB0
PB2
VDD
PG1
PE10
PE15
VSS
VDD
PH12
PB14
Figure 15. STM32F47x WLCSP168 pinout
1. The above figure shows the package bottom view.
Table 10. STM32F479xx pin and ball definitions (continued)
Pin number
Pin name
(function after
LQFP100
LQFP144
UFBGA169
WLCSP168
UFBGA176
LQFP176
LQFP208
TFBGA216
reset)
(1)
Pin types
I/O structures
Alternate functions
Notes
77110 D10 C2 G13 131 150 F11VDDS----
TIM8_CH1N, CAN1_TX,
--D9B1--151 E12PH13I/OFT-
FMC_D21, LCD_G2,
EVENTOUT
TIM8_CH2N, FMC_D22,
--C13 D3--152 E13PH14I/OFT-
DCMI_D4, LCD_G3,
EVENTOUT
TIM8_CH3N, FMC_D23,
--C12 E4--153 D13PH15I/OFT-
DCMI_D11, LCD_G4,
EVENTOUT
TIM5_CH4,
--B13E5 E14 132 154 E14PI0I/OFT-
SPI2_NSS/I2S2_WS
FMC_D24, DCMI_D13,
LCD_G5, EVENTOUT
(7)
--C11 C3 D14 133 155 D14PI1I/OFT-
SPI2_SCK/I2S2_CK
FMC_D25, DCMI_D8,
LCD_G6, EVENTOUT
TIM8_CH4, SPI2_MISO,
--B12A1-
NC
156 C14PI2I/OFT-
(2)
I2S2ext_SD, FMC_D26,
DCMI_D9, LCD_G7,
EVENTOUT
TIM8_ETR,
--B10B2 C13 134 157 C13PI3I/OFT-
SPI2_MOSI/I2S2_SD,
FMC_D27, DCMI_D10,
EVENTOUT
78---D9 135-F9VSSS----
---B5C9 136 158 E10VDDS----
79111 A10 D4 A14 137 159 A14
PA14(JTCK-
SWCLK)
I/OFT-JTCK-SWCLK, EVENTOUT-
JTDI,
TIM2_CH1/TIM2_ETR,
80112 B11 A2 A13 138 160 A13PA15(JTDI)I/OFT-
SPI1_NSS,
SPI3_NSS/I2S3_WS,
EVENTOUT
SPI3_SCK/I2S3_CK,
USART3_TX, UART4_TX,
81113 C10 D5 B14 139 161 B14PC10I/OFT-
QUADSPI_BK1_IO1,
SDIO_D2, DCMI_D8,
LCD_R2, EVENTOUT
I2S3ext_SD, SPI3_MISO,
USART3_RX, UART4_RX,
82114 B9B3 B13 140 162 B13PC11I/OFT-
QUADSPI_BK2_NCS,
SDIO_D3, DCMI_D4,
EVENTOUT
(7)
,
,
Additional
functions
-
-
-
-
-
-
-
-
-
-
66 /22 0DS 1111 8 Rev 6
STM32F479xxPinouts and pin description
Table 10. STM32F479xx pin and ball definitions (continued)
Pin number
Pin name
(function after
LQFP100
LQFP144
UFBGA169
WLCSP168
83115 A9C4 A12 141 163 A12PC12I/OFT-
84116 C9E6 B12 142 164 B12PD0I/OFT-
85117 C7A3 C12 143 165 C12PD1I/OFT-
86118 B8C5 D12 144 166 D12PD2I/OFT-
87119 C8D6 D11 145 167 C11PD3I/OFT-
88 120 C6B4 D10 146 168 D11PD4I/OFT-
89 121B7C6 C11 147 169 C10PD5I/OFT-
-122F8A4D8 148 170F8VSSS----
-123F7-C8149 171E9VDDS----
90 124 D7E7B11 150 172 B11PD6I/OFT-
91-A8A5A11 151 173 A11PD7I/OFT-
------174B10 PJ12 I/OFT-
------175B9PJ13I/OFT-
------176C9PJ14I/OFT-LCD_B2, EVENTOUT-
------177 D10PJ15I/OFT-LCD_B3, EVENTOUT-
-125E6D7 C10 152 178 D9PG9I/OFT-
-126E7C7 B10 153 179 C8PG10I/OFT-
-127B6B6B9154 180B8PG11I/OFT-
UFBGA176
LQFP176
LQFP208
TFBGA216
reset)
(1)
Pin types
I/O structures
Alternate functions
Notes
TRACED3,
SPI3_MOSI/I2S3_SD,
USART3_CK, UART5_TX,
SDIO_CK, DCMI_D9,
EVENTOUT
CAN1_RX, FMC_D2,
EVENTOUT
CAN1_TX, FMC_D3,
EVENTOUT
TRACED2, TIM3_ETR,
UART5_RX, SDIO_CMD,
DCMI_D11, EVENTOUT
SPI2_SCK/I2S2_CK,
USART2_CTS, FMC_CLK,
DCMI_D5, LCD_G7,
EVENTOUT
USART2_RTS, FMC_NOE,
EVENTOUT
USART2_TX, FMC_NWE,
EVENTOUT
SPI3_MOSI/I2S3_SD,
SAI1_SD_A, USART2_RX,
FMC_NWAIT, DCMI_D10,
LCD_B2, EVENTOUT
USART2_CK, FMC_NE1,
EVENTOUT
LCD_G3, LCD_B0,
EVENTOUT
LCD_G4, LCD_B1,
EVENTOUT
USART6_RX,
QUADSPI_BK2_IO2,
FMC_NE2/FMC_NCE,
DCMI_VSYNC, EVENTOUT
LCD_G3, FMC_NE3,
DCMI_D2, LCD_B2,
EVENTOUT
ETH_MII_TX_EN/ETH_RMI
I_TX_EN, DCMI_D3,
LCD_B3, EVENTOUT
Additional
functions
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DS 1111 8 Rev 667/ 2 2 0
83
Pinouts and pin descriptionSTM32F479xx
Table 10. STM32F479xx pin and ball definitions (continued)
Pin number
Pin name
(function after
LQFP100
LQFP144
UFBGA169
WLCSP168
-128A7A6B8155 181C7PG12I/OFT-
--A6E8A8 156 182 B3PG13I/OFT-
----A7 157 183 A4PG14I/OFT-
-129-B7D7 158 184F7VSSS----
-130-A7C7 159 185E8VDDS----
------186D8PK3I/OFT-LCD_B4, EVENTOUT-
------187D7PK4I/OFT-LCD_B5, EVENTOUT-
------188C6PK5I/OFT-LCD_B6, EVENTOUT-
------189C5PK6I/OFT-LCD_B7, EVENTOUT-
------190C4PK7I/OFT-LCD_DE, EVENTOUT-
-131F6D8B7 160 191B7PG15I/OFT-
92 132B5A8 A10 161 192 A10
93 133 D6C8A9 162 193 A9PB4(NJTRST)I/OFT-
94 134 D5B8A6163 194 A8PB5I/OFT-
95 135 C5G8B6 164 195 B6PB6I/OFT-
UFBGA176
LQFP176
LQFP208
TFBGA216
PB3(JTDO/TRA
(1)
reset)
CESWO)
Pin types
I/O structures
I/OFT-
Alternate functions
Notes
SPI6_MISO,
USART6_RTS, LCD_B4,
FMC_NE4, LCD_B1,
EVENTOUT
TRACED0, SPI6_SCK,
USART6_CTS,
ETH_MII_TXD0/ETH_RMII
_TXD0, FMC_A24,
LCD_R0, EVENTOUT
TRACED1, SPI6_MOSI,
USART6_TX,
QUADSPI_BK2_IO3,
ETH_MII_TXD1/ETH_RMII
_TXD1, FMC_A25,
LCD_B0, EVENTOUT
USART6_CTS,
FMC_SDNCAS,
DCMI_D13, EVENTOUT
JTDO/TRACESWO,
TIM2_CH2, SPI1_SCK,
SPI3_SCK/I2S3_CK,
EVENTOUT
NJTRST, TIM3_CH1,
SPI1_MISO, SPI3_MISO,
I2S3ext_SD, EVENTOUT
TIM3_CH2, I2C1_SMBA,
SPI1_MOSI,
SPI3_MOSI/I2S3_SD,
CAN2_RX,
OTG_HS_ULPI_D7,
ETH_PPS_OUT,
FMC_SDCKE1, DCMI_D10,
LCD_G7, EVENTOUT
TIM4_CH1, I2C1_SCL,
USART1_TX, CAN2_TX,
QUADSPI_BK1_NCS,
FMC_SDNE1, DCMI_D5,
EVENTOUT
Additional
functions
-
-
-
-
-
-
-
-
68 /22 0DS 1111 8 Rev 6
STM32F479xxPinouts and pin description
Table 10. STM32F479xx pin and ball definitions (continued)
Pin number
Pin name
(function after
LQFP100
LQFP144
UFBGA169
WLCSP168
UFBGA176
LQFP176
LQFP208
TFBGA216
reset)
(1)
Pin types
I/O structures
Alternate functions
Notes
TIM4_CH2, I2C1_SDA,
96 136B4A9B5 165 196B5PB7I/OFT-
USART1_RX, FMC_NL,
DCMI_VSYNC, EVENTOUT
97 137A5F8D6 166 197 E6BOOT0IB--VPP
TIM4_CH3, TIM10_CH1,
I2C1_SCL, CAN1_RX,
98 138 D4B9A5167 198 A7PB8I/OFT-
ETH_MII_TXD3, SDIO_D4,
DCMI_D6, LCD_B6,
EVENTOUT
TIM4_CH4, TIM11_CH1,
I2C1_SDA,
99 139 C4E9B4168 199 B4PB9I/OFT-
SPI2_NSS/I2S2_WS,
CAN1_TX, SDIO_D5,
DCMI_D7, LCD_B7,
EVENTOUT
NC
140 A4 A10A4 169 200 A6PE0I/OFT-
(2)
TIM4_ETR, UART8_Rx,
FMC_NBL0, DCMI_D2,
EVENTOUT
NC
141 A3C9A3 170 201A5PE1I/OFT-
(2)
UART8_Tx, FMC_NBL1,
DCMI_D3, EVENTOUT
--E3 B10 D5-202F6VSSS----
-142 C3D9C6 171 203 E5PDR_ONS----
100 143 D3A11 C5 172 204E7VDDS----
TIM8_BKIN, FMC_NBL2,
--B3 D10 D4 173 205C3PI4I/OFT-
DCMI_D5, LCD_B4,
EVENTOUT
TIM8_CH1, FMC_NBL3,
--A2 C10 C4 174 206D3PI5I/OFT-
DCMI_VSYNC, LCD_B5,
EVENTOUT
TIM8_CH2, FMC_D28,
--A1B11 C3 175 207 D6PI6I/OFT-
DCMI_D6, LCD_B6,
EVENTOUT
TIM8_CH3, FMC_D29,
--B1 A12 C2 176 208 D4PI7I/OFT-
DCMI_D7, LCD_B7,
EVENTOUT
1. Function availability depends on the chosen device.
2. NC (not-connected) pins are not bonded. They must be configured by software to output push-pull and forced to “0” in the
output data register to avoid extra current consumption in low power modes.
3. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF.
- These I/Os must not be used as a current source (e.g. to drive an LED).
4. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after
reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC
register description sections in the STM32F4xx reference manual, available from www.st.com.
5. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).
Additional
functions
-
-
-
-
-
-
-
-
-
DS 1111 8 Rev 669/ 2 2 0
83
Pinouts and pin descriptionSTM32F479xx
6. If the device is delivered in an WLCSP168, UFBGA169, UFBGA176, LQFP176 or TFBGA216 package, and the
BYPASS_REG pin is set to VDD (Regulator OFF/internal reset ON mode), then PA0 is used as an internal Reset (active
low).
7. PI0 and PI1 cannot be used for I2S2 full-duplex mode.
1. The reserved boundary address are shown in grayed cells
88 /22 0DS 1111 8 Rev 6
STM32F479xxElectrical characteristics
5 Electrical characteristics
5.1 Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
5.1.1 Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3σ).
5.1.2 Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the
1.7 V V
tested.
3.6 V voltage range). They are given only as design guidelines and are not
DD
= 25 °C and TA = TAmax (given by
A
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated
5.1.3 Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4 Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 22.
5.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 23.
Figure 22. Pin loading conditionsFigure 23. Pin input voltage
C = 50 pF
MCU pin
(mean±2σ).
MCU pin
V
IN
MS19011V2
DS 1111 8 Rev 689/ 2 2 0
MS19010V2
191
Electrical characteristicsSTM32F479xx
MS38256V1
Backup circuitry
(OSC32K,RTC,
Wakeup logic
Backup registers,
backup RAM)
Kernel logic
(CPU, digital
& RAM)
Analog:
RCs, PLL,..
Power
switch
V
BAT
GPIOs
OUT
IN
20 × 100 nF
+ 1 × 4.7 μF
V
BAT
= 1.65 to 3.6 V
Voltage
regulator
V
DDA
ADC
Level shifter
IO
Logic
V
DD
100 nF
+ 1 μF
Flash memory
V
CAP_1
V
CAP_2
2 × 2.2 μF
BYPASS_REG
PDR_ON
Reset
controller
V
DD
1/2/...19/20
V
SS
1/2/...19/20
V
DD
V
REF+
V
REF-
V
SSA
V
REF
100 nF
+ 1 μF
OTG-FS
PHY
V
DDUSB
100 nF
V
DDUSB
DSI
PHY
DSI
Voltage
regulator
V
DDDSI
V
CAPDSI
V
DD12DSI
V
SSDSI
2.2 μF
5.1.6 Power supply scheme
Figure 24. Power supply scheme
1. To connect BYPASS_REG and PDR_ON pins, refer to Section 2.19 and Section 2.20.
2. The two 2.2 µF ceramic capacitors on V
Caution:Each power supply pair (VDD/VSS, V
capacitors when the voltage regulator is OFF.
3. The 4.7 µF ceramic capacitor must be connected to one of the V
DDA
and V
4. V
capacitors as shown above. These capacitors must be placed as close as possible to, or
must be connected to VDD and VSS, respectively.
SSA
below, the appropriate pins on the underside of the PCB to ensure good operation of the
device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.
This might cause incorrect operation of the device.
CAP_1
DDA/VSSA
and V
should be replaced by two 100 nF decoupling
CAP_2
pin.
DD
...) must be decoupled with filtering ceramic
90 /22 0DS 1111 8 Rev 6
STM32F479xxElectrical characteristics
ai14126
V
BAT
V
DD
V
DDA
IDD_V
BAT
I
DD
5.1.7 Current consumption measurement
Figure 25. Current consumption measurement scheme
5.2 Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Tab le 14 , Table 15, and Tabl e 16
may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these conditions is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
Table 14. Voltage characteristics
SymbolRatingsMinMaxUnit
V
DD–VSS
External main supply voltage
(including V
Input voltage on FT pins
DDA, VDD, VDDUSB, VDDDSI
(2)
and V
BAT
(1)
)
Input voltage on TTa pinsV
V
IN
Input voltage on any other pinV
Input voltage on BOOT pin V
|Variations between different VDD power pins-50
|V
DDx
|V
SSX VSS
V
ESD(HBM)
1. All main power (VDD, V
the external power supply, in the permitted range.
2. VIN maximum value must always be respected. Refer to Ta bl e 1 5 for the values of the maximum allowed
injected current.
3. Including V
|Variations between all the different ground pins
Electrostatic discharge voltage (human body model)see Section 5.3.18
REF-
pin
DDA
, V
DDUSB
, V
) and ground (VSS, V
DDDSI
(3)
) pins must always be connected to
SSA
− 0.34.0
VSS− 0.3 VDD+4.0
− 0.34.0
SS
− 0.34.0
SS
SS
9.0
-50
V
mV
DS 1111 8 Rev 691/ 2 2 0
191
Electrical characteristicsSTM32F479xx
Table 15. Current characteristics
SymbolRatings Max.Unit
(1)
(1)
(1)
(1)
290
− 290
100
− 100
I
I
I
VDDUSB
I
I
VDD
VSS
VDD
VSS
Total current into sum of all V
DD_x
Total current out of sum of all V
Total current into V
Maximum current into each V
power line (source)25
DDUSB
DD_x
Maximum current out of each V
power lines (source)
ground lines (sink)
SS_x
power line (source)
ground line (sink)
SS_x
Output current sunk by any I/O and control pin25
I
IO
I
IO
I
INJ(PIN)
I
INJ(PIN)
1. All main power (VDD, V
supply, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
LQFP packages.
3. Negative injection disturbs the analog performance of the device. See note in Section 5.3.24.
4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
5. A positive injection is induced by VIN>V
never be exceeded. Refer to Table 14 for the values of the maximum allowed input voltage.
6. When several inputs are submitted to a current injection, the maximum ΣI
positive and negative injected currents (instantaneous values).
Output current sourced by any I/Os and control pin− 25
Total output current sunk by sum of all I/O and control pins
(2)
Total output current sunk by sum of all USB I/Os25
Total output current sourced by sum of all I/Os and control pins
Injected current on FT pins
(3)
Injected current on NRST and BOOT0 pins
Injected current on TTa pins
(5)
Total injected current (sum of all I/O and control pins)
) and ground (VSS, V
DDA
(4)
(4)
(5)
(6)
) pins must always be connected to the external power
SSA
while a negative injection is induced by VIN<VSS. I
DDA
is the absolute sum of the
INJ(PIN)
(2)
120
− 120
− 5/+0
±5
±25
INJ(PIN)
mA
must
Table 16. Thermal characteristics
SymbolRatings ValueUnit
T
STG
T
J
Storage temperature range− 65 to +150°C
Maximum junction temperature125°C
92 /22 0DS 1111 8 Rev 6
STM32F479xxElectrical characteristics
5.3 Operating conditions
5.3.1 General operating conditions
Table 17. General operating conditions
SymbolParameter Conditions
Power Scale 3 (VOS[1:0] bits in PWR_CR
register = 0x01),
Regulator ON, over-drive OFF
Power Scale 2 (VOS[1:0] bits
in PWR_CR register = 0x10),
f
HCLK
Internal AHB clock frequency
Regulator ON
Power Scale 1 (VOS[1:0] bits
in PWR_CR register= 0x11),
Regulator ON
Over-drive OFF0 -42
f
PCLK1
Internal APB1 clock frequency
Over-drive ON0 -45
Over-drive OFF0 -84
f
PCLK2
V
Internal APB2 clock frequency
Over-drive ON0 -90
Standard operating voltage-1.7
DD
Analog operating voltage
V
DDA
Analog operating voltage
Must be the same potential as V
(ADC limited to 1.2 M samples)
(3)(4)
(ADC limited to 2.4 M samples)
V
DDUSB
V
DDDSI
V
BAT
USB supply voltage
(supply voltage for PA11, PA12,
PB14 and PB15 pins)
DSI system operating voltage-1.7
Backup operating voltage-1.65-3.6
USB not used03.33.6
USB used3.0-3.6
(1)
Over-drive
OFF
Over-drive
ON
Over-drive
OFF
Over-drive
ON
(5)
DD
MinTypMaxUnit
0-120
-144
0
-168
-168
MHz
0
-180
(2)
-3.6
(2)
1.7
-2.4
2.4-3.6
(2)
-3.6
V
DS 1111 8 Rev 693/ 2 2 0
191
Electrical characteristicsSTM32F479xx
Table 17. General operating conditions (continued)
SymbolParameter Conditions
Power Scale 3 ((VOS[1:0] bits in
PWR_CR register = 0x01), 120 MHz
HCLK max frequency
Power Scale 2 ((VOS[1:0] bits in
Regulator ON: 1.2 V internal
voltage on V
V
12
CAP_1/VCAP_2
PWR_CR register = 0x10), 144 MHz
HCLK max frequency with over-drive OFF
pins
or 168 MHz with over-drive ON
Power Scale 1 ((VOS[1:0] bits in
PWR_CR register = 0x11), 168 MHz
HCLK max frequency with over-drive OFF
or 180 MHz with over-drive ON
Regulator OFF: 1.2 V external
voltage must be supplied from
external regulator on
V
CAP_1/VCAP_2
Input voltage on RST and FT
(7)
pins
V
IN
Input voltage on TTa pins-− 0.3-
pins
(6)
Max frequency 120 MHz1.10 1.141.20
Max frequency 144 MHz1.20 1.261.32
Max frequency 168 MHz1.26 1.321.38
2V VDD 3.6 V− 0.3-5.5
2V− 0.3-5.2
V
DD
(1)
MinTypMaxUnit
1.08 1.141.20
1.20 1.261.32
V
1.26 1.321.40
V
DDA
V
+0.3
Input voltage on BOOT0 pin -0-9
LQFP100--465
LQFP144--500
WLCSP168--645
Power dissipation
P
at T
D
= 85 °C for suffix 6
A
or TA = 105 °C for suffix 7
UFBGA169--385
(8)
LQFP176--526
UFBGA176--513
LQFP208--1053
TFBGA216--690
Ambient temperature for 6
suffix version
T
A
Ambient temperature for 7
suffix version
T
JJunction temperature range
Maximum power dissipation− 40-85
Low power dissipation
(9)
Maximum power dissipation − 40-105
Low power dissipation
(9)
6 suffix version− 40-105
7 suffix version− 40-125
1. The over-drive mode is not supported at the voltage ranges from 1.7 to 2.1 V.
2. V
3. When the ADC is used, refer to Table 76.
4. If V
5. It is recommended to power V
V
6. The over-drive mode is not supported when the internal regulator is OFF.
minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 2.19.2).
DD/VDDA
pin is present, it must respect the following condition: V
REF+
and V
can be tolerated during power-up and power-down operation.
DDA
DD
from the same source. A maximum difference of 300 mV between V
DDA
DDA-VREF+
< 1.2 V.
− 40-105
− 40-125
and
DD
mW
°C
94 /22 0DS 1111 8 Rev 6
STM32F479xxElectrical characteristics
MS19044V2
ESR
R
Leak
C
7. To sustain a voltage higher than VDD+0.3, the internal Pull-up and Pull-Down resistors must be disabled
8. If T
9. In low power dissipation state, T
is lower, higher PD values are allowed as long as TJ does not exceed T
A
can be extended to this range as long as TJ does not exceed T
A
Table 18. Limitations depending on the operating power supply range
Jmax
.
.
Jmax
Maximum Flash
Operating
power
supply range
=
V
DD
1.7 to 2.1 V
(3)
ADC
operation
memory access
frequency with
no wait states
(f
Flashmax
20 MHz
)
(4)
Conversion time
up to 1.2 Msps
=
V
DD
2.1 to 2.4 V
=
V
DD
2.4 to 2.7 V
22 MHz
24 MHz
Conversion time
up to 2.4 Msps
=
V
DD
2.7 to 3.6 V
1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is
required.
2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does not impact the
execution speed from Flash memory since the ART accelerator allows to achieve a performance equivalent to 0 wait state
program execution.
3. V
4. Prefetch is not available.
5. When V
electrical characteristics of D- and D+ pins will be degraded between 2.7 and 3 V.
(5)
minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 2.19.2).
DD/VDDA
is connected to VDD, the voltage range for USB full speed PHYs can drop down to 2.7 V. However the
DDUSB
30 MHz
Maximum HCLK
frequency
vs.
Flash memory wait
states
(1)(2)
168 MHz
with 8 wait states
and over-drive OFF
180 MHz
with 8 wait states
and over-drive ON
180 MHz
with 7 wait states
and over-drive ON
180 MHz
with 5 wait states
and over-drive ON
I/O operation
No I/O
compensation
I/O compensation
works
Possible Flash
memory
operations
8-bit erase
and program
operations only
16-bit erase
and program
operations
16-bit erase
and program
operations
32-bit erase
and program
operations
5.3.2 VCAP1/VCAP2 external capacitor
Stabilization for the main regulator is achieved by connecting an external capacitor C
the VCAP1/VCAP2 pins. C
1. Legend: ESR is the equivalent series resistance.
is specified in Tab le 1 9.
EXT
Figure 26. External capacitor C
DS 1111 8 Rev 695/ 2 2 0
EXT
EXT
to
191
Electrical characteristicsSTM32F479xx
Table 19. VCAP1/VCAP2 operating conditions
(1)
SymbolParameterConditions
CEXTCapacitance of external capacitor2.2 µF
ESRESR of external capacitor< 2
1. When bypassing the voltage regulator, the two 2.2 µF V
replaced by two 100 nF decoupling capacitors.
capacitors are not required and should be
CAP
5.3.3 Operating conditions at power-up / power-down (regulator ON)
Subject to general operating conditions for TA.
Table 20. Operating conditions at power-up / power-down (regulator ON)
SymbolParameterMinMaxUnit
t
VDD
VDD rise time rate20
fall time rate20
V
DD
5.3.4 Operating conditions at power-up / power-down (regulator OFF)
Subject to general operating conditions for TA.
Table 21. Operating conditions at power-up / power-down (regulator OFF)
µs/V
(1)
SymbolParameterConditionsMinMaxUnit
VDD rise time ratePower-up 20
t
VDD
t
VCAP
1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when V
1.08 V.
V
fall time ratePower-down 20
DD
V
CAP_1
V
CAP_1
and V
and V
rise time ratePower-up20
CAP_2
fall time ratePower-down20
CAP_2
5.3.5 Reset and power control block characteristics
The parameters given in Tab le 22 are derived from tests performed under ambient
temperature and V
supply voltage conditions summarized in Tabl e 17 .
DD
reach below
DD
µs/V
96 /22 0DS 1111 8 Rev 6
STM32F479xxElectrical characteristics
Table 22. Reset and power control block characteristics
SymbolParameterConditionsMinTyp MaxUnit
PLS[2:0]=000 (rising edge)2.092.142.19
PLS[2:0]=000 (falling edge)1.982.042.08
PLS[2:0]=001 (rising edge)2.232.302.37
PLS[2:0]=001 (falling edge)2.132.192.25
PLS[2:0]=010 (rising edge)2.392.452.51
PLS[2:0]=010 (falling edge)2.292.352.39
PLS[2:0]=011 (rising edge)2.542.602.65
V
PVD
Programmable voltage
detector level selection
PLS[2:0]=011 (falling edge)2.442.512.56
PLS[2:0]=100 (rising edge)2.702.762.82
PLS[2:0]=100 (falling edge)2.592.662.71
PLS[2:0]=101 (rising edge)2.862.932.99
PLS[2:0]=101 (falling edge)2.652.842.92
PLS[2:0]=110 (rising edge)2.963.033.10
PLS[2:0]=110 (falling edge)2.852.932.99
PLS[2:0]=111 (rising edge)3.073.143.21
PLS[2:0]=111 (falling edge)2.953.033.09
(1)
V
PVDhyst
V
POR/PDR
V
PDRhyst
PVD hysteresis--100-mV
Power-on/power-down
reset threshold
(1)
PDR hysteresis--40-mV
Falling edge1.601.681.76
Rising edge1.641.721.80
Falling edge2.132.192.24
V
BOR1
Brownout level 1 threshold
Rising edge2.232.292.33
Falling edge2.442.502.56
V
BOR2
Brownout level 2 threshold
Rising edge2.532.592.63
Falling edge2.752.832.88
V
BOR3
V
BORhyst
T
RSTTEMPO
I
RUSH
(1)
Brownout level 3 threshold
Rising edge2.852.922.97
(1)
BOR hysteresis--100-mV
(1)(2)
POR reset temporization-0.51.53.0ms
InRush current on voltage
regulator power-on (POR or
--160200mA
wakeup from Standby)
InRush energy on voltage
regulator power-on (POR or
E
RUSH
(1)
wakeup from Standby)
1. Guaranteed by design.
2. The reset temporization is measured from the power-on (POR reset or wakeup from V
instruction is read by the user application code.
= 1.7 V, TA = 105 °C,
V
DD
I
= 171 mA for 31 µs
RUSH
--5.4µC
) to the instant when first
BAT
V
V
V
DS 1111 8 Rev 697/ 2 2 0
191
Electrical characteristicsSTM32F479xx
5.3.6 Over-drive switching characteristics
When the over-drive mode switches from enabled to disabled or disabled to enabled, the
system clock is stalled during the internal voltage set-up.
The over-drive switching characteristics are given in Tab le 23 . They are subject to general
operating conditions for T
SymbolParameterConditionsMinTypMaxUnit
Table 23. Over-drive switching characteristics
.
A
(1)
HSI-45-
T
od_swen
T
od_swdis
1. Guaranteed by design.
Over_drive switch
enable time
Over_drive switch
disable time
HSE max for 4 MHz
and min for 26 MHz
External HSE
50 MHz
HSI -20-
HSE max for 4 MHz
and min for 26 MHz.
External HSE
50 MHz
5.3.7 Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 25.
All the run-mode current consumption measurements given in this section are performed
with a reduced code that gives a consumption equivalent to CoreMark
45-100
-40-
20-80
-15-
®
code.
µs
98 /22 0DS 1111 8 Rev 6
STM32F479xxElectrical characteristics
Typical and maximum current consumption
The MCU is placed under the following conditions:
All I/O pins are in input mode with a static value at V
All peripherals are disabled except if it is explicitly mentioned.
The Flash memory access time is adjusted both to f
(see Table 18: Limitations depending on the operating power supply range).
When the regulator is OFF, the V
is provided externally, as described in Table 17:
12
General operating conditions.
The voltage scaling and over-drive mode are adjusted to f
–Scale 3 for f
–Scale 2 for 120 MHz < f
–Scale 1 for 144 MHz < f
The system clock is HCLK, f
120 MHz
HCLK
144 MHz
HCLK
180 MHz. The over-drive is only ON at 180 MHz.
HCLK
PCLK1
= f
HCLK
/4, and f
External clock frequency is 25 MHz and PLL is ON when f
The typical current consumption values are obtained for 1.7 V
range and for ambient temperature T
The maximum values are obtained for 1.7 V
maximum ambient temperature (T
For the voltage range 1.7 V
V
= 25 °C unless otherwise specified.
A
V
), unless otherwise specified.
A
2.1 V the maximum frequency is 168 MHz.
DD
or VSS (no load).
DD
frequency and V
HCLK
frequency as follows:
HCLK
= f
PCLK2
3.6 V voltage range and a
DD
/2.
HCLK
is higher than 25 MHz.
HCLK
V
DD
DD
3.6 V voltage
range
DS 1111 8 Rev 699/ 2 2 0
191
Electrical characteristicsSTM32F479xx
Table 24. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator enabled except prefetch) or RAM,
regulator ON
(1)
Max
SymbolParameterConditionsf
All
peripherals
enabled
(2)(3)
Supply
I
DD
current in
Run mode
(MHz)Typ
HCLK
180103109
T
=
A
25 °C
(4)
TA =
85 °C
105 °C
142175
TA =
(4)
1689499124149
1508489114140
1447781104127
12057607998
9043466484
6030335170
3016193757
2514163454
167102848
8472646
4362444
2352343
1805056
(4)
89124
(4)
168455175102
15041467097
Unit
mA
14437426388
12028314969
All
peripherals
disabled
(2)
9021244263
6015173656
309112949
257102848
16472545
8362244
4352343
2252343
1. Guaranteed based on test during characterization.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC
for the analog part.
4. Guaranteed by test in production.
10 0 /220DS 1111 8 Rev 6
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