STMicroelectronics STM32F479AI, STM32F479AG, STM32F479BI, STM32F479BG, STM32F479II Datasheet

...

STM32F479xx

WLCSP168

UFBGA176 (10 x 10 mm)

TFBGA216 (13 x 13 mm)

LQFP100 (14 × 14 mm) LQFP144 (20 × 20 mm) LQFP176 (24 × 24 mm)

LQFP208 (28 × 28 mm)

UFBGA169 (7 × 7 mm)

Arm®Cortex®-M4 32b MCU+FPU, 225DMIPS, up to 2MB Flash/384+4KB RAM, USB OTG HS/FS,

Ethernet, FMC, dual Quad-SPI, Crypto, Graphical accelerator, Camera IF, LCD-TFT & MIPI DSI

Datasheet - production data

Features

 Core: Arm® 32-bit Cortex®-M4 CPU with FPU,

Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 180 MHz, MPU, 225 DMIPS/1.25 DMIPS/MHz (Dhrystone

2.1), and DSP instructions

 Memories

– Up to 2 MB of Flash memory organized into

two banks allowing read-while-write

– Up to 384+4 KB of SRAM including 64 KB of

CCM (core coupled memory) data RAM

– Flexible external memory controller with up

to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR, SDRAM, Flash NOR/NAND memories

– Dual-flash mode Quad-SPI interface

 Graphics:

– Chrom-ART Accelerator™ (DMA2D),

graphical hardware accelerator enabling enhanced graphical user interface with

minimum CPU load – LCD parallel interface, 8080/6800 modes – LCD TFT controller supporting up to XGA

resolution –MIPI

DSI host controller supporting up to

720p 30Hz resolution

 Clock, reset and supply management

– 1.7 V to 3.6 V application supply and I/Os – POR, PDR, PVD and BOR – 4-to-26 MHz crystal oscillator – Internal 16 MHz factory-trimmed RC (1%

accuracy) – 32 kHz oscillator for RTC with calibration – Internal 32 kHz RC with calibration

 Low power

– Sleep, Stop and Standby modes –V

supply for RTC, 20×32 bit backup

BAT

registers + optional 4 KB backup SRAM

 3×12-bit, 2.4 MSPS ADC: up to 24 channels and

7.2 MSPS in triple interleaved mode

 2×12-bit D/A converters  General-purpose DMA: 16-stream DMA

controller with FIFOs and burst support

 Up to 17 timers: up to twelve 16-bit and two 32-

bit timers up to 180 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input. 2x watchdogs and SysTick timer

 Debug mode

– SWD & JTAG interfaces –Cortex

-M4 Trace Macrocell™

 Up to 161 I/O ports with interrupt capability

– Up to 157 fast I/Os up to 90 MHz – Up to 159 5 V-tolerant I/Os

 Up to 21 communication interfaces

– Up to 3 × I

C interfaces (SMBus/PMBus)

– Up to 4 USARTs and 4 UARTs (11.25 Mbit/s,

ISO7816 interface, LIN, IrDA, modem control)

– Up to 6 SPIs (45 Mbits/s), 2 with muxed full-

duplex I

S for audio class accuracy via

internal audio PLL or external clock – 1 x SAI (serial audio interface) – 2 × CAN (2.0B Active) –SDIO interface

 Advanced connectivity

– USB 2.0 full-speed device/host/OTG

controller with on-chip PHY – USB 2.0 high-speed/full-speed

device/host/OTG controller with dedicated

DMA, on-chip full-speed PHY and ULPI – Dedicated USB power rail enabling on-chip

PHYs operation throughout the entire MCU

power supply range – 10/100 Ethernet MAC with dedicated DMA:

supports IEEE 1588v2 hardware, MII/RMII

 8- to 14-bit parallel camera interface up to

54 Mbytes/s

 Cryptographic accelerator

– HW accelerator for AES 128, 192, 256,

Triple DES, HASH (MD5, SHA-1, SHA-2)

and HMAC

 True random number generator  CRC calculation unit  RTC: subsecond accuracy, hardware calendar  96-bit unique ID

Reference Part numbers

STM32F479xx

Table 1. Device summary

STM32F479AI, STM32F479AG, STM32F479BI,

STM32F479BG, STM32F479II, STM32F479IG,

STM32F479NI, STM32F479NG, STM32479VG,

STM32479VI, STM32479ZG, STM32479ZI

Jan u ar y 2 021 DS 1111 8 Rev 6 1/ 220

This is information on a product in full production.

www.st.com

Contents STM32F479xx

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.1 Compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.1.1 LQFP176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

1.1.2 LQFP208 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.1.3 UFBGA176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.1.4 TFBGA216 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.1 Arm® Cortex®-M4 with FPU and embedded Flash and SRAM . . . . . . . . 21

2.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 21

2.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.5 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 22

2.6 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.7 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.8 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.9 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.10 Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.11 LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.12 DSI Host (DSIHOST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.13 Chrom-ART Accelerator™ (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.14 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 27

2.15 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.16 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.17 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.18 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.19 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.19.1 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.19.2 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.20 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.20.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.20.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

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2.20.3 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 35

2.21 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 35

2.22 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2.23 V

operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

BAT

2.24 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2.24.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 38

2.24.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

2.24.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

2.24.4 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

2.24.5 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

2.24.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

2.25 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

2.26 Universal synchronous/asynchronous receiver transmitters (USART) . . 40

2.27 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

2.28 Inter-integrated sound (I

S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

2.29 Serial Audio interface (SAI1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

2.30 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

2.31 Audio and LCD PLL(PLLSAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

2.32 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . . . 42

2.33 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . . . 43

2.34 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

2.35 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 44

2.36 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 44

2.37 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

2.38 Cryptographic accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

2.39 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

2.40 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 45

2.41 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

2.42 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

2.43 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

2.44 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 47

2.45 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

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Contents STM32F479xx

4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

5.3.2 VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

5.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . . 96

5.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . . 96

5.3.5 Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . 96

5.3.6 Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

5.3.7 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

5.3.8 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 114

5.3.9 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 115

5.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 119

5.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

5.3.12 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 123

5.3.13 MIPI D-PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

5.3.14 MIPI D-PHY PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

5.3.15 MIPI D-PHY regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 128

5.3.16 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

5.3.17 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

5.3.18 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 132

5.3.19 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

5.3.20 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

5.3.21 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

5.3.22 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

5.3.23 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

5.3.24 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

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5.3.25 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

5.3.26 V

5.3.27 Reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

5.3.28 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

5.3.29 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

5.3.30 Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

5.3.31 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 186

5.3.32 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 187

5.3.33 SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 189

5.3.34 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

BAT

6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

6.1 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

6.2 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

6.3 WLCSP168 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

6.4 UFBGA169 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

6.5 LQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

6.6 UFBGA(176+25) package information . . . . . . . . . . . . . . . . . . . . . . . . . . 207

6.7 LQFP208 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

6.8 TFBGA216 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

6.9 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Appendix A Recommendations when using internal reset OFF . . . . . . . . . . . 217

A.1 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

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List of tables STM32F479xx

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. STM32F479xx features and peripheral counts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 3. Voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 32

Table 4. Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 5. Voltage regulator modes in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 6. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 7. Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 8. USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 9. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 10. STM32F479xx pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 11. FMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 12. Alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 13. STM32F479xx register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 14. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 15. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 16. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 17. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 18. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 95

Table 19. VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 20. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 96

Table 21. Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 96

Table 22. Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 23. Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 24. Typical and maximum current consumption in Run mode, code with data processing

running from Flash memory (ART accelerator enabled except prefetch) or RAM,

regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 25. Typical and maximum current consumption in Run mode, code with data processing

running from Flash memory (ART accelerator disabled), regulator ON . . . . . . . . . . . . . . 101

Table 26. Typical and maximum current consumption in Run mode, code with data

processing running from Flash memory (ART accelerator enabled except prefetch),

regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 27. Typical and maximum current consumption in Sleep mode, regulator ON . . . . . . . . . . . . 103

Table 28. Typical and maximum current consumption in Sleep mode, regulator OFF . . . . . . . . . . . 104

Table 29. Typical and maximum current consumption in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 30. Typical and maximum current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . 106

Table 31. Typical and maximum current consumption in V

Table 32. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 33. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table 34. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 35. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Table 36. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Table 37. HSE 4-26 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 38. LSE oscillator characteristics (f

Table 39. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Table 40. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Table 41. Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Table 42. PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Table 43. PLLSAI (audio and LCD-TFT PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

LSE

mode. . . . . . . . . . . . . . . . . . . . . . . . 107

BAT

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STM32F479xx List of tables

Table 44. SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Table 45. MIPI D-PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Table 46. MIPI D-PHY AC characteristics LP mode and HS/LP transitions . . . . . . . . . . . . . . . . . . . 126

Table 47. DSI-PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Table 48. DSI regulator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Table 49. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 50. Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 51. Flash memory programming with V

PP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Table 52. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Table 53. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Table 54. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Table 55. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Table 56. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Table 57. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Table 58. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Table 59. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Table 60. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Table 61. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Table 62. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Table 63. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Table 64. SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Table 65. I

S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Table 66. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Table 67. USB OTG full speed startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Table 68. USB OTG full speed DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Table 69. USB OTG full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Table 70. USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Table 71. USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Table 72. Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 73. Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 154

Table 74. Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 155

Table 75. Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 155

Table 76. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Table 77. ADC static accuracy at f Table 78. ADC static accuracy at f Table 79. ADC static accuracy at f Table 80. ADC dynamic accuracy at f Table 81. ADC dynamic accuracy at f

= 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

ADC

= 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

ADC

= 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

ADC

= 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 159

ADC

= 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 159

ADC

Table 82. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Table 83. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Table 84. V

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

BAT

Table 85. internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Table 86. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Table 87. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Table 88. Asynchronous non-multiplexed SRAM/PSRAM/NOR - read timings . . . . . . . . . . . . . . . . 167

Table 89. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings . . . . . . . . . . 167

Table 90. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 168

Table 91. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings . . . . . . . . . . 169

Table 92. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Table 93. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 170

Table 94. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Table 95. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 172

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List of tables STM32F479xx

Table 96. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Table 97. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Table 98. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 177

Table 99. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Table 100. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Table 101. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Table 102. SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Table 103. LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Table 104. SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Table 105. LPSDR SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Table 106. Quad-SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Table 107. Quad-SPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Table 108. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Table 109. LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Table 110. Dynamic characteristics: SD / MMC characteristics, VDD = 2.7 to 3.6 V . . . . . . . . . . . . . 190

Table 111. Dynamic characteristics: SD / MMC characteristics, VDD = 1.71 to 1.9 V . . . . . . . . . . . . 191

Table 112. RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Table 113. LQFP100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Table 114. LQFP144 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Table 115. WLCSP168 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

Table 116. UFBGA169 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Table 117. UFBGA169 - Recommended PCB design rules (0.5 mm pitch BGA). . . . . . . . . . . . . . . . 201

Table 118. LQFP176 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Table 119. UFBGA(176+25) - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Table 120. UFBGA(176+25) - Recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . 208

Table 121. LQFP208 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Table 122. TFBGA216 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Table 123. TFBGA216 - Recommended PCB design rules (0.8 mm pitch) . . . . . . . . . . . . . . . . . . . . 213

Table 124. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

Table 125. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Table 126. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 217

Table 127. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

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STM32F479xx List of figures

List of figures

Figure 1. Incompatible board design for LQFP176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 2. Incompatible board design for LQFP208 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 3. UFBGA176 port-to-terminal assignment differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 4. TFBGA216 port-to-terminal assignment differences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 5. STM32F479xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 6. STM32F479xx Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 7. VDDUSB connected to an external independent power supply . . . . . . . . . . . . . . . . . . . . . 29

Figure 8. Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 30

Figure 9. PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 10. Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 11. Startup in regulator OFF: slow V

- power-down reset risen after V

Figure 12. Startup in regulator OFF mode: fast V

- power-down reset risen before V

Figure 13. STM32F47x LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 14. STM32F47x LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 15. STM32F47x WLCSP168 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 16. STM32F47x UFBGA169 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 17. STM32F47x UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 18. STM32F47x LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 19. STM32F47x LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 20. STM32F47x TFBGA216 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 21. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 22. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 23. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 24. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 25. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 26. External capacitor C Figure 27. Typical V

current consumption

BAT

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

EXT

(RTC ON / backup SRAM ON and LSE in Low drive mode) . . . . . . . . . . . . . . . . . . . . . . 107

Figure 28. Typical V

current consumption

BAT

(RTC ON / backup SRAM ON and LSE in High drive mode) . . . . . . . . . . . . . . . . . . . . . . 108

Figure 29. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 30. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 31. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 32. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 33. ACCHSI vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 34. ACC

versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

LSI

Figure 35. PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 36. PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 37. MIPI D-PHY HS/LP clock lane transition timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 127

Figure 38. MIPI D-PHY HS/LP data lane transition timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Figure 39. FT I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Figure 40. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Figure 41. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Figure 42. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Figure 43. SPI timing diagram - slave mode and CPHA = 1 Figure 44. SPI timing diagram - master mode

slope

CAP_1 , VCAP_2

slope

CAP_1 , VCAP_2

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

stabilization . . . . . . . . . . . . . . . . . . . . . . . 34

stabilization . . . . . . . . . . . . . . . . . . . . . . 35

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

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List of figures STM32F479xx

Figure 45. I2S slave timing diagram (Philips protocol) Figure 46. I

S master timing diagram (Philips protocol)

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Figure 47. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Figure 48. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Figure 49. USB OTG full speed timings: definition of data signal rise and fall time . . . . . . . . . . . . . . 151

Figure 50. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Figure 51. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Figure 52. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Figure 53. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Figure 54. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Figure 55. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Figure 56. Power supply and reference decoupling (V Figure 57. Power supply and reference decoupling (V

not connected to V

REF+

connected to V

REF+

). . . . . . . . . . . . . 161

DDA

). . . . . . . . . . . . . . . . 161

DDA

Figure 58. 12-bit buffered/non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Figure 59. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 166

Figure 60. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 168

Figure 61. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 169

Figure 62. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 171

Figure 63. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Figure 64. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Figure 65. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 177

Figure 66. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Figure 67. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Figure 68. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Figure 69. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 180

Figure 70. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 181

Figure 71. SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Figure 72. SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Figure 73. Quad-SPI SDR timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Figure 74. Quad-SPI DDR timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Figure 75. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Figure 76. LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Figure 77. LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Figure 78. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Figure 79. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Figure 80. LQFP100 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Figure 81. LQFP100 - Recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Figure 82. LQFP100 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Figure 83. LQFP144 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Figure 84. LQFP144 - Recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Figure 85. LQFP144 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Figure 86. WLCSP168 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Figure 87. UFBGA169 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Figure 88. UFBGA169 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Figure 89. UFBGA169 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Figure 90. LQFP176 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Figure 91. LQFP176 - Recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Figure 92. LQFP176 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Figure 93. UFBGA(176+25) - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Figure 94. UFBGA(176+25) - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

Figure 95. LQFP208 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Figure 96. LQFP208 - Recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

10 /22 0 DS 1111 8 Rev 6

STM32F479xx List of figures

Figure 97. LQFP208 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Figure 98. TFBGA216 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Figure 99. TFBGA216 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Figure 100. TFBGA216 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

DS 1111 8 Rev 6 11/ 2 2 0

Description STM32F479xx

1 Description

The STM32F479xx devices are based on the high-performance Arm RISC core operating at a frequency of up to 180 MHz. The Cortex Floating point unit (FPU) single precision which supports all Arm

®(a)

Cortex®-M4 32-bit

-M4 core features a

single-precision dataprocessing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security.

The STM32F479xx devices incorporate high-speed embedded memories (Flash memory up to 2 Mbytes, up to 384 Kbytes of SRAM), up to 4 Kbytes of backup SRAM, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.

All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose 16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers, a true random number generator (RNG), and a cryptographic acceleration cell. They also feature standard and advanced communication interfaces:

 Up to three I

 Six SPIs, two I

Ss full duplex. To achieve audio class accuracy, the I2S peripherals can be clocked via a dedicated internal audio PLL or via an external clock to allow synchronization.

 Four USARTs plus four UARTs

 An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the

ULPI)

 Two CANs

 One SAI serial audio interface

 An SDMMC host interface

 Ethernet and camera interface

 LCD-TFT display controller

 Chrom-ART Accelerator™

 DSI Host.

Advanced peripherals include an SDMMC interface, a flexible memory control (FMC) interface, a Quad-SPI Flash memory, camera interface for CMOS sensors and a cryptographic acceleration cell. Refer to Ta bl e 2 for the list of peripherals available on each part number.

The STM32F479xx devices operate in the –40 to +105 °C temperature range from a 1.7 to

3.6 V power supply. A dedicated supply input for USB (OTG_FS and OTG_HS) only in full speed mode, is available on all packages.

The supply voltage can drop to 1.7 V (refer to Section 2.19.2). A comprehensive set of power-saving mode allows the design of low-power applications.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

12 /22 0 DS 1111 8 Rev 6

STM32F479xx Description

The STM32F479xx devices are offered in eight packages, ranging from 100 to 216 pins. The set of included peripherals changes with the device chosen, according to Tab le 2.

These features make the STM32F479xx microcontrollers suitable for a wide range of applications:

 Motor drive and application control

 Medical equipment

 Industrial applications: PLC, inverters, circuit breakers

 Printers, and scanners

 Alarm systems, video intercom, and HVAC

 Home audio appliances

Figure 5 shows the general block diagram of the device family.

Peripherals

Table 2. STM32F479xx features and peripheral counts

STM32F479Vx

STM32F479Zx

STM32F479Ax

STM32F479Ix

STM32F479Bx

STM32F479Nx

Flash memory in Kbytes 1024 2048 1024 2048 1024 2048 1024 2048 1024 2048 1024 2048

SRAM in Kbytes

System 384(160+32+128+64)

Backup 4

FMC memory controller Yes

Quad-SPI Yes

Ethernet Yes

Timers

Generalpurpose

Advancedcontrol

Basic 2

Random number generator Yes

S 4/2(full duplex)

SPI / I

(1)

6/2(full duplex)

(1)

I2C3

USART/UART 4/3 4/4

Communication interfaces

USB OTG FS Yes

USB OTG HS Yes

CAN 2

SAI 1

SDIO Yes

Camera interface Yes

DS 1111 8 Rev 6 13/ 2 2 0

Description STM32F479xx

Table 2. STM32F479xx features and peripheral counts (continued)

Peripherals

STM32F479Vx

STM32F479Zx

STM32F479Ax

STM32F479Ix

STM32F479Bx

STM32F479Nx

MIPI-DSI Host Yes

LCD-TFT Yes

Chrom-ART Accelerator™ (DMA2D)

Yes

Cryptography Yes

GPIOs 71 131 114 131 161 161

12-bit ADC Number of channels

12-bit DAC Number of channels

14 20 24

Yes

Maximum CPU frequency 180 MHz

Operating voltage 1.7 to 3.6V

Operating temperatures

Package LQFP100 LQFP144

1. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode.

2. VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to Section 2.19.2).

Ambient operating temperature: −40 to 85 °C / −40 to 105 °C

Junction temperature: −40 to 105 °C / −40 to 125 °C

UFBGA169

WLCSP168

(2)

LQFP176

UFBGA176

LQFP208 TFBGA216

14 /22 0 DS 1111 8 Rev 6

STM32F479xx Description

1.1 Compatibility throughout the family

STM32F479xx devices are not compatible with other STM32F4xx devices.

Figure 1 and Figure 2 show incompatible board designs, respectively, for LQFP176 and

LQFP208 packages (highlighted pins).

The UFBGA176 and TFBGA216 ballouts are compatible with other STM32F4xx devices, only few IO port pins are substituted, as shown in Figure 3 and Figure 4.

The LQFP100, LQFP144 and UFBGA169 packages are incompatible with other STM32F4xx devices.

DS 1111 8 Rev 6 15/ 2 2 0

Description STM32F479xx

MS38294V2

VSS

PI3

PI1

135 134 133

132

PI0

131

VDD

130

VSS

129

VCAP2

128

PA13

127

PA12

126

PA11

125

PA10

124

PA9

123

PA8

122

PC9

121

PC8

120

PC7

119

PC6 VDDUSB

117

VSS

116

PG8

115

PG7

114

PG6

113

PG5

112

PG4

111

PG3

110

PG2

109

VSSDSI

108

DSIHOST_D1N

107

DSIHOST_D1P

106

VDD12DSI

105

DSIHOST_CKN

104

DSIHOST_CKP

103

VSSDSI

102

DSIHOST_D0N

101

DSIHOST_D0P

100

VCAPDSI

VDDSI

PD15

PD14

VDD

VSS

PD13

PD12

PD11

PD10

PD9

PD8

84 85

86 87

STM32F469xx/479xx

LQFP176

PH7

PB12

PB13

PB14

PB15

118

VSS

PI3

PI2

135 134

133

132

PI1 131 PI0 130

PH15 129

PH14 128

PH13 127

VDD 126

VSS 125

VCAP2 124

PA13 123

PA12 122

PA11 121

PA10 120

PA9 119

PA8 118

PC9 117

PC8 116

PC7 115

PC6

114

VDD

113

VSS

112

PG8

111

PG7

110

PG6

109

PG5

108

PG4

107

PG3

106

PG2

105

PD15

104

PD14

103

VDD

102

VSS

101

PD13

100

PD12

PD11

PD10

PD9

PD8

PB15

PB14

PB13

PB12

VDD

VSS

PH12

PH8

PH9

PH10

PH11

STM32F4xx

LQFP176

PH7

1.1.1 LQFP176 package

Figure 1. Incompatible board design for LQFP176 package

16 /22 0 DS 1111 8 Rev 6

1. Pins from 85 to 133 are not compatible.

STM32F479xx Description

MS38295V1

138

PC6

137 VDDUSB

VDD

136

VSS

135

PG8

134

PG7

133

PG6

132

PG5

131

PG4

130

PG3

129

PG2

128

VSSDSI

PK2

127

DSIHOST_D1N

PK1

126

DSIHOST_D1P

PK0

125

VDD12DSI

VSS

124

DSIHOST_CKN

VDD

123

DSIHOST_CKP

PJ11

122

VSSDSI

PJ10

121

DSIHOST_D0N

PJ9

120

DSIHOST_D0P

PJ8

119

VCAPDSI

PJ7

118

VDDDSI

PJ6

117

PD15

116

PD14

STM32F42x/STM32F43x

LQFP208

STM32F469xx/479xx

LQFP208

138 137 136 135 134 133 132 131 130

129 128

127 126 125 124 123

122 121 120

119

118 117 116

1.1.2 LQFP208 package

Figure 2. Incompatible board design for LQFP208 package

1. Pins from 118 to 128 and pin 137 are not compatible

DS 1111 8 Rev 6 17/ 2 2 0

Description STM32F479xx

DSI

HOST_

D0P

DSI

HOST_

D0N

DSI

HOST_

CKN

DSI

HOST_

CKP

VCAP

DSI

VDD DSI

VDD_

USB

VSS DSI

DSI

HOST_

D1P

DSI

HOST_

D1N

VDD12

DSI

MS39403V1

1 2 3 9 10 11 12 13 14 15

APE3PE2

PE1 PE 0 PB 8

PB5

PG1 4 PG1 3 PB 4 P B3 PD7 P C12 PA15 PA 14 PA 13

BPE4PE5

PE6

PB9 PB7

PB6

PG15 PG12 PG11 PG10 PD6 PD0 PC 11 PC10 PA12

VBAT

PI7 PI6 PI5

PDR _ON

VDD

PG9 PD5 PD1 PI3 PA11

PC13

PI8

PI9 PI4 BOOT0

VSS VSS VSS PD4 PD3 PD2

PI1

PA10

PC14

PF0 PI10

PI11

PI0 PA9

FPC15

VSS

VDD

PH2

VSS VCAP2 PC9 PA8

PH0

VSS V DD PH 3

VSS VDD PC8 PC7

PH1

PF2

PF1

PH4

PG8 PC6

NRS T P F3 PH 5

PG7 PG6

PF7

PF6

PF4

VDD

VSS

PG5 PG4 PG 3

PF10

BYPASS

_REG

PD15 PG2

MVSSAPC0

PF8

PC1 PC2 PC 3

PB2

PG1

VCAP

PH6 PD14 PD13

NVREF-

PA0

PA4

PC4

PF13

PG0 V DD VDD VDD PE 13 P H7 PD1 2 PD 11 PD10

PA2 PA6 P A5

PC5

PF12

PF15 PE8 PE9 PE11 PE14 PB12 PB13 PD9 PD8

PA3

PB1

PF11 PE7

PE1 2 PE15 PB 10 PB11 PB 14 PB15

VSS

45678

PA1

VDD

VREF+

VDDA

PA7

PB0

PF14

PF10

VSS VSS VSS VSS

VSSVSSVSS VSS VSS

VSS VSS

PF9

PF5

PD1 PI3

PI2

PD2

PI1

PH13

PI0

VSS VCAP2 PC9

VSS VDD PC8

VSS VDD

PG8

PG7

PG5 PG4

PD15

PD14

PH15

PH14

VDD

PH12

PH11

PH8 PH9

PH10

VDD

PD1 PI3

PD2

PI1

DSI

HOST_

D1P

PI0

VSS VCAP2 PC9

VSS VDD PC8

VSS

DSI

VDD_

USB

PG8

PG7

PG5 PG4

PD15

PD14

VDD12

DSI

HOST_

D1N

VDD

DSI

VCAP

DSI

HOST_

CKP

DSI

HOST_

D0P

DSI

HOST_

D0N

DSI

HOST_

CKN

VDD

STM32F42xx/3xx

STM32F40xx/41xx

STM32F469xx STM32F479xx

1.1.3 UFBGA176 package

Figure 3. UFBGA176 port-to-terminal assignment differences

18 /22 0 DS 1111 8 Rev 6

1. The highlighted pins are substituted with dedicated DSI IO pins on STM32F469xx/479xx devices.

STM32F479xx Description

MSv39404V1

123 4 5678 9101112131415

PG14

PE1

PE0

PB8

PB5

PB4

PB3

PD7

PC12 PA15

PA14 PA13

PE5 PE6 PG13 PB9

PB7

PB6

PG15

PG11 PJ13

PJ12 PD6

PD0

PC11 PC10

PA12

VBAT PI8

PI4

PK7 PK6 PK5

PG12

PG10 PJ14 PD5

PD1

PI3

PI2

PA11

PC13 PF0 PI5 PI7 PI10 PI6 PK4 PK3 PG9 PJ15 PD4 PD2 PH15 PI1 PA10

PC14 PF1 PI12 PI9 BOOT0 VDD

VDD

VDD VDD

VCAP2

PH13

PH14 PI0 PA 9

PC15 VSS PI11

VDD

PC9

PA8

PH0

PF2

PI13

PI15

VDD

PC8 PC7

PH1 PI14

PH4

VSS PG8

PC6

NRST PF4 PH5

PH3

VSS

VDD

PG7

PG6

PF7

PF6

PF5

PH2

VDD

VSS

VSS VSS VSS VSS VDD

PD15

PB13

PD10

PF10

PC3

BYPASS

-REG

PB12

PD9 PD8

VSSA

PG1

PD12 PD13 PG3 PG2 PJ5 PH12

VREF- PA1

PA0

PA4

PC4

PF13

PG0 PJ3

PE8

PD11 PG5

PG4

PH7

PH9

PH11

VREF+

PA2

PA6 PA5 PC5 PF14 PJ2 PF11 PE9

PE11

PE14

PB10 PH6 PH8 PH10

PA3 PA7 PB1

PB0 PJ0

PJ1

PE7 PE10 PE12

PE15 PE13

PB11 PB14

PB15

PF3

VDDA

PDR

PE4

PE3

PE2

VDD

VSS

VSS VSS VSS VSS VSS

VSS

VDD

PJ4PF15

VDD VDD VDD VCAP1 PD14

VDD

PF8

PF9

PC0

PC1 PC2 PB2 PF12

VDD

VSS

PD3

STM32F42xx/3xx

STM32F40xx/41xx

STM32F469xx STM32F479xx

VDD

PD15

VDD

PD15

VDD

DSI

HOST_

CKP

VDDD

USB

VSS DSI

VDD12

DSI

HOST_

CKN

DSI

HOST_

D0P

VCAP

DSI

HOST_

D0N

DSI

HOST_

D1P

DSI

HOST_

D1N

PJ8

VDD

PJ11

PK0

PJ10

PJ7

PJ6

PJ9

PK1

PL2

VDD

1.1.4 TFBGA216 package

Figure 4. TFBGA216 port-to-terminal assignment differences

1. The highlighted pins are substituted with dedicated DSI IO pins on STM32F469xx/479xx devices.

DS 1111 8 Rev 6 19/ 2 2 0

Description STM32F479xx

MS38297V1

USART 2MBpsGPIO PORT A

AHB/APB2

USART 2MBps

EXT IT. WKUP

168 AF

PA[15:0]

USART 2MBps

GPIO PORT B

PB[15:0]

USART 2MBps

TIMER 1 / PWM

4 compl. chan. (TIM1_CH1[1:4]N),

4 chan. (TIM8_CH1[1:4]ETR),

BKIN as AF

USART 2MBpsTIMER 8 / PWM

USART 2MBps

GPIO PORT C

PC[15:0]

USART 2MBps

USART 1

RX, TX, SCK,

CTS, RTS as AF

USART 2MBpsGPIO PORT D

PD[15:0]

USART 2MBpsGPIO PORT E

PE[15:0]

USART 2MBps

GPIO PORT F

PF[15:0]

USART 2MBpsGPIO PORT G

PG[15:0]

USART 2MBps

SPI1/I2S

APB 2 60 M H z

8 analog inputs common

to the 3 ADCs

8 analog inputs common

to the ADC1 & 2

DDREF_ADC

8 analog inputs to ADC3

4 Channels, ETR as AF

TIM2

TIM3

TIM4

4 Channels

TIM5

RX, TX, SCK,

USART2

RX, TX, SCK

USART3

RX, TX as AF

UART4

RX, TX as AF

UART5

MOSI, MISO, SCK

NSS/WS, MCK as AF

SPI2/I2S

MOSI, MISO, SCK

SPI3/I2S

NSS/WS, MCK as AF

SCL, SDA, SMBA as AF

I2C1/SMBUS

SCL, SDA, SMBA as AF

I2C2/SMBUS

TX, RX

bxCAN1

TX, RX

bxCAN2

DAC1 as AF

DAC1

DAC2 as AF

DAC2

ITF

TIMER6

TIMER7

WWDG

4KB BKPRAM

RTC_TAMP1 RTC_TAMP2 RTC_OUT RTC_REFIN RTC_TS

OSC32_IN OSC32_OUT

OSCIN OSCOUT

VDDA, VSSA, NRST

USART 2MBpsUSART 6

RX, TX, SCK,

CTS, RTS as AF

smcard

irDA

smcard

irDA

smcard

irDA

smcard irDA

16b

32b

16b

32b

16b

CTS, RTS as AF

SDIO / MMC

D[7:0]

CMD, CK as AF

VBAT = 1.8 to 3.6 V

DMA1

AHB/APB1

DMA2

SCL, SDA, SMBA as AF

I2C3/SMBUS

USART 2MBpsGPIO PORT H

PH[15:0]

JTAG & SW

ARM

Cortex M4

180 MHz

I-BUS

S-BUS

D-BUS

NVICETM

MPUFPU

JTRST, JTDI,

JTCK/SWCLK

JTDO/SWD, JTDO

TRACECK

TRACED(3:0)

USB

DMA/

FIFO

OTG HS

D+, D-

VDDUSB = 3.0 to 3.6 V

ULPI : CLK, D(7:0),

DIR, STP, NXT

SCL/SDA, INT, ID, VBUS

GP-DMA2

8 Streams

FIFO

GP-DMA1

8 Streams

FIFO

Flash 1MB

ACCEL/

CACHE

SRAM1 160KB

SRAM2 32KB

EXT MEM CTRL (FMC)

SRAM, PSRAM, NOR Flash

NAND Flash, SDRAM

CLK, NE[3:0], A[23:0], D[31:0], NOE, NWEN, NBL[3:0], SDCLKE[1:0], SDNE[1:0], NRAS, NCAS, NADV, NWAIT, INTR

CAMERA

HSYNC, VSYNC PIXCK, D(13:0)

ITF

USB

PHY

OTG FS

D+, D-, VDDUSB = 3.0 to 3.6 V, SCL, SDA, INT, ID, VBUS

FIFO

PHY

FIFO

USART 2MBps

TEMP SENSOR

ADC1

ADC2

ADC 3

@VDDA

POR/PDR/

SUPPLY

SUPERVISION

PVD

Reset

Int

POR

XTAL OSC

4-26MHz

XTAL 32kHz

MANAGT

RTC

RC HS

RC LS

Standbyinterface

IWDG

@VBAT

@VDDA

AWU

RESET&

CLOCK

CTRL

PLL1,2,3

@VDDA @VDD

Backup Register

AHB2 180MHz

2 Channels as AF

TIM12

1 Channels as AF

TIM13

1 CH as AF

TIM14

16b

USART 2MBpsTIMER 9

2 channels as AF

USART 2MBps

TIMER10

1 channel as AF

16b

USART 2MBps

TIMER11

1 channel as AF

16b

BOR

FIFO

UART7

UART8

USART 2MBpsSPI 4

SD, SCK, FS MCLK as AF

CRC

USART 2MBps

SAI 1

Dig. Filter

FIFO

QuadSPI

CLK, BK1_NCS, BK2_NCS, D[7:0]

USART 2MBps

SPI6

FIFO

Flash 1MB

SRAM3 128KB

3DES,

AES256

HASH

FIFO

RNG

AHB2 180 MHz

4 Channels, ETR as AF

USART 2MBpsGPIO PORT I

PI[15:0]

USART 2MBpsGPIO PORT J

PJ[15:0]

USART 2MBpsGPIO PORT K

PK[7:0]

AHB1 180 MHz

HCLKx

PCLKx

USART 2MBps

SPI5

MOSI, MISO, SCK,

NSS as AF

MOSI, MISO, SCK,

NSS as AF

MOSI, MISO, SCK,

NSS as AF

MOSI, MISO, SCK,

NSS as AF

CCM data RAM 64 KB

LCD-TFT

FIFO

DMA-2D

FIFO

DSI Host

DSI

PHI

DSIHOST_D0 P/N DSIHOST_D1 P/N

DSIHOST_CK P/N

VDD12DSI, VDDSI, VSSDSI

VCAPDSI

DSIHOST_TE

4 compl. chan. (TIM1_CH1[1:4]N),

4 chan. (TIM8_CH1[1:4]ETR),

BKIN as AF

RX, TX as AF

AHB BUS MATRIX

APB1 45 MHz

APB2 90 MHz

Figure 5. STM32F479xx block diagram

20 /22 0 DS 1111 8 Rev 6

1. The timers connected to APB2 are clocked from TIMxCLK up to 180 MHz, while the timers connected to APB1 are clocked from TIMxCLK either up to 90 MHz or 180 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register.

STM32F479xx Functional overview

2 Functional overview

2.1 Arm® Cortex®-M4 with FPU and embedded Flash and SRAM

The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm® processors for embedded systems, developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.

The Arm code-efficiency, delivering the high-performance expected from an Arm memory size usually associated with 8- and 16-bit devices.

The processor supports a set of DSP instructions that allow efficient signal processing and complex algorithm execution. Its single precision FPU (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation.

The STM32F47x line is compatible with all Arm

Figure 5 shows the general block diagram of the STM32F47x line.

Note: Cortex

Cortex®-M4 with FPU core is a 32-bit RISC processor that features exceptional

tools and software.

-M4 with FPU core is binary compatible with the Cortex®-M3 core.

core in the

2.2 Adaptive real-time memory accelerator (ART Accelerator™)

The ART Accelerator™ is a memory accelerator optimized for STM32 industry-standard

Arm

Cortex®-M4 with FPU processors. It balances the inherent performance advantage of the Arm the processor to wait for the Flash memory at higher frequencies.

To release the processor full 225 DMIPS performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 128-bit Flash memory. Based on CoreMark performance achieved thanks to the ART Accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 180 MHz.

Cortex®-M4 with FPU over Flash memory technologies, which normally require

benchmark, the

2.3 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 Gbytes of addressable memory.

The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

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Functional overview STM32F479xx

2.4 Embedded Flash memory

The devices embed a Flash memory of up to 2 Mbytes available for storing programs and data.

2.5 CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location.

2.6 Embedded SRAM

All devices embed:

 Up to 384Kbytes of system SRAM including 64 Kbytes of CCM (core coupled memory)

data RAM

RAM is accessed (read/write) at CPU clock speed with 0 wait states.

 4 Kbytes of backup SRAM

This area is accessible only from the CPU. Its content is protected against possible unwanted write accesses, and is retained in Standby or V

BAT mode.

2.7 Multi-AHB bus matrix

The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB HS, LCD-TFT, and DMA2D) and the slaves (Flash memory, RAM, FMC, QUADSPI, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously.

22 /22 0 DS 1111 8 Rev 6

STM32F479xx Functional overview

ARM

Cortex-M4

DMA1

DMA2

MAC

Ethernet

USB OTG

Bus matrix-S

ICODE

DCODE

ACCEL

Flash

memory

SRAM1

160 Kbyte

SRAM2

32 Kbyte

AHB2

peripherals

AHB1

peripherals

FMC external

MemCtl

I-bus

D-bus

S-bus

DMA_PI

DMA_MEM1

DMA_MEM2

DMA_P2

ETHERNET_M

USB_HS_M

MS33862V1

CCM data RAM

64-Kbyte

APB1

APB2

SRAM3

128 Kbyte

LCD-TFT

Chrom ART Accelerator(DMA2D)

LCD-TFT_M

DMA2D

QuadSPI

Figure 6. STM32F479xx Multi-AHB matrix

2.8 DMA controller (DMA)

The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB).

The two DMA controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code.

Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. Configuration is made by software and transfer sizes between source and destination are independent.

DS 1111 8 Rev 6 23/ 2 2 0

Functional overview STM32F479xx

The DMA can be used with the main peripherals:

 SPI and I

 I

 USART

 General-purpose, basic and advanced-control timers TIMx

 DAC

 SDIO

 Camera interface (DCMI)

 ADC

 SAI1

 QUADSPI.

2.9 Flexible memory controller (FMC)

The Flexible memory controller (FMC) includes three memory controllers:

 The NOR/PSRAM memory controller

 The NAND/memory controller

 The Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller

The main features of the FMC controller are the following:

 Interface with static-memory mapped devices including:

– Static random access memory (SRAM)

– NOR Flash memory/OneNAND Flash memory

– PSRAM

– NAND Flash memory with ECC hardware to check up to 8 Kbytes of data

 Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories

 8-,16-,32-bit data bus width

 Independent Chip Select control for each memory bank

 Independent configuration for each memory bank

 Write FIFO

 Read FIFO for SDRAM controller

 The Maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is

HCLK/2.

LCD parallel interface

The FMC can be configured to interface seamlessly with most graphic LCD controllers. It

supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to

specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost effective graphic applications using LCD modules with embedded controllers or high

performance solutions using external controllers with dedicated acceleration.

24 /22 0 DS 1111 8 Rev 6

STM32F479xx Functional overview

2.10 Quad-SPI memory interface (QUADSPI)

All STM32F479xx devices embed a Quad-SPI memory interface, which is a specialized communication interface targeting Single, Dual, Quad or Dual-flash SPI memories. It can work in direct mode through registers, external flash status register polling mode and memory mapped mode. Up to 256 Mbytes external Flash memory are mapped, supporting 8, 16 and 32-bit access. Code execution is supported.

The opcode and the frame format are fully programmable. Communication can be either in Single Data Rate or Dual Data Rate.

2.11 LCD-TFT controller

The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue) and delivers all signals to interface directly to a broad range of LCD and TFT panels up to XGA (1024x768) resolution with the following features:

 2 displays layers with dedicated FIFO (64x32-bit)

 Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer

 Up to 8 Input color formats selectable per layer

 Flexible blending between two layers using alpha value (per pixel or constant)

 Flexible programmable parameters for each layer

 Color keying (transparency color)

 Up to 4 programmable interrupt events.

2.12 DSI Host (DSIHOST)

The DSI Host is a dedicated peripheral for interfacing with MIPI DSI compliant displays. It includes a dedicated video interface internally connected to the LTDC and a generic APB interface that can be used to transmit information to the display.

These interfaces are as follows:

 LTDC interface:

– Used to transmit information in Video Mode, in which the transfers from the host

processor to the peripheral take the form of a real-time pixel stream (DPI).

– Through a customized for mode, this interface can be used to transmit information

in full bandwidth in the Adapted Command Mode (DBI).

 APB slave interface:

– Allows the transmission of generic information in Command mode, and follows a

proprietary register interface.

– Can operate concurrently with either LTDC interface in either Video Mode or

Adapted Command Mode.

 Video mode pattern generator:

– Allows the transmission of horizontal/vertical color bar and D-PHY BER testing

pattern without any kind of stimuli.

DS 1111 8 Rev 6 25/ 2 2 0

Functional overview STM32F479xx

The DSI Host main features:

 Compliant with MIPI

 Interface with MIPI

 Supports all commands defined in the MIPI

– Transmission of all Command mode packets through the APB interface

– Transmission of commands in low-power and high-speed during Video Mode

 Supports up to two D-PHY data lanes

 Bidirectional communication and escape mode support through data lane 0

 Supports non-continuous clock in D-PHY clock lane for additional power saving

 Supports Ultra Low-Power mode with PLL disabled

 ECC and Checksum capabilities

 Support for End of Transmission Packet (EoTp)

 Fault recovery schemes

 3D transmission support

 Configurable selection of system interfaces:

– AMBA APB for control and optional support for Generic and DCS commands

– Video Mode interface through LTDC

– Adapted Command Mode interface through LTDC

 Independently programmable Virtual Channel ID in

– Video Mode

– Adapted Command Mode

– APB Slave



Alliance standards



D-PHY



Alliance specification for DCS:

Video Mode interfaces features

 LTDC interface color coding mappings into 24-bit interface:

– 16-bit RGB, configurations 1, 2, and 3

– 18-bit RGB, configurations 1 and 2

– 24-bit RGB

 Programmable polarity of all LTDC interface signals

 Maximum resolution is limited by available DSI physical link bandwidth:

– Number of lanes: 2

– Maximum speed per lane: 500 Mbps

Adapted interface features

 Support for sending large amounts of data through the memory_write_start (WMS) and

memory_write_continue (WMC) DCS commands

 LTDC interface color coding mappings into 24-bit interface:

– 16-bit RGB, configurations 1, 2, and 3

– 18-bit RGB, configurations 1 and 2

– 24-bit RGB

26 /22 0 DS 1111 8 Rev 6

STM32F479xx Functional overview

Video mode pattern generator

 Vertical and horizontal color bar generation without LTDC stimuli

 BER pattern without LTDC stimuli

2.13 Chrom-ART Accelerator™ (DMA2D)

The Chrom-Art Accelerator™ (DMA2D) is a graphic accelerator which offers advanced bit blitting, row data copy and pixel format conversion. It supports the following functions:

 Rectangle filling with a fixed color

 Rectangle copy

 Rectangle copy with pixel format conversion

 Rectangle composition with blending and pixel format conversion.

Various image format coding are supported, from indirect 4bpp color mode up to 32bpp direct color. It embeds dedicated memory to store color lookup tables.

An interrupt can be generated when an operation is complete or at a programmed watermark.

All the operations are fully automatized and are running independently from the CPU or the DMAs.

2.14 Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 93 maskable interrupt channels plus the 16 interrupt lines of the Cortex M4 with FPU core.

 Closely coupled NVIC gives low-latency interrupt processing

 Interrupt entry vector table address passed directly to the core

 Allows early processing of interrupts

 Processing of late arriving, higher-priority interrupts

 Support tail chaining

 Processor state automatically saved on interrupt entry, and restored on interrupt exit,

with no instruction overhead

This hardware block provides flexible interrupt management features with minimum interrupt latency.

2.15 External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 23 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 159 GPIOs can be connected to the 16 external interrupt lines.

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Functional overview STM32F479xx

2.16 Clocks and startup

On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The 16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy over the full temperature range. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing to increase the frequency up to 180 MHz. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example if an indirectly used external oscillator fails).

Several prescalers allow the configuration of the two AHB buses, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB buses is 180 MHz while the maximum frequency of the high-speed APB domains is 90 MHz. The maximum allowed frequency of the low-speed APB domain is 45 MHz.

The devices embed a dedicated PLL (PLLI2S) and PLLSAI which allows to achieve audio class performance. In this case, the I frequencies from 8 kHz to 192 kHz.

2.17 Boot modes

At startup, boot pins are used to select one out of three boot options:

 Boot from user Flash

 Boot from system memory

 Boot from embedded SRAM

The boot loader is located in system memory. It is used to reprogram the Flash memory through a serial interface. Refer to application note AN2606 for details.

2.18 Power supply schemes

 VDD = 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when

enabled), provided externally through V

Note: V

 V

DD/VDDA

Section 2.19.2). Refer to Ta bl e 3 to identify the packages supporting this option.

 V

, V

SSA

blocks, RCs and PLL. V

BAT

= 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset

DDA

minimum value of 1.7 V is obtained when the internal reset is OFF (refer to

DDA

and V

= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and

backup registers (through power switch) when V

can be connected either to VDD or an external independent power supply (3.0

DDUSB

to 3.6 V) for USB transceivers. For example, when device is powered at 1.8V, an independent power supply 3.3 V can be connected to V it is independent from V

DDUSB

. When the V

or V

first to disappear.

S master clock can generate all standard sampling

pins.

must be connected to VDD and VSS, respectively.

SSA

is not present.

is connected to a separated power supply,

DDUSB

but it must be the last supply to be provided and the

DDA

28 /22 0 DS 1111 8 Rev 6

STM32F479xx Functional overview

MS37590V1

DDUSB_MIN

DD_MIN

time

DDUSB_MAX

USB functional area

VDD=V

DDA

USB non functional area

DDUSB

Power-on

Power-down

Operating mode

USB non functional area

The following conditions must be respected:

– During power-on phase (V

– During power-down phase (VDD < V

–V

rising and falling time rate specifications must be respected.

DDUSB

– In operating mode phase, V

< V

DDUSB

DD_MIN

), V

should be always lower than

DDUSB

should be always lower than

DDUSB

could be lower or higher than VDD:

– If USB (USB OTG_HS/OTG_FS) is used, the associated GPIOs powered by

are operating between V

DDUSB

DDUSB_MIN

and V

DDUSB_MAX

.The V

DDUSB

supplies both USB transceivers (USB OTG_HS and USB OTG_FS).

– If only one USB transceiver is used in the application, the GPIOs associated to

the other USB transceiver are still supplied by V

DDUSB

– If USB (USB OTG_HS/OTG_FS) is not used, the associated GPIOs powered

by V

are operating between V

DDUSB

DD_MIN

and V

DD_MAX

– If USB (USB OTG_HS/OTG_FS) is not used and the associated GPIOs

must not be floating).

DDUSB

are not used, then V

DDUSB

should be tied to VSS or VDD

DDUSB

Figure 7. V

connected to an external independent power supply

DDUSB

The DSI (Display Serial Interface) sub-system uses several power supply pins that are independent from the other supply pins:

 VDDDSI is an independent DSI power supply dedicated for DSI Regulator and MIPI

D-PHY. This supply must be connected to global VDD.

 VCAPDSI pin is the output of DSI Regulator (1.2 V), which must be connected

externally to VDD12DSI.

 VDD12DSI pin is used to supply the MIPI D-PHY, and to supply clock and data lanes

pins. An external capacitor of 2.2 µF must be connected on VDD12DSI pin.

 VSSDSI pin is an isolated supply ground used for DSI sub-system.

 If DSI functionality is not used at all, then:

– VDDDSI pin must be connected to global VDD.

DS 1111 8 Rev 6 29/ 2 2 0

Functional overview STM32F479xx

PDR_ON

STM32F479xx

VSS

PDR not active : 1.7 V < VDD < 3.6 V

VBAT

VDD

Application reset

signal (optional)

MSv36589V1

– VCAPDSI pin must be connected externally to VDD12DSI but the external

capacitor is no more needed.

– VSSDSI pin must be grounded.

2.19 Power supply supervisor

2.19.1 Internal reset ON

On packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high. On other packages the power supply supervisor is always enabled.

The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is reached, the option byte loading process starts, either to confirm or modify default BOR thresholds, or to disable BOR permanently. Three BOR thresholds are available through option bytes. The device remains in reset mode when V V

POR/PDR

or V

, without the need for an external reset circuit.

BOR

The device also features an embedded programmable voltage detector (PVD) that monitors the V

DD/VDDA

generated when V higher than the V

power supply and compares it to the V

DD/VDDA

PVD

drops below the V

threshold. The interrupt service routine can then generate a warning

threshold and/or when VDD/V

PVD

message and/or put the MCU into a safe state. The PVD is enabled by software.

is below a specified threshold,

threshold. An interrupt can be

PVD

DDA

2.19.2 Internal reset OFF

This feature is available only on packages featuring the PDR_ON pin. The internal power-on reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin.

An external power supply supervisor should monitor V the device in reset mode as long as V connected to VSS, as shown in Figure 8.

Figure 8. Power supply supervisor interconnection with internal reset OFF

is below a specified threshold. PDR_ON must be

and NRST and should maintain

30 /22 0 DS 1111 8 Rev 6

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