STMicroelectronics STM32F427, STM32F429, STM32F439, STM32F437 User Manual
STM32F42xx and STM32F43xx
Errata sheet
STM32F427/437 and STM32F429/439 line limitations
Silicon identification
This errata sheet applies to the revision A and Y of STMicroelectronics STM32F427/437
and STM32F429/439 microcontroller lines.
The STM32F42xx and STM32F43xx devices feature an ARM
FPU, for which an errata notice is also available (see Section 1 for details).
The full list of part numbers is shown in Table 2. The products are identifiable as shown in
Table 1:
• by the revision code marked below the order code on the device p ackage
• by the last three digits of the Internal order code printed on the box label
Order code Revision code marked on device
Table 1. Device identification
®
32-bit Cortex™-M4 core with
(1)
(2)
STM32F427xx, STM32F429xx
STM32F437xx, STM32F439xx
1. The REV_ID bits in the DBGMCU_IDCODE register show the revision code of the device (see the RM0090
STM32F4xx reference manual for details on how to find the revision code).
2. Refer to Appendix A: Revision code on device marking for details on how to identify the revision code and
the date code on the different packages.
Reference Part number
STM32F427xx
STM32F437xx
STM32F429xx
STM32F439xx
STM32F427VG, STM32F427ZG, STM32F427IG, STM32F427VI, STM32F427ZI,
STM32F427II
STM32F437VG, STM32F437ZG, STM32F437IG, STM32F437VI, STM32F437ZI,
STM32F437II
STM32F429VG , STM32F429ZG, STM32F429IG, STM32F429VI, STM32F429ZI,
STM32F429II, STM32F429BG, STM32F429BI, STM32F429NI, STM32F429NG
STM32F439VI, STM32F439VG , STM32F439ZG, STM32F439ZI, STM32F439IG,
STM32F439II, STM32F439BG, STM32F439BI, STM32F439NI, STM32F439NG
Table 2. Device summary
“A” and “Y”
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www.st.com
Contents STM32F42xx and STM32F43xx
Contents
1 ARM 32-bit Cortex-M4 with FPU limitations . . . . . . . . . . . . . . . . . . . . . . 7
1.1 Cortex-M4 interrupted loads to stack pointer can cause
erroneous behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 STM32F42xx and STM32F43xx silicon limitations . . . . . . . . . . . . . . . . . 8
2.1 System limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.1 Debugging Stop mode and system tick timer . . . . . . . . . . . . . . . . . . . . 10
2.1.2 Debugging Stop mode with WFE entry . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.3 Wakeup sequence from Standby mode when using more than
one wakeup source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1.4 Full JTAG configuration without NJTRST pin cannot be used . . . . . . . . 11
2.1.5 MPU attribute to RTC and IWDG registers could be managed
incorrectly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.6 Delay after an RCC peripheral clock enabling . . . . . . . . . . . . . . . . . . . . 12
2.1.7 Internal noise impacting the ADC accuracy . . . . . . . . . . . . . . . . . . . . . . 12
2.1.8 Over-drive and Under-drive modes unavailability . . . . . . . . . . . . . . . . . 13
2.2 IWDG peripheral limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.1 RVU and PVU flags are not reset in STOP mode . . . . . . . . . . . . . . . . . 13
2.3 I2C peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.1 SMBus standard not fully supported . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.2 Start cannot be generated after a misplaced Stop . . . . . . . . . . . . . . . . . 14
2.3.3 Mismatch on the “Setup time for a repeated Start condition” timing
parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.4 Data valid time (t
2.3.5 Both SDA and SCL maximum rise time (t
higher than ((VDD+0.3) / 0.7) V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
) violated without the OVR flag being set . . . . . 14
VD;DAT
) violated when VDD_I2C bus
r
2.4 I2S peripheral limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4.1 In I2S slave mode, WS level must be set by the external master
when enabling the I2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5 USART peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.5.1 Idle frame is not detected if receiver clock speed is deviated . . . . . . . . 16
2.5.2 In full duplex mode, the Parity Error (PE) flag can be cleared by
writing to the data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.5.3 Parity Error (PE) flag is not set when receiving in Mute mode
using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.5.4 Break frame is transmitted regardless of nCTS input line status . . . . . . 17
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STM32F42xx and STM32F43xx Contents
2.5.5 nRTS signal abnormally driven low after a protocol violation . . . . . . . . 17
2.6 OTG_FS peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.6.1 Data in RxFIFO is overwritten when all channels are disabled
simultaneously . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.6.2 OTG host blocks the receive channel when receiving IN packets and no
TxFIFO is configured . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.6.3 Host channel-halted interrupt not generated when the channel is
disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.6.4 Error in software-read OTG_FS_DCFG register values . . . . . . . . . . . . 18
2.7 Ethernet peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.7.1 Incorrect layer 3 (L3) checksum is inserted in transmitted IPv6 packets
without TCP, UDP or ICMP payloads . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.7.2 The Ethernet MAC processes invalid extension headers in the received
IPv6 frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.7.3 MAC stuck in the Idle state on receiving the TxFIFO flush command
exactly 1 clock cycle after a transmission completes . . . . . . . . . . . . . . . 19
2.7.4 Transmit frame data corruption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.7.5 Successive write operations to the same register might not be fully
taken into account . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.8 FMC peripheral limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.8.1 Dummy read cycles inserted when reading synchronous memories . . . 23
2.8.2 FMC synchronous mode and NWAIT signal disabled . . . . . . . . . . . . . . 23
2.8.3 Read access to a non-initialized FMC_SDRAM bank . . . . . . . . . . . . . . 23
2.8.4 Corruption of data read from the FMC . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.8.5 Interruption of CPU read burst access to an end of SDRAM row . . . . . 24
2.8.6 FMC NOR/PSRAM controller: asynchronous read access on bank 2 to 4
returns wrong data when bank 1 is in synchronous mode
(BURSTEN bit is set) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.8.7 FMC dynamic and static banks switching . . . . . . . . . . . . . . . . . . . . . . . 25
2.9 SDIO peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.9.1 SDIO HW flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.9.2 Wrong CCRCFAIL status after a response without CRC is received . . . 25
2.9.3 Data corruption in SDIO clock dephasing (NEGEDGE) mode . . . . . . . . 26
2.9.4 CE-ATA multiple write command and card busy signal management . . 26
2.9.5 No underrun detection with wrong data transmission . . . . . . . . . . . . . . 26
2.10 ADC peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.10.1 ADC sequencer modification during conversion . . . . . . . . . . . . . . . . . . 27
2.11 DAC peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.11.1 DMA underrun flag management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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Contents STM32F42xx and STM32F43xx
2.11.2 DMA request not automatically cleared by DMAEN=0 . . . . . . . . . . . . . 27
Appendix A Revision code on device marking . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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STM32F42xx and STM32F43xx List of tables
List of tables
Table 1. Device identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 3. Corte x- M 4 cor e limitat ions an d im pa ct on mi cr ocontroller behavior. . . . . . . . . . . . . . . . . . . 7
Table 4. Summary of silicon limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. Impacted registers and bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 6. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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List of figures STM32F42xx and STM32F43xx
List of figures
Figure 1. TFBGA216 top package view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 2. WLCSP143 top package view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 3. LQFP208 top package view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 4. UFBGA176 top package view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 5. LQFP176 top package view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 6. LQFP144 top package view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 7. LQFP100 top package view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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STM32F42xx and STM32F43xx ARM 32-bit Cortex-M4 with FPU limitations
1 ARM 32-bit Cortex-M4 with FPU limitations
An errata notice of the STM32F42xx and STM32F43xx core is available from the following
web address:
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b_errata_01/index.html.
All the described limitations are minor and related to the revision r0p1-v1 of the CortexM4
core. Table 3 summarizes these limitations and their implications on the behavior of
STM32F42xx and STM32F43xx devices.
Table 3. Cortex-M4 core limitations and impact on microcontroller behavior
ARM ID
752419 Cat 2
ARM
category
ARM summary of errata
Interrupted loads to SP can cause erroneous
behavior
Impact on STM32F42xx
and STM32F43xx
Minor
1.1 Cortex-M4 interrupted loads to stack pointer can cause erroneous behavior
Description
An interrupt occurring during the data-phase of a single word load to the stack pointer
(SP/R13) can cause an erroneous behavior of the device. In addition, returning from the
interrupt results in the load instruction being executed an additional time.
For all the instructions performing an update of the base register, the base register is
erroneously updated on each execution, resulting in the stack pointer being loaded from an
incorrect memory location.
The instructions affected by this limitation are the following:
• LDR SP, [Rn],#imm
• LDR SP, [Rn,#imm]!
• LDR SP, [Rn,#imm]
• LDR SP, [Rn]
• LDR SP, [Rn,Rm]
Workaround
As of today, no compiler generates these particular instructions. This limitation can only
occur with hand-written assembly code.
Both limitations can be solved by replacing the direct load to the stack pointer by an
intermediate load to a general-purpose register followed by a move to the stack pointer.
Example:
Replace LDR SP, [R0] by
LDR R2,[R0]
MOV SP,R2
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STM32F42xx and STM32F43xx silicon limitations STM32F42xx and STM32F43xx
2 STM32F42xx and STM32F43xx silicon limitations
Table 4 gives quick references to all documented limitations.
Legend for Table 4: A = workaround available; N = no workaround available; P = partial
workaround available, ‘-’ and grayed = fixed.
Table 4. Summary of silicon limitations
Links to silicon limitations Revision A Revision Y
Section 2.1.1: Debugging Stop mode and system tick timer AA
Section 2.1.2: Debugging Stop mode with WFE entry AA
Section 2.1: System
limitations
Section 2.2: IWDG
peripheral limitation
Section 2.3: I2C peripheral
limitations
Section 2.1.3: Wakeup sequence from Standby mode
when using more than one wakeup source
Section 2.1.4: Full JTAG configuration without NJTRST pin
cannot be used
Section 2.1.5: MPU attribute to RTC and IWDG registers
could be managed incorrectly
Section 2.1.6: Delay after an RCC peripheral clock
enabling
Section 2.1.7: Internal noise impacting the ADC accuracy AA
Section 2.1.8: Over-drive and Under-drive modes
unavailability
Section 2.2.1: RVU and PVU flags are not reset in STOP
mode
Section 2.3.1: SMBus standard not fully supported AA
Section 2.3.2: Start cannot be generated after a misplaced
Stop
Section 2.3.3: Mismatch on the “Setup time for a repeated
Start conditio n” ti ming parameter
Section 2.3.4: Data valid time (tVD;DAT) violated without
the OVR flag being set
Section 2.3.5: Both SDA and SCL maximum rise time (tr)
violated when VDD_I2C bus higher than ((VDD+0.3) /
0.7) V
AA
AA
AA
AA
N
AA
AA
AA
AA
AA
-
Section 2.4: I2S peripheral
limitation
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Section 2.4.1: In I2S slave mode, WS level must be set by
the external master when enabling the I2S
AA
STM32F42xx and STM32F43xx STM32F42xx and STM32F43xx silicon limitations
Table 4. Summary of silicon limitations (continued)
Links to silicon limitations Revision A Revision Y
Section 2.5: USART
peripheral limitations
Section 2.6: OTG_FS
peripheral limitations
Section 2.5.1: Idle frame is not detected if recei ve r clock
speed is deviated
Section 2.5.2: In full duplex mode, the Parity Error (PE) flag
can be cleared by writing to the data register
Section 2.5.3: Parity Error (PE) flag is not set when
receiving in Mute mode using address mark detection
Section 2.5.4: Break frame is transmitted regardless of
nCTS input line status
Section 2.5.5: nRTS signal abnormally driven low after a
protocol violation
Section 2.6.1: Data in RxFIFO is overwritten when all
channels are disabled simultaneously
Section 2.6.2: OTG host blocks the receive channel when
receiving IN packets and no TxFIFO is configured
Section 2.6.3: Host channel-halted interrupt not generated
when the channel is disabled
Section 2.6.4: Error in software-read OTG_FS_DCFG
register values
Section 2.7.1: Incorrect layer 3 (L3) checksum is inserted
in transmitted IPv6 packets without TCP, UDP or ICMP
payloads
NN
AA
NN
NN
AA
AA
AA
AA
AA
AA
Section 2.7: Ethernet
peripheral limitations
Section 2.8: FMC peripheral
limitation
Section 2.7.2: The Ethernet MAC processes invalid
extension headers in the received IPv6 frames
NN
Section 2.7.3: MAC stuck in the Idle state on receiving the
TxFIFO flush command exactly 1 clock cycle after a
AA
transmission completes
Section 2.7.4: Transmit frame data corruption AA
Section 2.7.5: Successive write operations to the same
register might not be fully taken into account
Section 2.8.1: Dummy read cycles inserted when reading
synchronous memories
Section 2.8.2: FMC synchronous mode and NWAIT signal
disabled
Section 2.8.3: Read access to a non-initialized
FMC_SDRAM bank
Section 2.8.4: Corruption of data read from the FMC A
Section 2.8.5: Interruption of CPU read burst access to an
end of SDRAM row
AA
NN
AA
PP
-
AA
Section 2.8.6: FMC NOR/PSRAM controller: asynchronous
read access on bank 2 to 4 returns wrong data when bank
AA
1 is in synchronous mode (BURSTEN bit is set)
Section 2.8.7: FMC dynamic and static banks switching AA
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Table 4. Summary of silicon limitations (continued)
Links to silicon limitations Revision A Revision Y
Section 2.9.1: SDIO HW flow control NN
Section 2.9.2: Wrong CCRCFAIL status after a response
without CRC is received
Section 2.9: SDIO
peripheral limitations
Section 2.10: ADC
peripheral limitations
Section 2.11: DAC
peripheral limitations
Section 2.9.3: Data corruption in SDIO clock dephasing
(NEGEDGE) mode
Section 2.9.4: CE-ATA multiple write command and card
busy signal management
Section 2.9.5: No underrun detection with wrong data
transmission
Section 2.10.1: ADC sequencer modification during
conversion
Section 2.11.1: DMA underrun flag management AA
Section 2.11.2: DMA request not automatically cleared by
DMAEN=0
2.1 System limitations
2.1.1 Debugging Stop mode and system tick timer
Description
If the system tick timer interrupt is enabled during the Stop mode debug (DBG_STOP bit set
in the DBGMCU_CR register), it will wake up the system from Stop mode.
AA
NN
AA
AA
AA
AA
Workaround
To debug the Stop mode, disable the system tick timer interrupt.
2.1.2 Debugging Stop mode with WFE entry
Description
When the Stop debug mode is enabled (DBG_STOP bit set in the DBGMCU_CR register),
this allows software debugging during Stop mode.
However, if the application software uses the WFE instruction to enter Stop mode, after
wakeup some instructions could be missed if the WFE is followed by sequential instructions.
This affects only Stop debug mode with WFE entry.
Workaround
To debug Stop mode with WFE entry, the WFE instruction must be inside a dedicated
function with 1 instruction (NOP) between the execution of the WFE and the Bx LR.
Example:
__asm void _WFE(void) {
WFE
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STM32F42xx and STM32F43xx STM32F42xx and STM32F43xx silicon limitations
NOP
BX lr }
2.1.3 Wakeup sequence from Standby mode when using more than one wakeup source
Description
The various wakeup sources are logically OR-ed in front of the rising-edge detector which
generates the wakeup flag (WUF). The WUF needs to be cleared prior to Standby mode
entry, otherwise the MCU wakes up immediately.
If one of the configured wakeup sources is kept high during the clearing of the WUF (by
setting the CWUF bit), it may mask further wakeup events on the input of the edge detector.
As a consequence, the MCU might not be able to wake up from Standby mode.
Workaround
To avoid this problem, the following sequence should be applied before entering
Standby mode:
• Disable all used wakeup sources,
• Clear all related wakeup flags,
• Re-enable all used wakeup sources,
• Enter Standby mode
Note: Be aware that, when applying this workaround, if one of the wakeup sources is still kept
high, the MCU enters Standby mode but then it wakes up immediately generating a power
reset.
2.1.4 Full JTAG configuration without NJTRST pin cannot be used
Description
When using the JT AG d ebug port in debug mod e, the connection with th e debugger is lost if
the NJTRST pin (PB4) is used as a GPIO. Only the 4-wire JTAG port configuration is
impacted.
Workaround
Use the SWD debug port instead of the full 4-wire JTAG port.
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