STMicroelectronics STM32F328C8 User manual

STM32F328C8

Errata sheet

STM32F328C8 Rev Z device limitations

Silicon identification

This errata sheet applies to revision Z of the STMicroelectronics STM32F328C8 product. These families feature an Arm® 32-bit Cortex®-M4 FPU core, for which an errata notice is also available (see Section 1 for details).

Section 2 gives a detailed description of the product silicon limitations. The products are identifiable as shown in Table 1:

•By the revision code marked below the order code on the device package

•By the last three digits of the Internal order code printed on the box label

Table 1. Device identification(1)(2)

Order code	Revision code marked on device
STM32F328C8	“Z”

1.The REV_ID bits in the DBGMCU_IDCODE register show the revision code of the device (see the STM32F328C8 reference manual for details on how to find the revision code).

2.Refer to datasheet for the device marking.

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Contents	STM32F328C8

Contents

1

Arm® 32-bit Cortex®-M4 FPU core limitations . . . . . . . . . . . . . . . . . . . .

4

1.1Cortex-M4 FPU core interrupted loads to stack pointer can

cause erroneous behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2VDIV or VSQRT instructions might not complete correctly

when very short ISRs are used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2	STM32F328C8 silicon limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6
	2.1 System limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7

2.1.1Wakeup sequence from Standby mode when using more than

one wakeup source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.2 Full JTAG configuration without NJTRST pin cannot be used . . . . . . . . . 8

2.1.3CCM RAM write protection register SYSCFG_RCR not reset by

system reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2	ADC peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		8
	2.2.1	DMA overrun in dual interleaved mode with single DMA channel . . . . .	. 8
	2.2.2	Sampling time shortened in JAUTO autodelayed mode . . . . . . . . . . . .	. 9
	2.2.3	Injected queue of context not available in case of JQM = 0 . . . . . . . . .	. 9
	2.2.4	Load multiple not supported by ADC interface . . . . . . . . . . . . . . . . . . .	. 9
	2.2.5	Possible voltage drop caused by a transitory phase when the ADC
		switches from a regular channel to an injected channel Rank 1 . . . . . .	10
	2.2.6	Overrun flag may not be set if converted data are not read before
		writing new data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
	2.2.7	ADC differential mode: common mode input range . . . . . . . . . . . . . . . .	10
	2.2.8	Imprecise VREFINT calibration values . . . . . . . . . . . . . . . . . . . . . . . . .	11

2.3	DAC peripheral limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		11
	2.3.1	PA5 cannot be used as GPIO when DAC1 channel 2 is used internally	11
2.4	SPI peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		11

2.4.1SPI CRC may be corrupted when a peripheral connected to the same DMA channel of the SPI is under DMA transaction near the end of

transfer or end of transfer ‘-1’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.4.2BSY bit may stay high at the end of a SPI data transfer in slave mode . 12

2.5 I2C peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.5.110-bit slave mode: wrong direction bit value after read header

reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.5.210-bit combined with 7-bit slave mode: ADDCODE may indicate wrong

slave address detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

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2.5.3Wakeup frames may not wake up the MCU mode when Stop mode

entry follows I2C enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.5.4Wrong behaviors related with MCU Stop mode when wakeup from Stop

mode by I2C peripheral disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.5.5Wakeup frame may not wake up from Stop if tHD(STA) is close to tsu(HSI) in Fast-mode and Fast-mode Plus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.5.6Wrong data sampling when data set-up time (tSU;DAT) is smaller than

one I2CCLK period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.5.7 Spurious bus error detection in master mode . . . . . . . . . . . . . . . . . . . . 16

2.6 USART peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.6.1When PCLK is selected as clock source for USART1, PCLK1

is used instead of PCLK2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16

2.6.2Start bit detected too soon when sampling for NACK signal

from the smartcard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.6.3Break request can prevent the transmission complete flag (TC) from

being set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.6.4 nRTS is active while RE or UE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . .

17

2.6.5Receiver timeout counter starting in case of two stop bit configuration . 17

2.6.6 Data corruption due to noisy receive line . . . . . . . . . . . . . . . . . . . . . . . . 17

2.7 GPIO peripheral limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.7.1GPIOx locking mechanism is not working properly for

GPIOx_OTYPE register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Arm® 32-bit Cortex®-M4 FPU core limitations		STM32F328C8
1	Arm® 32-bit Cortex®-M4 FPU core limitations

An errata notice of the STM32F328C8 core is available from the following web address: http://infocenter.arm.com.

All the described limitations are minor and related to the revision r0p1-v1 of the Cortex-M4 FPU core. Table 2 summarizes these limitations and their implications on the behavior of STM32F3xxxx devices.

1.1Cortex-M4 FPU core interrupted loads to stack pointer can cause erroneous behavior

Description

An interrupt occurring during the data-phase of a single word load to the stack pointer (SP/R13) can cause an erroneous behavior of the device. In addition, returning from the interrupt results in the load instruction being executed with an additional time.

For all the instructions performing an update of the base register, the base register is erroneously updated on each execution, resulting in the stack pointer being loaded from an incorrect memory location.

The instructions affected by this limitation are the following:

•LDR SP, [Rn],#imm

•LDR SP, [Rn,#imm]!

•LDR SP, [Rn,#imm]

•LDR SP, [Rn]

•LDR SP, [Rn,Rm]

Workaround

As of today, no compiler generates these particular instructions. This limitation can only occur with hand-written assembly code.

Both issues can be solved by replacing the direct load to the stack pointer by an intermediate load to a general-purpose register followed by a move to the stack pointer.

Example: Replace LDR SP, [R0] by LDR R2,[R0]

MOV SP,R2

1.2VDIV or VSQRT instructions might not complete correctly when very short ISRs are used

Description

On Cortex-M4 with FPU core, 14 cycles are required to execute a VDIV or VSQRT instruction.

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Arm® 32-bit Cortex®-M4 FPU core limitations

This limitation is present when the following conditions are met:

•A VDIV or VSQRT is executed.

•The destination register for VDIV or VSQRT is one of s0 - s15.

•An interrupt occurs and is taken.

•The ISR being executed does not contain a floating point instruction.

•14 cycles after the VDIV or VSQRT is executed, an interrupt return is executed.

In this case, if there are only one or two instructions inside the interrupt service routine, then the VDIV or VQSRT instruction does not complete correctly and the register bank and FPSCR are not updated, meaning that these registers hold incorrect out-of-date data.

Workaround

Two workarounds are applicable:

•Disable lazy context save of floating point state by clearing LSPEN to 0 (bit 30 of the FPCCR at address 0xE000EF34).

•Ensure that every ISR contains more than two instructions in addition to the exception return instruction.

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STM32F328C8 silicon limitations	STM32F328C8

2 STM32F328C8 silicon limitations

Table 2 gives quick references to all documented limitations.

Legend for Table 2 is as follows: A = workaround available;

N = no workaround available;

P = partial workaround available, ‘-’ and grayed = fixed.

Table 2. Summary of silicon limitations

		Links to silicon limitations	Revision Z
		Section 2.1.1: Wakeup sequence from Standby mode when using more	A
		than one wakeup source
	Section 2.1: System
		Section 2.1.2: Full JTAG configuration without NJTRST pin cannot be used	A
	limitations
		Section 2.1.3: CCM RAM write protection register SYSCFG_RCR not reset	A
		by system reset.
		Section 2.2.1: DMA overrun in dual interleaved mode with single DMA	A
		channel
		Section 2.2.2: Sampling time shortened in JAUTO autodelayed mode	A
		Section 2.2.3: Injected queue of context not available in case of JQM = 0	N
	Section 2.2: ADC	Section 2.2.4: Load multiple not supported by ADC interface	A
		Section 2.2.5: Possible voltage drop caused by a transitory phase when
	peripheral limitations		A
		the ADC switches from a regular channel to an injected channel Rank 1
		Section 2.2.6: Overrun flag may not be set if converted data are not read	A
		before writing new data
		Section 2.2.7: ADC differential mode: common mode input range	N
		Section 2.2.8: Imprecise VREFINT calibration values	N
	Section 2.3: DAC	Section 2.3.1: PA5 cannot be used as GPIO when DAC1 channel 2 is used	N
	peripheral limitation	internally
		Section 2.4.1: SPI CRC may be corrupted when a peripheral connected to
	Section 2.4: SPI	the same DMA channel of the SPI is under DMA transaction near the end	P
		of transfer or end of transfer ‘-1’
	peripheral limitations
		Section 2.4.2: BSY bit may stay high at the end of a SPI data transfer in	A
		slave mode

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