ST MICROELECTRONICS STM32F303RBT6 Datasheet

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STM32F303xB STM32F303xC

LQFP64 (10 × 10 mm) LQFP100 (14 × 14 mm)

LQFP48 (7 × 7 mm)

WLCSP100 (0.4 mm pitch)

Arm®-based Cortex®-M4 32b MCU+FPU, up to 256KB Flash+

48KB SRAM, 4 ADCs, 2 DAC ch., 7 comp, 4 PGA, timers, 2.0-3.6 V

Datasheet - production data

Features

• Core: Arm® Cortex®-M4 32-bit CPU with FPU (72 MHz max), single-cycle multiplication and HW division, instruction and MPU (memory protection unit)

• Operating conditions: –V

• Memories – 128 to 256 Kbytes of Flash memory – Up to 40 Kbytes of SRAM, with HW parity

check implemented on the first 16 Kbytes.

– Routine booster: 8 Kbytes of SRAM on

instruction and data bus, with HW parity check (CCM)

• CRC calculation unit

• Reset and supply management

– Power-on/power-down reset (POR/PDR) – Programmable voltage detector (PVD) – Low-power modes: Sleep, Stop and

Standby

–V

BAT

• Clock management –4

to 32 MHz crystal oscillator

– 32 kHz oscillator for RTC with calibration – Internal 8 MHz RC with x 16 PLL option –

Internal 40 kHz oscillator

• Up to 87 fast I/Os – All mappable on external interrupt vectors – Several 5 V-tolerant

• Interconnect matrix

• 12-channel DMA controller

•

Four ADCs 0.20 µS (up to 39 channels) with

selectable resolution of 12/10/8/6 bits, 0 to

3.6 V conversion range, single ended/differential input, separate analog supply from 2 to 3.6 V

•

Two 12-bit DAC channels with analog supply

from 2.4 to 3.6 V

90 DMIPS (from CCM), DSP

, V

voltage range: 2.0 V to 3.6 V

DDA

supply for RTC and backup registers

•

Seven fast rail-to-rail analog comparators with

analog supply from 2 to 3.6 V

•

Four operational amplifiers that can be used in

PGA mode, all terminals accessible with analog supply from 2.4 to 3.6 V

•

Up to 24 capacitive sensing channels supporting touchkey, linear and rotary touch sensor

• Up to

13 timers

– One 32-bit timer and two 16-bit timers with

up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input

–

Two 16-bit 6-channel advanced-control

timer

s, with up to 6 PWM channels,

deadtime generation and emergency stop

– One 16-bit timer with 2 IC/OCs, 1

OCN/PWM, deadtime generation and emergency stop

– Two 16-bit timers with IC/OC/OCN/PWM,

deadtime generation and emergency stop

– Two watchdog timers (independent,

window) – SysTick timer: 24-bit downcounter –

Two 16-bit basic timers to drive the DAC

• Calendar RTC with Alarm, periodic wakeup from Stop/Standby

• Communication interfaces – CAN interface (2.0B Active) –Two I

C Fast mode plus (1 Mbit/s) with 20 mA current sink, SMBus/PMBus, wakeup from STOP

October 2018 DS9118 Rev 14 1/149

This is information on a product in full production.

www.st.com

STM32F303xB STM32F303xC

– Up to five USART/UARTs (ISO 7816

interface, LIN, IrDA, modem control)

– Up to three SPIs, two with multiplexed

half/full duplex I2S interface, 4 to 16

programmable bit frames – USB 2.0 full speed interface –

Infrared transmitter

• Serial wire debug, Cortex JTAG

-M4 with FPU ETM,

• 96-bit unique ID

Table 1. Device summary

Reference Part number

STM32F303xB STM32F303CB, STM32F303RB, STM32F303VB

STM32F303xC STM32F303CC, STM32F303RC, STM32F303VC

2/149 DS9118 Rev 14

STM32F303xB STM32F303xC Contents

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.1 Arm® Cortex®-M4 core with FPU with embedded Flash and SRAM . . . . 14

3.2 Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.5 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.6 Cyclic redundancy check (CRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.7 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.7.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.7.2 Power supply supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.7.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.7.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.8 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.9 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.10 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.11 Direct memory access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.12 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.12.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 20

3.13 Fast analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.13.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.13.2 Internal voltage reference (V

3.13.3 V

3.13.4 OPAMP reference voltage (VREFOPAMP) . . . . . . . . . . . . . . . . . . . . . . 22

battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

BAT

) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

REFINT

3.14 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.15 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.16 Fast comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.17 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.17.1 Advanced timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

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Contents STM32F303xB STM32F303xC

3.17.2 General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16, TIM17) . . . 24

3.17.3 Basic timers (TIM6, TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.17.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.17.5 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.17.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.18 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 25

3.19 Inter-integrated circuit interface (I

C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.20 Universal synchronous/asynchronous receiver transmitter (USART) . . . 27

3.21 Universal asynchronous receiver transmitter (UART) . . . . . . . . . . . . . . . 27

3.22 Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I2S) . 28

3.23 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.24 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.25 Infrared Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.26 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.27 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.27.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.27.2 Embedded trace macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 61

6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 61

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6.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

6.3.6 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

6.3.10 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

6.3.16 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

6.3.17 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

6.3.18 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

6.3.19 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

6.3.20 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

6.3.21 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 122

6.3.22 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

6.3.23 V

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

BAT

7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

7.1 LQFP100 – 14 x 14 mm, low-profile quad flat package

information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

7.2 LQFP64 – 10 x 10 mm, low-profile quad flat package

information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

7.3 LQFP48 – 7 x 7 mm, low-profile quad flat package

information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

7.4 WLCSP100 - 0.4 mm pitch wafer level chip scale package information 135

7.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

7.5.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

7.5.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 140

8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

DS9118 Rev 14 5/149

List of tables STM32F303xB STM32F303xC

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2. STM32F303xB/STM32F303xC family device features and peripheral counts . . . . . . . . . . 12

Table 3. External analog supply values for analog peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 4. STM32F303xB/STM32F303xC peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . 17

Table 5. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 6. Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 7. STM32F303xB/STM32F303xC I

Table 8. USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 9. STM32F303xB/STM32F303xC SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 10. Capacitive sensing GPIOs available on STM32F303xB/STM32F303xC devices . . . . . . . 30

Table 11. No. of capacitive sensing channels available on STM32F303xB/STM32F303xC devices. 30

Table 12. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 13. STM32F303xB/STM32F303xC pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 14. Alternate functions for port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 15. Alternate functions for port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 16. Alternate functions for port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 17. Alternate functions for port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 18. Alternate functions for port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 19. Alternate functions for port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 20. STM32F303xB/STM32F303xC memory map, peripheral register boundary addresses . . 54

Table 21. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 22. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 23. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 24. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 25. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 26. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 27. Programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 28. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 29. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 30. Typical and maximum current consumption from V Table 31. Typical and maximum current consumption from the V Table 32. Typical and maximum V Table 33. Typical and maximum V

DDA

Table 34. Typical and maximum current consumption from V Table 35. Typical current consumption in Run mode, code with data processing running from Flash68

Table 36. Typical current consumption in Sleep mode, code running from Flash or RAM. . . . . . . . . 69

Table 37. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 38. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 39. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 40. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 41. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 42. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 43. LSE oscillator characteristics (f

Table 44. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 45. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 46. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 47. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 48. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

supply at V

DDA

supply . . . . . . . . . . . . . . . . . . 65

= 3.6V . . . . . . . . . . . 64

consumption in Stop and Standby modes. . . . . . . . . . . . . . . . 66

consumption in Stop and Standby modes. . . . . . . . . . . . . . . 66

supply. . . . . . . . . . . . . . . . . . . . . . 67

BAT

= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

LSE

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Table 49. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 50. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 51. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 52. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 53. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 54. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 55. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 56. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 57. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 58. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 59. IWDG min/max timeout period at 40 kHz (LSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 60. WWDG min-max timeout value @72 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 61. I2C timings specification (see I2C specification, rev.03, June 2007) . . . . . . . . . . . . . . . . . 95

Table 62. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 63. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 64. I

S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 65. USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 66. USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 67. USB: Full-speed electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 68. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 69. Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 70. ADC accuracy - limited test conditions, 100-pin packages . . . . . . . . . . . . . . . . . . . . . . . 109

Table 71. ADC accuracy, 100-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table 72. ADC accuracy - limited test conditions, 64-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 73. ADC accuracy, 64-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Table 74. ADC accuracy at 1MSPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Table 75. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Table 76. Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Table 77. Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 78. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Table 79. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Table 80. V

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

BAT

Table 81. LQPF100 – 14 x 14 mm, low-profile quad flat package mechanical data. . . . . . . . . . . . . 126

Table 82. LQFP64 – 10 x 10 mm, low-profile quad flat package mechanical data. . . . . . . . . . . . . . 129

Table 83. LQFP48 – 7 x 7 mm, low-profile quad flat package mechanical data. . . . . . . . . . . . . . . . 132

Table 84. WLCSP100 – 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Table 85. WLCSP100 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . 137

Table 86. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Table 87. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Table 88. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

DS9118 Rev 14 7/149

List of figures STM32F303xB STM32F303xC

List of figures

Figure 1. STM32F303xB/STM32F303xC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 3. Infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 4. STM32F303xB/STM32F303xC LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 5. STM32F303xB/STM32F303xC LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 6. STM32F303xB/STM32F303xC LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 7. STM32F303xB/STM32F303xC WLCSP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 8. STM32F303xB/STM32F303xC memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 9. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 10. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 11. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 12. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 13. Typical V

Figure 14. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 15. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 16. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 17. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 18. HSI oscillator accuracy characterization results for soldered parts . . . . . . . . . . . . . . . . . . 81

Figure 19. TC and TTa I/O input characteristics - CMOS port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 20. TC and TTa I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 21. Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port. . . . . . . . . . . . . . . . . 89

Figure 22. Five volt tolerant (FT and FTf) I/O input characteristics - TTL port. . . . . . . . . . . . . . . . . . . 89

Figure 23. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 24. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 25. I

C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 26. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Figure 27. SPI timing diagram - slave mode and CPHA = 1 Figure 28. SPI timing diagram - master mode Figure 29. I Figure 30. I

S slave timing diagram (Philips protocol)

S master timing diagram (Philips protocol)

Figure 31. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 32. ADC typical current consumption on VDDA pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 33. ADC typical current consumption on VREF+ pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 34. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 35. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 36. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 37. Maximum VREFINT scaler startup time from power down. . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 38. OPAMP voltage noise versus frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 39. LQFP100 – 14 x 14 mm, low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . 126

Figure 40. LQFP100 – 14 x 14 mm, low-profile quad flat package recommended footprint . . . . . . . 127

Figure 41. LQFP100 – 14 x 14 mm, low-profile quad flat package top view example . . . . . . . . . . . . 128

Figure 42. LQFP64 – 10 x 10 mm, low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . 129

Figure 43. LQFP64 – 10 x 10 mm, low-profile quad flat package recommended footprint . . . . . . . . 130

Figure 44. LQFP64 – 10 x 10 mm, low-profile quad flat package top view example . . . . . . . . . . . . . 131

Figure 45. LQFP48 – 7 x 7 mm, low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . 132

Figure 46. LQFP48 - 7 x 7 mm, low-profile quad flat package recommended footprint. . . . . . . . . . . 133

Figure 47. LQFP48 - 7 x 7 mm, low-profile quad flat package top view example . . . . . . . . . . . . . . . 134

Figure 48. WLCSP100 – 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale

current consumption (LSE and RTC ON/LSEDRV[1:0] = ’00’) . . . . . . . . . . . 67

BAT

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

8/149 DS9118 Rev 14

STM32F303xB STM32F303xC List of figures

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Figure 49. WLCSP100 – 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale

package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Figure 50. WLCSP100, 0.4 mm pitch wafer level chip scale package

top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

DS9118 Rev 14 9/149

Introduction STM32F303xB STM32F303xC

1 Introduction

This datasheet provides the ordering information and mechanical device characteristics of the STM32F303xB/STM32F303xC microcontrollers.

This STM32F303xB/STM32F303xC datasheet should be read in conjunction with the STM32F303x, STM32F358xC and STM32F328x4/6/8 reference manual (RM0316). The reference manual is available from the STMicroelectronics website www.st.com.

For information on the Arm

• Cortex®-M4 with FPU Technical Reference Manual, available from the

http://www.arm.com website.

• STM32F3xxx and STM32F4xxx Cortex

available from our website www.st.com.

®(a)

Cortex®-M4 core with FPU, refer to:

-M4 programming manual (PM0214)

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

10/149 DS9118 Rev 14

STM32F303xB STM32F303xC Description

2 Description

The STM32F303xB/STM32F303xC family is based on the high-performance Arm® Cortex®M4

32-bit RISC core with FPU operating at a frequency of up to 72 MHz, and embedding a floating point unit (FPU), a memory protection unit (MPU) and an embedded trace macrocell (ETM). The family incorporates high-speed embedded memories (up to 256 memory, up to 40 peripherals connected to two APB buses.

The devices offer up to four fast 12-bit ADCs (5 Msps), seven comparators, four operational amplifiers, up to two DAC channels, a low-power RTC, up to five general-purpose 16-bit timers, one general-purpose 32-bit timer, and two timers dedicated to motor control. They also feature standard and advanced communication interfaces: up to two I SPIs (two SPIs are with multiplexed full-duplex I2Ss), three USARTs, up to two UARTs, CAN and USB. To achieve audio class accuracy, the I2S peripherals can be clocked via an external PLL.

The STM32F303xB/STM32F303xC family operates in the -40 to +85 °C and -40 to +105 °C temperature ranges from a 2.0 to 3.6 mode allows the design of low-power applications.

The STM32F303xB/STM32F303xC family offers devices in four packages ranging from 48

pins to 100 pins.

Kbytes of SRAM) and an extensive range of enhanced I/Os and

V power supply. A comprehensive set of power-saving

Kbytes of Flash

Cs, up to three

The set of included peripherals changes with the device chosen.

DS9118 Rev 14 11/149

Description STM32F303xB STM32F303xC

Table 2. STM32F303xB/STM32F303xC family device features and peripheral counts

Peripheral STM32F303Cx STM32F303Rx STM32F303Vx

Flash (Kbytes) 128 256 128 256 128 256

SRAM (Kbytes) on data bus 32 40 32 40 32 40

CCM (Core Coupled Memory) RAM (Kbytes)

Advanced control

2 (16-bit)

Timers

General purpose

5 (16-bit) 1 (32-bit)

Basic 2 (16-bit)

PWM channels (all)

(1)

PWM channels (except complementary)

SPI (I2S)

Communication interfaces

USART 3

UART 0 2

(2)

31 33

22 24

3(2)

CAN 1

USB 1

Normal I/Os (TC, TTa)

20 27

45 in LQFP100

37 in WLCSP100

GPIOs

5-volt tolerant I/Os (FT, FTf)

17 25

42 in LQFP100

40 in WLCSP100

DMA channels 12

Capacitive sensing channels 17 18 24

12-bit ADCs

Number of channels

15 22

39 in LQFP100

32 in WLCSP100

12-bit DAC channels 2

Analog comparator 7

Operational amplifiers 4

CPU frequency 72 MHz

Operating voltage 2.0 to 3.6 V

Operating temperature

Ambient operating temperature: - 40 to 85 °C / - 40 to 105 °C

Packages LQFP48 LQFP64

1. This total number considers also the PWMs generated on the complementary output channels

2. The SPI interfaces can work in an exclusive way in either the SPI mode or the I2S audio mode.

12/149 DS9118 Rev 14

Junction temperature: - 40 to 125 °C

LQFP100

WLCSP100

STM32F303xB STM32F303xC Description

MS18960V4

Touch Sensing

Controller

TIMER 16

2 Channels,1 Comp Channel, BRK as AF

TIMER 17

TIMER 1 / PWM

TIMER 8 / PWM

4 Channels, 4 Comp channels, ETR, BRK as AF

SPI1

MOSI, MISO, SCK,NSS as AF

USART1

RX, TX, CTS, RTS, SmartCard as AF

WinWATCHDOG

BusMatrix

MPU/FPU

Cortex M4 CPU

max

: 72 MHz

NVIC

GP DMA1

7 channels

CCM RAM

8KB

Flash

interface

OBL

FLASH 256 KB

64 bits

JTRST

JTDI JTCK/SWCLK JTMS/SWDIO

JTDO As AF

Power

Voltage reg.

3.3 V to 1.8V

DD18

Supply

Supervision

POR /PDR

PVD

POR

Reset Int.

DDIO

= 2 to 3.6 V

NRESET V

DDA

SSA

Ind. WDG32K

Standby interface

PLL

DDIO

DDA

XTAL OSC

4 -32 MHz

Reset &

clock

control

AHBPCLK

APBP1CLK

APBP2CLK

AHB2 APB2

AHB2 APB1

CRC

APB1 F

max

= 36 MHz

APB2 f

max

= 72 MHz

GPIO PORT A

GPIO PORT B

GPIO PORT C

GPIO PORT D

GPIO PORT E

OSC_IN OSC_OUT

SPI3/I2S

SCL, SDA, SMBA as AF

USART2

SCL, SDA, SMBA as AF

USART3

RC LS

TIMER6

TIMER 4

SPI2/I2S

12bit DAC1IF

DDA

TIMER2

(32-bit/PWM)

PA[15:0]

PB[15:0]

PC[15:0]

MOSI/SD, MISO/ext_SD, SCK/CK, NSS/WS, MCLK as AF

4 Channels, ETR as AF

USB_DP, USB_DM

DAC1_CH1 as AF

HCLK FCLK

USARTCLK

RC HS 8MHz

SRAM 40 KB

ETM

Trace/Trig

SWJTAG

TPIU

Ibus

TRADECLK

TRACED[0-3]

as AF

Dbus

System

GP DMA2

5 channels

12-bit ADC1

12-bit ADC2

Temp. sensor

REF+

REF-

TIMER 15

EXT.IT WKUP

XX AF

1 Channel, 1 Comp Channel, BRK as AF

4 Channels, 4 Comp channels, ETR, BRK as AF

GPIO PORT F

PD[15:0]

PE[15:0]

TIMER7

USB SRAM 512B

PF[7:0]

12-bit ADC3

12-bit ADC4

I2CCLK ADC SAR 1/2/3/4 CLK

DDIO

DDA

@VSW

XTAL 32kHz

OSC32_IN OSC32_OUT

BAT

= 1.65V to 3.6V

RTC

AWU

Backup

Reg

(64Byte)

Backup

interface

ANTI-TAMP

TIMER 3

UART4

UART5

I2C1

I2C2

bx CAN &

512B SRAM

USB 2.0 FS

DAC1_CH2 as AF

OpAmp1

OpAmp2

OpAmp3

OpAmp4

DDA

INxx / OUTxx

INTERFACE

SYSCFG CTL

GP Comparator 7

GP Comparator...

GP Comparator 1

CAN TX, CAN RX

4 Channels, ETR as AF

MOSI/SD, MISO/ext_SD, SCK/CK, NSS/WS, MCLK as AF

RX, TX, CTS, RTS, as AF

RX, TX as AF

DDA

Xx Ins, 7 OUTs as AF

XX Groups of

4 channels as AF

AHB2

AHB3

Figure 1. STM32F303xB/STM32F303xC block diagram

1. AF: alternate function on I/O pins.

DS9118 Rev 14 13/149

Functional overview STM32F303xB STM32F303xC

3 Functional overview

3.1 Arm® Cortex®-M4 core with FPU with embedded Flash and SRAM

The Arm Cortex-M4 processor with FPU is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.

The Arm Cortex-M4 32-bit RISC processor with FPU features exceptional code-efficiency, delivering the high-performance expected from an Arm core in the memory size usually associated with 8- and 16-bit devices.

The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution.

Its single precision FPU speeds up software development by using metalanguage development tools, while avoiding saturation.

With its embedded Arm core, the STM32F303xB/STM32F303xC family is compatible with all Arm tools and software.

Figure 1 shows the general block diagram of the STM32F303xB/STM32F303xC family

devices.

3.2 Memory protection unit (MPU)

The memory protection unit (MPU) is used to separate the processing of tasks from the data protection. The MPU can manage up to 8 protection areas that can all be further divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory.

The memory protection unit is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-time operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

3.3 Embedded Flash memory

All STM32F303xB/STM32F303xC devices feature up to 256 Kbytes of embedded Flash memory available for storing programs and data. The Flash memory access time is adjusted to the CPU clock frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above).

14/149 DS9118 Rev 14

STM32F303xB STM32F303xC Functional overview

3.4 Embedded SRAM

STM32F303xB/STM32F303xC devices feature up to 48 Kbytes of embedded SRAM with hardware parity check. The memory can be accessed in read/write at CPU clock speed with 0 wait states, allowing the CPU to achieve 90 Dhrystone Mips at 72 MHz (when running code from the CCM (Core Coupled Memory) RAM).

• 8 Kbytes of CCM RAM mapped on both instruction and data bus, used to execute

critical routines or to access data (parity check on all of CCM RAM).

• 40 Kbytes of SRAM mapped on the data bus (parity check on first 16 Kbytes of SRAM).

3.5 Boot modes

At startup, Boot0 pin and Boot1 option bit are used to select one of three boot options:

• Boot from user Flash

• Boot from system memory

• Boot from embedded SRAM

The boot loader is located in the system memory. It is used to reprogram the Flash memory by using USART1 (PA9/PA10), USART2 (PD5/PD6) or USB (PA11/PA12) through DFU (device firmware upgrade).

3.6 Cyclic redundancy check (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.

DS9118 Rev 14 15/149

Functional overview STM32F303xB STM32F303xC

3.7 Power management

3.7.1 Power supply schemes

• VSS, V

= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. It is

provided externally through V

• V

SSA

, V

= 2.0 to 3.6 V: external analog power supply for ADC, DACs, comparators

DDA

operational amplifiers, reset blocks, RCs and PLL. The minimum voltage to be applied to V the V greater or equal to the V

• V

differs from one analog peripheral to another. Ta ble 3 provides the summary of

DDA

ranges for analog peripherals. The V

DDA

= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and

BAT

voltage level and must be provided first.

backup registers (through power switch) when V

Table 3. External analog supply values for analog peripherals

Analog peripheral Minimum V

ADC / COMP 2.0 V 3.6 V

DAC / OPAMP 2.4 V 3.6V

3.7.2 Power supply supervision

The device has an integrated power-on reset (POR) and power-down reset (PDR) circuits. They are always active, and ensure proper operation above a threshold of 2 V. The device remains in reset mode when the monitored supply voltage V

POR/PDR, without the need for an external reset circuit.

• The POR monitors only the VDD supply voltage. During the startup phase it is required

that V

• The PDR monitors both the V

supply supervisor can be disabled (by programming a dedicated Option bit) to reduce the power consumption if the application design ensures that V equal to V

The device features an embedded programmable voltage detector (PVD) that monitors the V

power supply and compares it to the VPVD threshold. An interrupt can be generated

when V

threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

should arrive first and be greater than or equal to VDD.

DDA

drops below the V

PVD

pins.

voltage level must be always

DDA

is not present.

supply Maximum V

DDA

is below a specified threshold,

and V

threshold and/or when VDD is higher than the V

supply voltages, however the V

DDA

is higher than or

supply

DDA

PVD

power

3.7.3 Voltage regulator

The regulator has three operation modes: main (MR), low-power (LPR), and power-down.

• The MR mode is used in the nominal regulation mode (Run)

• The LPR mode is used in Stop mode.

• The power-down mode is used in Standby mode: the regulator output is in high

impedance, and the kernel circuitry is powered down thus inducing zero consumption.

The voltage regulator is always enabled after reset. It is disabled in Standby mode.

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3.7.4 Low-power modes

The STM32F303xB/STM32F303xC supports three low-power modes to achieve the best compromise between low-power consumption, short startup time and available wakeup sources:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

• Stop mode

Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode.

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the USB wakeup, the RTC alarm, COMPx, I2Cx or U(S)ARTx.

• Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin or an RTC alarm occurs.

Note: The RTC, the IWDG and the corresponding clock sources are not stopped by entering Stop

or Standby mode.

3.8 Interconnect matrix

Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections allow fast and predictable latency.

Interconnect source

TIMx

COMPx TIMx Timer input: OCREF_CLR input, input capture

ADCx TIMx Timer triggered by analog watchdog

Table 4. STM32F303xB/STM32F303xC peripheral interconnect matrix

Interconnect

destination

TIMx Timers synchronization or chaining

ADCx DAC1

DMA Memory to memory transfer trigger

Compx Comparator output blanking

Conversion triggers

Interconnect action

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Functional overview STM32F303xB STM32F303xC

Table 4. STM32F303xB/STM32F303xC peripheral interconnect matrix (continued)

Interconnect source

GPIO RTCCLK HSE/32 MC0

CSS CPU (hard fault) COMPx PVD GPIO

GPIO

DAC1 COMPx Comparator inverting input

Interconnect

destination

TIM16

TIM1, TIM8, TIM15, 16, 17

TIMx External trigger, timer break

ADCx DAC1

Clock source used as input channel for HSI and LSI calibration

Timer break

Conversion external trigger

Interconnect action

Note: For more details about the interconnect actions, please refer to the corresponding sections

in the reference manual (RM0316).

3.9 Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-32

MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example with failure of an indirectly used external oscillator).

Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the high speed APB domains is 72 APB domain is 36

MHz.

MHz, while the maximum allowed frequency of the low speed

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STM32F303xB STM32F303xC Functional overview

/32

4-32 MHz HSE OSC

OSC_IN

OSC_OUT

OSC32_IN

OSC32_OUT

8 MHz

HSI RC

IWDGCLK to IWDG

PLL

x2,x3,..

x16

PLLMUL

AHB

APB1

prescaler

/1,2,4,8,16

HCLK

PLLCLK

to AHB bus, core, memory and DMA

LSE

LSI

HSI

HSE

to RTC

PLLSRC

SYSCLK

RTCCLK

RTCSEL[1:0]

to TIM 2,3,4,6,7

If (APB1 prescaler =1) x1 else x2

FLITFCLK to Flash programming interface

to I2Cx (x = 1,2)

to U(S)ARTx (x = 2..5)

LSE

HSI

SYSCLK

PCLK1

SYSCLK

HSI

PCLK1

MS19989V5

to I2Sx (x = 2,3)

USBCLK to USB interface

to cortex System timer FHCLK Cortex free running clock to APB1 peripherals

AHB prescaler /1,2,..512

CSS

/2,/3,...

/16

LSE OSC

32.768kHz

LSI RC 40kHz

USB

prescaler

/1,1.5

APB2

prescaler

/1,2,4,8,16

to TIM 15,16,17

If (APB2 prescaler =1) x1 else x2

to USART1

LSE

HSI

SYSCLK

PCLK2

to APB2 peripherals

TIM1/8

ADC

Prescaler

/1,2,4

to ADCxy (xy = 12, 34)

ADC

Prescaler

/1,2,4,6,8,10,12,16,

32,64,128,256

I2SSRC

SYSCLK

Ext. clock

I2S_CKIN

MCO

Main clock output

PLLCLK

HSI

HSE

MCO

SYSCLK

LSI

Figure 2. Clock tree

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Functional overview STM32F303xB STM32F303xC

3.10 General-purpose input/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current capable except for analog inputs.

The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.

Fast I/O handling allows I/O toggling up to 36 MHz.

3.11 Direct memory access (DMA)

The flexible general-purpose DMA is able to manage memory-to-memory, peripheral-tomemory and memory-to-peripheral transfers. The DMA controller supports circular buffer management, avoiding the generation of interrupts when the controller reaches the end of the buffer.

Each of the 12 DMA channels is connected to dedicated hardware DMA requests, with software trigger support for each channel. Configuration is done by software and transfer sizes between source and destination are independent.

The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose timers, DAC and ADC.

3.12 Interrupts and events

3.12.1 Nested vectored interrupt controller (NVIC)

The STM32F303xB/STM32F303xC devices embed a nested vectored interrupt controller (NVIC) able to handle up to 66 maskable interrupt channels and 16 priority levels.

The NVIC benefits are the following:

• Closely coupled NVIC gives low latency interrupt processing

• Interrupt entry vector table address passed directly to the core

• Closely coupled NVIC core interface

• Allows early processing of interrupts

• Processing of late arriving higher priority interrupts

• Support for tail chaining

• Processor state automatically saved

• Interrupt entry restored on interrupt exit with no instruction overhead

The NVIC hardware block provides flexible interrupt management features with minimal interrupt latency.

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3.13 Fast analog-to-digital converter (ADC)

four fast analog-to-digital converters 5 MSPS, with selectable resolution between 12 and 6 bit, are embedded in the STM32F303xB/STM32F303xC family devices. The ADCs have up to 39 external channels. Some of the external channels are shared between ADC1&2 and between ADC3&4. Channels can be configured to be either single-ended input or differential input. The ADCs can perform conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs.

The ADCs have also internal channels: Temperature sensor connected to ADC1 channel 16, V ADCs channel 18, VOPAMP1 connected to ADC1 channel 15, VOPAMP2 connected to ADC2 channel 17, VREFOPAMP3 connected to ADC3 channel 17 and VREFOPAMP4 connected to ADC4 channel 17.

Additional logic functions embedded in the ADC interface allow:

• Simultaneous sample and hold

• Interleaved sample and hold

• Single-shunt phase current reading techniques.

The ADC can be served by the DMA controller. 3 analog watchdogs per ADC are available.

An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

connected to ADC1 channel 17, Voltage reference V

BAT/2

connected to the 4

REFINT

The events generated by the general-purpose timers and the advanced-control timers (TIM1 and TIM8) can be internally connected to the ADC start trigger and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers.

3.13.1 Temperature sensor

The temperature sensor (TS) generates a voltage V temperature.

The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only.

To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode.

3.13.2 Internal voltage reference (V

The internal voltage reference (V ADC and Comparators. V

REFINT

channel. The precise voltage of V production test and stored in the system memory area. It is accessible in read-only mode.

REFINT

is internally connected to the ADCx_IN18, x=1...4 input

REFINT

that varies linearly with

SENSE

REFINT

)

) provides a stable (bandgap) voltage output for the

is individually measured for each part by ST during

DS9118 Rev 14 21/149

Functional overview STM32F303xB STM32F303xC

3.13.3 V

battery voltage monitoring

BAT

This embedded hardware feature allows the application to measure the V using the internal ADC channel ADC1_IN17. As the V and thus outside the ADC input range, the V divider by 2. As a consequence, the converted digital value is half the V

pin is internally connected to a bridge

BAT

3.13.4 OPAMP reference voltage (VREFOPAMP)

Every OPAMP reference voltage can be measured using a corresponding ADC internal channel: VREFOPAMP1 connected to ADC1 channel 15, VREFOPAMP2 connected to ADC2 channel 17, VREFOPAMP3 connected to ADC3 channel 17, VREFOPAMP4 connected to ADC4 channel 17.

3.14 Digital-to-analog converter (DAC)

Two 12-bit buffered DAC channels can be used to convert digital signals into analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration.

This digital interface supports the following features:

• Two DAC output channels

• 8-bit or 10-bit monotonic output

• Left or right data alignment in 12-bit mode

• Synchronized update capability

• Noise-wave generation

• Triangular-wave generation

• Dual DAC channel independent or simultaneous conversions

• DMA capability (for each channel)

• External triggers for conversion

battery voltage

voltage may be higher than V

BAT

voltage.

DDA

3.15 Operational amplifier (OPAMP)

The STM32F303xB/STM32F303xC embeds four operational amplifiers with external or internal follower routing and PGA capability (or even amplifier and filter capability with external components). When an operational amplifier is selected, an external ADC channel is used to enable output measurement.

The operational amplifier features:

• 8.2 MHz bandwidth

• 0.5 mA output capability

• Rail-to-rail input/output

• In PGA mode, the gain can be programmed to be 2, 4, 8 or 16.

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3.16 Fast comparators (COMP)

The STM32F303xB/STM32F303xC devices embed seven fast rail-to-rail comparators with programmable reference voltage (internal or external), hysteresis and speed (low speed for low-power) and with selectable output polarity.

The reference voltage can be one of the following:

• External I/O

• DAC output pin

• Internal reference voltage or submultiple (1/4, 1/2, 3/4). Refer to Table 28: Embedded

internal reference voltage on page 63 for the value and precision of the internal

reference voltage.

All comparators can wake up from STOP mode, generate interrupts and breaks for the timers and can be also combined per pair into a window comparator

3.17 Timers and watchdogs

The STM32F303xB/STM32F303xC includes two advanced control timers, up to six generalpurpose timers, two basic timers, two watchdog timers and a SysTick timer. The table below compares the features of the advanced control, general purpose and basic timers.

Table 5. Timer feature comparison

Timer type Timer

Advanced

General-

purpose

General-

purpose

General-

purpose

General-

purpose

Basic

TIM1,

TIM8

TIM2 32-bit

TIM3, TIM4 16-bit

TIM15 16-bit Up

TIM16, TIM17 16-bit Up

TIM6,

TIM7

Counter

resolution

16-bit

16-bit Up

Counter

type

Up, Down,

Up/Down

Up, Down,

Up/Down

Up, Down,

Up/Down

Prescaler

factor

Any integer

between 1 and 65536

Any integer

between 1 and 65536

Any integer

between 1 and 65536

Any integer

between 1 and 65536

Any integer

between 1 and 65536

Any integer

between 1 and 65536

DMA

request

generation

Yes 4 Yes

Yes 4 No

Yes 2 1

Yes 1 1

Yes 0 No

Capture/

compare

Channels

Complementary

outputs

Note: TIM1/8 can have PLL as clock source, and therefore can be clocked at 144 MHz.

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Functional overview STM32F303xB STM32F303xC

3.17.1 Advanced timers (TIM1, TIM8)

The advanced-control timers (TIM1 and TIM8) can each be seen as a three-phase PWM multiplexed on six channels. They have complementary PWM outputs with programmable inserted dead-times. They can also be seen as complete general-purpose timers. The four independent channels can be used for:

• Input capture

• Output compare

• PWM generation (edge or center-aligned modes) with full modulation capability (0-

100%)

• One-pulse mode output

In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled to turn off any power switches driven by these outputs.

Many features are shared with those of the general-purpose TIM timers (described in

Section 3.17.2 using the same architecture, so the advanced-control timers can work

together with the TIM timers via the Timer Link feature for synchronization or event chaining.

3.17.2 General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16, TIM17)

There are up to six synchronizable general-purpose timers embedded in the STM32F303xB/STM32F303xC (see can be used to generate PWM outputs, or act as a simple time base.

• TIM2, 3, and TIM4

These are full-featured general-purpose timers:

– TIM2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler

– TIM3 and 4 have 16-bit auto-reload up/downcounters and 16-bit prescalers.

These timers all feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. They can work together, or with the other generalpurpose timers via the Timer Link feature for synchronization or event chaining.

The counters can be frozen in debug mode.

All have independent DMA request generation and support quadrature encoders.

• TIM15, 16 and 17

These three timers general-purpose timers with mid-range features:

They have 16-bit auto-reload upcounters and 16-bit prescalers.

– TIM15 has 2 channels and 1 complementary channel

– TIM16 and TIM17 have 1 channel and 1 complementary channel

All channels can be used for input capture/output compare, PWM or one-pulse mode output.

The timers can work together via the Timer Link feature for synchronization or event chaining. The timers have independent DMA request generation.

The counters can be frozen in debug mode.

Tab l e 5 for differences). Each general-purpose timer

3.17.3 Basic timers (TIM6, TIM7)

These timers are mainly used for DAC trigger generation. They can also be used as a generic 16-bit time base.

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STM32F303xB STM32F303xC Functional overview

3.17.4 Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.

3.17.5 Window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

3.17.6 SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features:

• A 24-bit down counter

• Autoreload capability

• Maskable system interrupt generation when the counter reaches 0.

• Programmable clock source

3.18 Real-time clock (RTC) and backup registers

The RTC and the 16 backup registers are supplied through a switch that takes power from either the V registers used to store 64 bytes of user application data when V

They are not reset by a system or power reset, or when the device wakes up from Standby mode.

The RTC is an independent BCD timer/counter.It supports the following features:

• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format.

• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision.

• Automatic correction for 28, 29 (leap year), 30 and 31 days of the month.

• Two programmable alarms with wake up from Stop and Standby mode capability.

• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to

synchronize it with a master clock.

• Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal inaccuracy.

• Three anti-tamper detection pins with programmable filter. The MCU can be woken up from Stopand Standby modes on tamper event detection.

• Timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be woken up from Stop and Standby modes on timestamp event detection.

supply when present or the V

pin. The backup registers are sixteen 32-bit

BAT

power is not present.

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Functional overview STM32F303xB STM32F303xC

• 17-bit Auto-reload counter for periodic interrupt with wakeup from STOP/STANDBY capability.

The RTC clock sources can be:

• A 32.768 kHz external crystal

• A resonator or oscillator

• The internal low-power RC oscillator (typical frequency of 40 kHz)

• The high-speed external clock divided by 32.

3.19 Inter-integrated circuit interface (I2C)

Up to two I2C bus interfaces can operate in multimaster and slave modes. They can support standard (up to 100

Both support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2

addresses, 1 with configurable mask). They also include programmable analog and

digital noise filters.

KHz), fast (up to 400 KHz) and fast mode + (up to 1 MHz) modes.

Table 6. Comparison of I2C analog and digital filters

Analog filter Digital filter

Pulse width of suppressed spikes

Benefits Available in Stop mode

Drawbacks

50 ns

Variations depending on temperature, voltage, process

Programmable length from 1 to 15 I2C peripheral clocks

1. Extra filtering capability vs. standard requirements.

2. Stable length

Wakeup from Stop on address match is not available when digital filter is enabled.

In addition, they provide hardware support for SMBUS 2.0 and PMBUS 1.1: ARP capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and ALERT protocol management. They also have a clock domain independent from the CPU clock, allowing the I2Cx (x=1,2) to wake up the MCU from Stop mode on address match.

The I2C interfaces can be served by the DMA controller.

Refer to Tab le 7 for the features available in I2C1 and I2C2.

7-bit addressing mode X X

10-bit addressing mode X X

Standard mode (up to 100 kbit/s) X X

Fast mode (up to 400 kbit/s) X X

Fast Mode Plus with 20mA output drive I/Os (up to 1 Mbit/s) X X

Table 7. STM32F303xB/STM32F303xC I2C implementation

I2C features

(1)

I2C1 I2C2

Independent clock X X

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Table 7. STM32F303xB/STM32F303xC I2C implementation (continued)

I2C features

SMBus X X

Wakeup from STOP X X

1. X = supported.

(1)

I2C1 I2C2

3.20 Universal synchronous/asynchronous receiver transmitter (USART)

The STM32F303xB/STM32F303xC devices have three embedded universal synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3).

The USART interfaces are able to communicate at speeds of up to 9 Mbits/s.

They provide hardware management of the CTS and RTS signals, they support IrDA SIR ENDEC, the multiprocessor communication mode, the single-wire half-duplex communication mode and have LIN Master/Slave capability. The USART interfaces can be served by the DMA controller.

3.21 Universal asynchronous receiver transmitter (UART)

The STM32F303xB/STM32F303xC devices have 2 embedded universal asynchronous receiver transmitters (UART4, and UART5). The UART interfaces support IrDA SIR ENDEC, multiprocessor communication mode and single-wire half-duplex communication mode. The UART4 interface can be served by the DMA controller.

Refer to Tab le 8 for the features available in all U(S)ART interfaces.

Table 8. USART features

USART modes/features

Hardware flow control for modem X X X - -

Continuous communication using DMA X X X X -

Multiprocessor communication X X X X X

Synchronous mode X X X - -

Smartcard mode X X X - -

Single-wire half-duplex communication X X X X X

IrDA SIR ENDEC block X X X X X

LIN mode XXXXX

Dual clock domain and wakeup from Stop mode X X X X X

Receiver timeout interrupt XXXXX

Modbus communication X X X X X

Auto baud rate detection X X X - -

(1)

USART1 USART2 USART3 UART4 UART5

Driver Enable X X X - -

1. X = supported.

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Functional overview STM32F303xB STM32F303xC

3.22 Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I2S)

Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits.

Two standard I2S interfaces (multiplexed with SPI2 and SPI3) supporting four different audio standards can operate as master or slave at half-duplex and full duplex communication modes. They can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data resolution and synchronized by a specific signal. Audio sampling frequency from 8 kHz up to 192 kHz can be set by 8-bit programmable linear prescaler. When operating in master mode it can output a clock for an external audio component at 256 times the sampling frequency.

Refer to Tab le 9 for the features available in SPI1, SPI2 and SPI3.

Hardware CRC calculation X X X

Rx/Tx FIFO X X X

NSS pulse mode X X X

Table 9. STM32F303xB/STM32F303xC SPI/I2S implementation

SPI features

(1)

SPI1 SPI2 SPI3

I2S mode - X X

TI mode XXX

1. X = supported.

3.23 Controller area network (CAN)

The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and 14 scalable filter banks.

3.24 Universal serial bus (USB)

The STM32F303xB/STM32F303xC devices embed an USB device peripheral compatible with the USB full-speed 12 Mbs. The USB interface implements a full-speed (12 Mbit/s) function interface. It has software-configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator). The USB has a dedicated 512-bytes SRAM memory for data transmission and reception.

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STM32F303xB STM32F303xC Functional overview

MSv30365V1

TIMER 16

(for envelop)

TIMER 17

(for carrier)

PB9/PA13

3.25 Infrared Transmitter

The STM32F303xB/STM32F303xC devices provide an infrared transmitter solution. The solution is based on internal connections between TIM16 and TIM17 as shown in the figure below.

TIM17 is used to provide the carrier frequency and TIM16 provides the main signal to be sent. The infrared output signal is available on PB9 or PA13.

To generate the infrared remote control signals, TIM16 channel 1 and TIM17 channel 1 must be properly configured to generate correct waveforms. All standard IR pulse modulation modes can be obtained by programming the two timers output compare channels.

Figure 3. Infrared transmitter

3.26 Touch sensing controller (TSC)

The STM32F303xB/STM32F303xC devices provide a simple solution for adding capacitive sensing functionality to any application. These devices offer up to 24 capacitive sensing channels distributed over 8 analog I/O groups.

Capacitive sensing technology is able to detect the presence of a finger near a sensor which is protected from direct touch by a dielectric (glass, plastic, ...). The capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. It consists of charging the sensor capacitance and then transferring a part of the accumulated charges into a sampling capacitor until the voltage across this capacitor has reached a specific threshold. To limit the CPU bandwidth usage this acquisition is directly managed by the hardware touch sensing controller and only requires few external components to operate.

The touch sensing controller is fully supported by the STMTouch touch sensing firmware library which is free to use and allows touch sensing functionality to be implemented reliably in the end application.

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Functional overview STM32F303xB STM32F303xC

Table 10. Capacitive sensing GPIOs available on STM32F303xB/STM32F303xC

devices

Group

Capacitive sensing

signal name

TSC_G1_IO1 PA0

name

Group

Capacitive sensing

signal name

TSC_G5_IO1 PB3

TSC_G1_IO2 PA1 TSC_G5_IO2 PB4

TSC_G1_IO3 PA2 TSC_G5_IO3 PB6

TSC_G1_IO4 PA3 TSC_G5_IO4 PB7

TSC_G2_IO1 PA4

TSC_G6_IO1 PB11

TSC_G2_IO2 PA5 TSC_G6_IO2 PB12

TSC_G2_IO3 PA6 TSC_G6_IO3 PB13

TSC_G2_IO4 PA7 TSC_G6_IO4 PB14

TSC_G3_IO1 PC5

TSC_G7_IO1 PE2

TSC_G3_IO2 PB0 TSC_G7_IO2 PE3

TSC_G3_IO3 PB1 TSC_G7_IO3 PE4

TSC_G3_IO4 PB2 TSC_G7_IO4 PE5

TSC_G4_IO1 PA9

TSC_G8_IO1 PD12

TSC_G4_IO2 PA10 TSC_G8_IO2 PD13

TSC_G4_IO3 PA13 TSC_G8_IO3 PD14

TSC_G4_IO4 PA14 TSC_G8_IO4 PD15

Table 11. No. of capacitive sensing channels available on

STM32F303xB/STM32F303xC devices

name

Number of capacitive sensing channels

Analog I/O group

STM32F303Vx STM32F303Rx STM32F303Cx

G1 3 3 3

G2 3 3 3

G3 3 3 2

G4 3 3 3

G5 3 3 3

G6 3 3 3

G7 3 0 0

G8 3 0 0

Number of capacitive

sensing channels

24 18 17

30/149 DS9118 Rev 14

STM32F303xB STM32F303xC Functional overview

3.27 Development support

3.27.1 Serial wire JTAG debug port (SWJ-DP)

The Arm SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

3.27.2 Embedded trace macrocell™

The Arm embedded trace macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F303xB/STM32F303xC through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using a high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. TPA hardware is commercially available from common development tool vendors. It operates with third party debugger software tools.

DS9118 Rev 14 31/149

Pinouts and pin description STM32F303xB STM32F303xC

MSv40448V1

47 46 45 44 43 42 41

VSS

BOOT0

PB5

40 39 38 37

21 22 23 24

PB4

PB3

VDD

VSS

PA12

PB15

PB14

PB13

PB12

PB10

VSS

PB11

VDD

2 3

VBAT

PC14/OSC32_IN

PC15/OSC32_OUT

NRST

VSSA/VREF-

VDDA

PA0

PA1

PA2

VDD

PF0/OSC_IN

PF1/OSC_OUT

PC13

14 15 16 17 18 19 20

PA7

PB1

PB2

LQFP48

PA13

PA11

PA10

PA9

PA8

PA3

PA4

PA5

PA6

PB0

PB9

PB8

PB7

PB6

PA15

PA14

4 Pinouts and pin description

Figure 4. STM32F303xB/STM32F303xC LQFP48 pinout

32/149 DS9118 Rev 14

STM32F303xB STM32F303xC Pinouts and pin description

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

48 47 46

45 44 43

42 41

40 39 38

37 36 35

34 33

17 18 19 20 21 22 23 24 29 30 31 3225 26 27 28

2 3

5 6

10 11 12

14 15

VBAT

PC14/OSC32_IN

PC15/OSC32_OUT

NRST

PC0 PC1 PC2 PC3

VSSA/VREF-

VDDA

PA0 PA1 PA2

VDD

PD2

PC12

PC11

PC10

VDD VSS

PC8 PC7 PC6

PB12

PF4

PA3

VDD

PC4

PC5

PB2

PB10

PF1/OSC_OUT

PF0/OSC_IN

PC13

VSS

PB11

VSS

VDD

LQFP64

MS40449V2

PA13 PA12

PA11 PA10 PA9

PA8 PC9

PB15 PB14 PB13

PA4

PA5

PA6

PA7

PB0

PB1

PB9

PB8

BOOT0

PB7

PB6

PB5

PB4

PB3

PA15

PA14

Figure 5. STM32F303xB/STM32F303xC LQFP64 pinout

DS9118 Rev 14 33/149

Pinouts and pin description STM32F303xB STM32F303xC

100999897969594939291908988878685848382818079787776 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

PE2 PE3 PE4 PE5 PE6

VBAT

PC14/OSC32_IN

PC15/OSC32_OUT

PF9

PF10

PF0/OSC_IN

NRST

PC0 PC1 PC2 PC3 PF2

VSSA/VREF-

VREF+

VDDA

PA0 PA1 PA2

VDD VSS PF6 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12

PA3

PF4

VDD

PA4

PA5

PA6

PA7

PC4

PC5

PB0

PB1

PB2

PE7

PE8

PE9

PE10

PE11

PE12

PE13

PE14

PE15

PB10

VSS

VDD

VSS

PE1

PE0

PB9

PB8

BOOT0

PB7

PB6

PB5

PB4

PB3

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

PC12

PC11

PC10

PA15

PA14

26272829303132333435363738394041424344454647484950

MS40450V1

LQFP100

PC13

PF1/OSC_OUT

PB11

Figure 6. STM32F303xB/STM32F303xC LQFP100 pinout

34/149 DS9118 Rev 14

STM32F303xB STM32F303xC Pinouts and pin description

MSv40453V1

PA2

PA3

PA5

PA4

PA7

BOOT0

PE0

VSS

PE3

PE6

PA8

PE12

PE11

VDD

PB2

PB3

PB4

PB7

PB8

PA9

PC5

PC4

PA6

PB0

PB1

PB5

PB6

PB9

PE2

PE8

PC6

PD9

PB15

PB12

PB10

PD2

PD3

PD4

PD7

PC10

PC12

PA13

PC9

PD13

PD10

PB13

PB11

PD0

PD1

PC11

PC7

PD14

PD11

PB14

VSS

PA15

PA14

VDD

PA11

PC8

PD15

PD12

VSS

PF6

PA12

PA10

PC2

VSSA

VREF+

VDD

PE7

PE1

VDD

PE4

VBAT

PF2

PF0

OSCIN

PC0

PC3

VDDA

VSS

VDD

PC14 OSC32IN

PF9

PF10

PC13

PC15

OSC32OUT

NRST

PC1

PA0

PA1

VSS

PF1

OSCOUT

VDD

PE5

Figure 7. STM32F303xB/STM32F303xC WLCSP100 pinout

DS9118 Rev 14 35/149

Pinouts and pin description STM32F303xB STM32F303xC

functions

Table 12. Legend/abbreviations used in the pinout table

Name Abbreviation Definition

Pin name

Pin type

I/O structure

Notes

Alternate functions

Additional

functions

Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name

S Supply pin

I Input only pin

I/O Input / output pin

FT 5 V tolerant I/O

FTf 5 V tolerant I/O, FM+ capable

TTa 3.3 V tolerant I/O directly connected to ADC

TC Standard 3.3V I/O

B Dedicated BOOT0 pin

RST Bidirectional reset pin with embedded weak pull-up resistor

Unless otherwise specified by a note, all I/Os are set as floating inputs during

and after reset

Functions selected through GPIOx_AFR registers

Functions directly selected/enabled through peripheral registers

Table 13. STM32F303xB/STM32F303xC pin definitions

Pin number

Pin name

(function

after

Pin type

LQFP100

WLCSP100

LQFP64

LQFP48

reset)

D6 1 - - PE2 I/O FT

D7 2 - - PE3 I/O FT

C8 3 - - PE4 I/O FT

B9 4 - - PE5 I/O FT

E7 5 - - PE6 I/O FT

D8611 V

S - - Backup power supply

BAT

Pin functions

Alternate functions Additional functions

Notes

I/O structure

TRACECK, TIM3_CH1,

(1)

TSC_G7_IO1, EVENTOUT

TRACED0, TIM3_CH2,

(1)

TSC_G7_IO2, EVENTOUT

TRACED1, TIM3_CH3,

(1)

TSC_G7_IO3, EVENTOUT

TRACED2, TIM3_CH4,

(1)

TSC_G7_IO4, EVENTOUT

(1)

TRACED3, EVENTOUT WKUP3, RTC_TAMP3

36/149 DS9118 Rev 14

STM32F303xB STM32F303xC Pinouts and pin description

Table 13. STM32F303xB/STM32F303xC pin definitions (continued)

Pin number

LQFP100

WLCSP100

Pin name

(function

after

LQFP64

reset)

LQFP48

Pin type

I/O structure

Alternate functions Additional functions

Notes

Pin functions

C9722PC13

C10833

(2)

PC14

OSC32_IN

I/O TC - TIM1_CH1N

I/O TC - - OSC32_IN

(PC14)

(2)

D9944

PC15

OSC32_

OUT

I/O TC - - OSC32_OUT

(PC15)

D10 10 - - PF9 I/O FT

E10 11 - - PF10 I/O FT

PF0-

F10 12 5 5

OSC_IN

I/O FTf - TIM1_CH3N, I2C2_SDA, OSC_IN

(PF0)

PF1-

F9 13 6 6

OSC_OUT

I/O FTf - I2C2_SCL OSC_OUT

(PF1)

E9 14 7 7 NRST I/O

G10 15 8 - PC0 I/O TTa

G9 16 9 - PC1 I/O TTa

G8 17 10 - PC2 I/O TTa

H10 18 11 - PC3 I/O TTa

E8 19 - - PF2 I/O TTa

H8 20 12 8

J8 21 - - VREF+

J10 22 - - VDDA S

--139

VSSA/ VREF-

VDDA/

VREF+

(3)

H9 23 14 10 PA0 I/O TTa

WKUP2, RTC_TAMP1, RTC_TS, RTC_OUT

TIM15_CH1, SPI2_SCK,

(1)

EVENTOUT

TIM15_CH2, SPI2_SCK,

(1)

EVENTOUT

Device reset input / internal reset output (active low)

(1)

EVENTOUT ADC12_IN6, COMP7_INM

(1)

EVENTOUT ADC12_IN7, COMP7_INP

(1)

COMP7_OUT, EVENTOUT ADC12_IN8

(1)

TIM1_BKIN2, EVENTOUT ADC12_IN9

(1)

EVENTOUT ADC12_IN10

- Analog ground/Negative reference voltage

- Positive reference voltage

- Analog power supply

- Analog power supply/Positive reference voltage

USART2_CTS, TIM2_CH1_ETR,TIM8_BKIN,

(4)

TIM8_ETR,TSC_G1_IO1, COMP1_OUT, EVENTOUT

ADC1_IN1, COMP1_INM, RTC_ TAMP2, WKUP1, COMP7_INP

DS9118 Rev 14 37/149

Pinouts and pin description STM32F303xB STM32F303xC

Table 13. STM32F303xB/STM32F303xC pin definitions (continued)

Pin number

LQFP100

WLCSP100

Pin name

(function

after

LQFP64

reset)

LQFP48

Pin type

I/O structure

Alternate functions Additional functions

Notes

Pin functions

J9 24 15 11 PA1 I/O TTa

F7 25 16 12 PA2 I/O TTa

G7 26 17 13 PA3 I/O TTa

- 27 18 - PF4 I/O TTa

K9,

K10

- - - VSS S - - Digital ground

USART2_RTS_DE, TIM2_CH2, TSC_G1_IO2,

(4)

TIM15_CH1N, RTC_REFIN, EVENTOUT

USART2_TX, TIM2_CH3,

(4)

TIM15_CH1, TSC_G1_IO3,

(5)

COMP2_OUT, EVENTOUT

USART2_RX, TIM2_CH4,

(4)

TIM15_CH2, TSC_G1_IO4, EVENTOUT

(1)

COMP1_OUT, EVENTOUT ADC1_IN5

(4)

ADC1_IN2, COMP1_INP, OPAMP1_VINP, OPAMP3_VINP

ADC1_IN3, COMP2_INM, OPAMP1_VOUT

ADC1_IN4, OPAMP1_VINP, COMP2_INP, OPAMP1_VINM

K8 28 19 - VDD S -- Digital power supply

ADC2_IN1, DAC1_OUT1,

J7 29 20 14 PA4 I/O TTa

SPI1_NSS,

(4)

SPI3_NSS,I2S3_WS,

(5)

USART2_CK, TSC_G2_IO1, TIM3_CH2, EVENTOUT

OPAMP4_VINP, COMP1_INM, COMP2_INM, COMP3_INM, COMP4_INM, COMP5_INM, COMP6_INM, COMP7_INM

ADC2_IN2, DAC1_OUT2 OPAMP1_VINP, OPAMP2_VINM, OPAMP3_VINP COMP1_INM, COMP2_INM,

H7 30 21 15 PA5 I/O TTa

(4)

SPI1_SCK, TIM2_CH1_ETR,

(5)

TSC_G2_IO2, EVENTOUT

COMP3_INM, COMP4_INM, COMP5_INM, COMP6_INM, COMP7_INM

SPI1_MISO, TIM3_CH1,

(4)

H6 31 22 16 PA6 I/O TTa

TIM8_BKIN, TIM1_BKIN,

(5)

TIM16_CH1, COMP1_OUT,

ADC2_IN3, OPAMP2_VOUT

TSC_G2_IO3, EVENTOUT

K7 32 23 17 PA7 I/O TTa

G6 33 24 - PC4 I/O TTa

SPI1_MOSI, TIM3_CH2, TIM17_CH1, TIM1_CH1N,

(4)

TIM8_CH1N, TSC_G2_IO4, COMP2_OUT, EVENTOUT

(1)

USART1_TX, EVENTOUT ADC2_IN5

(4)

ADC2_IN4, COMP2_INP, OPAMP2_VINP, OPAMP1_VINP

38/149 DS9118 Rev 14

STM32F303xB STM32F303xC Pinouts and pin description

Table 13. STM32F303xB/STM32F303xC pin definitions (continued)

Pin number

LQFP100

WLCSP100

Pin name

(function

after

LQFP64

reset)

LQFP48

Pin type

I/O structure

Alternate functions Additional functions

Notes

Pin functions

F6 34 25 - PC5 I/O TTa

J6 35 26 18 PB0 I/O TTa -

K6 36 27 19 PB1 I/O TTa

USART1_RX, TSC_G3_IO1,

(1)

EVENTOUT

TIM3_CH3, TIM1_CH2N, TIM8_CH2N,TSC_G3_IO2, EVENTOUT

TIM3_CH4, TIM1_CH3N,

(4)

TIM8_CH3N, COMP4_OUT,

(5)

ADC2_IN11, OPAMP2_VINM, OPAMP1_VINM

ADC3_IN12, COMP4_INP, OPAMP3_VINP, OPAMP2_VINP

ADC3_IN1, OPAMP3_VOUT-

TSC_G3_IO3, EVENTOUT

K5 37 28 20 PB2 I/O TTa - TSC_G3_IO4, EVENTOUT

(1)

F8 38 - - PE7 I/O TTa

E6 39 - - PE8 I/O TTa

- 40 - - PE9 I/O TTa

- 41 - - PE10 I/O TTa

H5 42 - - PE11 I/O TTa

G5 43 - - PE12 I/O TTa

- 44 - - PE13 I/O TTa

- 45 - - PE14 I/O TTa

- 46 - - PE15 I/O TTa

K4 47 29 21 PB10 I/O TTa -

K3 48 30 22 PB11 I/O TTa -

TIM1_ETR, EVENTOUT ADC3_IN13, COMP4_INP

(1)

TIM1_CH1N, EVENTOUT COMP4_INM, ADC34_IN6

(4)

TIM1_CH1, EVENTOUT ADC3_IN2

(1)

TIM1_CH2N, EVENTOUT ADC3_IN14

(1)

TIM1_CH2, EVENTOUT ADC3_IN15

(1)

TIM1_CH3N, EVENTOUT ADC3_IN16

(1)

TIM1_CH3, EVENTOUT ADC3_IN3

(4)

TIM1_CH4, TIM1_BKIN2,

(1)

EVENTOUT

(4)

USART3_RX, TIM1_BKIN,

(1)

EVENTOUT

USART3_TX, TIM2_CH3, TSC_SYNC, EVENTOUT

USART3_RX, TIM2_CH4, TSC_G6_IO1, EVENTOUT

ADC2_IN12, COMP4_INM, OPAMP3_VINM

ADC4_IN1

ADC4_IN2

COMP5_INM, OPAMP4_VINM, OPAMP3_VINM

COMP6_INP, OPAMP4_VINP

K1,

J1, K249 31 23 VSS S - - Digital ground

J5 50 32 24 VDD S - - Digital power supply

SPI2_NSS,I2S2_WS,I2C2_S

(4)

J4 51 33 25 PB12 I/O TTa

MBA, USART3_CK,

(5)

TIM1_BKIN, TSC_G6_IO2,

ADC4_IN3, COMP3_INM, OPAMP4_VOUT

EVENTOUT

DS9118 Rev 14 39/149

Pinouts and pin description STM32F303xB STM32F303xC

Table 13. STM32F303xB/STM32F303xC pin definitions (continued)

Pin number

LQFP100

WLCSP100

Pin name

(function

after

LQFP64

reset)

LQFP48

Pin type

I/O structure

Alternate functions Additional functions

Notes

Pin functions

J3 52 34 26 PB13 I/O TTa

J2 53 35 27 PB14 I/O TTa

H4 54 36 28 PB15 I/O TTa

- 55 - - PD8 I/O TTa

G4 56 - - PD9 I/O TTa

H3 57 - - PD10 I/O TTa

H2 58 - - PD11 I/O TTa

H1 59 - - PD12 I/O TTa

G3 60 - - PD13 I/O TTa

G2 61 - - PD14 I/O TTa

G1 62 - - PD15 I/O TTa

F4 63 37 - PC6 I/O FT

F2 64 38 - PC7 I/O FT

F1 65 39 - PC8 I/O FT

F3 66 40 - PC9 I/O FT

SPI2_SCK,I2S2_CK,USART3

(4)

_CTS, TIM1_CH1N, TSC_G6_IO3, EVENTOUT

ADC3_IN5, COMP5_INP, OPAMP4_VINP, OPAMP3_VINP

SPI2_MISO,I2S2ext_SD, USART3_RTS_DE,

(4)

TIM1_CH2N, TIM15_CH1,

COMP3_INP, ADC4_IN4, OPAMP2_VINP

TSC_G6_IO4, EVENTOUT

SPI2_MOSI, I2S2_SD, TIM1_CH3N, RTC_REFIN,

(4)

TIM15_CH1N, TIM15_CH2,

ADC4_IN5, COMP6_INM

EVENTOUT

(1)

USART3_TX, EVENTOUT ADC4_IN12, OPAMP4_VINM

(1)

USART3_RX, EVENTOUT ADC4_IN13

(1)

USART3_CK, EVENTOUT ADC34_IN7, COMP6_INM

(1)

USART3_CTS, EVENTOUT

USART3_RTS_DE,

(1)

TIM4_CH1, TSC_G8_IO1,

ADC34_IN8, COMP6_INP, OPAMP4_VINP

ADC34_IN9, COMP5_INP

EVENTOUT

TIM4_CH2, TSC_G8_IO2,

(1)

EVENTOUT

TIM4_CH3, TSC_G8_IO3,

(1)

EVENTOUT

SPI2_NSS, TIM4_CH4,

(1)

TSC_G8_IO4, EVENTOUT

I2S2_MCK, COMP6_OUT,

(1)

TIM8_CH1, TIM3_CH1,

ADC34_IN10, COMP5_INM

COMP3_INP, ADC34_IN11, OPAMP2_VINP

COMP3_INM

EVENTOUT

I2S3_MCK, TIM8_CH2,

(1)

TIM3_CH2, COMP5_OUT,

EVENTOUT

TIM8_CH3, TIM3_CH3,

(1)

COMP3_OUT, EVENTOUT

TIM8_CH4,

(1)

TIM8_BKIN2,TIM3_CH4,

I2S_CKIN, EVENTOUT

40/149 DS9118 Rev 14

STM32F303xB STM32F303xC Pinouts and pin description

Table 13. STM32F303xB/STM32F303xC pin definitions (continued)

Pin number

Pin name

(function

after

Pin type

I/O structure

WLCSP100

LQFP64

LQFP100

reset)

LQFP48

F5 67 41 29 PA8 I/O FT -

E5 68 42 30 PA9 I/O FTf -

E1 69 43 31 PA10 I/O FTf -

E2 70 44 32 PA11 I/O FT -

D1 71 45 33 PA12 I/O FT -

E3 72 46 34 PA13 I/O FT -

C1 73 - - PF6 I/O FTf

A1, A2, B174 47 35 VSS S

Alternate functions Additional functions

Notes

I2C2_SMBA,I2S2_MCK, USART1_CK, TIM1_CH1, TIM4_ETR, MCO, COMP3_OUT, EVENTOUT

I2C2_SCL,I2S3_MCK, USART1_TX, TIM1_CH2, TIM2_CH3, TIM15_BKIN, TSC_G4_IO1, COMP5_OUT, EVENTOUT

I2C2_SDA, USART1_RX, TIM1_CH3, TIM2_CH4, TIM8_BKIN, TIM17_BKIN, TSC_G4_IO2, COMP6_OUT, EVENTOUT

USART1_CTS, USB_DM, CAN_RX, TIM1_CH1N, TIM1_CH4, TIM1_BKIN2, TIM4_CH1, COMP1_OUT, EVENTOUT

USART1_RTS_DE, USB_DP, CAN_TX, TIM1_CH2N, TIM1_ETR, TIM4_CH2, TIM16_CH1, COMP2_OUT, EVENTOUT

USART3_CTS, TIM4_CH3, TIM16_CH1N, TSC_G4_IO3, IR_OUT, SWDIO-JTMS, EVENTOUT

I2C2_SCL,

(1)

USART3_RTS_DE, TIM4_CH4, EVENTOUT

- Ground

Pin functions

D2 75 48 36 VDD S

C2 76 49 37 PA14 I/O FTf -

- Digital power supply

I2C1_SDA, USART2_TX, TIM8_CH2,TIM1_BKIN, TSC_G4_IO4, SWCLK-JTCK,

EVENTOUT

DS9118 Rev 14 41/149

Pinouts and pin description STM32F303xB STM32F303xC

Table 13. STM32F303xB/STM32F303xC pin definitions (continued)

Pin number

Pin name

(function

after

Pin type

I/O structure

WLCSP100

LQFP64

LQFP100

reset)

LQFP48

B2 77 50 38 PA15 I/O FTf -

E4 78 51 - PC10 I/O FT

D3 79 52 - PC11 I/O FT

A3 80 53 - PC12 I/O FT

B3 81 - - PD0 I/O FT

C3 82 - - PD1 I/O FT

A4 83 54 - PD2 I/O FT

B4 84 - - PD3 I/O FT

C4 85 - - PD4 I/O FT

- 86 - - PD5 I/O FT

- 87 - - PD6 I/O FT

D4 88 - - PD7 I/O FT

A5 89 55 39 PB3 I/O FT -

Alternate functions Additional functions

Notes

I2C1_SCL, SPI1_NSS, SPI3_NSS, I2S3_WS, JTDI, USART2_RX, TIM1_BKIN, TIM2_CH1_ETR, TIM8_CH1, EVENTOUT

SPI3_SCK, I2S3_CK,

(1)

USART3_TX, UART4_TX, TIM8_CH1N, EVENTOUT

SPI3_MISO, I2S3ext_SD,

(1)

USART3_RX, UART4_RX, TIM8_CH2N, EVENTOUT

SPI3_MOSI, I2S3_SD,

(1)

USART3_CK, UART5_TX, TIM8_CH3N, EVENTOUT

(1)

CAN_RX, EVENTOUT -

CAN_TX, TIM8_CH4,

(1)

TIM8_BKIN2,EVENTOUT

UART5_RX, TIM3_ETR,

(1)

TIM8_BKIN, EVENTOUT

USART2_CTS,

(1)

TIM2_CH1_ETR, EVENTOUT

USART2_RTS_DE,

(1)

TIM2_CH2, EVENTOUT

(1)

USART2_TX, EVENTOUT -

USART2_RX, TIM2_CH4,

(1)

EVENTOUT

USART2_CK, TIM2_CH3,

(1)

EVENTOUT

SPI3_SCK, I2S3_CK, SPI1_SCK, USART2_TX, TIM2_CH2, TIM3_ETR, TIM4_ETR, TIM8_CH1N, TSC_G5_IO1, JTDOTRACESWO, EVENTOUT

Pin functions

42/149 DS9118 Rev 14

STM32F303xB STM32F303xC Pinouts and pin description

Table 13. STM32F303xB/STM32F303xC pin definitions (continued)

Pin number

Pin name

(function

WLCSP100

after

LQFP64

LQFP100

reset)

LQFP48

Pin type

I/O structure

Alternate functions Additional functions

Notes

SPI3_MISO, I2S3ext_SD, SPI1_MISO, USART2_RX,

B5 90 56 40 PB4 I/O FT -

TIM3_CH1, TIM16_CH1, TIM17_BKIN, TIM8_CH2N, TSC_G5_IO2, NJTRST, EVENTOUT

SPI3_MOSI, SPI1_MOSI, I2S3_SD, I2C1_SMBA,

A6 91 57 41 PB5 I/O FT -

USART2_CK, TIM16_BKIN, TIM3_CH2, TIM8_CH3N, TIM17_CH1, EVENTOUT

I2C1_SCL, USART1_TX, TIM16_CH1N, TIM4_CH1,

B6 92 58 42 PB6 I/O FTf -

TIM8_CH1,TSC_G5_IO3, TIM8_ETR, TIM8_BKIN2, EVENTOUT

I2C1_SDA, USART1_RX,

C5 93 59 43 PB7 I/O FTf -

TIM3_CH4, TIM4_CH2, TIM17_CH1N, TIM8_BKIN, TSC_G5_IO4, EVENTOUT

A7 94 60 44 BOOT0 I B - Boot memory selection

I2C1_SCL, CAN_RX, TIM16_CH1, TIM4_CH3,

D5 95 61 45 PB8 I/O FTf -

TIM8_CH2, TIM1_BKIN, TSC_SYNC, COMP1_OUT, EVENTOUT

I2C1_SDA, CAN_TX,

C6 96 62 46 PB9 I/O FTf -

TIM17_CH1, TIM4_CH4, TIM8_CH3, IR_OUT, COMP2_OUT, EVENTOUT

USART1_TX, TIM4_ETR,

B7 97 - - PE0 I/O FT

A8 98 - - PE1 I/O FT

(1)

TIM16_CH1, EVENTOUT

USART1_RX, TIM17_CH1,

(1)

EVENTOUT

C7 99 63 47 VSS S - - Ground

A9,

A10,

100 64 48 VDD S - - Digital power supply

B10,

Pin functions

DS9118 Rev 14 43/149

Pinouts and pin description STM32F303xB STM32F303xC

1. Function availability depends on the chosen device. When using the small packages (48 and 64 pin packages), the GPIO pins which are not present on these packages, must not be configured in analog mode.

2. PC13, PC14 and PC15 are supplied through the power switch. Since the switch sinks only a limited amount of current (3 mA), the use of GPIO PC13 to PC15 in output mode is limited:

- The speed should not exceed 2 MHz with a maximum load of 30 pF

- These GPIOs must not be used as current sources (e.g. to drive an LED).

After the first backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the Backup registers which is not reset by the main reset. For details on how to manage these GPIOs, refer to the Battery backup domain and BKP register description sections in the RM0316 reference manual.

3. The VREF+ functionality is available only on the 100 pin package. On the 64-pin and 48-pin packages, the VREF+ is internally connected to VDDA.

4. Fast ADC channel.

5. These GPIOs offer a reduced touch sensing sensitivity. It is thus recommended to use them as sampling capacitor I/O.

44/149 DS9118 Rev 14

Port

Name

STM32F303xB STM32F303xC Pinouts and pin description

Table 14. Alternate functions for port A

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF14 AF15

DS9118 Rev 14 45/149

TIM2_

PA0 -

RTC_

PA1

REFIN

PA2 -

PA3 -

PA4 - -

PA5 -

PA6 -

PA7 -

PA8 M CO - - -

PA9 - - -

PA1 0 -

PA11 - - - - - - TIM1_CH1N

CH1_ ETR

TIM2_ CH2

TIM2_ CH3

TIM2_ CH4

TIM2_ CH1_ ETR

TIM16_ CH1

TIM17_ CH1

TIM17_ BKIN

TIM3_ CH2

TIM3_ CH1

TIM3_ CH2

TSC_ G1_IO1

TSC_ G1_IO2

TSC_ G1_IO3

TSC_ G1_IO4

TSC_ G2_IO1

TSC_ G2_IO2

TSC_ G2_IO3

TSC_ G2_IO4

TSC_ G4_IO1

TSC_ G4_IO2

-- -

TIM8_ BKIN

TIM8_ CH1N

I2C2_ SMBA

I2C2_ SCL

I2C2_ SDA

SPI1_ NSS

SPI1_ SCK

SPI1_ MISO

SPI1_ MOSI

I2S2_ MCK

I2S3_ MCK

SPI3_NSS, I2S3_WS

TIM1_BKIN -

TIM1_CH1N -

TIM1_CH1

TIM1_CH2

- TIM1_CH3

--------

USART2_ CTS

USART2_ RTS_DE

USART2_TXCOMP2

USART2_ RX

USART2_ CK

USART1_CKCOMP3

USART1_TXCOMP5

USART1_RXCOMP6

USART1_ CTS

COMP1 _OUT

_OUT

--- - --

COMP1 _OUT

COMP2 _OUT

_OUT

COMP1 _OUT

TIM8_ BKIN

TIM15_ CH1N

TIM15_ CH1

TIM15_ CH2

TIM15_ BKIN

CAN_RX

TIM8_ ETR

----

-- - --

TIM4_

ETR

TIM2_ CH3

TIM2_

CH4

TIM4_ CH1

---

TIM8_BKIN - -

TIM1_CH4

TIM1_ BKIN2

USB_ DMEVENT

EVENT OUT

OUT

46/149 DS9118 Rev 14

Port

Name

Table 14. Alternate functions for port A (continued)

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF14 AF15

Pinouts and pin description STM32F303xB STM32F303xC

PA1 2 -

SWDIO

PA1 3

-JTMS

SWCLK

PA1 4

-JTCK

PA1 5 JT DI

TIM16_ CH1

TIM16_ CH1N

TIM2_ CH1_ ETR

TIM8_ CH1

- - - - TIM1_CH2N

TSC_ G4_IO3

TSC_ G4_IO4

I2C1_ SDA

I2C1_ SCL

IR_

OUT

TIM8_ CH2

SPI1_ NSS

TIM1_BKIN

SPI3_NSS, I2S3_WS

USART1_ RTS_DE

USART3_ CTS

USART2_ TX

USART2_ RX

COMP2 _OUT

CAN_TX

--- - --

TIM1_

BKIN

TIM4_ CH2

TIM4_ CH3

TIM1_ETR -

---

----

USB_ DPEVENT

OUT

EVENT OUT

Port

Name

STM32F303xB STM32F303xC Pinouts and pin description

Table 15. Alternate functions for port B

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF12 AF15

DS9118 Rev 14 47/149

PB0 - -

PB1 - -

PB2 - - -

JTDO-

PB3

TRACES WO

PB4 NJTRST

PB5 -

PB6 -

PB7 -

PB8 -

PB9 -

PB10 -

PB11 -

TIM2_ CH2

TIM16_ CH1

TIM16_ BKIN

TIM16_ CH1N

TIM17_ CH1N

TIM16_ CH1

TIM17_ CH1

TIM2_ CH3

TIM2_ CH4

TIM3_ CH3

TIM3_ CH4

TIM4_ ETR

TIM3_ CH1

TIM3_ CH2

TIM4_ CH1

TIM4_ CH2

TIM4_ CH3

TIM4_ CH4

TSC_ G3_IO2

TSC_ G3_IO3

TSC_ G3_IO4

TSC_ G5_IO1

TSC_ G5_IO2

TIM8_ CH3N

TSC_ G5_IO3

TSC_ G5_IO4

TSC_ SYNC

TSC_ G6_IO1

TIM8_ CH2N

TIM8_ CH3N

-- ------

TIM8_ CH1N

TIM8_ CH2N

I2C1_ SMBA

I2C1_SCL TIM8_CH1

I2C1_ SDA

I2C1_SCL - - -

I2C1_ SDA

-- -

- TIM1_CH2N - - - - -

- TIM1_CH3N -

SPI1_ SCK

SPI1_ MISO

SPI1_ MOSI

TIM8_ BKIN

-IR_OUT-

SPI3_SCK, I2S3_CK

SPI3_MISO, I2S3ext_SD

SPI3_MOSI, I2S3_SD

TIM8_ ETR

USART2_ TX

USART2_ RX

USART2_ CK

USART1_ TX

USART1_ RX

USART3_ TX

USART3_ RX

COMP4_

OUT

COMP1_ OUT

COMP2_ OUT

----

---

TIM3_ ETR

TIM17_ BKIN

TIM17_ CH1

TIM8_ BKIN2

TIM3_ CH4

CAN_RX

CAN_TX

TIM8_ CH2

TIM8_ CH3

TIM1_ BKIN

EVENT OUT

PB12 - - -

TSC_ G6_IO2

I2C2_ SMBA

SPI2_NSS, I2S2_WS

TIM1_ BKIN

USART3_ CK

----

EVENT OUT

48/149 DS9118 Rev 14

Port

Name

Table 15. Alternate functions for port B (continued)

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF12 AF15

Pinouts and pin description STM32F303xB STM32F303xC

PB13 - - -

PB14 -

PB15

RTC_ REFIN

TIM15_ CH1

TIM15_ CH2

TIM15_ CH1N

TSC_ G6_IO3

TSC_ G6_IO4

TIM1_ CH3N

SPI2_SCK, I2S2_CK

SPI2_MISO, I2S2ext_SD

SPI2_MOSI, I2S2_SD

TIM1_ CH1N

TIM1_ CH2N

------

USART3_ CTS

USART3_ RTS_DE

----

EVENT OUT

DS9118 Rev 14 49/149

Table 16. Alternate functions for port C

Port &

Name

PC0 EVENTOUT - - - - - -

PC1 EVENTOUT - - - - - -

PC2 EVENTOUT - COMP7_OUT - - - -

PC3 EVENTOUT - - - - TIM1_BKIN2 -

PC4 EVENTOUT - - - - - USART1_TX

PC5 EVENTOUT - TSC_G3_IO1 - - - USART1_RX

PC6 EVENTOUT TIM3_CH1 - TIM8_CH1 - I2S2_MCK COMP6_OUT

PC7 EVENTOUT TIM3_CH2 - TIM8_CH2 - I2S3_MCK COMP5_OUT

PC8 EVENTOUT TIM3_CH3 - TIM8_CH3 - - COMP3_OUT

PC9 EVENTOUT TIM3_CH4 - TIM8_CH4 I2S_CKIN TIM8_BKIN2 -

PC10 EVENTOUT - - TIM8_CH1N UART4_TX SPI3_SCK, I2S3_CK USART3_TX

PC11 EVENTOUT - - TIM8_CH2N UART4_RX SPI3_MISO, I2S3ext_SD USART3_RX

PC12 EVENTOUT - - TIM8_CH3N UART5_TX SPI3_MOSI, I2S3_SD USART3_CK

PC13 - - - TIM1_CH1N - - -

PC14 - - - - - - -

AF1 AF2 AF3 AF4 AF5 AF6 AF7

STM32F303xB STM32F303xC Pinouts and pin description

PC15 - - - - - - -

50/149 DS9118 Rev 14

Pinouts and pin description STM32F303xB STM32F303xC

Table 17. Alternate functions for port D

Port &

Pin Name

PD0 EVENTOUT - - - - - CAN_RX

PD1 EVENTOUT - - TIM8_CH4 - TIM8_BKIN2 CAN_TX

PD2 EVENTOUT TIM3_ETR - TIM8_BKIN UART5_RX - -

PD3 EVENTOUT TIM2_CH1_ETR - - - - USART2_CTS

PD4 EVENTOUT TIM2_CH2 - - - - USART2_RTS_DE

PD5 EVENTOUT - - - - - USART2_TX

PD6 EVENTOUT TIM2_CH4 - - - - USART2_RX

PD7 EVENTOUT TIM2_CH3 - - - - USART2_CK

PD8 EVENTOUT - - - - - USART3_TX

PD9 EVENTOUT - - - - - USART3_RX

PD10 EVENTOUT - - - - - USART3_CK

PD11 EVENTOUT - - - - - USART3_CTS

PD12 EVENTOUT TIM4_CH1 TSC_G8_IO1 - - - USART3_RTS_DE

PD13 EVENTOUT TIM4_CH2 TSC_G8_IO2 - - - -

PD14 EVENTOUT TIM4_CH3 TSC_G8_IO3 - - - -

PD15 EVENTOUT TIM4_CH4 TSC_G8_IO4 - - SPI2_NSS -

AF1 AF2 AF3 AF4 AF5 AF6 AF7

Table 18. Alternate functions for port E

STM32F303xB STM32F303xC Pinouts and pin description

DS9118 Rev 14 51/149

Port &

Pin Name

PE0 - EVENTOUT TIM4_ETR - TIM16_CH1 - USART1_TX

PE1 - EVENTOUT - - TIM17_CH1 - USART1_RX

PE2 TRACECK EVENTOUT TIM3_CH1 TSC_G7_IO1 - - -

PE3 TRACED0 EVENTOUT TIM3_CH2 TSC_G7_IO2 - - -

PE4 TRACED1 EVENTOUT TIM3_CH3 TSC_G7_IO3 - - -

PE5 TRACED2 EVENTOUT TIM3_CH4 TSC_G7_IO4 - - -

PE6 TRACED3 EVENTOUT - - - -

PE7 - EVENTOUT TIM1_ETR - - - -

PE8 - EVENTOUT TIM1_CH1N - - - -

PE9 - EVENTOUT TIM1_CH1 - - - -

PE10 - EVENTOUT TIM1_CH2N - - - -

PE11 - EVENTOUT TIM1_CH2 - - - -

PE12 - EVENTOUT TIM1_CH3N - - - -

PE13 - EVENTOUT TIM1_CH3 - - - -

PE14 - EVENTOUT TIM1_CH4 - - TIM1_BKIN2 -

PE15 - EVENTOUT TIM1_BKIN - - - USART3_RX

AF0 AF1 AF2 AF3 AF4 AF6 AF7

52/149 DS9118 Rev 14

Pinouts and pin description STM32F303xB STM32F303xC

Table 19. Alternate functions for port F

Port &

Pin Name

PF0 - - - I2C2_SDA - TIM1_CH3N -

PF1 - - - I2C2_SCL - - -

PF2 EVENTOUT - - - - - -

PF4 EVENTOUT COMP1_OUT - - - - -

PF6 EVENTOUT TIM4_CH4 - I2C2_SCL - - USART3_RTS_DE

PF9 EVENTOUT - TIM15_CH1 - SPI2_SCK - -

PF10 EVENTOUT - TIM15_CH2 - SPI2_SCK - -

AF1 AF2 AF3 AF4 AF5 AF6 AF7

STM32F303xB STM32F303xC Memory mapping

0xFFFF FFFF

0xE000 0000

0xC000 0000

0xA000 0000

0x8000 0000

0x6000 0000

0x4000 0000

0x2000 0000

0x0000 0000

Cortex-M4

with FPU

Internal

Peripherals

SRAM

CODE

Option bytes

System memory

CCM RAM

Flash memory

Flash, system

memory or SRAM,

depending on BOOT

configuration

AHB2

AHB1

APB2

APB1

0x5000 0000

0x4800 1800

0x4800 0000

0x4002 43FF

0x4002 0000

0x4001 6C00

0x4001 0000

0x4000 A000

0x4000 0000

0x1FFF FFFF

0x1FFF F800

0x1FFF D800

0x1000 2000

0x0804 0000

0x0800 0000

0x0004 0000

0x0000 0000

0x1000 0000

Reserved

MSv30355V2

AHB3

0x5000 07FF

Reserved

5 Memory mapping

Figure 8. STM32F303xB/STM32F303xC memory map

DS9118 Rev 14 53/149

Memory mapping STM32F303xB STM32F303xC

Table 20. STM32F303xB/STM32F303xC memory map, peripheral register boundary

addresses

(1)

Bus Boundary address

0x5000 0400 - 0x5000 07FF 1 K ADC3 - ADC4

AHB3

0x5000 0000 - 0x5000 03FF 1 K ADC1 - ADC2

0x4800 1800 - 0x4FFF FFFF ~132 M Reserved

0x4800 1400 - 0x4800 17FF 1 K GPIOF

0x4800 1000 - 0x4800 13FF 1 K GPIOE

0x4800 0C00 - 0x4800 0FFF 1 K GPIOD

AHB2

0x4800 0800 - 0x4800 0BFF 1 K GPIOC

0x4800 0400 - 0x4800 07FF 1 K GPIOB

0x4800 0000 - 0x4800 03FF 1 K GPIOA

0x4002 4400 - 0x47FF FFFF ~128 M Reserved

0x4002 4000 - 0x4002 43FF 1 K TSC

0x4002 3400 - 0x4002 3FFF 3 K Reserved

0x4002 3000 - 0x4002 33FF 1 K CRC

0x4002 2400 - 0x4002 2FFF 3 K Reserved

0x4002 2000 - 0x4002 23FF 1 K Flash interface

AHB1

0x4002 1400 - 0x4002 1FFF 3 K Reserved

Size

(bytes)

Peripheral

APB2

0x4002 1000 - 0x4002 13FF 1 K RCC

0x4002 0800 - 0x4002 0FFF 2 K Reserved

0x4002 0400 - 0x4002 07FF 1 K DMA2

0x4002 0000 - 0x4002 03FF 1 K DMA1

0x4001 8000 - 0x4001 FFFF 32 K Reserved

0x4001 4C00 - 0x4001 7FFF 13 K Reserved

0x4001 4800 - 0x4001 4BFF 1 K TIM17

0x4001 4400 - 0x4001 47FF 1 K TIM16

0x4001 4000 - 0x4001 43FF 1 K TIM15

0x4001 3C00 - 0x4001 3FFF 1 K Reserved

0x4001 3800 - 0x4001 3BFF 1 K USART1

0x4001 3400 - 0x4001 37FF 1 K TIM8

0x4001 3000 - 0x4001 33FF 1 K SPI1

0x4001 2C00 - 0x4001 2FFF 1 K TIM1

0x4001 0800 - 0x4001 2BFF 9 K Reserved

0x4001 0400 - 0x4001 07FF 1 K EXTI

0x4001 0000 - 0x4001 03FF 1 K SYSCFG + COMP + OPAMP

54/149 DS9118 Rev 14

STM32F303xB STM32F303xC Memory mapping

Table 20. STM32F303xB/STM32F303xC memory map, peripheral register boundary

addresses

Bus Boundary address

(1)

(continued)

Size

(bytes)

Peripheral

0x4000 8000 - 0x4000 FFFF 32 K Reserved

0x4000 7800 - 0x4000 7FFF 2 K Reserved

0x4000 7400 - 0x4000 77FF 1 K DAC (dual)

0x4000 7000 - 0x4000 73FF 1 K PWR

0x4000 6800 - 0x4000 6FFF 2 K Reserved

0x4000 6400 - 0x4000 67FF 1 K bxCAN

0x4000 6000 - 0x4000 63FF 1 K USB SRAM 512 bytes

0x4000 5C00 - 0x4000 5FFF 1 K USB device FS

0x4000 5800 - 0x4000 5BFF 1 K I2C2

0x4000 5400 - 0x4000 57FF 1 K I2C1

0x4000 5000 - 0x4000 53FF 1 K UART5

0x4000 4C00 - 0x4000 4FFF 1 K UART4

0x4000 4800 - 0x4000 4BFF 1 K USART3

0x4000 4400 - 0x4000 47FF 1 K USART2

APB1

0x4000 4000 - 0x4000 43FF 1 K I2S3ext

0x4000 3C00 - 0x4000 3FFF 1 K SPI3/I2S3

0x4000 3800 - 0x4000 3BFF 1 K SPI2/I2S2

0x4000 3400 - 0x4000 37FF 1 K I2S2ext

0x4000 3000 - 0x4000 33FF 1 K IWDG

0x4000 2C00 - 0x4000 2FFF 1 K WWDG

0x4000 2800 - 0x4000 2BFF 1 K RTC

0x4000 1800 - 0x4000 27FF 4 K Reserved

0x4000 1400 - 0x4000 17FF 1 K TIM7

0x4000 1000 - 0x4000 13FF 1 K TIM6

0x4000 0C00 - 0x4000 0FFF 1 K Reserved

0x4000 0800 - 0x4000 0BFF 1 K TIM4

0x4000 0400 - 0x4000 07FF 1 K TIM3

0x4000 0000 - 0x4000 03FF 1 K TIM2

1. The gray color is used for reserved Flash memory addresses.

DS9118 Rev 14 55/149

Electrical characteristics STM32F303xB STM32F303xC

MS19210V1

MCU pin

C = 50 pF

MS19211V1

MCU pin

6 Electrical characteristics

6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

6.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at T the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3

6.1.2 Typical values

σ).

= 25 °C and TA = TAmax (given by

Unless otherwise specified, typical data are based on TA = 25 °C, V are given only as design guidelines and are not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated

6.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 9.

6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 10.

Figure 9. Pin loading conditions Figure 10. Pin input voltage

(mean±2σ).

= V

= 3.3 V. They

DDA

56/149 DS9118 Rev 14

STM32F303xB STM32F303xC Electrical characteristics

MS19875V5

Level shifter

Analog: RCs, PLL,comparators, OPAMP,

....

Power switch

ADC/DAC

Kernel logic

(CPU,

digital

& memories)

I/O logic

Backup circuitry

(LSE, RTC,

Wakeup logic,

Backup registers)

BAT

1.65 – 3.6 V

GP I/Os

OUT

Regulator

4 x V

DDA

REF+

REF-

SSA

4 x 100 nF

+ 1 x 4.7 μF

10 nF

+ 1 μF

6.1.6 Power supply scheme

Figure 11. Power supply scheme

1. Dotted lines represent the internal connections on low pin count packages, joining the dedicated supply pins.

Caution: Each power supply pair (VDD/VSS, V

ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below the appropriate pins on the underside of the PCB to ensure the good functionality of the device.

DS9118 Rev 14 57/149

DDA/VSSA

etc..) must be decoupled with filtering

125

Electrical characteristics STM32F303xB STM32F303xC

MS19213V1

BAT

DDA

DD_VBAT

6.1.7 Current consumption measurement

Figure 12. Current consumption measurement scheme

6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Tab le 21: Voltage characteristics,

Tab l e 22: Current characteristics, and Tab le 23: Thermal characteristics may cause

permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 21. Voltage characteristics

Symbol Ratings Min Max Unit

DD–VSS

DD–VDDA

REF+–VDDA

External main supply voltage (including V and VDD)

Allowed voltage difference for VDD > V

(2)

Allowed voltage difference for V

REF+

DDA, VBAT

-0.4

DDA

> V

DDA

Input voltage on FT and FTf pins V

(3)

Input voltage on TTa pins V

Input voltage on any other pin V

Input voltage on Boot0 pin 0 9

|ΔV

| Variations between different V

DDx

− VSS| Variations between all the different ground pins

SSX

ESD(HBM)

1. All main power (VDD, V permitted range. The following relationship must be respected between V

must power on before or at the same time as VDD in the power up sequence.

DDA

must be greater than or equal to VDD.

DDA

Electrostatic discharge voltage (human body model)

) and ground (VSS, V

DDA

power pins - 50

(4)

) pins must always be connected to the external power supply, in the

SSA

(1)

-0.3 4.0

-0.4

− 0.3 V

− 0.3 4.0

-50

see Section 6.3.12: Electrical

sensitivity characteristics

and VDD:

DDA

+ 4.0

58/149 DS9118 Rev 14

STM32F303xB STM32F303xC Electrical characteristics

2. V

3. V

must be always lower or equal than V

REF+

maximum must always be respected. Refer to Table 22: Current characteristics for the maximum allowed injected

current values.

DDA

REF+

≤ V

. If unused then it must be connected to V

DDA)

DDA

4. Include VREF- pin.

Table 22. Current characteristics

Symbol Ratings Max. Unit

ΣI

VDD

VSS

VDD

VSS

Total current into sum of all V

power lines (source) 160

Total current out of sum of all VSS ground lines (sink) − 160

Maximum current into each V

Maximum current out of each V

power line (source)

ground line (sink)

(1)

100

− 100

Output current sunk by any I/O and control pin 25

IO(PIN)

ΣI

IO(PIN)

INJ(PIN)

ΣI

INJ(PIN)

1. All main power (VDD, V permitted range.

2. This current consumption must be correctly distributed over all I/Os and control pins.The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.

3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.

4. A positive injection is induced by V exceeded. Refer to Table 21: Voltage characteristics for the maximum allowed input voltage values.

5. A positive injection is induced by V exceeded. Refer also to Table 21: Voltage characteristics for the maximum allowed input voltage values. Negative injection disturbs the analog performance of the device. See note

6. When several inputs are submitted to a current injection, the maximum ΣI negative injected currents (instantaneous values).

Output current source by any I/O and control pin − 25

Total output current sunk by sum of all IOs and control pins

Total output current sourced by sum of all IOs and control pins

Injected current on FT, FTf and B pins

Injected current on TC and RST pin

Injected current on TTa pins

(5)

(3)

(4)

Total injected current (sum of all I/O and control pins)

) and ground (VSS and V

DDA

> VDD while a negative injection is induced by VIN< VSS. I

> V

DDA

while a negative injection is induced by VIN< VSS. I

) pins must always be connected to the external power supply, in the

SSA

(2)

below Table 70.

INJ(PIN)

(2)

− 80

-5/+0

± 5

(6)

INJ(PIN)

is the absolute sum of the positive and

± 25

must never be

(PIN) must never be

INJ

Table 23. Thermal characteristics

Symbol Ratings Value Unit

STG

Storage temperature range –65 to +150 °C

Maximum junction temperature 150 °C

DS9118 Rev 14 59/149

125

Electrical characteristics STM32F303xB STM32F303xC

6.3 Operating conditions

6.3.1 General operating conditions

Table 24. General operating conditions

Symbol Parameter Conditions Min Max Unit

HCLK

PCLK1

PCLK2

DDA

BAT

Internal AHB clock frequency - 0 72

Internal APB1 clock frequency - 0 36

Internal APB2 clock frequency - 0 72

Standard operating voltage - 2 3.6 V

Analog operating voltage (OPAMP and DAC not used)

Must have a potential

23.6

equal to or higher than

Analog operating voltage (OPAMP and DAC used)

2.4 3.6

Backup operating voltage - 1.65 3.6 V

DDA

+0.3

I/O input voltage

TC I/O –0.3 V

TTa I/O –0.3 V

FT and FTf I/O

(1)

–0.3 5.5

BOOT0 0 5.5

WLCSP100 - 500

Power dissipation at T

85 °C for suffix 6 or TA =

105 °C for suffix 7

(2)

LQFP100 - 488

LQFP64 - 444

LQFP48 - 364

MHzf

Ambient temperature for 6

dissipation

suffix version

Low-power dissipation

Maximum power

Ambient temperature for 7

dissipation

suffix version

Low-power dissipation

6 suffix version –40 105

J Junction temperature range

7 suffix version –40 125

1. To sustain a voltage higher than VDD+0.3 V, the internal pull-up/pull-down resistors must be disabled.

2. If TA is lower, higher PD values are allowed as long as TJ does not exceed T

characteristics).

3. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed T

Section 7.5: Thermal characteristics).

60/149 DS9118 Rev 14

–40 85

(3)

–40 105

(3)

–40 125

(see Section 7.5: Thermal

Jmax

°C

(see

STM32F303xB STM32F303xC Electrical characteristics

6.3.2 Operating conditions at power-up / power-down

The parameters given in Tab le 25 are derived from tests performed under the ambient temperature condition summarized in Tab le 24.

Symbol Parameter Conditions Min Max Unit

Table 25. Operating conditions at power-up / power-down

VDD

VDDA

VDD rise time rate

fall time rate 20

rise time rate

DDA

fall time rate 20

DDA

6.3.3 Embedded reset and power control block characteristics

The parameters given in Tab le 26 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 24.

POR/PDR

RSTTEMPO

1. The PDR detector monitors VDD and also V

2. The product behavior is guaranteed by design down to the minimum V

3. Guaranteed by design.

Table 26. Embedded reset and power control block characteristics

Symbol Parameter Conditions Min Typ Max Unit

Power on/power down

(1)

reset threshold

(1)

PDRhyst

PDR hysteresis - - 40 - mV

POR reset

(3)

temporization

monitors only VDD.

Falling edge

Rising edge 1.84 1.92 2.0 V

- 1.5 2.5 4.5 ms

(if kept enabled in the option bytes). The POR detector

DDA

POR/PDR

(2)

1.8

value.

∞

µs/V

∞

1.88 1.96 V

DS9118 Rev 14 61/149

125

Electrical characteristics STM32F303xB STM32F303xC

Table 27. Programmable voltage detector characteristics

Symbol Parameter Conditions Min

Rising edge 2.1 2.18 2.26

PVD0

PVD threshold 0

Falling edge 2 2.08 2.16

Rising edge 2.19 2.28 2.37

PVD1

PVD threshold 1

Falling edge 2.09 2.18 2.27

Rising edge 2.28 2.38 2.48

PVD2

PVD threshold 2

Falling edge 2.18 2.28 2.38

Rising edge 2.38 2.48 2.58

PVD3

PVD threshold 3

Falling edge 2.28 2.38 2.48

Rising edge 2.47 2.58 2.69

PVD4

PVD threshold 4

Falling edge 2.37 2.48 2.59

Rising edge 2.57 2.68 2.79

PVD5

PVD threshold 5

Falling edge 2.47 2.58 2.69

Rising edge 2.66 2.78 2.9

PVD6

PVD threshold 6

Falling edge 2.56 2.68 2.8

Rising edge 2.76 2.88 3

PVD7

PVDhyst

IDD(PVD)

1. Guaranteed by characterization results.

2. Guaranteed by design.

PVD threshold 7

Falling edge 2.66 2.78 2.9

(2)

PVD hysteresis - - 100 - mV

PVD current consumption

- - 0.15 0.26 µA

(1)

Typ Max

(1)

Unit

62/149 DS9118 Rev 14

STM32F303xB STM32F303xC Electrical characteristics

6.3.4 Embedded reference voltage

The parameters given in Tab le 28 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 24.

Symbol Parameter Conditions Min Typ Max Unit

Table 28. Embedded internal reference voltage

REFINT

Internal reference voltage

ADC sampling time when

S_vrefint

reading the internal reference voltage

Internal reference voltage

RERINT

spread over the temperature range

Coeff

1. Guaranteed by characterization results.

2. Guaranteed by design.

Temperature coefficient - - -

Table 29. Internal reference voltage calibration values

Calibration value name Description Memory address

Raw data acquired at

REFINT_CAL

temperature of 30 °C

= 3.3 V

DDA

6.3.5 Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 12: Current consumption

measurement scheme.

All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to CoreMark code.

–40 °C < T

< +105 °C 1.2 1.23 1.25 V

< +85 °C 1.2 1.23 1.24

-2.2--µs

VDD = 3 V ±10 mV - -

0x1FFF F7BA - 0x1FFF F7BB

100

(2)

(1)

(2)

ppm/°C

Typical and maximum current consumption

The MCU is placed under the following conditions:

• All I/O pins are in input mode with a static value at VDD or VSS (no load)

• All peripherals are disabled except when explicitly mentioned

• The Flash memory access time is adjusted to the f

to 24 MHz,1 wait state from 24 to 48 MHz and 2 wait states from 48 to 72 MHz)

• Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling)

• When the peripherals are enabled f

• When f

> 8 MHz, the PLL is ON and the PLL input is equal to HSI/2 (4 MHz) or

HCLK

PCLK2

= f

HCLK

HSE (8 MHz) in bypass mode.

DS9118 Rev 14 63/149

frequency (0 wait state from 0

HCLK

and f

PCLK1

= f

HCLK/2

125

Electrical characteristics STM32F303xB STM32F303xC

The parameters given in Tab le 30 to Ta bl e 34 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Tab le 24.

Table 30. Typical and maximum current consumption from VDD supply at V

All peripherals enabled All peripherals disabled

DD =

3.6V

Symbol Parameter Conditions f

External clock (HSE bypass)

Supply current in Run mode, executing from Flash

Internal clock (HSI)

External clock (HSE bypass)

Supply current in Run mode, executing from RAM

Internal clock (HSI)

HCLK

Typ

Max @ T

(1)

Max @ T

Typ

(1)

25 °C 85 °C 105 °C 25 °C 85 °C 105 °C

72 MHz 61.2 65.8 67.6 68.5 27.8 30.3 30.7 31.5

64 MHz 54.7 59.1 60.2 61.1 24.6 27.2 27.6 28.3

48 MHz 41.7 45.1 46.2 47.2 19.2 21.1 21.4 21.8

32 MHz 28.1 31.5 32.5 32.7 12.9 14.6 14.8 15.3

24 MHz 21.4 23.7 24.4 25.2 10.0 11.4 11.4 12.1

8 MHz 7.4 8.4 8.6 9.4 3.6 4.1 4.4 5.0

1 MHz 1.3 1.6 1.8 2.6 0.8 1.0 1.2 2.1

64 MHz 49.7 54.4 55.4 56.3 24.5 27.2 27.4 28.1

48 MHz 37.9 42.2 43.0 43.5 18.9 21.4 21.5 21.6

32 MHz 25.8 29.2 29.2 30.0 12.7 14.2 14.6 15.2

24 MHz 19.7 22.3 22.6 23.2 6.7 7.7 7.9 8.5

8 MHz 6.9 7.8 8.3 8.8 3.5 4.0 4.4 5.0

72 MHz 60.8 66.2

(2)

69.7 70.4

(2)

27.4 31.7

(2)

32.2 32.5

64 MHz 54.3 59.1 62.2 63.3 24.3 28.3 28.7 28.8

48 MHz 41.0 45.6 47.3 47.9 18.3 21.6 21.9 22.1

32 MHz 27.6 32.4 32.4 32.9 12.3 15.0 15.2 15.4

24 MHz 20.8 23.9 24.3 25.0 9.3 11.3 11.4 12.0

8 MHz 6.9 7.8 8.7 9.0 3.1 3.7 4.2 4.9

1 MHz 0.9 1.2 1.5 2.3 0.4 0.6 1.0 1.8

64 MHz 49.2 53.9 55.2 57.4 23.9 27.8 28.2 28.4

48 MHz 37.3 40.8 41.4 44.1 18.2 21.0 21.6 21.9

32 MHz 25.1 27.6 29.1 30.1 12.0 14.0 14.5 15.1

24 MHz 19.0 21.6 22.1 22.9 6.3 7.2 7.7 8.1

8 MHz 6.4 7.3 7.9 8.4 3.0 3.5 4.0 4.7

(2)

Unit

64/149 DS9118 Rev 14

STM32F303xB STM32F303xC Electrical characteristics

Table 30. Typical and maximum current consumption from VDD supply at V

All peripherals enabled All peripherals disabled

Symbol Parameter Conditions f

HCLK

Max @ T

Typ

25 °C 85 °C 105 °C 25 °C 85 °C 105 °C

72 MHz 44.0 48.4 49.4 50.5 6.6 7.5 7.9 8.7

64 MHz 39.2 43.3 44.0 45.2 6.0 6.8 7.2 7.9

48 MHz 29.6 32.7 33.3 34.3 4.5 5.2 5.6 6.3

32 MHz 19.7 23.3 23.3 23.5 3.1 3.5 4.0 4.8

24 MHz 14.9 17.6 17.8 18.3 2.4 2.8 3.3 3.9

8 MHz 4.9 5.7 6.1 6.9 0.8 1.0 1.4 2.2

1 MHz 0.6 0.9 1.2 2.1 0.1 0.3 0.6 1.5

64 MHz 34.2 38.1 39.2 40.3 5.7 6.3 6.8 7.5

Supply current in Sleep mode, executing from Flash or RAM

External clock (HSE bypass)

48 MHz 25.8 28.7 29.6 30.3 4.3 4.8 5.2 5.9 Internal clock (HSI)

32 MHz 17.4 19.4 19.9 20.7 2.9 3.2 3.7 4.5

24 MHz 13.2 15.1 15.6 15.9 1.5 1.8 2.2 2.9

8 MHz 4.5 5.0 5.6 6.2 0.7 0.9 1.2 2.1

1. Guaranteed by characterization results unless otherwise specified.

2. Data based on characterization results and tested in production with code executing from RAM.

(1)

Typ

3.6V (continued)

DD =

Max @ T

(1)

Unit

Table 31. Typical and maximum current consumption from the V

Symbol Parameter

Supply

current in

Conditions

(1)

HSE

bypass

Run/Sleep

DDA

mode,

code

executing

from Flash

or RAM

HSI clock

1. Current consumption from the V PLL is off, I

2. Guaranteed by characterization results.

is independent from the frequency.

DDA

supply is independent of whether the peripherals are on or off. Furthermore when the

DDA

supply

DDA

HCLK

Typ

2.4 V V

DDA =

Max @ T

(2)

Typ

DDA =

Max @ T

3.6 V

(2)

25 °C 85 °C 105 °C 25 °C 85 °C 105 °C

72 MHz 225 276 289 297 245 302 319 329

64 MHz 198 249 261 268 216 270 284 293

48 MHz 149 195 204 211 159 209 222 230

32 MHz 102 145 152 157 110 154 162 169

24 MHz 80 119 124 128 86 126 131 135

8 MHz 2 3 4 6 3 4 5 9

1 MHz 2 3 5 7 3 4 6 9

64 MHz 270 323 337 344 299 354 371 381

48 MHz 220 269 280 286 244 293 309 318

32 MHz 173 218 228 233 193 239 251 257

24 MHz 151 194 200 204 169 211 219 225

8 MHz 73 97 99 103 88 105 110 116

Unit

µA

DS9118 Rev 14 65/149

125

Electrical characteristics STM32F303xB STM32F303xC

Table 32. Typical and maximum VDD consumption in Stop and Standby modes

Symbol Parameter Conditions

Typ @VDD (VDD=V

)Max

DDA

2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V

25 °C

TA =

85 °C

(1)

TA =

105 °C

Unit

Supply

Regulator in run mode, all oscillators OFF

20.05 20.33 20.42 20.50 20.67 20.80 44.2

current in

Regulator in low-power mode, all oscillators OFF

7.63 7.77 7.90 8.07 8.17 8.33 30.6

LSI ON and IWDG ON 0.80 0.96 1.09 1.23 1.37 1.51 - - -

Stop mode

Supply current in Standby

LSI OFF and IWDG OFF 0.60 0.74 0.83 0.93 1.02 1.11 5.0

mode

1. Guaranteed by characterization results unless otherwise specified.

2. Data based on characterization results and tested in production.

Table 33. Typical and maximum V

consumption in Stop and Standby modes

DDA

Typ @ V

Symbol Parameter Conditions

2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V

Supply current in Stop mode

Regulator in run mode, all oscillators OFF

Regulator in low-power mode, all oscillators

1.81 1.95 2.07 2.20 2.35 2.52 3.7 5.5 8.8

OFF

DDA

Supply current in Standby mode

Supply current in Stop mode

LSI ON and IWDG ON 2.22 2.42 2.59 2.78 3.0 3.24 - - -

monitoring ON

DDA

LSI OFF and IWDG

OFF

Regulator in run mode, all oscillators OFF

1.69 1.82 1.94 2.08 2.23 2.40 3.5 5.4 9.2

1.05 1.08 1.10 1.15 1.22 1.29 - - -

Regulator in low-power mode, all oscillators

1.05 1.08 1.10 1.15 1.22 1.29 - - -

OFF

Supply current in Standby mode

1. Guaranteed by characterization results.

LSI ON and IWDG ON 1.44 1.52 1.60 1.71 1.84 1.98 - - -

monitoring OFF

DDA

LSI OFF and IWDG

OFF

0.93 0.95 0.98 1.02 1.08 1.15 - - -

(2)

350 735

(2)

335 720

(2)

7.8 13.3

= V

)Max

DDA

TA =

25 °C

85 °C

(1)

(2)

TA =

105 °C

µA

Unit

µA

The total consumption is the sum of IDD and IDDA.

66/149 DS9118 Rev 14

STM32F303xB STM32F303xC Electrical characteristics

25°C 60°C 85°C 105°C

1.6

1.8

2 V

2.4

2.7

3 V

3.3

3.6

(°C)

(μA)

VBAT

MS31124V1

Table 34. Typical and maximum current consumption from V

Typ @V

Symbol

Para

meter

Conditions

(1)

1.65V 1.8V 2V 2.4V 2.7V 3V 3.3V 3.6V

LSE & RTC ON; "Xtal mode" lower driving

0.48 0.50 0.52 0.58 0.65 0.72 0.80 0.90 1.1 1.5 2.0

capability;

DD_VBAT

Backup domain supply current

LSEDRV[1: 0] = '00'

LSE & RTC ON; "Xtal mode" higher driving

0.83 0.86 0.90 0.98 1.03 1.10 1.20 1.30 1.5 2.2 2.9

capability; LSEDRV[1: 0] = '11'

1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values.

2. Guaranteed by characterization results.

BAT

25°C

supply

Max

BAT

TA =

85°C

= 3.6 V

TA =

105°C

(2)

Unit

µA

Figure 13. Typical V

current consumption (LSE and RTC ON/LSEDRV[1:0] = ’00’)

BAT

1.4

1.2 5 V

0.8 V

0.6

0.4 V

0.2 V

DS9118 Rev 14 67/149

125

Electrical characteristics STM32F303xB STM32F303xC

Typical current consumption

The MCU is placed under the following conditions:

• V

• All I/O pins available on each package are in analog input configuration

• The Flash access time is adjusted to f

• When the peripherals are enabled, f

• PLL is used for frequencies greater than 8 MHz

• AHB prescaler of 2, 4, 8,16 and 64 is used for the frequencies 4 MHz, 2 MHz, 1 MHz,

Table 35. Typical current consumption in Run mode, code with data processing running from

Symbol Parameter Conditions f

(1) (2)

DDA

1. V

DDA

2. When peripherals are enabled, the power consumption of the analog part of peripherals such as ADC, DAC, Comparators, OpAmp etc. is not included. Refer to the tables of characteristics in the subsequent sections.

Supply current in Run mode from V

DDA

monitoring is ON.

= V

DDA

= 3.3 V

frequency (0 wait states from 0 to 24 MHz,

HCLK

1 wait state from 24 to 48 MHz and 2 wait states from 48 MHz to 72 MHz), and Flash prefetch is ON

APB1

= f

AHB/2

, f

APB2

= f

AHB

500 kHz and 125 kHz respectively.

Flash

Typ

supply

Running from HSE crystal clock 8 MHz, code executing from Flash

HCLK

72 MHz 61.3 28.0

64 MHz 54.8 25.4

48 MHz 41.9 19.3

32 MHz 28.5 13.3

24 MHz 21.8 10.4

16 MHz 14.9 7.2

8 MHz 7.7 3.9

4 MHz 4.5 2.5

2 MHz 2.8 1.7

1 MHz 1.9 1.3

500 kHz 1.4 1.1

125 kHz 1.1 0.9

72 MHz 240.3 239.5

64 MHz 210.9 210.3

48 MHz 155.8 155.6

32 MHz 105.7 105.6

24 MHz 82.1 82.0

16 MHz 58.8 58.8

8 MHz 2.4 2.4

4 MHz 2.4 2.4

2 MHz 2.4 2.4

1 MHz 2.4 2.4

500 kHz 2.4 2.4

125 kHz 2.4 2.4

Peripherals

enabled

Peripherals

disabled

Unit

µA

68/149 DS9118 Rev 14

STM32F303xB STM32F303xC Electrical characteristics

Table 36. Typical current consumption in Sleep mode, code running from Flash or RAM

Typ

Symbol Parameter Conditions f

HCLK

Peripherals

enabled

Peripherals

disabled

72 MHz 44.1 7.0

64 MHz 39.7 6.3

48 MHz 30.3 4.9

32 MHz 20.5 3.5

24 MHz 15.4 2.8

Supply current in Sleep mode from

supply

16 MHz 10.6 2.0

8 MHz 5.4 1.1

4 MHz 3.2 1.0

2 MHz 2.1 0.9

1 MHz 1.5 0.8

Running from HSE crystal clock 8 MHz, code executing from Flash or RAM

500 kHz 1.2 0.8

125 kHz 1.0 0.8

72 MHz 239.7 238.5

64 MHz 210.5 209.6

48 MHz 155.0 155.6

32 MHz 105.3 105.2

24 MHz 81.9 81.8

DDA

(1) (2)

Supply current in Sleep mode from V

supply

DDA

16 MHz 58.7 58.6

8 MHz 2.4 2.4

4 MHz 2.4 2.4

2 MHz 2.4 2.4

1 MHz 2.4 2.4

500 kHz 2.4 2.4

125 kHz 2.4 2.4

1. V

2. When peripherals are enabled, the power consumption of the analog part of peripherals such as ADC, DAC, Comparators,

monitoring is ON.

DDA

OpAmp etc. is not included. Refer to the tables of characteristics in the subsequent sections.

Unit

µA

DS9118 Rev 14 69/149

125

Electrical characteristics STM32F303xB STM32F303xC

DDfSW

C××=

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in

For the output pins, any external pull-down or external load must also be considered to estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs.

Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,

as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.

Tab l e 54: I/O static characteristics.

I/O dynamic current consumption

In addition to the internal peripheral current consumption (seeTab le 38: Peripheral current

consumption), the I/Os used by an application also contribute to the current consumption.

When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin:

where

ISW is the current sunk by a switching I/O to charge/discharge the capacitive load

is the MCU supply voltage

is the I/O switching frequency

C is the total capacitance seen by the I/O pin: C = C

INT

+ C

EXT+CS

The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.

70/149 DS9118 Rev 14

STM32F303xB STM32F303xC Electrical characteristics

Table 37. Switching output I/O current consumption

Symbol Parameter Conditions

ext

C = C

INT

ext

C = C

INT

I/O current

consumption

C = C

ext

INT

= 3.3 V

= 0 pF

+ C

EXT

= 3.3 V

= 10 pF

+ C

EXT +CS

= 3.3 V

= 22 pF

+ C

EXT +CS

(1)

+ C

I/O toggling

frequency (fSW)

Typ Unit

2 MHz 0.90

4 MHz 0.93

8 MHz 1.16

18 MHz 1.60

36 MHz 2.51

48 MHz 2.97

2 MHz 0.93

4 MHz 1.06

8 MHz 1.47

18 MHz 2.26

36 MHz 3.39

48 MHz 5.99

2 MHz 1.03

4 MHz 1.30

8 MHz 1.79

18 MHz 3.01

1. CS = 5 pF (estimated value).

VDD = 3.3 V

C = C

INT

C = C

INT

= 33 pF

ext

+ C

= 3.3 V

= 47 pF

ext

+ C

EXT

+ C

36 MHz 5.99

2 MHz 1.10

4 MHz 1.31

8 MHz 2.06

18 MHz 3.47

36 MHz 8.35

2 MHz 1.20

4 MHz 1.54

8 MHz 2.46

18 MHz 4.51

36 MHz 9.98

DS9118 Rev 14 71/149

125

Electrical characteristics STM32F303xB STM32F303xC

On-chip peripheral current consumption

The MCU is placed under the following conditions:

• all I/O pins are in analog input configuration

• all peripherals are disabled unless otherwise mentioned

• the given value is calculated by measuring the current consumption

– with all peripherals clocked off

– with only one peripheral clocked on

• ambient operating temperature at 25°C and V

Table 38. Peripheral current consumption

Typical consumption

Peripheral

BusMatrix

GPIOA 10.0

GPIOB 10.3

GPIOC 2.2

GPIOD 8.8

GPIOE 3.3

GPIOF 3.0

ADC1&2 17.3

ADC3&4 18.8

APB2-Bridge

SYSCFG 7.3

USART1 23.3

APB1-Bridge

(2)

DMA1 7.6

DMA2 6.1

CRC 2.1

TSC 5.5

(3)

TIM1 40.0

SPI1 8.8

TIM8 36.4

TIM15 17.1

TIM16 10.1

TIM17 11.0

(3)

TIM2 49.1

TIM3 38.8

TIM4 38.3

12.6

3.6

6.1

= V

DDA

= 3.3 V.

(1)

Unit

µA/MHz

72/149 DS9118 Rev 14

STM32F303xB STM32F303xC Electrical characteristics

Table 38. Peripheral current consumption (continued)

Typical consumption

Peripheral

TIM6 9.7

TIM7 12.1

WWDG 6.4

SPI2 40.4

SPI3 40.0

USART2 41.9

USART3 40.2

UART4 36.5

UART5 30.8

I2C1 10.5

I2C2 10.4

USB 26.2

CAN 33.4

PWR 5.7

DAC 15.4

(1)

Unit

µA/MHz

1. The power consumption of the analog part (I etc. is not included. Refer to the tables of characteristics in the subsequent sections.

2. BusMatrix is automatically active when at least one master is ON (CPU, DMA1 or DMA2).

3. The APBx bridge is automatically active when at least one peripheral is ON on the same bus.

) of peripherals such as ADC, DAC, Comparators, OpAmp

DDA

DS9118 Rev 14 73/149

125

Electrical characteristics STM32F303xB STM32F303xC

6.3.6 Wakeup time from low-power mode

The wakeup times given in Tab le 39 are measured starting from the wakeup event trigger up to the first instruction executed by the CPU:

• For Stop or Sleep mode: the wakeup event is WFE.

• WKUP1 (PA0) pin is used to wakeup from Standby, Stop and Sleep modes.

All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in

Table 39. Low-power mode wakeup timings

Tab l e 24.

Symbol Parameter Conditions

Regulator in

WUSTOP

WUSTANDBY

WUSLEEP

1. Guaranteed by characterization results.

Wakeup from Stop mode

Wakeup from

(1)

Standby mode

Wakeup from Sleep mode

run mode

Regulator in low-power mode

LSI and IWDG OFF

Typ @ V DD, V

= V

DDA

Max Unit

2.0 V 2.4 V 2.7 V 3 V 3.3 V 3.6 V

4.1 3.9 3.8 3.7 3.6 3.5 4.5

7.9 6.7 6.1 5.7 5.4 5.2 9

µs

69.2 60.3 56.4 53.7 51.7 50 100

CPU

-6-

clock

cycles

74/149 DS9118 Rev 14

STM32F303xB STM32F303xC Electrical characteristics

MS19214V2

HSEH

f(HSE)

90%

10%

HSE

r(HSE)

HSEL

w(HSEH)

w(HSEL)

6.3.7 External clock source characteristics

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in recommended clock input waveform is shown in Figure 14.

Symbol Parameter Conditions Min Typ Max Unit

Table 40. High-speed external user clock characteristics

Section 6.3.14. However, the

HSE_ext

HSEH

HSEL

w(HSEH)

w(HSEL)

r(HSE)

f(HSE)

1. Guaranteed by design.

User external clock source frequency

OSC_IN input pin high level voltage 0.7V

OSC_IN input pin low level voltage V

OSC_IN high or low time

OSC_IN rise or fall time

Figure 14. High-speed external clock source AC timing diagram

(1)

1832MHz

-V

-0.3V

15 - -

--20

DS9118 Rev 14 75/149

125

Electrical characteristics STM32F303xB STM32F303xC

MS19215V2

LSEH

f(LSE)

90%

10%

LSE

r(LSE)

LSEL

w(LSEH)

w(LSEL)

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in recommended clock input waveform is shown in Figure 15

Symbol Parameter Conditions Min Typ Max Unit

Table 41. Low-speed external user clock characteristics

Section 6.3.14. However, the

LSE_ext

LSEH

LSEL

w(LSEH)

w(LSEL)

r(LSE)

f(LSE)

1. Guaranteed by design.

User External clock source frequency

OSC32_IN input pin high level voltage

OSC32_IN input pin low level voltage

OSC32_IN high or low time

OSC32_IN rise or fall time

Figure 15. Low-speed external clock source AC timing diagram

(1)

- 32.768 1000 kHz

0.7V

-V

-0.3V

450 - -

--50

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STM32F303xB STM32F303xC Electrical characteristics

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Symbol Parameter Conditions

Table 42. HSE oscillator characteristics

(1)

Min

Table 42. In the

(2)

Typ Ma x

(2)

Unit

OSC_IN

SU(HSE)

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

2. Guaranteed by design.

3. This consumption level occurs during the first 2/3 of the t

4. t

SU(HSE)

oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

Oscillator frequency - 4 8 32 MHz

Feedback resistor - - 200 kΩ

During startup

=3.3 V, Rm= 30Ω,

CL=10 pF@8 MHz

=3.3 V, Rm= 45Ω,

CL=10 pF@8 MHz

HSE current consumption

=3.3 V, Rm= 30Ω,

CL=5 pF@32 MHz

=3.3 V, Rm= 30Ω,

CL=10 pF@32 MHz

=3.3 V, Rm= 30Ω,

CL=20 pF@32 MHz

Oscillator transconductance Startup 10 - - mA/V

(4)

Startup time VDD is stabilized - 2 - ms

SU(HSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz

(3)

startup time.

--8.5

-0.4-

-0.5-

-0.8-

-1-

-1.5-

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Electrical characteristics STM32F303xB STM32F303xC

MS19876V1

(1)

OSC_IN

OSC_OUT

Bias

controlled

gain

HSE

EXT

8 MHz

resonator

Resonator with integrated capacitors

For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5

pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match

the requirements of the crystal or resonator (see

Figure 16). CL1 and C

are usually the

same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C

and CL2. PCB and MCU pin capacitance must be included (10 pF

can be used as a rough estimate of the combined pin and board capacitance) when sizing C

and CL2.

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator

design guide for ST microcontrollers” available from the ST website www.st.com.

Figure 16. Typical application with an 8 MHz crystal

1. R

value depends on the crystal characteristics.

EXT

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STM32F303xB STM32F303xC Electrical characteristics

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Symbol Parameter Conditions

Table 43. LSE oscillator characteristics (f

= 32.768 kHz)

LSE

(1)

Min

(2)

Table 43. In the

Typ Max

(2)

Unit

LSEDRV[1:0]=00

lower driving capability

LSEDRV[1:0]=10

medium low driving capability

LSE current consumption

LSEDRV[1:0]=01

medium high driving capability

LSEDRV[1:0]=11

higher driving capability

LSEDRV[1:0]=00

lower driving capability

LSEDRV[1:0]=10

Oscillator transconductance

medium low driving capability

LSEDRV[1:0]=01

medium high driving capability

LSEDRV[1:0]=11

higher driving capability

(3)

SU(LSE)

1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST microcontrollers”.

2. Guaranteed by design.

3. t

SU(LSE)

reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer.

Startup time VDD is stabilized - 2 - s

is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is

-0.50.9

--1

--1.3

--1.6

5--

8--

µA/V

15 - -

25 - -

µA

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator

design guide for ST microcontrollers” available from the ST website www.st.com.

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Electrical characteristics STM32F303xB STM32F303xC

MS30253V2

OSC32_IN

OSC32_OUT

Drive

programmable

amplifier

LSE

32.768 kHz resonator

Resonator with integrated capacitors

Figure 17. Typical application with a 32.768 kHz crystal

Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden

to add one.

6.3.8 Internal clock source characteristics

The parameters given in Tab le 44 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 24.

High-speed internal (HSI) RC oscillator

Table 44. HSI oscillator characteristics

(1)

Symbol Parameter Conditions Min Typ Max Unit

HSI

TRIM HSI user trimming step - - - 1

DuCy

ACC

su(HSI)

DDA(HSI)

1. V

DDA

2. Guaranteed by design.

3. Guaranteed by characterization results.

4. Factory calibrated, parts not soldered.

Frequency - - 8 - MHz

-2.8

(2)

(3)

-55

-3.8

-2.3

-2

-1 - 1

(2)

-2

Duty cycle - 45

(HSI)

= -40 to

105°C

= -10 to 85°C -1.9

Accuracy of the HSI oscillator

HSI

TA = 0 to 85°C -1.9

TA = 0 to 70°C -1.3

TA = 0 to 55°C -1

TA = 25°C

HSI oscillator startup time - 1

HSI oscillator power consumption

= 3.3 V, TA = –40 to 105 °C unless otherwise specified.

(4)

- - 80 100

(2)

(3)

(2)

µs

µA

80/149 DS9118 Rev 14

STM32F303xB STM32F303xC Electrical characteristics

MS30985V4

T [ºC]

MAX

MIN

-40 -20 0 20 40 60 80 100 120

-1%

-2%

-3%

-4%

Figure 18. HSI oscillator accuracy characterization results for soldered parts

Low-speed internal (LSI) RC oscillator

Table 45. LSI oscillator characteristics

(1)

Symbol Parameter Min Typ Max Unit

LSI

su(LSI)

DD(LSI)

1. V

DDA

2. Guaranteed by design.

Frequency 30 40 50 kHz

(2)

LSI oscillator startup time - - 85 µs

(2)

LSI oscillator power consumption - 0.75 1.2 µA

= 3.3 V, TA = –40 to 105 °C unless otherwise specified.

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Electrical characteristics STM32F303xB STM32F303xC

6.3.9 PLL characteristics

The parameters given in Tab le 46 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 24.

Symbol Parameter

PLL input clock

PLL_IN

PLL_OUT

LOCK

PLL input clock duty cycle 40

PLL multiplier output clock 16

PLL lock time - - 200

Jitter Cycle-to-cycle jitter - - 300

1. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by f

2. Guaranteed by design.

PLL_OUT

Table 46. PLL characteristics

Min Typ Max

(1)

(2)

Value

Unit

-24

-60

(2)

MHz

-72MHz

(2)

µs

6.3.10 Memory characteristics

Flash memory

The characteristics are given at TA = –40 to 105 °C unless otherwise specified.

Symbol Parameter Conditions Min Typ Max

prog

16-bit programming time TA = –40 to +105 °C 40 53.5 60 µs

Page (2 KB) erase time TA = –40 to +105 °C 20 - 40 ms

Mass erase time TA = –40 to +105 °C 20 - 40 ms

Supply current

Table 48. Flash memory endurance and data retention

ERASE

1. Guaranteed by design.

Symbol Parameter Conditions

RET

END

Endurance

Data retention

Table 47. Flash memory characteristics

Write mode - - 10 mA

Erase mode - - 12 mA

= –40 to +85 °C (6 suffix versions)

= –40 to +105 °C (7 suffix versions)

1 kcycle

10 kcycles

(2)

at TA = 85 °C

(2)

at TA = 105 °C 10

(2)

at TA = 55 °C 20

Value

(1)

Min

10 kcycles

(1)

Unit

Years1 kcycle

1. Guaranteed by characterization results.

2. Cycling performed over the whole temperature range.

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6.3.11 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until

a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

• FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V

through a 100 pF capacitor, until a functional disturbance occurs. This test is

compliant with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed.

The test results are given in Tab le 49. They are based on the EMS levels and classes defined in the application note AN1709.

Table 49. EMS characteristics

and

Symbol Parameter Conditions

= 3.3 V, LQFP100, TA = +25°C,

FESD

EFTB

Voltage limits to be applied on any I/O pin to induce a functional disturbance

Fast transient voltage burst limits to be applied through 100 pF on VDD and V pins to induce a functional disturbance

= 72 MHz

HCLK

conforms to IEC 61000-4-2

= 3.3 V, LQFP100, TA = +25°C,

= 72 MHz

HCLK

conforms to IEC 61000-4-4

Level/

Class

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• Corrupted program counter

• Unexpected reset

• Critical Data corruption (control registers...)

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Electrical characteristics STM32F303xB STM32F303xC

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC

61967-2 standard which specifies the test board and the pin loading.

Table 50. EMI characteristics

Symbol Parameter Conditions

= 3.6 V, TA = 25 °C,

EMI

Peak level

LQFP100 package compliant with IEC 61967-2

6.3.12 Electrical sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114,

Symbol Ratings Conditions Packages Class

Table 51. ESD absolute maximum ratings

ANSI/ESD STM5.3.1 standard.

Monitored

frequency band

Max vs. [f

8/72 MHz

HSE/fHCLK

]

Unit

0.1 to 30 MHz 7

dBµV30 to 130 MHz 20

130 MHz to 1GHz 27

SAE EMI Level 4 -

Maximum

(1)

value

Unit

Electrostatic

ESD(HBM)

discharge voltage (human body model)

Electrostatic

ESD(CDM)

discharge voltage (charge device model)

1. Guaranteed by characterization results.

= +25 °C, conforming

to ANSI/ESDA/JEDEC JS-001

= +25 °C, conforming

to ANSI/ESDA/JEDEC JS-002

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All C2a 500

STM32F303xB STM32F303xC Electrical characteristics

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up performance:

• A supply overvoltage is applied to each power supply pin

• A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Symbol Parameter Conditions Class

Table 52. Electrical sensitivities

LU Static latch-up class T

= +105 °C conforming to JESD78A II level A

6.3.13 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or above V operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of –5 µA/+0 µA range), or other functional failure (for example reset occurrence or oscillator frequency deviation).

The test results are given in Tab le 53.

(for standard, 3 V-capable I/O pins) should be avoided during normal product

DS9118 Rev 14 85/149

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Electrical characteristics STM32F303xB STM32F303xC

Table 53. I/O current injection susceptibility

Symbol Description

Injected current on BOOT0 – 0 NA

Injected current on PC0, PC1, PC2, PC3, PF2, PA0, PA1, PA2, PA3, PF4, PA4, PA5, PA6, PA7, PC4, PC5, PB2 with induced leakage current on other pins from this group less than -50 µA

Injected current on PB0, PB1, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PB12, PB13, PB14, PB15, PD8, PD9, PD10, PD11, PD12, PD13, PD14 with induced leakage current on other pins from this group less than -50 µA

INJ

Injected current on PC0, PC1, PC2, PC3, PF2, PA0, PA1, PA2, PA3, PF4, PA4, PA5, PA6, PA7, PC4, PC5, PB2, PB0, PB1, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PB12, PB13, PB14, PB15, PD8, PD9, PD10, PD11, PD12, PD13, PD14 with induced leakage current on other pins from this group less than 400 µA

Injected current on any other FT and FTf pins – 5 NA

Injected current on any other pins – 5 +5

Functional susceptibility

Negative injection

Positive

injection

– 5 -

-+5

Unit

Note: It is recommended to add a Schottky diode (pin to ground) to analog pins which may

potentially inject negative currents.

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STM32F303xB STM32F303xC Electrical characteristics

6.3.14 I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Tab le 54 are derived from tests performed under the conditions summarized in Table 24. All I/Os are CMOS and TTL compliant.

Table 54. I/O static characteristics

Symbol Parameter Conditions Min Typ

TC and TTa I/O - - 0.3 V

Low level input voltage

FT and FTf I/O - - 0.475 V

BOOT0 - - 0.3 VDD–0.3

All I/Os except BOOT0 - - 0.3 V

(2)

(1)

High level input voltage

TC and TTa I/O 0.445 VDD+0.398

FT and FTf I/O 0.5 V

BOOT0 0.2 V

All I/Os except BOOT0 0.7 V

+0.2

+0.95

TC and TTa I/O - 200

Schmitt trigger

hys

hysteresis

BOOT0 - 300

TC, FT and FTf I/O

TTa I/O in digital mode

≤ V

TTa I/O in digital mode

lkg

Input leakage current

(3)

≤ V

DDA

TTa I/O in analog mode

≤ V

= V

≤ V

≤ 5 V

DDA

(4)

FT and FTf I/O

Weak pull-up

equivalent resistor

(5)

--±0.1

--1

--±0.2

--10

25 40 55 kΩ

(1)

Max Unit

(1)

+0.07

-0.2

(2)

(1)

mVFT and FTf I/O - 100

µA

1. Data based on design simulation.

2. Tested in production.

3. Leakage could be higher than the maximum value. if negative current is injected on adjacent pins. Refer to Table 53: I/O

4. To sustain a voltage higher than V

5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

Weak pull-down

equivalent resistor

I/O pin capacitance - - 5 - pF

current injection susceptibility.

PMOS/NMOS contribution to the series resistance is minimum (~10% order).

(5)

= V

+0.3 V, the internal pull-up/pull-down resistors must be disabled.

25 40 55 kΩ

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125

Electrical characteristics STM32F303xB STM32F303xC

MS30255V2

(V)

IHmin

2.0

ILmax

0.7

(V)

1.3

2.0 3.6

ILmax

= 0.3V

+0.07

0.6

2.7 3.0 3.3

CMOS standard requirements VILmax = 0.3V

IHmin

= 0.445V

+0.398

Area not determined

Tested in production

Based on design simulations

CMOS standard requirements V

min = 0.7V

MS30256V2

(V)

IHmin

2.0

ILmax

0.8

(V)

1.3

2.0 3.6

ILmax

= 0.3V

+0.07

0.7

2.7 3.0 3.3

TTL standard requirements VILmax = 0.8V

IHmin

= 0.445V

+0.398

Area not determined

Based on design simulations

TTL standard requirements VIHmin = 2V

All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in

Figure 19 and Figure 20 for standard I/Os.

Figure 19. TC and TTa I/O input characteristics - CMOS port

Figure 20. TC and TTa I/O input characteristics - TTL port

88/149 DS9118 Rev 14

STM32F303xB STM32F303xC Electrical characteristics

(V)

2.0

0.5

(V)

2.0 3.6

1.0

2.7

Area not determined

MS30257V3

ILmax

= 0.475V

-0.2

IHmin

= 0.5V

+0.2

Based on design simulations

CMOS standard requirements V

min = 0.7V

CMOS standard requirements V

max = 0.3V

MS30258V2

(V)

2.0

(V)

1.0

2.0 3.6

ILmin

= 0.475V

-0.2

0.5

IHmin

= 0.5V

+0.2

Area not determined

2.7

TTL standard requirements VIHmin = 2V

TTL standard requirements

VILmax = 0.8V

0.8

Based on design simulations

Figure 21. Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port

Figure 22. Five volt tolerant (FT and FTf) I/O input characteristics - TTL port

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Electrical characteristics STM32F303xB STM32F303xC

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or source up to +/- 20

mA (with a relaxed V

OL/VOH

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in

• The sum of the currents sourced by all the I/Os on V

consumption of the MCU sourced on V

(see Table 22).

VDD

• The sum of the currents sunk by all the I/Os on V

consumption of the MCU sunk on V

(see Table 22).

VSS

cannot exceed the absolute maximum rating

Section 6.2:

plus the maximum Run

cannot exceed the absolute maximum rating

DD,

plus the maximum Run

Output voltage levels

Unless otherwise specified, the parameters given in Tab le 55 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in

Tab l e 24. All I/Os (FT, TTa and TC unless otherwise specified) are CMOS and TTL

compliant.

Table 55. Output voltage characteristics

Symbol Parameter Conditions Min Max Unit

= +8 mA

< 3.6 V

(2)

= +8 mA

< 3.6 V

= +6 mA

< 2.7 V

< 3.6 V

(2)

-0.4

-1.3

-0.4

(1)

(3)

(1)

(3)

(1)(4)

(3)(4)

(1)(4)

(3)(4)

OLFM+

1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 22 and the sum of (I/O ports and control pins) must not exceed ΣI

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

3. The I

4. Data based on design simulation.

current sourced by the device must always respect the absolute maximum rating specified in Table 22 and the sum

(I/O ports and control pins) must not exceed ΣI

of I

Output low level voltage for an I/O pin CMOS port

Output high level voltage for an I/O pin VDD–0.4 -

2.7 V < V

Output low level voltage for an I/O pin TTL port

Output high level voltage for an I/O pin 2.4 -

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin VDD–1.3 -

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin VDD–0.4 -

Output low level voltage for an FTf I/O pin in

(1)(4)

FM+ mode

IO(PIN)

2.7 V < V

= +20 mA

2.7 V < VDD < 3.6 V

2 V < V

= +20 mA

2.7 V < V

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STM32F303xB STM32F303xC Electrical characteristics

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in Figure 23 and

Tab l e 56, respectively.

Unless otherwise specified, the parameters given are derived from tests performed under ambient temperature and V

Table 56. I/O AC characteristics

supply voltage conditions summarized in Tabl e 24.

(1)

OSPEEDRy [1:0]

value

(1)

FM+

configuration

-t

Symbol Parameter Conditions Min Max Unit

(2)

CL = 50 pF, V

(2)

CL = 50 pF, V

CL = 30 pF, V

(2)

CL = 30 pF, V

CL = 50 pF, V

CL = 30 pF, V

CL = 50 pF, V

(2)

= 50 pF, V

= 50 pF, VDD = 2.7 V to 3.6 V - 30

= 50 pF, V

= 2 V to 3.6 V - 2

= 2 V to 3.6 V

= 2 V to 3.6 V - 10

= 2 V to 3.6 V

= 2.7 V to 3.6 V - 50

= 2 V to 2.7 V - 20

= 2.7 V to 3.6 V - 5

= 2.7 V to 3.6 V - 8

= 2 V to 2.7 V - 12

= 2.7 V to 3.6 V - 5

= 2.7 V to 3.6 V - 8

= 2 V to 2.7 V - 12

CL = 50 pF, VDD = 2 V to 3.6 V

-10

- 125

-25

-2

-12

-34

(3)

(4)

max(IO)out

f(IO)out

r(IO)out

max(IO)out

f(IO)out

r(IO)out

max(IO)out

f(IO)out

r(IO)out

max(IO)out

f(IO)out

r(IO)out

EXTIpw

Maximum frequency

Output high to low level fall time

Output low to high level rise time

Maximum frequency

Output high to low level fall time

Output low to high level rise time

Maximum frequency

Output high to low level fall time

Output low to high level rise time

Maximum frequency

Output high to low level fall time

Output low to high level rise time

Pulse width of external signals detected by the

(3)

(4)

-ns

EXTI controller

1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the RM0316 reference manual for a description of GPIO Port configuration register.

2. The maximum frequency is defined in Figure 23.

3. Guaranteed by design.

4. The I/O speed configuration is bypassed in FM+ I/O mode. Refer to the STM32F303x STM32F313xx reference manual RM0316 for a description of FM+ I/O mode configuration.

MHz

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Electrical characteristics STM32F303xB STM32F303xC

ai14131c

10%

90%

50%

r(IO)out

OUTPUT

EXTERNAL

ON 50pF

Maximum frequency is achieved if (tr + tf) ≤ 2/3)T and if the duty cycle is (45-55%)

10%

50%

90%

when loaded by 50pF

f(IO)out

Figure 23. I/O AC characteristics definition

6.3.15 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, R

Unless otherwise specified, the parameters given in Tab le 57 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in

Tab l e 24.

(see Tab le 54).

Table 57. NRST pin characteristics

Symbol Parameter Conditions Min Typ Max Unit

IL(NRST)

IH(NRST)

NF(NRST)

1. Guaranteed by design.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution

(1)

NRST Input low level voltage - - -

(1)

NRST Input high level voltage -

hys(NRST)

F(NRST)

resistance must be minimum

NRST Schmitt trigger voltage hysteresis - - 200 - mV

Weak pull-up equivalent resistor

(1)

NRST Input filtered pulse - - - 100

(1)

NRST Input not filtered pulse - 500

(~10% order).

(2)

0.445V

0.398

= V

DD (1)

25 40 55 kΩ

(1)

0.3V

(1)

0.07

(1)

--ns

to the series

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STM32F303xB STM32F303xC Electrical characteristics

MS19878V1

External reset circuitry

(1)

NRST

(2)

0.1 μF

Filter

Internal reset

Figure 24. Recommended NRST pin protection

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the V

Table 57. Otherwise the reset will not be taken into account by the device.

max level specified in

IL(NRST)

6.3.16 Timer characteristics

The parameters given in Tab le 58 are guaranteed by design.

Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output).

Table 58. T I M x

(1)(2)

characteristics

Symbol Parameter Conditions Min Max Unit

-1-

res(TIM)

EXT

Res

Timer resolution time

Timer external clock frequency on CH1 to CH4

Timer resolution

TIM

TIMxCLK

x=1.8

TIMxCLK

TIMx (except TIM2) - 16

TIM2 - 32

= 72 MHz 13.9 - ns

= 144 MHz

-0

6.95 - ns

TIMxCLK

= 72 MHz 0 36 MHz

- 1 65536

COUNTER

16-bit counter clock period

TIMxCLK

x=1.8

= 72 MHz 0.0139 910 µs

= 144 MHz

0.0069 455 µs

- - 65536 × 65536

MAX_COUNT

Maximum possible count with 32-bit counter

f x=1.8

1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3, TIM4, TIM8, TIM15, TIM16 and TIM17 timers.

2. Guaranteed by design.

= 72 MHz - 59.65 s

TIMxCLK

= 144 MHz

TIMxCLK

- 29.825 s

TIMxCLK

MHz

bit

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125

Electrical characteristics STM32F303xB STM32F303xC

Table 59. IWDG min/max timeout period at 40 kHz (LSI)

Prescaler divider PR[2:0] bits

Min timeout (ms) RL[11:0]=

0x000

Max timeout (ms) RL[11:0]=

(1)

0xFFF

/4 0 0.1 409.6

/8 1 0.2 819.2

/16 2 0.4 1638.4

/32 3 0.8 3276.8

/64 4 1.6 6553.6

/128 5 3.2 13107.2

/256 7 6.4 26214.4

1. These timings are given for a 40 kHz clock but the microcontroller’s internal RC frequency can vary from 30 to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.

Table 60. WWDG min-max timeout value @72 MHz (PCLK)

(1)

Prescaler WDGTB Min timeout value Max timeout value

1 0 0.05687 3.6409

2 1 0.1137 7.2817

4 2 0.2275 14.564

8 3 0.4551 29.127

1. Guaranteed by design.

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6.3.17 Communications interfaces

I2C interface characteristics

The I2C interface meets the timings requirements of the I2C-bus specification and user manual rev.03 for:

• Standard-mode (Sm) : with a bit rate up to 100 Kbits/s

• Fast-mode (Fm) : with a bit rate up to 400 Kbits/s

• Fast-mode Plus (Fm+) : with a bit rate up to 1Mbits/s

The I2C timings requirements are guaranteed by design when the I2C peripheral is properly configured (refer to Reference manual).

The SDA and SCL I/O requirements are met with the following restrictions: the SDA and SCL I/O pins are “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDDIOx is disabled, but is still present. Only FTf I/O pins support Fm+ low level output current maximum requirement. Refer to

characteristics.

All I2C I/Os embed an analog filter. refer to theTabl e 62: I2C analog filter characteristics.

Table 61. I2C timings specification (see I2C specification, rev.03, June 2007)

Symbol Parameter

Standard mode Fast mode Fast Mode Plus

Min Max Min Max Min Max

Section 6.3.14: I/O port

(1)

Unit

SCL

LOW

HIGH

HD;DAT

VD;DAT

VD;ACK

SU;DAT

HD:STA

SU:STA

SU:STO

BUF

SCL clock frequency 0 100 0 400 0 1000 KHz

Low period of the SCL clock 4.7 - 1.3 - 0.5 - µs

High Period of the SCL clock 4 0.6 0.26 - µs

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

- 1000 - 300 - 120 ns

- 300 - 300 - 120 ns

Data hold time 0 - 0 - 0 - µs

Data valid time - 3.45

Data valid acknowledge time - 3.45

(2)

-0.9

(2)

-0.45

Data setup time 250 - 100 - 50 - ns

Hold time (repeated) START condition

Set-up time for a repeated START condition

4.0 - 0.6 - 0.26 - µs

4.7 - 0.6 - 0.26 µs

Set-up time for STOP condition 4.0 - 0.6 - 0.26 - µs

Bus free time between a STOP and START condition

Capacitive load for each bus line - 400 - 400 - 550 pF

Pulse width of spikes that are suppressed by the analog filter for

4.7 - 1.3 - 0.5 - µs

050

(3)

050

(3)

--ns

Standard and Fast mode

(2)

µs

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Electrical characteristics STM32F303xB STM32F303xC

MS19879V3

I2C bus

DD_I2C

MCU

SDA

SCL

DD_I2C

continued

SDA

SCL

SDA

SCL

70%

30%

70%

30%

70%

30%

70%

30%

70%

30%

70%

30%

SU;DAT

HD;DAT

HIGH

VD;DAT

1 / f

SCL

LOW

9th clock

1st clock cycle

SU;STA

HD;STA

VD;ACK

SU;STO

BUF

9th clock

HD;STA

1. The I2C characteristics are the requirements from I2C bus specification rev03. They are guaranteed by design when I2Cx_TIMING register is correctly programmed (Refer to the RM0316 reference manual).

2. The maximum tHD;DAT could be 3.45 µs, 0.9 µs and 0.45 µs for standard mode, fast mode and fast mode plus, but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time.

3. The minimum width of the spikes filtered by the analog filter is above t

(max).

Table 62. I2C analog filter characteristics

(1)

Symbol Parameter Min Max Unit

1. Guaranteed by design.

Pulse width of spikes that are suppressed by the analog filter

50 260 ns

Figure 25. I2C bus AC waveforms and measurement circuit

1. Rs: Series protection resistors, Rp: Pull-up resistors, VDD_I2C: I2C bus supply.

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SPI/I2S characteristics

Unless otherwise specified, the parameters given in Tab le 63 for SPI or in Ta bl e 64 for I2S are derived from tests performed under ambient temperature, f supply voltage conditions summarized in

Tabl e 24.

Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S).

Table 63. SPI characteristics

Symbol Parameter Conditions Min Typ Max Unit

(1)

frequency and VDD

PCLKx

Master mode, SPI1

2.7<VDD<3.6

Slave mode, SPI1

<3.6

1/t

SCK

c(SCK)

SPI clock frequency

2.7<V

Master mode, SPI1/2/3 2<V

Slave mode, SPI1/2/3

<3.6

2<V

SCK) Duty cycle of SPI clock frequency Slave mode 30 50 70 %

DuCy(

su(NSS)

h(NSS)

w(SCKH)

w(SCKL)

su(MI)

su(SI)

h(MI)

h(SI)

a(SO)

dis(SO)

NSS setup time Slave mode, SPI presc = 2 4*Tpclk - -

NSS hold time Slave mode, SPI presc = 2 2*Tpclk - -

SCK high and low time Master mode Tpclk-2 Tpclk Tpclk+2

Master mode 5.5 - -

Data input setup time

Slave mode 6.5 - -

Master mode 5 - -

Data input hold time

Slave mode 5 - -

Data output access time Slave mode 0 - 4*Tpclk

Data output disable time Slave mode 0 - 24

Slave mode - 12 27

v(SO)

v(MO)

h(SO)

h(MO)

1. Guaranteed by characterization results.

Data output valid time

Data output hold time

Slave mode, SPI1

2.7<V

<3.6V

-1218

Master mode - 1.5 3

Slave mode 11 - -

Master mode 0 - -

MHz

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Electrical characteristics STM32F303xB STM32F303xC

ai14135b

NSS input

SU(NSS)

tc(SCK)

th(NSS)

SCK input

CPHA=1 CPOL=0

CPHA=1 CPOL=1

w(SCKH)

tw(SCKL)

ta(SO)

tv(SO)

th(SO)

tr(SCK) tf(SCK)

tdis(SO)

MISO

OUTPUT

MOSI

INPUT

su(SI)

th(SI)

MSB OUT

MSB IN

BIT6 OUT

LSB OUT

LSB IN

BIT 1 IN

Figure 26. SPI timing diagram - slave mode and CPHA = 0

Figure 27. SPI timing diagram - slave mode and CPHA = 1

1. Measurement points are done at 0.5V

and with external CL = 30 pF.

(1)

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ai14136c

SCK Output

CPHA=0

MOSI

OUTPUT

MISO

INP U T

CPHA=0

LSB OUT

LSB IN

CPOL=0

CPOL=1

B I T1 OUT

NSS input

c(SCK)

w(SCKH)

w(SCKL)

r(SCK)

f(SCK)

h(MI)

High

SCK Output

CPHA=1

CPOL=0

CPOL=1

su(MI)

v(MO)

h(MO)

MSB IN

BIT6 IN

MSB OUT

Figure 28. SPI timing diagram - master mode

(1)

1. Measurement points are done at 0.5V

and with external CL = 30 pF.

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Electrical characteristics STM32F303xB STM32F303xC

Table 64. I2S characteristics

(1)

Symbol Parameter Conditions Min Max Unit

1/t

c(CK)

r(CK)

f(CK)

w(CKH)

Master data: 16 bits,

I2S clock frequency

audio freq=48 kHz

I2S clock rise and fall

time

I2S clock high time Master f

Slave 0 12.288

Capacitive load

CL = 30 pF

= 36 MHz,

PCLK

1.496 1.503

-8

331 -

audio frequency =

w(CKL)

v(WS)

h(WS)

su(WS)

h(WS)

Duty Cycle

su(SD_MR)

su(SD_SR)

h(SD_MR)

h(SD_SR)

v(SD_ST)

h(SD_ST)

v(SD_MT)

h(SD_MT)

I2S clock low time 332 -

48 kHz

WS valid time Master mode 4 -

WS hold time Master mode 4 -

WS setup time Slave mode 4 -

WS hold time Slave mode 0 -

S slave input clock

duty cycle

Slave mode 30 70 %

Data input setup time Master receiver 9 -

Data input setup time Slave receiver 2 -

Master receiver 0 -

Data input hold time

Slave receiver 0 -

Data output valid time

Data output hold time

Data output valid time

Data output hold time

Slave transmitter

(after enable edge)

Slave transmitter

(after enable edge)

Master transmitter

(after enable edge)

Master transmitter

(after enable edge)

-29

12 -

-3

MHz

1. Guaranteed by characterization results.

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ST MICROELECTRONICS STM32F303RBT6 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Table 1. Device summary

1 Introduction

2 Description

Table 2. STM32F303xB/STM32F303xC family device features and peripheral counts

Figure 1. STM32F303xB/STM32F303xC block diagram

3 Functional overview

3.1 Arm® Cortex®-M4 core with FPU with embedded Flash and SRAM

3.2 Memory protection unit (MPU)

3.3 Embedded Flash memory

3.4 Embedded SRAM

3.5 Boot modes

3.6 Cyclic redundancy check (CRC)

3.7 Power management

3.7.1 Power supply schemes

Table 3. External analog supply values for analog peripherals

3.7.2 Power supply supervision

3.7.3 Voltage regulator

3.7.4 Low-power modes

3.8 Interconnect matrix

3.9 Clocks and startup

Figure 2. Clock tree

3.10 General-purpose input/outputs (GPIOs)

3.11 Direct memory access (DMA)

3.12 Interrupts and events

3.12.1 Nested vectored interrupt controller (NVIC)

3.13 Fast analog-to-digital converter (ADC)

3.13.1 Temperature sensor

3.13.4 OPAMP reference voltage (VREFOPAMP)

3.14 Digital-to-analog converter (DAC)

3.15 Operational amplifier (OPAMP)

3.16 Fast comparators (COMP)

3.17 Timers and watchdogs

Table 5. Timer feature comparison

3.17.1 Advanced timers (TIM1, TIM8)

3.17.2 General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16, TIM17)

3.17.3 Basic timers (TIM6, TIM7)

3.17.4 Independent watchdog (IWDG)

3.17.5 Window watchdog (WWDG)

3.17.6 SysTick timer

3.18 Real-time clock (RTC) and backup registers

3.19 Inter-integrated circuit interface (I2C)

Table 6. Comparison of I2C analog and digital filters

3.20 Universal synchronous/asynchronous receiver transmitter (USART)

3.21 Universal asynchronous receiver transmitter (UART)

Table 8. USART features

3.22 Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I2S)

Table 9. STM32F303xB/STM32F303xC SPI/I2S implementation

3.23 Controller area network (CAN)

3.24 Universal serial bus (USB)

3.25 Infrared Transmitter

Figure 3. Infrared transmitter

3.26 Touch sensing controller (TSC)

3.27 Development support

3.27.1 Serial wire JTAG debug port (SWJ-DP)

3.27.2 Embedded trace macrocell™

4 Pinouts and pin description

Figure 4. STM32F303xB/STM32F303xC LQFP48 pinout

Figure 5. STM32F303xB/STM32F303xC LQFP64 pinout

Figure 6. STM32F303xB/STM32F303xC LQFP100 pinout

Figure 7. STM32F303xB/STM32F303xC WLCSP100 pinout

Table 12. Legend/abbreviations used in the pinout table

Table 16. Alternate functions for port C

Table 17. Alternate functions for port D

Table 18. Alternate functions for port E

Table 19. Alternate functions for port F

5 Memory mapping

Figure 8. STM32F303xB/STM32F303xC memory map

6 Electrical characteristics

6.1 Parameter conditions

6.1.1 Minimum and maximum values

6.1.2 Typical values

6.1.3 Typical curves

6.1.4 Loading capacitor

6.1.5 Pin input voltage

Figure 9. Pin loading conditions Figure 10. Pin input voltage

6.1.6 Power supply scheme