ST MICROELECTRONICS STM32F303RBT6 Datasheet

STM32F303xB STM32F303xC

LQFP64 (10 × 10 mm)
LQFP100 (14 × 14 mm)

LQFP48 (7 × 7 mm)

WLCSP100 (0.4 mm pitch)

Arm®-based Cortex®-M4 32b MCU+FPU, up to 256KB Flash+

48KB SRAM, 4 ADCs, 2 DAC ch., 7 comp, 4 PGA, timers, 2.0-3.6 V

Datasheet - production data

Features

• Core: Arm® Cortex®-M4 32-bit CPU with FPU
(72 MHz max), single-cycle multiplication and
HW division,
instruction and MPU (memory protection unit)

• Operating conditions:
–V

DD

• Memories
– 128 to 256 Kbytes of Flash memory
– Up to 40 Kbytes of SRAM, with HW parity

check implemented on the first 16 Kbytes.

– Routine booster: 8 Kbytes of SRAM on

instruction and data bus, with HW parity
check (CCM)

• CRC calculation unit

• Reset and supply management

– Power-on/power-down reset (POR/PDR)
– Programmable voltage detector (PVD)
– Low-power modes: Sleep, Stop and

Standby

–V

BAT

• Clock management
–4

to 32 MHz crystal oscillator

– 32 kHz oscillator for RTC with calibration
– Internal 8 MHz RC with x 16 PLL option
–

Internal 40 kHz oscillator

• Up to 87 fast I/Os
– All mappable on external interrupt vectors
– Several 5 V-tolerant

• Interconnect matrix

• 12-channel DMA controller

•

Four ADCs 0.20 µS (up to 39 channels) with

selectable resolution of 12/10/8/6 bits, 0 to

3.6 V conversion range, single
ended/differential input, separate analog
supply from 2 to 3.6 V

•

Two 12-bit DAC channels with analog supply

from 2.4 to 3.6 V

90 DMIPS (from CCM), DSP

, V

voltage range: 2.0 V to 3.6 V

DDA

supply for RTC and backup registers

•

Seven fast rail-to-rail analog comparators with

analog supply from 2 to 3.6 V

•

Four operational amplifiers that can be used in

PGA mode, all terminals accessible with
analog supply from 2.4 to 3.6 V

•

Up to 24 capacitive sensing channels supporting
touchkey, linear and rotary touch sensor

• Up to

13 timers

s

– One 32-bit timer and two 16-bit timers with

up to 4 IC/OC/PWM or pulse counter and
quadrature (incremental) encoder input

–

Two 16-bit 6-channel advanced-control

timer

s, with up to 6 PWM channels,

deadtime generation and emergency stop

– One 16-bit timer with 2 IC/OCs, 1

OCN/PWM, deadtime generation and
emergency stop

– Two 16-bit timers with IC/OC/OCN/PWM,

deadtime generation and emergency stop

– Two watchdog timers (independent,

window)
– SysTick timer: 24-bit downcounter
–

Two 16-bit basic timers to drive the DAC

• Calendar RTC with Alarm, periodic wakeup
from Stop/Standby

• Communication interfaces
– CAN interface (2.0B Active)
–Two I

2

C Fast mode plus (1 Mbit/s) with
20 mA current sink, SMBus/PMBus,
wakeup from STOP

October 2018 DS9118 Rev 14 1/149

This is information on a product in full production.

www.st.com

STM32F303xB STM32F303xC

– Up to five USART/UARTs (ISO 7816

interface, LIN, IrDA, modem control)

– Up to three SPIs, two with multiplexed

half/full duplex I2S interface, 4 to 16

programmable bit frames
– USB 2.0 full speed interface
–

Infrared transmitter

• Serial wire debug, Cortex
JTAG

®

-M4 with FPU ETM,

• 96-bit unique ID

Table 1. Device summary

Reference Part number

STM32F303xB STM32F303CB, STM32F303RB, STM32F303VB

STM32F303xC STM32F303CC, STM32F303RC, STM32F303VC

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STM32F303xB STM32F303xC Contents

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.1 Arm® Cortex®-M4 core with FPU with embedded Flash and SRAM . . . . 14

3.2 Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.5 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.6 Cyclic redundancy check (CRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.7 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.7.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.7.2 Power supply supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.7.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.7.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.8 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.9 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.10 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.11 Direct memory access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.12 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.12.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 20

3.13 Fast analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.13.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.13.2 Internal voltage reference (V

3.13.3 V

3.13.4 OPAMP reference voltage (VREFOPAMP) . . . . . . . . . . . . . . . . . . . . . . 22

battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

BAT

) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

REFINT

3.14 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.15 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.16 Fast comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.17 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.17.1 Advanced timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

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5

Contents STM32F303xB STM32F303xC

3.17.2 General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16, TIM17) . . . 24

3.17.3 Basic timers (TIM6, TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.17.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.17.5 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.17.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.18 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 25

3.19 Inter-integrated circuit interface (I

2

C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.20 Universal synchronous/asynchronous receiver transmitter (USART) . . . 27

3.21 Universal asynchronous receiver transmitter (UART) . . . . . . . . . . . . . . . 27

3.22 Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I2S) . 28

3.23 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.24 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.25 Infrared Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.26 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.27 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.27.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.27.2 Embedded trace macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 61

6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 61

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6.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

6.3.6 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

6.3.10 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

6.3.16 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

6.3.17 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

6.3.18 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

6.3.19 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

6.3.20 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

6.3.21 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 122

6.3.22 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

6.3.23 V

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

BAT

7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

7.1 LQFP100 – 14 x 14 mm, low-profile quad flat package

information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

7.2 LQFP64 – 10 x 10 mm, low-profile quad flat package

information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

7.3 LQFP48 – 7 x 7 mm, low-profile quad flat package

information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

7.4 WLCSP100 - 0.4 mm pitch wafer level chip scale package information 135

7.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

7.5.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

7.5.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 140

8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

DS9118 Rev 14 5/149

5

List of tables STM32F303xB STM32F303xC

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2. STM32F303xB/STM32F303xC family device features and peripheral counts . . . . . . . . . . 12

Table 3. External analog supply values for analog peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 4. STM32F303xB/STM32F303xC peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . 17

Table 5. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 6. Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 7. STM32F303xB/STM32F303xC I

Table 8. USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 9. STM32F303xB/STM32F303xC SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 10. Capacitive sensing GPIOs available on STM32F303xB/STM32F303xC devices . . . . . . . 30

Table 11. No. of capacitive sensing channels available on STM32F303xB/STM32F303xC devices. 30

Table 12. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 13. STM32F303xB/STM32F303xC pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 14. Alternate functions for port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 15. Alternate functions for port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 16. Alternate functions for port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 17. Alternate functions for port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 18. Alternate functions for port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 19. Alternate functions for port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 20. STM32F303xB/STM32F303xC memory map, peripheral register boundary addresses . . 54

Table 21. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 22. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 23. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 24. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 25. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 26. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 27. Programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 28. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 29. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 30. Typical and maximum current consumption from V
Table 31. Typical and maximum current consumption from the V
Table 32. Typical and maximum V
Table 33. Typical and maximum V

DD

DDA

Table 34. Typical and maximum current consumption from V
Table 35. Typical current consumption in Run mode, code with data processing running from Flash68

Table 36. Typical current consumption in Sleep mode, code running from Flash or RAM. . . . . . . . . 69

Table 37. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 38. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 39. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 40. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 41. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 42. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 43. LSE oscillator characteristics (f

Table 44. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 45. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 46. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 47. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 48. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

2

C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

supply at V

DD

DDA

supply . . . . . . . . . . . . . . . . . . 65

= 3.6V . . . . . . . . . . . 64

DD

consumption in Stop and Standby modes. . . . . . . . . . . . . . . . 66

consumption in Stop and Standby modes. . . . . . . . . . . . . . . 66

supply. . . . . . . . . . . . . . . . . . . . . . 67

BAT

= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

LSE

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Table 49. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 50. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 51. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 52. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 53. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 54. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 55. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 56. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 57. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 58. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 59. IWDG min/max timeout period at 40 kHz (LSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 60. WWDG min-max timeout value @72 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 61. I2C timings specification (see I2C specification, rev.03, June 2007) . . . . . . . . . . . . . . . . . 95

Table 62. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 63. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 64. I

2

S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 65. USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 66. USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 67. USB: Full-speed electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 68. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 69. Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 70. ADC accuracy - limited test conditions, 100-pin packages . . . . . . . . . . . . . . . . . . . . . . . 109

Table 71. ADC accuracy, 100-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table 72. ADC accuracy - limited test conditions, 64-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 73. ADC accuracy, 64-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Table 74. ADC accuracy at 1MSPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Table 75. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Table 76. Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Table 77. Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 78. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Table 79. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Table 80. V

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

BAT

Table 81. LQPF100 – 14 x 14 mm, low-profile quad flat package mechanical data. . . . . . . . . . . . . 126

Table 82. LQFP64 – 10 x 10 mm, low-profile quad flat package mechanical data. . . . . . . . . . . . . . 129

Table 83. LQFP48 – 7 x 7 mm, low-profile quad flat package mechanical data. . . . . . . . . . . . . . . . 132

Table 84. WLCSP100 – 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Table 85. WLCSP100 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . 137

Table 86. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Table 87. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Table 88. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

DS9118 Rev 14 7/149

7

List of figures STM32F303xB STM32F303xC

List of figures

Figure 1. STM32F303xB/STM32F303xC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 3. Infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 4. STM32F303xB/STM32F303xC LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 5. STM32F303xB/STM32F303xC LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 6. STM32F303xB/STM32F303xC LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 7. STM32F303xB/STM32F303xC WLCSP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 8. STM32F303xB/STM32F303xC memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 9. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 10. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 11. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 12. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 13. Typical V

Figure 14. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 15. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 16. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 17. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 18. HSI oscillator accuracy characterization results for soldered parts . . . . . . . . . . . . . . . . . . 81

Figure 19. TC and TTa I/O input characteristics - CMOS port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 20. TC and TTa I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 21. Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port. . . . . . . . . . . . . . . . . 89

Figure 22. Five volt tolerant (FT and FTf) I/O input characteristics - TTL port. . . . . . . . . . . . . . . . . . . 89

Figure 23. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 24. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 25. I

2

C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 26. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Figure 27. SPI timing diagram - slave mode and CPHA = 1
Figure 28. SPI timing diagram - master mode
Figure 29. I
Figure 30. I

2

S slave timing diagram (Philips protocol)

2

S master timing diagram (Philips protocol)

Figure 31. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 32. ADC typical current consumption on VDDA pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 33. ADC typical current consumption on VREF+ pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 34. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 35. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 36. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 37. Maximum VREFINT scaler startup time from power down. . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 38. OPAMP voltage noise versus frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 39. LQFP100 – 14 x 14 mm, low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . 126

Figure 40. LQFP100 – 14 x 14 mm, low-profile quad flat package recommended footprint . . . . . . . 127

Figure 41. LQFP100 – 14 x 14 mm, low-profile quad flat package top view example . . . . . . . . . . . . 128

Figure 42. LQFP64 – 10 x 10 mm, low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . 129

Figure 43. LQFP64 – 10 x 10 mm, low-profile quad flat package recommended footprint . . . . . . . . 130

Figure 44. LQFP64 – 10 x 10 mm, low-profile quad flat package top view example . . . . . . . . . . . . . 131

Figure 45. LQFP48 – 7 x 7 mm, low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . 132

Figure 46. LQFP48 - 7 x 7 mm, low-profile quad flat package recommended footprint. . . . . . . . . . . 133

Figure 47. LQFP48 - 7 x 7 mm, low-profile quad flat package top view example . . . . . . . . . . . . . . . 134

Figure 48. WLCSP100 – 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale

current consumption (LSE and RTC ON/LSEDRV[1:0] = ’00’) . . . . . . . . . . . 67

BAT

(1)

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

8/149 DS9118 Rev 14

STM32F303xB STM32F303xC List of figures

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Figure 49. WLCSP100 – 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale

package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Figure 50. WLCSP100, 0.4 mm pitch wafer level chip scale package

top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

DS9118 Rev 14 9/149

9

Introduction STM32F303xB STM32F303xC

1 Introduction

This datasheet provides the ordering information and mechanical device characteristics of
the STM32F303xB/STM32F303xC microcontrollers.

This STM32F303xB/STM32F303xC datasheet should be read in conjunction with the
STM32F303x, STM32F358xC and STM32F328x4/6/8 reference manual (RM0316). The
reference manual is available from the STMicroelectronics website www.st.com.

For information on the Arm

• Cortex®-M4 with FPU Technical Reference Manual, available from the

http://www.arm.com website.

• STM32F3xxx and STM32F4xxx Cortex

available from our website www.st.com.

®(a)

Cortex®-M4 core with FPU, refer to:

®

-M4 programming manual (PM0214)

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

10/149 DS9118 Rev 14

STM32F303xB STM32F303xC Description

2 Description

The STM32F303xB/STM32F303xC family is based on the high-performance Arm® Cortex®­M4

32-bit RISC core with FPU operating at a frequency of up to 72 MHz, and embedding a
floating point unit (FPU), a memory protection unit (MPU) and an embedded trace macrocell
(ETM). The family incorporates high-speed embedded memories (up to 256
memory, up to 40
peripherals connected to two APB buses.

The devices offer up to four fast 12-bit ADCs (5 Msps), seven comparators, four operational
amplifiers, up to two DAC channels, a low-power RTC, up to five general-purpose 16-bit
timers, one general-purpose 32-bit timer, and two timers dedicated to motor control. They
also feature standard and advanced communication interfaces: up to two I
SPIs (two SPIs are with multiplexed full-duplex I2Ss), three USARTs, up to two UARTs, CAN
and USB. To achieve audio class accuracy, the I2S peripherals can be clocked via an
external PLL.

The STM32F303xB/STM32F303xC family operates in the -40 to +85 °C and -40 to +105 °C
temperature ranges from a 2.0 to 3.6
mode allows the design of low-power applications.

The STM32F303xB/STM32F303xC family offers devices in four packages ranging from
48

pins to 100 pins.

Kbytes of SRAM) and an extensive range of enhanced I/Os and

V power supply. A comprehensive set of power-saving

Kbytes of Flash

2

Cs, up to three

The set of included peripherals changes with the device chosen.

DS9118 Rev 14 11/149

55

Description STM32F303xB STM32F303xC

Table 2. STM32F303xB/STM32F303xC family device features and peripheral counts

Peripheral STM32F303Cx STM32F303Rx STM32F303Vx

Flash (Kbytes) 128 256 128 256 128 256

SRAM (Kbytes) on data bus 32 40 32 40 32 40

CCM (Core Coupled Memory)
RAM (Kbytes)

Advanced
control

8

2 (16-bit)

Timers

General purpose

5 (16-bit)
1 (32-bit)

Basic 2 (16-bit)

PWM channels (all)

(1)

PWM channels (except
complementary)

SPI (I2S)

2

C2

I

Communication
interfaces

USART 3

UART 0 2

(2)

31 33

22 24

3(2)

CAN 1

USB 1

Normal I/Os
(TC, TTa)

20 27

45 in LQFP100

37 in WLCSP100

GPIOs

5-volt tolerant
I/Os (FT, FTf)

17 25

42 in LQFP100

40 in WLCSP100

DMA channels 12

Capacitive sensing channels 17 18 24

12-bit ADCs

Number of channels

15 22

4

39 in LQFP100

32 in WLCSP100

12-bit DAC channels 2

Analog comparator 7

Operational amplifiers 4

CPU frequency 72 MHz

Operating voltage 2.0 to 3.6 V

Operating temperature

Ambient operating temperature: - 40 to 85 °C / - 40 to 105 °C

Packages LQFP48 LQFP64

1. This total number considers also the PWMs generated on the complementary output channels

2. The SPI interfaces can work in an exclusive way in either the SPI mode or the I2S audio mode.

12/149 DS9118 Rev 14

Junction temperature: - 40 to 125 °C

LQFP100

WLCSP100

STM32F303xB STM32F303xC Description

MS18960V4

Touch Sensing

Controller

TIMER 16

2 Channels,1 Comp
Channel, BRK as AF

TIMER 17

TIMER 1 / PWM

TIMER 8 / PWM

4 Channels,
4 Comp channels,
ETR, BRK as AF

SPI1

MOSI, MISO,
SCK,NSS as AF

USART1

RX, TX, CTS, RTS,
SmartCard as AF

WinWATCHDOG

BusMatrix

MPU/FPU

Cortex M4 CPU

F

max

: 72 MHz

NVIC

GP DMA1

7 channels

CCM RAM

8KB

Flash

interface

OBL

FLASH 256 KB

64 bits

JTRST

JTDI
JTCK/SWCLK
JTMS/SWDIO

JTDO
As AF

Power

Voltage reg.

3.3 V to 1.8V

V

DD18

Supply

Supervision

POR /PDR

PVD

POR

Reset
Int.

V

DDIO

= 2 to 3.6 V

V

SS

NRESET
V

DDA

V

SSA

Ind. WDG32K

Standby
interface

PLL

@V

DDIO

@V

DDA

XTAL OSC

4 -32 MHz

Reset &

clock

control

AHBPCLK

APBP1CLK

APBP2CLK

AHB2
APB2

AHB2
APB1

CRC

APB1 F

max

= 36 MHz

APB2 f

max

= 72 MHz

GPIO PORT A

GPIO PORT B

GPIO PORT C

GPIO PORT D

GPIO PORT E

OSC_IN
OSC_OUT

SPI3/I2S

SCL, SDA, SMBA as AF

USART2

SCL, SDA, SMBA as AF

USART3

RC LS

TIMER6

TIMER 4

SPI2/I2S

12bit DAC1IF

@V

DDA

TIMER2

(32-bit/PWM)

PA[15:0]

PB[15:0]

PC[15:0]

MOSI/SD, MISO/ext_SD,
SCK/CK, NSS/WS, MCLK as AF

4 Channels, ETR as AF

USB_DP, USB_DM

DAC1_CH1 as AF

HCLK
FCLK

USARTCLK

RC HS 8MHz

SRAM
40 KB

ETM

Trace/Trig

SWJTAG

TPIU

Ibus

TRADECLK

TRACED[0-3]

as AF

Dbus

System

GP DMA2

5 channels

12-bit ADC1

12-bit ADC2

IF

Temp. sensor

V

REF+

V

REF-

TIMER 15

EXT.IT
WKUP

XX AF

1 Channel, 1 Comp
Channel, BRK as AF

1 Channel, 1 Comp
Channel, BRK as AF

4 Channels,
4 Comp channels,
ETR, BRK as AF

GPIO PORT F

PD[15:0]

PE[15:0]

TIMER7

USB SRAM 512B

PF[7:0]

12-bit ADC3

IF

12-bit ADC4

I2CCLK
ADC SAR
1/2/3/4 CLK

@V

DDIO

@V

DDA

@VSW

XTAL 32kHz

OSC32_IN
OSC32_OUT

V

BAT

= 1.65V to 3.6V

RTC

AWU

Backup

Reg

(64Byte)

Backup

interface

ANTI-TAMP

TIMER 3

UART4

UART5

I2C1

I2C2

bx CAN &

512B SRAM

USB 2.0 FS

DAC1_CH2 as AF

OpAmp1

OpAmp2

OpAmp3

OpAmp4

@V

DDA

INxx / OUTxx

INxx / OUTxx

INxx / OUTxx

INxx / OUTxx

INTERFACE

SYSCFG CTL

GP Comparator 7

p

GP Comparator...

GP Comparator 1

CAN TX, CAN RX

4 Channels, ETR as AF

4 Channels, ETR as AF

MOSI/SD, MISO/ext_SD,
SCK/CK, NSS/WS, MCLK as AF

RX, TX, CTS, RTS, as AF

RX, TX, CTS, RTS, as AF

RX, TX as AF

RX, TX as AF

@V

DDA

Xx Ins, 7 OUTs as AF

XX Groups of

4 channels as AF

AHB2

AHB3

Figure 1. STM32F303xB/STM32F303xC block diagram

1. AF: alternate function on I/O pins.

DS9118 Rev 14 13/149

55

Functional overview STM32F303xB STM32F303xC

3 Functional overview

3.1 Arm® Cortex®-M4 core with FPU with embedded Flash and SRAM

The Arm Cortex-M4 processor with FPU is the latest generation of Arm processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.

The Arm Cortex-M4 32-bit RISC processor with FPU features exceptional code-efficiency,
delivering the high-performance expected from an Arm core in the memory size usually
associated with 8- and 16-bit devices.

The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.

Its single precision FPU speeds up software development by using metalanguage
development tools, while avoiding saturation.

With its embedded Arm core, the STM32F303xB/STM32F303xC family is compatible with
all Arm tools and software.

Figure 1 shows the general block diagram of the STM32F303xB/STM32F303xC family

devices.

3.2 Memory protection unit (MPU)

The memory protection unit (MPU) is used to separate the processing of tasks from the data
protection. The MPU can manage up to 8 protection areas that can all be further divided up
into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes
of addressable memory.

The memory protection unit is especially helpful for applications where some critical or
certified code has to be protected against the misbehavior of other tasks. It is usually
managed by an RTOS (real-time operating system). If a program accesses a memory
location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS
environment, the kernel can dynamically update the MPU area setting, based on the
process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

3.3 Embedded Flash memory

All STM32F303xB/STM32F303xC devices feature up to 256 Kbytes of embedded Flash
memory available for storing programs and data. The Flash memory access time is adjusted
to the CPU clock frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz
and 2 wait states above).

14/149 DS9118 Rev 14

STM32F303xB STM32F303xC Functional overview

3.4 Embedded SRAM

STM32F303xB/STM32F303xC devices feature up to 48 Kbytes of embedded SRAM with
hardware parity check. The memory can be accessed in read/write at CPU clock speed with
0 wait states, allowing the CPU to achieve 90 Dhrystone Mips at 72 MHz (when running
code from the CCM (Core Coupled Memory) RAM).

• 8 Kbytes of CCM RAM mapped on both instruction and data bus, used to execute

critical routines or to access data (parity check on all of CCM RAM).

• 40 Kbytes of SRAM mapped on the data bus (parity check on first 16 Kbytes of SRAM).

3.5 Boot modes

At startup, Boot0 pin and Boot1 option bit are used to select one of three boot options:

• Boot from user Flash

• Boot from system memory

• Boot from embedded SRAM

The boot loader is located in the system memory. It is used to reprogram the Flash memory
by using USART1 (PA9/PA10), USART2 (PD5/PD6) or USB (PA11/PA12) through DFU
(device firmware upgrade).

3.6 Cyclic redundancy check (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.

Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at
linktime and stored at a given memory location.

DS9118 Rev 14 15/149

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Functional overview STM32F303xB STM32F303xC

3.7 Power management

3.7.1 Power supply schemes

• VSS, V

= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. It is

DD

provided externally through V

• V

SSA

, V

= 2.0 to 3.6 V: external analog power supply for ADC, DACs, comparators

DDA

operational amplifiers, reset blocks, RCs and PLL. The minimum voltage to be applied
to V
the V
greater or equal to the V

• V

differs from one analog peripheral to another. Ta ble 3 provides the summary of

DDA

ranges for analog peripherals. The V

DDA

= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and

BAT

voltage level and must be provided first.

DD

backup registers (through power switch) when V

Table 3. External analog supply values for analog peripherals

Analog peripheral Minimum V

ADC / COMP 2.0 V 3.6 V

DAC / OPAMP 2.4 V 3.6V

3.7.2 Power supply supervision

The device has an integrated power-on reset (POR) and power-down reset (PDR) circuits.
They are always active, and ensure proper operation above a threshold of 2 V. The device
remains in reset mode when the monitored supply voltage
V

POR/PDR, without the need for an external reset circuit.

• The POR monitors only the VDD supply voltage. During the startup phase it is required

that V

• The PDR monitors both the V

supply supervisor can be disabled (by programming a dedicated Option bit) to reduce
the power consumption if the application design ensures that V
equal to V

The device features an embedded programmable voltage detector (PVD) that monitors the
V

power supply and compares it to the VPVD threshold. An interrupt can be generated

DD

when V

DD

threshold. The interrupt service routine can then generate a warning message and/or put
the MCU into a safe state. The PVD is enabled by software.

should arrive first and be greater than or equal to VDD.

DDA

.

DD

drops below the V

PVD

pins.

DD

voltage level must be always

DDA

is not present.

DD

supply Maximum V

DDA

is below a specified threshold,

and V

DD

threshold and/or when VDD is higher than the V

supply voltages, however the V

DDA

DDA

DDA

is higher than or

supply

DDA

PVD

power

3.7.3 Voltage regulator

The regulator has three operation modes: main (MR), low-power (LPR), and power-down.

• The MR mode is used in the nominal regulation mode (Run)

• The LPR mode is used in Stop mode.

• The power-down mode is used in Standby mode: the regulator output is in high

impedance, and the kernel circuitry is powered down thus inducing zero consumption.

The voltage regulator is always enabled after reset. It is disabled in Standby mode.

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STM32F303xB STM32F303xC Functional overview

3.7.4 Low-power modes

The STM32F303xB/STM32F303xC supports three low-power modes to achieve the best
compromise between low-power consumption, short startup time and available wakeup
sources:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.

• Stop mode

Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low-power mode.

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output, the USB wakeup, the RTC
alarm, COMPx, I2Cx or U(S)ARTx.

• Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a
rising edge on the WKUP pin or an RTC alarm occurs.

Note: The RTC, the IWDG and the corresponding clock sources are not stopped by entering Stop

or Standby mode.

3.8 Interconnect matrix

Several peripherals have direct connections between them. This allows autonomous
communication between peripherals, saving CPU resources thus power supply
consumption. In addition, these hardware connections allow fast and predictable latency.

Interconnect source

TIMx

COMPx TIMx Timer input: OCREF_CLR input, input capture

ADCx TIMx Timer triggered by analog watchdog

Table 4. STM32F303xB/STM32F303xC peripheral interconnect matrix

Interconnect

destination

TIMx Timers synchronization or chaining

ADCx
DAC1

DMA Memory to memory transfer trigger

Compx Comparator output blanking

Conversion triggers

Interconnect action

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Functional overview STM32F303xB STM32F303xC

Table 4. STM32F303xB/STM32F303xC peripheral interconnect matrix (continued)

Interconnect source

GPIO
RTCCLK
HSE/32
MC0

CSS
CPU (hard fault)
COMPx
PVD
GPIO

GPIO

DAC1 COMPx Comparator inverting input

Interconnect

destination

TIM16

TIM1, TIM8,
TIM15, 16, 17

TIMx External trigger, timer break

ADCx
DAC1

Clock source used as input channel for HSI and
LSI calibration

Timer break

Conversion external trigger

Interconnect action

Note: For more details about the interconnect actions, please refer to the corresponding sections

in the reference manual (RM0316).

3.9 Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-32

MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example with
failure of an indirectly used external oscillator).

Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and
the low speed APB (APB1) domains. The maximum frequency of the AHB and the high
speed APB domains is 72
APB domain is 36

MHz.

MHz, while the maximum allowed frequency of the low speed

18/149 DS9118 Rev 14

STM32F303xB STM32F303xC Functional overview

/32

4-32 MHz
HSE OSC

OSC_IN

OSC_OUT

OSC32_IN

OSC32_OUT

8 MHz

HSI RC

IWDGCLK
to IWDG

PLL

x2,x3,..

x16

PLLMUL

AHB

APB1

prescaler

/1,2,4,8,16

HCLK

PLLCLK

to AHB bus, core,
memory and DMA

LSE

LSI

HSI

HSI

HSE

to RTC

PLLSRC

SW

/8

SYSCLK

RTCCLK

RTCSEL[1:0]

to TIM 2,3,4,6,7

If (APB1 prescaler
=1) x1 else x2

FLITFCLK
to Flash programming interface

to I2Cx (x = 1,2)

to U(S)ARTx (x = 2..5)

LSE

HSI

SYSCLK

/2

PCLK1

SYSCLK

HSI

PCLK1

MS19989V5

to I2Sx (x = 2,3)

USBCLK
to USB interface

to cortex System timer
FHCLK Cortex free
running clock
to APB1 peripherals

AHB
prescaler
/1,2,..512

CSS

/2,/3,...

/16

LSE OSC

32.768kHz

LSI RC
40kHz

USB

prescaler

/1,1.5

APB2

prescaler

/1,2,4,8,16

to TIM 15,16,17

If (APB2 prescaler
=1) x1 else x2

to USART1

LSE

HSI

SYSCLK

PCLK2

PCLK2

to APB2 peripherals

TIM1/8

ADC

Prescaler

/1,2,4

to ADCxy
(xy = 12, 34)

ADC

Prescaler

/1,2,4,6,8,10,12,16,

32,64,128,256

I2SSRC

SYSCLK

Ext. clock

I2S_CKIN

x2

MCO

Main clock
output

/2

PLLCLK

HSI

HSE

MCO

SYSCLK

LSI

Figure 2. Clock tree

DS9118 Rev 14 19/149

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Functional overview STM32F303xB STM32F303xC

3.10 General-purpose input/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current
capable except for analog inputs.

The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.

Fast I/O handling allows I/O toggling up to 36 MHz.

3.11 Direct memory access (DMA)

The flexible general-purpose DMA is able to manage memory-to-memory, peripheral-to­memory and memory-to-peripheral transfers. The DMA controller supports circular buffer
management, avoiding the generation of interrupts when the controller reaches the end of
the buffer.

Each of the 12 DMA channels is connected to dedicated hardware DMA requests, with
software trigger support for each channel. Configuration is done by software and transfer
sizes between source and destination are independent.

The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose timers,
DAC and ADC.

3.12 Interrupts and events

3.12.1 Nested vectored interrupt controller (NVIC)

The STM32F303xB/STM32F303xC devices embed a nested vectored interrupt controller
(NVIC) able to handle up to 66 maskable interrupt channels and 16 priority levels.

The NVIC benefits are the following:

• Closely coupled NVIC gives low latency interrupt processing

• Interrupt entry vector table address passed directly to the core

• Closely coupled NVIC core interface

• Allows early processing of interrupts

• Processing of late arriving higher priority interrupts

• Support for tail chaining

• Processor state automatically saved

• Interrupt entry restored on interrupt exit with no instruction overhead

The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.

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STM32F303xB STM32F303xC Functional overview

3.13 Fast analog-to-digital converter (ADC)

four fast analog-to-digital converters 5 MSPS, with selectable resolution between 12 and 6
bit, are embedded in the STM32F303xB/STM32F303xC family devices. The ADCs have up
to 39 external channels. Some of the external channels are shared between ADC1&2 and
between ADC3&4. Channels can be configured to be either single-ended input or differential
input. The ADCs can perform conversions in single-shot or scan modes. In scan mode,
automatic conversion is performed on a selected group of analog inputs.

The ADCs have also internal channels: Temperature sensor connected to ADC1 channel
16, V
ADCs channel 18, VOPAMP1 connected to ADC1 channel 15, VOPAMP2 connected to
ADC2 channel 17, VREFOPAMP3 connected to ADC3 channel 17 and VREFOPAMP4
connected to ADC4 channel 17.

Additional logic functions embedded in the ADC interface allow:

• Simultaneous sample and hold

• Interleaved sample and hold

• Single-shunt phase current reading techniques.

The ADC can be served by the DMA controller. 3 analog watchdogs per ADC are available.

An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.

connected to ADC1 channel 17, Voltage reference V

BAT/2

connected to the 4

REFINT

The events generated by the general-purpose timers and the advanced-control timers
(TIM1 and TIM8) can be internally connected to the ADC start trigger and injection trigger,
respectively, to allow the application to synchronize A/D conversion and timers.

3.13.1 Temperature sensor

The temperature sensor (TS) generates a voltage V
temperature.

The temperature sensor is internally connected to the ADC1_IN16 input channel which is
used to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.

To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.

3.13.2 Internal voltage reference (V

The internal voltage reference (V
ADC and Comparators. V

REFINT

channel. The precise voltage of V
production test and stored in the system memory area. It is accessible in read-only mode.

REFINT

is internally connected to the ADCx_IN18, x=1...4 input

REFINT

that varies linearly with

SENSE

REFINT

)

) provides a stable (bandgap) voltage output for the

is individually measured for each part by ST during

DS9118 Rev 14 21/149

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Functional overview STM32F303xB STM32F303xC

3.13.3 V

battery voltage monitoring

BAT

This embedded hardware feature allows the application to measure the V
using the internal ADC channel ADC1_IN17. As the V
and thus outside the ADC input range, the V
divider by 2. As a consequence, the converted digital value is half the V

pin is internally connected to a bridge

BAT

3.13.4 OPAMP reference voltage (VREFOPAMP)

Every OPAMP reference voltage can be measured using a corresponding ADC internal
channel: VREFOPAMP1 connected to ADC1 channel 15, VREFOPAMP2 connected to
ADC2 channel 17, VREFOPAMP3 connected to ADC3 channel 17, VREFOPAMP4
connected to ADC4 channel 17.

3.14 Digital-to-analog converter (DAC)

Two 12-bit buffered DAC channels can be used to convert digital signals into analog voltage
signal outputs. The chosen design structure is composed of integrated resistor strings and
an amplifier in inverting configuration.

This digital interface supports the following features:

• Two DAC output channels

• 8-bit or 10-bit monotonic output

• Left or right data alignment in 12-bit mode

• Synchronized update capability

• Noise-wave generation

• Triangular-wave generation

• Dual DAC channel independent or simultaneous conversions

• DMA capability (for each channel)

• External triggers for conversion

battery voltage

voltage may be higher than V

BAT

BAT

BAT

voltage.

DDA

,

3.15 Operational amplifier (OPAMP)

The STM32F303xB/STM32F303xC embeds four operational amplifiers with external or
internal follower routing and PGA capability (or even amplifier and filter capability with
external components). When an operational amplifier is selected, an external ADC channel
is used to enable output measurement.

The operational amplifier features:

• 8.2 MHz bandwidth

• 0.5 mA output capability

• Rail-to-rail input/output

• In PGA mode, the gain can be programmed to be 2, 4, 8 or 16.

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3.16 Fast comparators (COMP)

The STM32F303xB/STM32F303xC devices embed seven fast rail-to-rail comparators with
programmable reference voltage (internal or external), hysteresis and speed (low speed for
low-power) and with selectable output polarity.

The reference voltage can be one of the following:

• External I/O

• DAC output pin

• Internal reference voltage or submultiple (1/4, 1/2, 3/4). Refer to Table 28: Embedded

internal reference voltage on page 63 for the value and precision of the internal

reference voltage.

All comparators can wake up from STOP mode, generate interrupts and breaks for the
timers and can be also combined per pair into a window comparator

3.17 Timers and watchdogs

The STM32F303xB/STM32F303xC includes two advanced control timers, up to six general­purpose timers, two basic timers, two watchdog timers and a SysTick timer. The table below
compares the features of the advanced control, general purpose and basic timers.

Table 5. Timer feature comparison

Timer type Timer

Advanced

General-

purpose

General-

purpose

General-

purpose

General-

purpose

Basic

TIM1,

TIM8

TIM2 32-bit

TIM3, TIM4 16-bit

TIM15 16-bit Up

TIM16, TIM17 16-bit Up

TIM6,

TIM7

Counter

resolution

16-bit

16-bit Up

Counter

type

Up, Down,

Up/Down

Up, Down,

Up/Down

Up, Down,

Up/Down

Prescaler

factor

Any integer

between 1
and 65536

Any integer

between 1
and 65536

Any integer

between 1
and 65536

Any integer

between 1
and 65536

Any integer

between 1
and 65536

Any integer

between 1
and 65536

DMA

request

generation

Yes 4 Yes

Yes 4 No

Yes 4 No

Yes 2 1

Yes 1 1

Yes 0 No

Capture/

compare

Channels

Complementary

outputs

Note: TIM1/8 can have PLL as clock source, and therefore can be clocked at 144 MHz.

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Functional overview STM32F303xB STM32F303xC

3.17.1 Advanced timers (TIM1, TIM8)

The advanced-control timers (TIM1 and TIM8) can each be seen as a three-phase PWM
multiplexed on six channels. They have complementary PWM outputs with programmable
inserted dead-times. They can also be seen as complete general-purpose timers. The four
independent channels can be used for:

• Input capture

• Output compare

• PWM generation (edge or center-aligned modes) with full modulation capability (0-

100%)

• One-pulse mode output

In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled to turn off any power switches driven by these outputs.

Many features are shared with those of the general-purpose TIM timers (described in

Section 3.17.2 using the same architecture, so the advanced-control timers can work

together with the TIM timers via the Timer Link feature for synchronization or event chaining.

3.17.2 General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16, TIM17)

There are up to six synchronizable general-purpose timers embedded in the
STM32F303xB/STM32F303xC (see
can be used to generate PWM outputs, or act as a simple time base.

• TIM2, 3, and TIM4

These are full-featured general-purpose timers:

– TIM2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler

– TIM3 and 4 have 16-bit auto-reload up/downcounters and 16-bit prescalers.

These timers all feature 4 independent channels for input capture/output compare,
PWM or one-pulse mode output. They can work together, or with the other general­purpose timers via the Timer Link feature for synchronization or event chaining.

The counters can be frozen in debug mode.

All have independent DMA request generation and support quadrature encoders.

• TIM15, 16 and 17

These three timers general-purpose timers with mid-range features:

They have 16-bit auto-reload upcounters and 16-bit prescalers.

– TIM15 has 2 channels and 1 complementary channel

– TIM16 and TIM17 have 1 channel and 1 complementary channel

All channels can be used for input capture/output compare, PWM or one-pulse mode
output.

The timers can work together via the Timer Link feature for synchronization or event
chaining. The timers have independent DMA request generation.

The counters can be frozen in debug mode.

Tab l e 5 for differences). Each general-purpose timer

3.17.3 Basic timers (TIM6, TIM7)

These timers are mainly used for DAC trigger generation. They can also be used as a
generic 16-bit time base.

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3.17.4 Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 40 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free running timer for application timeout
management. It is hardware or software configurable through the option bytes. The counter
can be frozen in debug mode.

3.17.5 Window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.

3.17.6 SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:

• A 24-bit down counter

• Autoreload capability

• Maskable system interrupt generation when the counter reaches 0.

• Programmable clock source

3.18 Real-time clock (RTC) and backup registers

The RTC and the 16 backup registers are supplied through a switch that takes power from
either the V
registers used to store 64 bytes of user application data when V

They are not reset by a system or power reset, or when the device wakes up from Standby
mode.

The RTC is an independent BCD timer/counter.It supports the following features:

• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.

• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.

• Automatic correction for 28, 29 (leap year), 30 and 31 days of the month.

• Two programmable alarms with wake up from Stop and Standby mode capability.

• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to

synchronize it with a master clock.

• Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal
inaccuracy.

• Three anti-tamper detection pins with programmable filter. The MCU can be woken up
from Stopand Standby modes on tamper event detection.

• Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be
woken up from Stop and Standby modes on timestamp event detection.

supply when present or the V

DD

pin. The backup registers are sixteen 32-bit

BAT

power is not present.

DD

DS9118 Rev 14 25/149

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Functional overview STM32F303xB STM32F303xC

• 17-bit Auto-reload counter for periodic interrupt with wakeup from STOP/STANDBY
capability.

The RTC clock sources can be:

• A 32.768 kHz external crystal

• A resonator or oscillator

• The internal low-power RC oscillator (typical frequency of 40 kHz)

• The high-speed external clock divided by 32.

3.19 Inter-integrated circuit interface (I2C)

Up to two I2C bus interfaces can operate in multimaster and slave modes. They can support
standard (up to 100

Both support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses
(2

addresses, 1 with configurable mask). They also include programmable analog and

digital noise filters.

KHz), fast (up to 400 KHz) and fast mode + (up to 1 MHz) modes.

Table 6. Comparison of I2C analog and digital filters

Analog filter Digital filter

Pulse width of
suppressed spikes

Benefits Available in Stop mode

Drawbacks

50 ns

Variations depending on
temperature, voltage, process

Programmable length from 1 to 15
I2C peripheral clocks

1. Extra filtering capability vs.
standard requirements.

2. Stable length

Wakeup from Stop on address
match is not available when digital
filter is enabled.

In addition, they provide hardware support for SMBUS 2.0 and PMBUS 1.1: ARP capability,
Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and
ALERT protocol management. They also have a clock domain independent from the CPU
clock, allowing the I2Cx (x=1,2) to wake up the MCU from Stop mode on address match.

The I2C interfaces can be served by the DMA controller.

Refer to Tab le 7 for the features available in I2C1 and I2C2.

7-bit addressing mode X X

10-bit addressing mode X X

Standard mode (up to 100 kbit/s) X X

Fast mode (up to 400 kbit/s) X X

Fast Mode Plus with 20mA output drive I/Os (up to 1 Mbit/s) X X

Table 7. STM32F303xB/STM32F303xC I2C implementation

I2C features

(1)

I2C1 I2C2

Independent clock X X

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Table 7. STM32F303xB/STM32F303xC I2C implementation (continued)

I2C features

SMBus X X

Wakeup from STOP X X

1. X = supported.

(1)

I2C1 I2C2

3.20 Universal synchronous/asynchronous receiver transmitter (USART)

The STM32F303xB/STM32F303xC devices have three embedded universal
synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3).

The USART interfaces are able to communicate at speeds of up to 9 Mbits/s.

They provide hardware management of the CTS and RTS signals, they support IrDA SIR
ENDEC, the multiprocessor communication mode, the single-wire half-duplex
communication mode and have LIN Master/Slave capability. The USART interfaces can be
served by the DMA controller.

3.21 Universal asynchronous receiver transmitter (UART)

The STM32F303xB/STM32F303xC devices have 2 embedded universal asynchronous
receiver transmitters (UART4, and UART5). The UART interfaces support IrDA SIR
ENDEC, multiprocessor communication mode and single-wire half-duplex communication
mode. The UART4 interface can be served by the DMA controller.

Refer to Tab le 8 for the features available in all U(S)ART interfaces.

Table 8. USART features

USART modes/features

Hardware flow control for modem X X X - -

Continuous communication using DMA X X X X -

Multiprocessor communication X X X X X

Synchronous mode X X X - -

Smartcard mode X X X - -

Single-wire half-duplex communication X X X X X

IrDA SIR ENDEC block X X X X X

LIN mode XXXXX

Dual clock domain and wakeup from Stop mode X X X X X

Receiver timeout interrupt XXXXX

Modbus communication X X X X X

Auto baud rate detection X X X - -

(1)

USART1 USART2 USART3 UART4 UART5

Driver Enable X X X - -

1. X = supported.

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Functional overview STM32F303xB STM32F303xC

3.22 Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I2S)

Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in
full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame size is configurable from 4 bits to 16 bits.

Two standard I2S interfaces (multiplexed with SPI2 and SPI3) supporting four different
audio standards can operate as master or slave at half-duplex and full duplex
communication modes. They can be configured to transfer 16 and 24 or 32 bits with 16-bit
or 32-bit data resolution and synchronized by a specific signal. Audio sampling frequency
from 8 kHz up to 192 kHz can be set by 8-bit programmable linear prescaler. When
operating in master mode it can output a clock for an external audio component at 256 times
the sampling frequency.

Refer to Tab le 9 for the features available in SPI1, SPI2 and SPI3.

Hardware CRC calculation X X X

Rx/Tx FIFO X X X

NSS pulse mode X X X

Table 9. STM32F303xB/STM32F303xC SPI/I2S implementation

SPI features

(1)

SPI1 SPI2 SPI3

I2S mode - X X

TI mode XXX

1. X = supported.

3.23 Controller area network (CAN)

The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It
can receive and transmit standard frames with 11-bit identifiers as well as extended frames
with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and
14 scalable filter banks.

3.24 Universal serial bus (USB)

The STM32F303xB/STM32F303xC devices embed an USB device peripheral compatible
with the USB full-speed 12 Mbs. The USB interface implements a full-speed (12 Mbit/s)
function interface. It has software-configurable endpoint setting and suspend/resume
support. The dedicated 48 MHz clock is generated from the internal main PLL (the clock
source must use a HSE crystal oscillator). The USB has a dedicated 512-bytes SRAM
memory for data transmission and reception.

28/149 DS9118 Rev 14

STM32F303xB STM32F303xC Functional overview

MSv30365V1

TIMER 16

(for envelop)

TIMER 17

(for carrier)

OC

OC

PB9/PA13

3.25 Infrared Transmitter

The STM32F303xB/STM32F303xC devices provide an infrared transmitter solution. The
solution is based on internal connections between TIM16 and TIM17 as shown in the figure
below.

TIM17 is used to provide the carrier frequency and TIM16 provides the main signal to be
sent. The infrared output signal is available on PB9 or PA13.

To generate the infrared remote control signals, TIM16 channel 1 and TIM17 channel 1 must
be properly configured to generate correct waveforms. All standard IR pulse modulation
modes can be obtained by programming the two timers output compare channels.

Figure 3. Infrared transmitter

3.26 Touch sensing controller (TSC)

The STM32F303xB/STM32F303xC devices provide a simple solution for adding capacitive
sensing functionality to any application. These devices offer up to 24 capacitive sensing
channels distributed over 8 analog I/O groups.

Capacitive sensing technology is able to detect the presence of a finger near a sensor which
is protected from direct touch by a dielectric (glass, plastic, ...). The capacitive variation
introduced by the finger (or any conductive object) is measured using a proven
implementation based on a surface charge transfer acquisition principle. It consists of
charging the sensor capacitance and then transferring a part of the accumulated charges
into a sampling capacitor until the voltage across this capacitor has reached a specific
threshold. To limit the CPU bandwidth usage this acquisition is directly managed by the
hardware touch sensing controller and only requires few external components to operate.

The touch sensing controller is fully supported by the STMTouch touch sensing firmware
library which is free to use and allows touch sensing functionality to be implemented reliably
in the end application.

DS9118 Rev 14 29/149

55

Functional overview STM32F303xB STM32F303xC

Table 10. Capacitive sensing GPIOs available on STM32F303xB/STM32F303xC

devices

Group

1

2

3

4

Capacitive sensing

signal name

TSC_G1_IO1 PA0

Pin

name

Group

Capacitive sensing

signal name

TSC_G5_IO1 PB3

TSC_G1_IO2 PA1 TSC_G5_IO2 PB4

5

TSC_G1_IO3 PA2 TSC_G5_IO3 PB6

TSC_G1_IO4 PA3 TSC_G5_IO4 PB7

TSC_G2_IO1 PA4

TSC_G6_IO1 PB11

TSC_G2_IO2 PA5 TSC_G6_IO2 PB12

6

TSC_G2_IO3 PA6 TSC_G6_IO3 PB13

TSC_G2_IO4 PA7 TSC_G6_IO4 PB14

TSC_G3_IO1 PC5

TSC_G7_IO1 PE2

TSC_G3_IO2 PB0 TSC_G7_IO2 PE3

7

TSC_G3_IO3 PB1 TSC_G7_IO3 PE4

TSC_G3_IO4 PB2 TSC_G7_IO4 PE5

TSC_G4_IO1 PA9

TSC_G8_IO1 PD12

TSC_G4_IO2 PA10 TSC_G8_IO2 PD13

8

TSC_G4_IO3 PA13 TSC_G8_IO3 PD14

TSC_G4_IO4 PA14 TSC_G8_IO4 PD15

Table 11. No. of capacitive sensing channels available on

STM32F303xB/STM32F303xC devices

Pin

name

Number of capacitive sensing channels

Analog I/O group

STM32F303Vx STM32F303Rx STM32F303Cx

G1 3 3 3

G2 3 3 3

G3 3 3 2

G4 3 3 3

G5 3 3 3

G6 3 3 3

G7 3 0 0

G8 3 0 0

Number of capacitive

sensing channels

24 18 17

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