ST MICROELECTRONICS STM32 F103VBT6 Instructions
STM32F103x6
STM32F103x8 STM32F103xB
Performance line, ARM-based 32-bit MCU with Flash, USB, CAN,
seven 16-bit timers, two ADCs and nine communication interfaces
Preliminary Data
Features
■ Core: ARM 32-bit Cortex™-M3 CPU
– 72 MHz, 90 DMIPS with 1.25 DMIPS/MHz
– Single-cycle multiplication and hardware
division
– Nested interrupt controller with 43
maskable interrupt channels
– Interrupt processing (down to 6 CPU
cycles) with tail chaining
■ Memories
– 32-to -1 2 8 Kbytes of Flash me m ory
– 6-to- 20 Kbytes of SRAM
■ Clock, reset and supply management
– 2.0 to 3.6 V application supply and I/Os
– POR, PDR, and programmable voltage
detector (PVD)
– 4-to-16 MHz quartz oscillator
– Internal 8 MHz factory-trimmed RC
– Internal 32 kHz RC
– PLL for CPU clock
– Dedicated 32 kHz oscillator for RTC with
calibration
■ Low power
– Sleep, Stop and Standby modes
–V
■ 2 x 12-bit, 1 µs A/D converters (16-channel)
supply for RTC and backup registers
BAT
– Conversion range: 0 to 3.6 V
– Dual-sample and hold capability
– Synchronizable with advanced control timer
– Temperature sensor
■ DMA
– 7-channel DMA controller
– Peripherals supported: timers, ADC, SPIs,
2
I
Cs and USARTs
LQFP48
7 x 7 mm
■ Debug mode
LQFP100
14 x 14 mm
– Serial wire debug (SWD) & JTAG int erfaces
■ Up to 80 fast I/O ports
– 32/49/80 5 V-tolerant I/Os
– All mappable on 16 external interrupt
vectors
– Atomi c re ad /m o dif y/write operations
■ Up to 7 timers
– Up to three 16-bit timers, each with up to 4
IC/OC/PWM or pulse counter
– 16-bit, 6-channel advanced control timer:
up to 6 channels for PWM output
Dead time generation and emergency
stop
– 2 x 16-bit watchdog timers (Independent
and Window)
– SysTick timer: a 24-bit downcounter
■ Up to 9 communication interfaces
– Up to 2 x I
2
C interfaces (SMBus/PMBus)
– Up to 3 USARTs (ISO 7816 interface, LIN,
IrDA capability, modem control)
– Up to 2 SPIs (18 Mbit/s)
– CAN interface (2.0B Active)
– USB 2.0 full speed interface
Table 1. Device summary
Reference Root part number
STM32F103x6 STM32F103C6, STM32F103R6
STM32F103x8
STM32F103xB STM32F103RB STM32F103VB
STM32F103C8, STM32F103R8
STM32F103V8
LQFP64
10 x 10 mm
BGA100
10 x 10 mm
July 2007 Rev 2 1/67
This is preliminary information on a new product now in development or undergoing ev aluation. Details are subject to
change without notice.
www.st.com
1
Contents STM32F103xx
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1 Test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 27
5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 28
5.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.3.11 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 42
5.3.12 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.3.13 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
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STM32F103xx Contents
5.3.14 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.3.15 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.3.16 CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.3.17 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.3.18 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.1 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
7.1 Future family enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3/67
List of tables STM32F103xx
List of tables
Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Device features and peripheral counts (STM32F103xx performance line). . . . . . . . . . . . . . 7
Table 3. Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 4. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 5. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 6. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 7. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 8. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 9. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 10. Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 11. Maximum current consumption in Run and Sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 12. Maximum current consumption in Stop and Standby modes . . . . . . . . . . . . . . . . . . . . . . . 30
Table 13. Typical current consumption in Run and Sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 14. Typical current consumption in Stop and Standby modes . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 15. High-speed external (HSE) user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 16. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 17. HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 18. LSE oscillator characteristics (f
Table 19. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 20. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 21. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 22. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 23. Flash memory characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 24. Flash memory endurance and data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 25. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 26. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 27. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 28. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 29. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 30. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 31. I/O AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 32. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 33. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 34. I
Table 35. SCL frequency (f
2
C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
= 36 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
PCLK1
Table 36. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 37. USB DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 38. USB: Full speed electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 39. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 40. ADC accuracy (f
PCLK2
= 14 MHz, f
Table 41. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 42. LFBGA100 - low profile fine pitch ball grid array package mechanical data. . . . . . . . . . . . 59
Table 43. LQFP100 – 100-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . 61
Table 44. LQFP64 – 64 pin low-profile quad flat package mechanical data. . . . . . . . . . . . . . . . . . . . 62
Table 45. LQFP48 – 48 pin low-profile quad flat package mechanical data. . . . . . . . . . . . . . . . . . . . 63
Table 46. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 47. Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
LSE
= 14 MHz, R
ADC
<10 kΩ, V
AIN
= 3.3 V). . . . . . . . . 55
DDA
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STM32F103xx List of figures
List of figures
Figure 1. STM32F103xx performance line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 2. STM32F103xx performance line LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 3. STM32F103xx performance line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 4. STM32F103xx performance line LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 5. STM32F103xx performance line BGA100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 6. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 7. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 8. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 9. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 10. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 11. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 12. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 13. Typical application with a 8-MHz crystal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 14. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 15. Unused I/O pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 16. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 17. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 18. I
Figure 19. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 20. SPI timing diagram - slave mode and CPHA = 11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 21. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 22. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 23. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 24. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 25. Power supply and reference decoupling (V
Figure 26. Power supply and reference decoupling (V
Figure 27. LFBGA100 - low profile fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . 59
Figure 28. Recommended PCB design rules (0.80/0.75 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . . 60
Figure 29. LQFP100 – 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 30. LQFP64 – 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 31. LQFP48 – 48 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2
C bus AC waveforms and measurement circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
not connected to V
REF+
connected to V
REF+
DDA
). . . . . . . . . . . . . . 57
DDA
). . . . . . . . . . . . . . . . . 57
5/67
Introduction STM32F103xx
1 Introduction
This datasheet provides the STM32F103xx performance line ordering information and
mechanical device characteristics.
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM32F10xxx Flash pr og ra mming reference manual, pm0042 , available
from www.st.com.
For information on the Cortex-M3 core please refer to the Cortex-M3 Technical Reference
Manual.
2 Description
The STM32F103xx performance line family incorporates the high-performance ARM
Cortex-M3 32-bit RISC core operating at a 72 MHz frequency, high-speed embedded
memories (Flash memory up to 128Kbytes and SRAM up to 20 Kbytes), and an extensive
range of enhanced I/Os and peripherals connected to two APB buses. All devices offer two
12-bit ADCs, three general purpose 16-bit timers plus one PWM timer, as well as standard
and advanced communication interfaces: up to tw o I
and a CAN.
2
Cs and SPIs, three USARTs, an USB
The STM32F103xx performance line family operates in the −40 to +105 °C temperature
range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allo ws
to design low-power applications.
The complete STM32F103xx performance line f amily includes devices in 4 different
package types: from 48 pins to 100 pins. Depending on the device chosen, different sets of
peripherals are included, the description below gives an overview of the complete range of
peripherals proposed in this family.
These features make t he STM32F103xx performance line microcontroller family suitab le for
a wide range of applications:
● Motor drive and application control
● Medical and handheld equipment
● PC peripherals gaming and GPS platforms
● Industrial applications: PLC, inverters, printers, and scanners
● Alarm systems, Video intercom, and HVAC
Figure 1 shows the general block diagram of the device family.
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STM32F103xx Description
2.1 Device overview
Table 2. Device features and peripheral counts (STM32F103xx performance line)
Peripheral
Flash - Kbytes 32 64 32 64 128 64 128
SRAM - Kbytes 10 20 10 20 20
General purpose 232 3 3
Advanced Control 111
Timers
SPI 121 2 2
2
I
C 121 2 2
USART 232 3 3
USB 111 1 1
Communication
CAN 1 1 1 1 1
GPIOs 32 49 80
STM32F103Cx STM32F103Rx STM32F103Vx
12-bit synchronized ADC
Number of channels
2
10 channels
2
16 channels
CPU frequency 72 MHz
Operating voltage 2.0 to 3.6 V
Operating temperature -40 to +85 °C / -40 to +105 °C
Packages LQFP48 LQFP64
LQFP100,
BGA100
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Description STM32F103xx
2.2 Overview
ARM® CortexTM-M3 core with embedded Flash and SRAM
The ARM Cortex-M3 processor is the latest generation of ARM processors for embedded
systems. It has been de v eloped t o prov ide a low- cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex-M3 32-bit RISC processor features exceptional code-efficiency, delivering
the high-performance expected from an ARM core in the memory size usually associated
with 8- and 16-bit devices.
The STM32F103xx performance line family having an embedded ARM core, is therefore
compatible with all ARM tools and software.
Figure 1 shows the general block diagram of the device family.
Embedded Flash memory
● Up to 128 Kbytes of embedded Flash is available for storing programs and data.
Embedded SRAM
Up to 20 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states.
Nested vectored interrupt controller (NVIC)
The STM32F103xx performance line embeds a Nested Vectored Interrupt Controller able to
handle up to 43 maskable interrupt channels (not including the 16 interrupt lines of CortexM3) and 16 priority levels.
● Closely coupled NVIC gives low latency interrupt processing
● Interrupt entry vector table address passed directly to the core
● Closely coupled NVIC core interface
● Allows early processing of interrupts
● Processing of late arriving higher priority inte r rupts
● Support for tail-chaining
● Processor state automatically saved
● Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 19 edge detectors lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge , falling edge, both) and ca n be mask ed ind ependently. A pending register
maintains the status of the interrupt requests. The EXTI can detect external line with pulse
width lower than the Internal APB2 clock period. Up to 80 GPIOs are connected to the 16
external interrupt lines.
8/67
STM32F103xx Description
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-16 MHz clock can be selected and is
monitored for failure. During such a scenario, it is disabled and software interrupt
management follo ws . Similarly, full interrupt management of the PLL clock entry is available
when necessary (for example with failure of an indirectly used external oscillator).
Several prescalers allow the configuration of the AHB frequency, the High Speed APB
(APB2) and the low Speed APB (APB1) domains. The maximum frequency of the AHB and
the High Speed APB domains is 72 MHz. The maximum allowed frequency of the Low
Speed APB domain is 36 MHz.
Boot modes
At startup, boot pins are used to select one of three boot options:
● Boot from User Flash
● Boot from System Memory
● Boot from SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using the USART.
Power supply schemes
● V
● V
● V
= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.
DD
Provided externally through V
, V
SSA
and PLL. In V
BAT
= 2.0 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs
DDA
range (ADC is limited at 2.4 V).
DD
= 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup
registers (through power switch) when V
DD
pins.
is not present.
DD
Power supply supervisor
The device has an integrated Power On Reset (POR)/Power Down Reset (PDR) circuitry. It
is always active, and ensures proper operation starting from/down to 2 V. The device
remains in reset mode when V
for an e xternal reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
V
power supply and compares it to the V
DD
when V
drops below the V
DD
interrupt service routine can then generate a warning message and/or put the MCU into a
safe state. The PVD is enabled by software.
Refer to Table 9: Embedded reset and power control block characteristics for the v alues of
V
POR/PDR
and V
PVD
.
is below a specified threshold, V
DD
threshold. An interrupt can be generated
and/or when VDD is higher than the V
PVD
PVD
POR/PDR
PVD
, without the need
threshold. The
9/67
Description STM32F103xx
Voltage regulator
The regulator has three operation modes: ma in (M R ), low power (LPR) and power down.
● MR is used in the nominal regulation mode (Run)
● LPR is used in the Stop modes.
● Power down is used in Standby Mode: the regulator output is in high impedance: the
kernel circuitry is powered-down, inducing zero consumption (but the contents of the
registers and SRAM are lost)
This regulator is alwa ys enabled after reset. It is disabled in Standby Mode, providing high
impedance output.
Low-power modes
The STM32F103xx performance line supports three low-power modes to achieve the best
compromise between low power consumption, short startup time and available wakeup
sources:
● Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
● Stop mode
Stop mode allows to achieve the lowest po we r consumption while re taining the co ntent
of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI
and the HSE RC oscillators are disabled. The voltage regulator can also be put either in
normal or in low power mode.
The device can be wok en up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD ou tp ut , the RTC alarm or the USB
wakeup.
● Standby mode
The Standby mode allows to achieve the lo west power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI and the HSE RC oscillators are also switched off. After entering Standby
mode, SRAM and registers content are lost except for registers in the Backup domain
and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a
rising edge on the WKUP pin, or an RTC alarm occurs.
Note: The RTC, the IWDG, and the cor responding cloc k sources are n ot stopped b y entering Stop
or Standby mode.
DMA
The flexible 7-channel general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals: SPI, I
advanced control timers TIMx and ADC.
10/67
2
C, USART, general purpose and
STM32F103xx Description
RTC (real-time clock) and backup registers
The RTC and the bac kup registers are supplied through a switch that takes po wer either on
V
supply when present or through the V
DD
registers) can be used to store data when V
pin. The backup registers (ten 16-bit
BAT
power is not present.
DD
The real-time clock provides a set of continuously running counters which can be used with
suitable software to pro vide a cloc k calendar funct ion, and prov ides an alarm interrupt and a
periodic interrupt. It is clocked by an external 32.768 kHz oscillator, the internal low power
RC oscillator or the High Speed External clock divided by 128. The internal low power RC
has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz
output to compensate for any natural quartz deviation. The RTC features a 32-bit
programmable counter for long term measurement using the Compare register to generate
an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to
generate a time base of 1 second from a clock at 32.768 kHz.
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a prob lem occurs , or as a free running timer f or applicati on time out
management. It is hardware o r software configurable through the option bytes. The counter
can be frozen in debug mode.
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the de vice when a prob lem occurs . It is clock ed from the
main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
SysTick timer
This timer is dedicated for OS, but could also be used as a standard down counter. It
features:
● A 24-bit down counter
● Autoreload capability
● Maskable system interrupt generation whe n th e co un te r re ach e s 0.
● Programmable clock source
General purpose timers (TIMx)
There are up to 3 synchronizable standard timers embedded in the STM32F103xx
performance line devices. These timers are based on a 16-bit auto -reloa d up/down counter,
a 16-bit prescaler and feature 4 independent channels each for input capture/output
compare, PWM or one pulse mode output. This gives up to 12 input captures / outpu t
compares / PWMs on the largest packages. They can work together with the Advanced
Control Timer via the Timer Link feature for synchronization or event chaining.
The counter can be frozen in debug mode.
Any of the standard timers can be used to generate PWM outputs. Each of the timers has
independent DMA request generations.
11/67
Description STM32F103xx
Advanced control timer (TIM1)
The advanced control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6
channels. It can also be seen as a complete general-purpose timer. The 4 independent
channels can be used for
● Input Capture
● Output Compare
● PWM generation (edge or center-aligne d mo d es )
● One Pulse Mode output
● Complementary PWM outputs with programmable inserted dead-times.
If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If
configured as the 16-bit PWM generator, it has full modulation capability (0-100%).
The counter can be frozen in debug mode.
Many features are shared with those of the standard TIM timers which have the same
architecture. The adv anced control timer can theref ore w ork together with the TIM timers via
the Timer Link feature for synchronization or e vent chaining.
I²C bus
Up to two I²C bus interf aces can oper ate in multi-maste r and slav e modes . They can sup port
standard and fast modes.
They support dual slave addressing (7-bit only) and both 7/10-bit addressing in master
mode. A hardware CRC generation/verification is embedded.
They can be served by DMA and they support SM Bus 2.0/PM Bus.
Universal synchronous/asynchronous receiver transmitter (USART)
One of the USART interfaces is able to communicate at speeds of up to 4.5 Mbit/s. The
other available interfaces communicate at up to 2.25 Mbit/s. They provide hardware
management of the CTS and RTS signals, IrDA SIR ENDEC support, are ISO 7816
compliant and have LIN Master/Slave capability.
All USART interfaces can be served by the DMA controller.
Serial peripheral interface (SPI)
Up to two SPIs are able to communicate up to 18 Mbits/s in slave and master modes in fullduplex and simplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable from 8-bit to 16-bit. The hardware CRC
generation/ve rification supports basic SD Card/MMC modes.
Both SPIs can be served by the DMA controller.
Controller area network (CAN)
The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It
can receive and transmit standard frames with 11-bit identifiers as well as extended frames
with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and
14 scalable filter banks.
12/67
STM32F103xx Description
Universal serial bus (USB)
The STM32F103xx performance line embeds a USB device peripheral compatible with the
USB Full-speed 12 Mbs. The USB interface implements a full speed (12 Mbit/s) function
interface. It has software configurable endpoint setting and suspend/resume support. The
dedicated 48 MHz clock source is generated from the internal main PLL.
GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured b y softw are as output ( push-pull or open-dr ain), as
input (with or without pull-up or pull-down) or as pe ripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
I/Os on APB2 with up to 18 MHz toggling speed
ADC (analog to digital converter)
Two 12-bit Analog to Digital Converters are embedded into STM32F103xx performance line
devices and each ADC shares up to 16 external channels, performing conversions in singleshot or scan modes. In scan mode, automatic conversion is performed on a selected group
of analog inputs.
Additional logic functions embedded in the ADC interface allow:
● Simultaneous sample and hold
● Interleaved sample and hold
● Single shunt
The ADC can be served by the DMA controller.
An analog watchdog f eatur e allo ws very precise monitoring of the converted voltage of one ,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The ev ents gener ated b y the sta ndard timer s (TIMx) and the Adv an ced Contro l timer (TIM 1)
can be internally connected to the ADC start trigger, injection trigger, and DMA trigger
respectively, to allow the application to synchronize A/D conversion and timers.
Temperature sensor
The temperature sensor has to generate a linear voltage with any variation in temperature.
The conversion range is between 2 V < V
< 3.6 V. The tem pe ratur e sen so r is inte rnally
DDA
connected to the ADC_IN16 input channel which is used to convert the sensor output
voltage into a digital value.
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP Interface is embedded. and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
13/67
Description STM32F103xx
Figure 1. STM32F103xx performance line block diagram
JNTRST
JTDI
JTCK/SWCLK
JTMS/SWDIO
JTDO
as AF
NRST
VDDA
VSSA
80AF
PA[15:0]
PB[15:0]
PC[15:0]
PD[15:0]
PE[15:0]
4 Channels
3 compl. Channels
Brk input
MOSI,MISO,
SCK,NSS as AF
RX,TX, CTS, RTS,
SmartCard as AF
16AF
V
REF+
V
REF-
JTAG & SWD
CORTEX M3 CPU
F
: 72 MHz
max
NVIC
GP DMA
7 channels
@VDDA
SUPPLY
SUPERVISION
POR / PDR
PVD
EXTI
WAKEUP
GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
TIM1
SPI1
USART1
@VDDA
12bit ADC1
12bit ADC2
Temp sensor
Ibus
=48 / 72 MHz
APB2 : F
max
BusMatrix
Controller
AHB2
APB2
Trace
=48/72 MHz
max
AHB:F
obl
FLASH 128 KB
Interface
flash
SRAM
20 KB
PCLK1
PCLK2
HCLK
FCLK
RC 8 MHz
RC 32 kHz
@VDDA
AHB2
APB1
64 bit
PLL &
CLOCK
MANAGT
@VBAT
=24 / 36 MHz
max
APB1 : F
POWER
VOLT. REG.
3.3V TO 1.8V
@VDD
@VDD
XTAL OSC
4-16 MHz
IWDG
Standby
interface
XTAL 32 kHz
Backup
RTC
AWU
Backup interface
TIM2
TIM3
TIM 4
USART2
USART3
SPI2
2x(8x16bit)
I2C1
I2C2
bxCAN
USB 2.0 FS
SRAM 512B
WWDG
reg
V
= 2 to 3.6V
DD
V
SS
OSC_IN
OSC_OUT
V
BAT
OSC32_IN
OSC32_OUT
ANTI_TAMP
4 Channels
4 Channels
8 Channels
RX,TX, CTS, RTS,
SmartCard as AF
RX,TX, CTS, RTS,
SmartCard as AF
MOSI,MISO,SCK,NSS
as AF
SCL,SDA,SMBAL
as AF
SCL,SDA
as AF
USBDP/CANTX
USBDM/CANRX
pbus
Dbus
System
Rst
Int
IF
IFIF
1. TA = –40 °C to +105 °C (junction temperature up to 125 °C).
2. AF = alternate function on I/O port pin.
14/67
ai14390
STM32F103xx Pin descriptions
3 Pin descriptions
Figure 2. STM32F103xx performance line LQFP100 pinout
VDD_3
VSS_3
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
PE2
PE3
PE4
PE5
PE6
VBAT
PC13-ANTI_T AMP
PC14-OSC32_IN
PC15-OSC32_OUT
VSS_5
VDD_5
OSC_IN
OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VREF-
VREF+
VDDA
PA0-WKUP
PA1
PA2
100999897969594939291908988878685848382818079787776
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26272829303132333435363738394041424344454647484950
PA3
PA4
PA5
PA6
VSS_4
VDD_4
LQFP100
PA7
PB0
PB1
PB2
PE7
PE8
PC4
PC5
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VSS_1
75
VDD_2
74
VSS_2
73
NC
72
PA 13
71
PA 12
70
PA 11
69
PA 10
68
PA 9
67
PA 8
66
PC9
65
PC8
64
PC7
63
PC6
62
PD15
61
PD14
60
PD13
59
PD12
58
PD11
57
PD10
56
PD9
55
PD8
54
PB15
53
PB14
52
PB13
51
PB12
VDD_1
ai14391
15/67
Pin descriptions STM32F103xx
Figure 3. STM32F103xx performance line LQFP64 pinout
VDD_3
VSS_3
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PD2
PC12
PC11
PC10
PA15
PA14
PC13-ANTI_T AMP
VBAT
PC14-OSC32_IN
PC15-OSC32_OUT
PD0 OSC_IN
PD1 OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VDDA
PA0-WKUP
PA1
PA2
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 29 30 31 3225 26 27 28
PA3
VSS_4
VDD_4
LQFP64
PA4
PA5
PA6
PA7
PB0
PB1
PC5
PB2
PB10
PB11
PC4
VDD_2
48
VSS_2
47
PA13
46
PA12
45
PA11
44
PA10
43
PA9
42
PA8
41
PC9
40
PC8
39
PC7
38
PC6
37
PB15
36
PB14
35
PB13
34
33
PB12
VSS_1
VDD_1
ai14392
Figure 4. STM32F103xx performance line LQFP48 pinout
VDD_3
VSS_3
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PA15
PC13-ANTI_TAMP
VBAT
PC14-OSC32_IN
PC15-OSC32_OUT
PD0 OSC_IN
PD1 OSC_OUT
NRST
VSSA
VDDA
PA0-WKUP
PA1
PA2
48 47 46 45
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22
PA3
44 43 42 41 40 39 38 37
LQFP48
PA4
PA5
PA6
PA7
PB0
PB1
PB2
36
34
33
32
31
30
29
28
27
26
25
24
23
PB10
PB11
VSS_1
VDD_1
PA14
35
VDD_2
VSS_2
PA13
PA12
PA11
PA10
PA9
PA8
PB15
PB14
PB13
PB12
ai14393
16/67
STM32F103xx Pin descriptions
Figure 5. STM32F103xx performance line BGA100 ballout
A
B PC11PD2
C
D PD4
E
F
PC14-
OSC32_IN
PC15-
OSC32_OUT
OSC_IN
OSC_OUT V
PC0
PC13-
ANTI_TAMP
V
BAT
V
SS_5
DD_5
PCD
PC1
PE2
PE4
PE5
PC3
PB9
PB8PE3
PE1
PE0
V
SS_4
V
DD_4
PB7
PB6
PB5
BOOT0
V
SS_3
DD_3
PB4
PD5
PD6
PD7
V
V
DD_2
SS_2
PB3
PD3
V
SS_1
V
DD_1
87654321
PA15
PC12
PD0
PD1PE6NRST
NCV
PA14
PC10
PA9
PA8
PC9
PC8
109
APA13
PA12
PA11
PA10
PC7
PC6
G
H
K
V
V
J
V
SSA
REF–
REF+
DDA
PA0-WKUP
PA1
PA2
PA3
PC4PA4
PC5PA5
PB0PA6
PB1PA7
PB2
PE8
PE10
PE11PE7
PE12
PE13PE9V
PE14
PE15
PB10
PB11
PB15
PB14
PB13
PB12
PD11
PD10
PD9
PD8
PD15
PD14
PD13
PD12
AI16001
17/67
Pin descriptions STM32F103xx
Pins
LQFP48
(2)
Pin name
(1)
Type
LQFP64
LQFP100
BAT
(4)
(4)
(4)
SS_5
DD_5
SV
I/O PC13 ANTI_TAMP
I/O PC14-OSC32_IN
I/O PC15-OSC32_OUT
SV
SV
I / O Level
FT
FT
FT
FT
FT
Main function
(after reset)
PE2 TRACECK
PE3 TRACED0
PE4 TRACED1
PE5 TRACED2
PE6 TRACED3
SS_5
DD_5
BAT
(3)
Default alternate functions
Table 3. Pin definitions
BGA100
A3 - - 1 PE2/TRACECK I/O
B3 - - 2 PE3/TRACED0 I/O
C3 - - 3 PE4/TRACED1 I/O
D3 - - 4 PE5/TRACED2 I/O
E3 - - 5 PE6/TRACED3 I/O
B2 1 1 6 V
A2 2 2 7 PC13-ANTI_TAMP
A1 3 3 8 PC14-OSC32_IN
B1 4 4 9 PC15-OSC32_OUT
C2 - - 10 V
D2 - - 11 V
C1 5 5 12 OSC_IN I OSC_IN
D1 6 6 13 OSC_OUT O OSC_OUT
E1 7 7 14 NRST I/O NRST
F1 - 8 15 PC0/ADC_IN10 I/O PC0 ADC_IN10
F2 - 9 16 PC1/ADC_IN11 I/O PC1 ADC_IN11
E2 - 10 17 PC2/ADC_IN12 I/O PC2 ADC_IN12
F3 - 11 18 PC3/ADC_IN13 I/O PC3 ADC_IN13
G1 8 12 19 V
H1 - - 20 V
J1 - - 21 V
K1 9 13 22 V
PA0-WKUP/
G2 10 14 23
USART2_CTS/
ADC_IN0/TIM2_CH1_ETR
H2 11 15 24
J2 12 16 25
K2 13 17 26
PA1/USAR T2_RTS/
ADC_IN1/TIM2_CH2
PA2/USART2_TX/
ADC_IN2/ TIM2_CH3
PA3/USART2_RX/
ADC_IN3/TIM2_CH4
E4 - 18 27 V
F4 - 19 28 V
SSA
REF-
REF+
DDA
SS_4
DD_4
SV
SV
SV
SV
SSA
REF-
REF+
DDA
WKUP/USART2_CTS
I/O PA0
I/O PA1
I/O PA2
I/O PA3
SV
SV
SS_4
DD_4
ADC_IN2/ TIM2_CH3
ADC_IN3/TIM2_CH4
C_IN0/
TIM2_CH1_ETR
USART2_RTS
ADC_IN1/
TIM2_CH2
USART2_TX
USART2_RX
(6)
(6)
(6)
(6)
(6)
(6)
/
/
/
/AD
(6)
(6)
18/67
STM32F103xx Pin descriptions
Table 3. Pin definitions (continued)
Pins
Pin name
LQFP48
BGA100
G3 14 20 29
LQFP64
LQFP100
PA4/SPI1_NSS/
USART2_CK/ADC_IN4
I/O PA4
H3 15 21 30 PA5/SPI1_SCK/ ADC_IN5 I/O PA5 SPI1_SCK
J3 16 22 31
K3 17 23 32
PA6/SPI1_MISO/
ADC_IN6/TIM3_CH1
PA7/SPI1_MOSI/
ADC_IN7/TIM3_CH2
I/O PA6
I/O PA7
(2)
(1)
Type
Main function
(after reset)
(3)
Default alternate functions
I / O Level
(6)
(6)
/ ADC_IN4
(6)
/ ADC_IN5
(6)
(6)
/
/
(6)
/
(6)
SPI1_NSS
USART2_CK
SPI1_MISO
ADC_IN6/TIM3_CH1
SPI1_MOSI
ADC_IN7/TIM3_CH2
G4 - 24 33 PC4/ADC_IN14 I/O PC4 ADC_IN14
H4 - 25 34 PC5/ADC_IN15 I/O PC5 ADC_IN15
J4 18 26 35 PB0/ADC_IN8/ TIM3_CH3 I/O PB0 ADC_IN8/TIM3_CH3
K4 19 27 36 PB1/ADC_IN9/ TIM3_CH4 I/O PB1 ADC_IN9/TIM3_CH4
(6)
(6)
G5 20 28 37 PB2 / BOOT1 I/O FT PB2/BOOT1
H5 - - 38 PE7 I/O FT PE7
J5 - - 39 PE8 I/O FT PE8
K5 - - 40 PE9 I/O FT PE9
G6 - - 41 PE10 I/O FT PE10
H6 - - 42 PE11 I/O FT PE11
J6 - - 43 PE12 I/O FT PE12
K6 - - 44 PE13 I/O FT PE13
G7 - - 45 PE14 I/O FT PE14
H7 - - 46 PE15 I/O FT PE15
J7 21 29 47
K7 22 30 48
PB10/I2C2_SCL/
USART3_TX
PB11/I2C2_SDA /
USART3_RX
E7 23 31 49 V
F7 24 32 50 V
PB12/SPI2_NSS /
K8 25 33 51
I2C2_SMBAl/ USART3_CK /
TIM1_BKIN
PB13/SPI2_SCK /
J8 26 34 52
USART3_CTS /
TIM1_CH1N
PB14/SPI2_MISO /
H8 27 35 53
USART3_RTS /
TIM1_CH2N
SS_1
DD_1
I/O FT PB10 I2C2_SCL/USART3_TX
I/O FT PB11
SV
SV
SS_1
DD_1
I2C2_SDA/
USART3_RX
SPI2_NSS
I/O FT PB12
/I2C2_SMBAl
USART3_CK
TIM1_BKIN
SPI2_SCK
I/O FT PB13
USART3_CTS
TIM1_CH1N
SPI2_MISO
I/O FT PB14
/USART3_RTS
TIM1_CH2N
(5)(6)
(5)
(5)
(5)(6)
(6)
(5)
/
(5)(6)
(6)
(5)
(5)(6)
(6)
(5)(6)
/
/
/
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Pin descriptions STM32F103xx
Table 3. Pin definitions (continued)
Pins
LQFP48
BGA100
LQFP64
G8 28 36 54
Pin name
LQFP100
PB15/SPI2_MOSI
TIM1_CH3N
I/O FT PB15
(2)
(1)
Type
Main function
(after reset)
(3)
Default alternate functions
I / O Level
SPI2_MOSI
TIM1_CH3N
K9 - - 55 PD8 I/O FT PD8
J9 - - 56 PD9 I/O FT PD9
H9 - - 57 PD10 I/O FT PD10
G9 - - 58 PD11 I/O FT PD11
K10 - - 59 PD12 I/O FT PD12
J10 - - 60 PD13 I/O FT PD13
H10 - - 61 PD14 I/O FT PD14
G10 - - 62 PD15 I/O FT PD15
F10 - 37 63 PC6 I/O FT PC6
E10 38 64 PC7 I/O FT PC7
F9 39 65 PC8 I/O FT PC8
E9 - 40 66 PC9 I/O FT PC9
D9 29 41 67
C9 30 42 68
D10314369
C10324470
B10334571
PA8/USART1_CK/
TIM1_CH1/MCO
PA9/USART1_TX/
TIM1_CH2
PA10/USART1_RX/
TIM1_CH3
PA11 / USART1_CTS/
CANRX / USBDM/
TIM1_CH4
PA12 / USART1_RTS/
CANTX / USBDP/
TIM1_ETR
I/O FT PA8
I/O FT PA9
I/O FT PA10
I/O FT PA11
I/O FT PA12
USART1_CK/
TIM1_CH1
USART1_TX
TIM1_CH2
USART1_RX
TIM1_CH3
USART1_CTS/
CANRX
TIM1_CH4
USART1_RTS/
CANTX
TIM1_ETR
(6)
(6)
A10344672 PA13/JTMS/SWDIO I/O FT JTMS/SWDIO PA13
F8 - - 73 Not connected
E6 35 47 74 V
F6 36 48 75 V
SS_2
DD_2
SV
SV
SS_2
DD_2
A9 37 49 76 PA14/JTCK/SWCLK I/O FT JTCK/SWCLK PA14
A8 38 50 77 PA15/JTDI I/O FT JTDI PA15
B9 - 51 78 PC10 I/O FT PC10
B8 - 52 79 PC11 I/O FT PC11
C8 - 53 80 PC12 I/O FT PC12
(5)
/
(6)
(6)
/MCO
(6)
/
(6)
(6)
/
(6)
(6)
/
/ USBDM
(6)
/
/ USBDP
20/67
STM32F103xx Pin descriptions
Table 3. Pin definitions (continued)
Pins
Pin name
LQFP48
BGA100
LQFP64
LQFP100
D8 5 5 81 PD0 I/O FT OSC_IN
E8 6 6 82 PD1 I/O FT OSC_OUT
(2)
(1)
Type
Main function
(after reset)
(3)
Default alternate functions
I / O Level
(7)
(7)
B7 54 83 PD2/TIM3_ETR I/O FT PD2 TIM3_ETR
C7 - - 84 PD3 I/O FT PD3
D7 - - 85 PD4 I/O FT PD4
B6 - - 86 PD5 I/O FT PD5
C6 - - 87 PD6 I/O FT PD6
D6 - - 88 PD7 I/O FT PD7
A7 39 55 89 PB3/JTDO/TRACESWO I/O FT JTDO PB3/TRACESWO
A6 40 56 90 PB4/JNTRST I/O FT JNTRST PB4
C5 41 57 91 PB5/I2C1_SMBAl I/O PB5 I2C1_SMBAl
B5 42 58 92 PB6/I2C1_SCL/ TIM4_CH1 I/O FT PB6
A5 43 59 93 PB7/I2C1_SDA/ TIM4_CH2 I/O FT PB7
I2C1_SCL
TIM4_CH1
I2C1_SDA
TIM4_CH2
(6)
(5)(6)
(6)
(5) (6)
/
/
D5 44 60 94 BOOT0 I BOOT0
B4 45 61 95 PB8/TIM4_CH3 I/O FT PB8 TIM4_CH3
A4 46 62 96 PB9/TIM4_CH4 I/O FT PB9 TIM4_CH4
D4 - - 97 PE0/TIM4_ETR I/O FT PE0 TIM4_ETR
(5) (6)
(5) (6)
(5)
C4 - - 98 PE1 I/O FT PE1
E5 47 63 99 V
F5 48 64 100 V
1. I = input, O = output, S = supply, HiZ = high impedance.
2. FT= 5 V tolerant.
3. Function availability depends on the chosen device. Refer to Table 2 on page 7.
4. PC13, PC14 and PC15 are supplied through the power switch, and so their use in ouptut mode is limited: they can be used
only in output 2 MHz mode with a maximum load of 30 pF and only one pin can be put in output mode at a time.
5. Available only on devices with a Flash memory density equal or higher than 64 Kbytes.
6. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual,
UM0306, available from the STMicroelectronics website: www.st.com.
7. For the LQFP48 and LQFP64 packages, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset,
however the functionality of PD0 and PD1 can be remapped by software on these pins.
SS_3
DD_3
SV
SV
SS_3
DD_3
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