ST MICROELECTRONICS STM32F072VBT6 Datasheet
STM32F072x8 STM32F072xB
LQFP100 14x14 mm
LQFP64 10x10 mm
LQFP48 7x7 mm
UFQFPN48
7x7 mm
UFBGA100
7x7 mm
UFBGA64
5x5 mm
WLCSP49
3.3x3.1 mm
Arm®-based 32-bit MCU, up to 128 KB Flash, crystal-less USB
FS 2.0, CAN, 12 timers, ADC, DAC & comm. interfaces, 2.0 - 3.6 V
Datasheet - production data
Features
• Core: Arm® 32-bit Cortex®-M0 CPU, frequency
up to 48 MHz
• Memories
– 64 to 128 Kbytes of Flash memory
– 16 Kbytes of SRAM with HW parity
• CRC calculation unit
• Reset and power management
– Digital and I/O supply: V
– Analog supply: V
– Selected I/Os: V
DDA
DDIO2
– Power-on/Power down reset (POR/PDR)
– Programmable voltage detector (PVD)
– Low power modes: Sleep, Stop, Standby
–V
supply for RTC and backup registers
BAT
• Clock management
– 4 to 32 MHz crystal oscillator
– 32 kHz oscillator for RTC with calibration
– Internal 8 MHz RC with x6 PLL option
– Internal 40 kHz RC oscillator
– Internal 48 MHz oscillator with automatic
trimming based on ext. synchronization
• Up to 87 fast I/Os
– All mappable on external interrupt vectors
– Up to 68 I/Os with 5V tolerant capability
and 19 with independent supply V
• 7-channel DMA controller
• One 12-bit, 1.0 µs ADC (up to 16 channels)
– Conversion range: 0 to 3.6 V
– Separate analog supply: 2.4 V to 3.6 V
• One 12-bit D/A converter (with 2 channels)
• 2 fast low-power analog comparators with
programmable input and output
• Up to 24 capacitive sensing channels for
touchkey, linear and rotary touch sensors
= 2.0 V to 3.6 V
DD
= VDD to 3.6 V
= 1.65 V to 3.6 V
DDIO2
FBGA
• Calendar RTC with alarm and periodic wakeup
from Stop/Standby
• 12 timers
– One 16-bit advanced-control timer for
six-channel PWM output
– One 32-bit and seven 16-bit timers, with up
to four IC/OC, OCN, usable for IR control
decoding or DAC control
– Independent and system watchdog timers
– SysTick timer
• Communication interfaces
2
–2 I
C interfaces supporting Fast Mode Plus
(1 Mbit/s) with 20 mA current sink, one
supporting SMBus/PMBus and wakeup
– 4 USARTs supporting master synchronous
SPI and modem control, two with ISO7816
interface, LIN, IrDA, auto baud rate
detection and wakeup feature
– 2 SPIs (18 Mbit/s) with 4 to 16
programmable bit frames, and with I
2
S
interface multiplexed
– CAN interface
– USB 2.0 full-speed interface, able to run
from internal 48 MHz oscillator and with
BCD and LPM support
• HDMI CEC wakeup on header reception
• Serial wire debug (SWD)
• 96-bit unique ID
• All packages ECOPACK
Reference Part number
STM32F072x8
STM32F072xB
Table 1. Device summary
STM32F072C8, STM32F072R8, STM32F072V8,
STM32F072CB, STM32F072RB, STM32F072VB
®
2
September 2019 DS9826 Rev 6 1/128
This is information on a product in full production.
www.st.com
Contents STM32F072x8 STM32F072xB
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 Arm®-Cortex®-M0 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 14
3.5 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5.2 Power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.6 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.7 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.8 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.9 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.9.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 17
3.9.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 18
3.10 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.10.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.10.2 Internal voltage reference (V
3.10.3 V
battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
BAT
) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
REFINT
3.11 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.12 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.13 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.14 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.14.2 General-purpose timers (TIM2, 3, 14, 15, 16, 17) . . . . . . . . . . . . . . . . . 22
3.14.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.14.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.14.5 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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STM32F072x8 STM32F072xB Contents
3.14.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.15 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 23
3.16 Inter-integrated circuit interface (I
2
C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.17 Universal synchronous/asynchronous receiver/transmitter (USART) . . . 25
3.18 Serial peripheral interface (SPI) / Inter-integrated sound interface (I
2
S) . 26
3.19 High-definition multimedia interface (HDMI) - consumer
electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.20 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.21 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.22 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.23 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5 Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 54
6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 54
6.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.3.6 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
DS9826 Rev 6 3/128
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Contents STM32F072x8 STM32F072xB
6.3.10 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.3.16 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.3.17 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.3.18 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.3.19 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.3.20 V
6.3.21 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.3.22 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
BAT
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.1 UFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.2 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7.3 UFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
7.4 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
7.5 WLCSP49 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
7.6 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
7.7 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
7.8 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
7.8.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
7.8.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 121
8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4/128 DS9826 Rev 6
STM32F072x8 STM32F072xB List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. STM32F072x8/xB family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . 11
Table 3. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 4. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 5. Capacitive sensing GPIOs available on STM32F072x8/xB devices. . . . . . . . . . . . . . . . . . 20
Table 6. Number of capacitive sensing channels available
on STM32F072x8/xB devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 8. Comparison of I
Table 9. STM32F072x8/xB I
Table 10. STM32F072x8/xB USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 11. STM32F072x8/xB SPI/I
Table 12. Peripheral register boundary addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 13. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 14. STM32F072x8/xB pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 15. Alternate functions selected through GPIOA_AFR registers for port A . . . . . . . . . . . . . . . 44
Table 16. Alternate functions selected through GPIOB_AFR registers for port B . . . . . . . . . . . . . . . 45
Table 17. Alternate functions selected through GPIOC_AFR registers for port C . . . . . . . . . . . . . . . 46
Table 18. Alternate functions selected through GPIOD_AFR registers for port D . . . . . . . . . . . . . . . 46
Table 19. Alternate functions selected through GPIOE_AFR registers for port E . . . . . . . . . . . . . . . 47
Table 20. Alternate functions available on port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 21. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 22. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 23. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 24. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 25. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 26. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 27. Programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 28. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 29. Typical and maximum current consumption from V
Table 30. Typical and maximum current consumption from the V
Table 31. Typical and maximum consumption in Stop and Standby modes . . . . . . . . . . . . . . . . . . . 59
Table 32. Typical and maximum current consumption from the V
Table 33. Typical current consumption, code executing from Flash memory,
running from HSE 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 34. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 35. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 36. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 37. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 38. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 39. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 40. LSE oscillator characteristics (f
Table 41. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 42. HSI14 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 43. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 44. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 45. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 46. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
2
C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2
C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2
S implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
supply at VDD = 3.6 V . . . . . . . . . . 56
DD
= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
LSE
supply . . . . . . . . . . . . . . . . . 58
DDA
supply. . . . . . . . . . . . . . . . . . . 60
BAT
DS9826 Rev 6 5/128
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List of tables STM32F072x8 STM32F072xB
Table 47. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 48. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 49. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 50. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 51. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 52. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 53. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 54. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 55. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 56. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 57. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 58. R
max for f
AIN
= 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
ADC
Table 59. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 60. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 61. Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 62. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 63. V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
BAT
Table 64. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 65. IWDG min/max timeout period at 40 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 66. WWDG min/max timeout value at 48 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 67. I
Table 68. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 69. I
2
C analog filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
2
S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 70. USB electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 71. UFBGA100 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 72. UFBGA100 recommended PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 73. LQPF100 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 74. UFBGA64 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 75. UFBGA64 recommended PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 76. LQFP64 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 77. WLCSP49 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 78. LQFP48 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 79. UFQFPN48 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 80. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 81. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
6/128 DS9826 Rev 6
STM32F072x8 STM32F072xB List of figures
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 3. STM32F072xB memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 4. UFBGA100 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 5. LQFP100 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 6. UFBGA64 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 7. LQFP64 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 8. LQFP48 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 9. UFQFPN48 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 10. WLCSP49 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 11. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 12. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 13. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 14. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 15. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 16. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 17. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 18. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 19. HSI oscillator accuracy characterization results for soldered parts . . . . . . . . . . . . . . . . . . 71
Figure 20. HSI14 oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 21. HSI48 oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 22. TC and TTa I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 23. Five volt tolerant (FT and FTf) I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 24. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 25. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 26. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 27. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 28. 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 29. Maximum V
Figure 30. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 31. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 32. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 33. I
Figure 34. I
2
S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
2
S master timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 35. UFBGA100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 36. Recommended footprint for UFBGA100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 37. UFBGA100 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 38. LQFP100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 39. Recommended footprint for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 40. LQFP100 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 41. UFBGA64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 42. Recommended footprint for UFBGA64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 43. UFBGA64 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 44. LQFP64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 45. Recommended footprint for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 46. LQFP64 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 47. WLCSP49 package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 48. WLCSP49 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
scaler startup time from power down . . . . . . . . . . . . . . . . . . . . . . . . . . 91
REFINT
DS9826 Rev 6 7/128
8
List of figures STM32F072x8 STM32F072xB
Figure 49. LQFP48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 50. Recommended footprint for LQFP48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 51. LQFP48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 52. UFQFPN48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 53. Recommended footprint for UFQFPN48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 54. UFQFPN48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 55. LQFP64 P
max versus TA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
D
8/128 DS9826 Rev 6
STM32F072x8 STM32F072xB Introduction
1 Introduction
This datasheet provides characteristics and ordering information of the STM32F072x8/xB
microcontrollers.
This document should be read in conjunction with the STM32F0xxxx reference manual
(RM0091). The reference manual is available from the STMicroelectronics website
www.st.com.
For information on the Arm
Technical Reference Manual, available from the www.arm.com website.
®(a)
Cortex®-M0 core, please refer to the Arm® Cortex®-M0
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
DS9826 Rev 6 9/128
27
Description STM32F072x8 STM32F072xB
2 Description
The STM32F072x8/xB microcontrollers incorporate the high-performance
Arm®Cortex®-M0 32-bit RISC core operating at up to 48 MHz frequency, high-speed
embedded memories (up to 128
extensive range of enhanced peripherals and I/Os. All devices offer standard
communication interfaces (two I
USB Full-speed device (crystal-less), one CAN, one 12-bit ADC, one 12-bit DAC with two
channels, seven 16-bit timers, one 32-bit timer and an advanced-control PWM timer.
The STM32F072x8/xB microcontrollers operate in the -40 to +85 °C and -40 to +105 °C
temperature ranges, from a 2.0 to 3.6 V power supply. A comprehensive set of
power-saving modes allows the design of low-power applications.
The STM32F072x8/xB microcontrollers include devices in seven different packages ranging
from 48 pins to 100 pins with a die form also available upon request. Depending on the
device chosen, different sets of peripherals are included.
These features make the STM32F072x8/xB microcontrollers suitable for a wide range of
applications such as application control and user interfaces, hand-held equipment, A/V
receivers and digital TV, PC peripherals, gaming and GPS platforms, industrial applications,
PLCs, inverters, printers, scanners, alarm systems, video intercoms and HVACs.
Kbytes of Flash memory and 16 Kbytes of SRAM), and an
2
Cs, two SPI/I2S, one HDMI CEC and four USARTs), one
10/128 DS9826 Rev 6
STM32F072x8 STM32F072xB Description
Table 2. STM32F072x8/xB family device features and peripheral counts
Peripheral STM32F072Cx STM32F072Rx STM32F072Vx
Flash memory (Kbyte) 64 128 64 128 64 128
SRAM (Kbyte) 16
Timers
Advanced
control
General
purpose
Basic 2 (16-bit)
2S](1)
SPI [I
2
C2
I
1 (16-bit)
5 (16-bit)
1 (32-bit)
2 [2]
Comm.
interfaces
USART 4
CAN 1
USB 1
CEC 1
12-bit ADC
(number of channels)
1
(10 ext. + 3 int.)
12-bit DAC
(number of channels)
Analog comparator 2
GPIOs 37 51 87
Capacitive sensing
channels
17 18 24
Max. CPU frequency 48 MHz
Operating voltage 2.0 to 3.6 V
Operating temperature
Packages
1. The SPI interface can be used either in SPI mode or in I2S audio mode.
Ambient operating temperature: -40°C to 85°C / -40°C to 105°C
Junction temperature: -40°C to 105°C / -40°C to 125°C
LQFP48
UFQFPN48
WLCSP49
LQFP64
UFBGA64
1
(16 ext. + 3 int.)
1
(2)
LQFP100
UFBGA100
DS9826 Rev 6 11/128
27
Description STM32F072x8 STM32F072xB
MSv31404V4
Power domain of analog blocks :
V
BAT
V
DDIO2
4 channels
3 compl. channels
BRK, ETR input as AF
@ V
DD
@ V
DDA
System and peripheral
clocks
PA[15:0]
PB[15:0]
PC[15:0]
PF[10:9], PF6
PF[3:0]
8 groups of
4 channels
SYNC
87 AF
MOSI/SD
MISO/MCK
SCK/CK
NSS/WS as AF
@ V
DDA
V
DDA
V
SSA
SWCLK
SWDIO
as AF
16x
AD input
OSC_IN
OSC_OUT
V
BAT
= 1.65 to 3.6 V
OSC32_IN
OSC32_OUT
3 TAMPER-RTC
(ALARM OUT)
@ V
BAT
SYNC
MOSI/SD
MISO/MCK
SCK/CK
NSS/WS as AF
HSI14
HSI
LSI
HSI48
PLLCLK
V
DD
IR_OUT as AF
1 channel
1 compl, BRK as AF
1 channel
1 compl, BRK as AF
1 channel as AF
4 ch., ETR as AF
4 ch., ETR as AF
GP DMA
7 channels
CORTEX-M0 CPU
f
MAX
= 48 MHz
Serial Wire
Debug
NVIC
Touch
Sensing
Controller
PAD
Analog
switches
EXT. IT WKUP
SPI1/I2S1
SPI2/I2S2
SYSCFG IF
DBGMCU
Window WDG
APB
AHB
CRC
RESET & CLOCK
CONTROL
Power
Controller
XTAL OSC
4-32 MHz
Ind. Window WDG
SRAM
16 KB
Temp.
sensor
IF
12-bit ADC
RTC
Backup
reg
RTC interface
CRS
RC 14 MHz
RC 8 MHz
RC 40 kHz
PLL
RC 48MHz
AHB decoder
XTAL32 kHz
SRAM
controller
Bus matrix
Flash
memory
interface
Flash GPL
up to 128 KB
32-bit
Obl
V
DD
2 channels
1 compl, BRK as AF
RX, TX,CTS, RTS,
CK as AF
RX, TX,CTS, RTS,
CK as AF
RX, TX,CTS, RTS,
CK as AF
RX, TX,CTS, RTS,
CK as AF
SCL, SDA
(20 mA FM+) as AF
SCL, SDA, SMBA
(20 mA FM+) as AF
CEC as AF
I2C1
I2C2
12-bit DAC
12-bit DAC
IF
DAC_OUT1
DAC_OUT2
@ V
DDA
TIMER 6
TIMER 7
GP comparator 1
GP comparator 2
INPUT +
INPUT -
OUTPUT
as AF
@ V
DDA
GPIO port F
GPIO port E
GPIO port D
GPIO port C
GPIO port B
GPIO port A
PD[15:0]
PE[15:0]
V
DDA
SUPPLY
SUPERVISION
POWER
@ V
DDA
@ V
DD
V
DD18
POR
Reset
Int
V
DD
= 2 to 3.6 V
V
SS
NRST
V
DDA
V
SSA
V
DDIO2
OKIN
V
DD
PVD
POR/PDR
VOLT.REG
3.3 V to 1.8 V
USART4
USART3
USART2
USART1
HDMI-CEC
TIMER 17
TIMER 16
TIMER 15
TIMER 14
TIMER 3
TIMER 2 32-bit
PWM TIMER 1
TX, RX as AF
D+, D-
@ V
DDIO2
BxCAN
USB
PHY
USB
SRAM 768B
SRAM 256B
Figure 1. Block diagram
12/128 DS9826 Rev 6
STM32F072x8 STM32F072xB Functional overview
3 Functional overview
Figure 1 shows the general block diagram of the STM32F072x8/xB devices.
3.1 Arm®-Cortex®-M0 core
The Arm® Cortex®-M0 is a generation of Arm 32-bit RISC processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The Arm® Cortex®-M0 processors feature exceptional code-efficiency, delivering the high
performance expected from an Arm core, with memory sizes usually associated with 8- and
16-bit devices.
The STM32F072x8/xB devices embed Arm core and are compatible with all Arm tools and
software.
3.2 Memories
The device has the following features:
• 16 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states and featuring embedded parity checking with exception generation for fail-critical
applications.
• The non-volatile memory is divided into two arrays:
– 64 to 128 Kbytes of embedded Flash memory for programs and data
– Option bytes
The option bytes are used to write-protect the memory (with 4 KB granularity) and/or
readout-protect the whole memory with the following options:
– Level 0: no readout protection
– Level 1: memory readout protection, the Flash memory cannot be read from or
written to if either debug features are connected or boot in RAM is selected
– Level 2: chip readout protection, debug features (Arm
and boot in RAM selection disabled
3.3 Boot modes
At startup, the boot pin and boot selector option bit are used to select one of the three boot
options:
• boot from User Flash memory
• boot from System Memory
• boot from embedded SRAM
®
Cortex®-M0 serial wire)
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART on pins PA14/PA15, or PA9/PA10 or I
DFU interface.
DS9826 Rev 6 13/128
2
C on pins PB6/PB7 or through the USB
27
Functional overview STM32F072x8 STM32F072xB
3.4 Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
3.5 Power management
3.5.1 Power supply schemes
• VDD = V
= 2.0 to 3.6 V: external power supply for I/Os (V
DDIO1
regulator. It is provided externally through VDD pins.
• V
= from VDD to 3.6 V: external analog power supply for ADC, DAC, Reset blocks,
DDA
RCs and PLL (minimum voltage to be applied to V
are used). It is provided externally through VDDA pin. The V
always greater or equal to the V
• V
= 1.65 to 3.6 V: external power supply for marked I/Os. V
DDIO2
externally through the VDDIO2 pin. The V
from V
V
DDIO2
(V
REFINT
DD
or V
, but it must not be provided without a valid supply on VDD. The
DDA
supply is monitored and compared with the internal reference voltage
). When the V
DDIO2
are disabled by hardware. The output of this comparator is connected to EXTI line 31
and it can be used to generate an interrupt. Refer to the pinout diagrams or tables for
concerned I/Os list.
• V
= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
BAT
backup registers (through power switch) when V
For more details on how to connect power pins, refer to Figure 13: Power supply scheme.
3.5.2 Power supply supervisors
The device has integrated power-on reset (POR) and power-down reset (PDR) circuits.
They are always active, and ensure proper operation above a threshold of 2 V. The device
remains in reset mode when the monitored supply voltage is below a specified threshold,
V
POR/PDR
• The POR monitors only the VDD supply voltage. During the startup phase it is required
• The PDR monitors both the V
The device features an embedded programmable voltage detector (PVD) that monitors the
V
DD
when V
, without the need for an external reset circuit.
that V
should arrive first and be greater than or equal to VDD.
DDA
supply supervisor can be disabled (by programming a dedicated Option bit) to reduce
the power consumption if the application design ensures that V
equal to V
DD
.
power supply and compares it to the V
drops below the V
DD
PVD
) and the internal
DDIO1
is 2.4 V when the ADC or DAC
DDA
voltage level and must be established first.
DD
voltage level is completely independent
DDIO2
voltage level must be
DDA
is provided
DDIO2
is below this threshold, all the I/Os supplied from this rail
is not present.
DD
and V
DD
threshold and/or when VDD is higher than the V
supply voltages, however the V
DDA
is higher than or
DDA
threshold. An interrupt can be generated
PVD
DDA
power
PVD
14/128 DS9826 Rev 6
STM32F072x8 STM32F072xB Functional overview
threshold. The interrupt service routine can then generate a warning message and/or put
the MCU into a safe state. The PVD is enabled by software.
3.5.3 Voltage regulator
The regulator has two operating modes and it is always enabled after reset.
• Main (MR) is used in normal operating mode (Run).
• Low power (LPR) can be used in Stop mode where the power demand is reduced.
In Standby mode, it is put in power down mode. In this mode, the regulator output is in high
impedance and the kernel circuitry is powered down, inducing zero consumption (but the
contents of the registers and SRAM are lost).
3.5.4 Low-power modes
The STM32F072x8/xB microcontrollers support three low-power modes to achieve the best
compromise between low power consumption, short startup time and available wakeup
sources:
• Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
• Stop mode
Stop mode achieves very low power consumption while retaining the content of SRAM
and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the
HSE crystal oscillators are disabled. The voltage regulator can also be put either in
normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI lines. The EXTI line
source can be one of the 16 external lines, the PVD output, RTC, I2C1, USART1,
USART2, USB, COMPx, V
The CEC, USART1, USART2 and I2C1 peripherals can be configured to enable the
HSI RC oscillator so as to get clock for processing incoming data. If this is used when
the voltage regulator is put in low power mode, the regulator is first switched to normal
mode before the clock is provided to the given peripheral.
• Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the RTC
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a
rising edge on the WKUP pins, or an RTC event occurs.
supply comparator or the CEC.
DDIO2
Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
3.6 Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
DS9826 Rev 6 15/128
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Functional overview STM32F072x8 STM32F072xB
MSv31418V2
OSC_IN
OSC_OUT
OSC32_IN
OSC32_OUT
IWDG
PLLMUL
MCO
Main clock
output
PLLCLK
HSI
HSE
PLLCLK
ADC
asynchronous
clock input
LSE
LSI
HSI
HSE
RTC
PLLSRC
SW
MCO
RTCCLK
RTCSEL
SYSCLK
TIM1,2,3,6,7,
14,15,16,17
FLITFCLK
Flash memory
programming
interface
HSI14
HSI14
LSE
I2C1
USART1
LSE
HSI
SYSCLK
PCLK
SYSCLK
HSI
PCLK
I2S1/SPI1
I2S2/SPI2
CEC
APB
peripherals
LSI
LSE
PREDIV
HSI48
PLLNODIV
MCOPRE
TIM14
LSE
HSE
SYNC
CSS
Trim
Legend
white
clock tree control element
clock line
control line
black
clock tree element
/32
4-32 MHz
HSE OSC
/1,/2,/4,
/8,/16
/1,/2
14 MHz RC
HSI14
/1,/2,…
…/512
8 MHz
HSI RC
/1,/2,..
../16
32.768 kHz
LSE OSC
40 kHz
LSI RC
PLL
x2,x3,..
...x16
48 MHz
HSI RC
x1, x2
/1,/2,/4,..
../128
USARTxSW
PPRE
PPREHPRE
CECSW
/244
I2C1SW
SYSCLK
CRS
HSI
HSI48
HSI48
HSI48
HSI
SYNCSRC
USART2
HCLK
AHB, core, memory, DMA,
Cortex FCLK free-run clock
Cortex
system timer
/8
USB
HSI48
USBSW
LSE
USB SOF
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Figure 2. Clock tree
16/128 DS9826 Rev 6
Several prescalers allow the application to configure the frequency of the AHB and the APB
domains. The maximum frequency of the AHB and the APB domains is 48 MHz.
STM32F072x8 STM32F072xB Functional overview
Additionally, also the internal RC 48 MHz oscillator can be selected for system clock or PLL
input source. This oscillator can be automatically fine-trimmed by the means of the CRS
peripheral using the external synchronization.
3.7 General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions.
The I/O configuration can be locked if needed following a specific sequence in order to
avoid spurious writing to the I/Os registers.
3.8 Direct memory access controller (DMA)
The 7-channel general-purpose DMAs manage memory-to-memory, peripheral-to-memory
and memory-to-peripheral transfers.
The DMA supports circular buffer management, removing the need for user code
intervention when the controller reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
DMA can be used with the main peripherals: SPIx, I2Sx, I2Cx, USARTx, all TIMx timers
(except TIM14), DAC and ADC.
3.9 Interrupts and events
3.9.1 Nested vectored interrupt controller (NVIC)
The STM32F0xx family embeds a nested vectored interrupt controller able to handle up to
32 maskable interrupt channels (not including the 16 interrupt lines of Cortex
priority levels.
• Closely coupled NVIC gives low latency interrupt processing
• Interrupt entry vector table address passed directly to the core
• Closely coupled NVIC core interface
• Allows early processing of interrupts
• Processing of late arriving higher priority interrupts
• Support for tail-chaining
• Processor state automatically saved
• Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
®
-M0) and 4
DS9826 Rev 6 17/128
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Functional overview STM32F072x8 STM32F072xB
3.9.2 Extended interrupt/event controller (EXTI)
The extended interrupt/event controller consists of 32 edge detector lines used to generate
interrupt/event requests and wake-up the system. Each line can be independently
configured to select the trigger event (rising edge, falling edge, both) and can be masked
independently. A pending register maintains the status of the interrupt requests. The EXTI
can detect an external line with a pulse width shorter than the internal clock period. Up to 87
GPIOs can be connected to the 16 external interrupt lines.
3.10 Analog-to-digital converter (ADC)
The 12-bit analog-to-digital converter has up to 16 external and 3 internal (temperature
sensor, voltage reference, VBAT voltage measurement) channels and performs conversions
in single-shot or scan modes. In scan mode, automatic conversion is performed on a
selected group of analog inputs.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
3.10.1 Temperature sensor
The temperature sensor (TS) generates a voltage V
temperature.
The temperature sensor is internally connected to the ADC_IN16 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
Calibration value name Description Memory address
TS_CAL1
TS_CAL2
Table 3. Temperature sensor calibration values
SENSE
TS ADC raw data acquired at a
temperature of 30 °C (± 5 °C),
V
= 3.3 V (± 10 mV)
DDA
TS ADC raw data acquired at a
temperature of 110 °C (± 5 °C),
V
= 3.3 V (± 10 mV)
DDA
that varies linearly with
0x1FFF F7B8 - 0x1FFF F7B9
0x1FFF F7C2 - 0x1FFF F7C3
3.10.2 Internal voltage reference (V
The internal voltage reference (V
ADC and comparators. V
18/128 DS9826 Rev 6
REFINT
REFINT
) provides a stable (bandgap) voltage output for the
REFINT
is internally connected to the ADC_IN17 input channel. The
)
STM32F072x8 STM32F072xB Functional overview
precise voltage of V
is individually measured for each part by ST during production
REFINT
test and stored in the system memory area. It is accessible in read-only mode.
3.10.3 V
Calibration value name Description Memory address
VREFINT_CAL
battery voltage monitoring
BAT
Table 4. Internal voltage reference calibration values
Raw data acquired at a
temperature of 30 °C (± 5 °C),
V
= 3.3 V (± 10 mV)
DDA
This embedded hardware feature allows the application to measure the V
using the internal ADC channel ADC_IN18. As the V
and thus outside the ADC input range, the V
pin is internally connected to a bridge
BAT
divider by 2. As a consequence, the converted digital value is half the V
3.11 Digital-to-analog converter (DAC)
The two 12-bit buffered DAC channels can be used to convert digital signals into analog
voltage signal outputs. The chosen design structure is composed of integrated resistor
strings and an amplifier in non-inverting configuration.
This digital Interface supports the following features:
• 8-bit or 12-bit monotonic output
• Left or right data alignment in 12-bit mode
• Synchronized update capability
• Noise-wave generation
• Triangular-wave generation
• Dual DAC channel independent or simultaneous conversions
• DMA capability for each channel
• External triggers for conversion
0x1FFF F7BA - 0x1FFF F7BB
battery voltage
voltage may be higher than V
BAT
BAT
voltage.
BAT
DDA
,
Six DAC trigger inputs are used in the device. The DAC is triggered through the timer trigger
outputs and the DAC interface is generating its own DMA requests.
3.12 Comparators (COMP)
The device embeds two fast rail-to-rail low-power comparators with programmable
reference voltage (internal or external), hysteresis and speed (low speed for low power) and
with selectable output polarity.
The reference voltage can be one of the following:
• External I/O
• DAC output pins
• Internal reference voltage or submultiple (1/4, 1/2, 3/4).Refer to Table 28: Embedded
internal reference voltage for the value and precision of the internal reference voltage.
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Functional overview STM32F072x8 STM32F072xB
Both comparators can wake up from STOP mode, generate interrupts and breaks for the
timers and can be also combined into a window comparator.
3.13 Touch sensing controller (TSC)
The STM32F072x8/xB devices provide a simple solution for adding capacitive sensing
functionality to any application. These devices offer up to 24 capacitive sensing channels
distributed over 8 analog I/O groups.
Capacitive sensing technology is able to detect the presence of a finger near a sensor which
is protected from direct touch by a dielectric (glass, plastic...). The capacitive variation
introduced by the finger (or any conductive object) is measured using a proven
implementation based on a surface charge transfer acquisition principle. It consists in
charging the sensor capacitance and then transferring a part of the accumulated charges
into a sampling capacitor until the voltage across this capacitor has reached a specific
threshold. To limit the CPU bandwidth usage, this acquisition is directly managed by the
hardware touch sensing controller and only requires few external components to operate.
For operation, one capacitive sensing GPIO in each group is connected to an external
capacitor and cannot be used as effective touch sensing channel.
The touch sensing controller is fully supported by the STMTouch touch sensing firmware
library, which is free to use and allows touch sensing functionality to be implemented reliably
in the end application.
Table 5. Capacitive sensing GPIOs available on STM32F072x8/xB devices
Group
1
2
3
4
Capacitive sensing
signal name
TSC_G1_IO1 PA0
TSC_G1_IO2 PA1 TSC_G5_IO2 PB4
TSC_G1_IO3 PA2 TSC_G5_IO3 PB6
TSC_G1_IO4 PA3 TSC_G5_IO4 PB7
TSC_G2_IO1 PA4
TSC_G2_IO2 PA5 TSC_G6_IO2 PB12
TSC_G2_IO3 PA6 TSC_G6_IO3 PB13
TSC_G2_IO4 PA7 TSC_G6_IO4 PB14
TSC_G3_IO1 PC5
TSC_G3_IO2 PB0 TSC_G7_IO2 PE3
TSC_G3_IO3 PB1 TSC_G7_IO3 PE4
TSC_G3_IO4 PB2 TSC_G7_IO4 PE5
TSC_G4_IO1 PA9
TSC_G4_IO2 PA10 TSC_G8_IO2 PD13
TSC_G4_IO3 PA11 TSC_G8_IO3 PD14
TSC_G4_IO4 PA12 TSC_G8_IO4 PD15
Pin
name
Group
5
6
7
8
Capacitive sensing
signal name
TSC_G5_IO1 PB3
TSC_G6_IO1 PB11
TSC_G7_IO1 PE2
TSC_G8_IO1 PD12
Pin
name
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STM32F072x8 STM32F072xB Functional overview
Table 6. Number of capacitive sensing channels available
on STM32F072x8/xB devices
Analog I/O group
STM32F072Vx STM32F072Rx STM32F072Cx
G1 3 3 3
G2 3 3 3
G3 3 3 2
G4 3 3 3
G5 3 3 3
G6 3 3 3
G7 3 0 0
G8 3 0 0
Number of capacitive
sensing channels
3.14 Timers and watchdogs
The STM32F072x8/xB devices include up to six general-purpose timers, two basic timers
and an advanced control timer.
Number of capacitive sensing channels
24 18 17
Timer
type
Advanced
control
General
purpose
Basic
Tab le 7 compares the features of the different timers.
Timer
Counter
resolution
TIM1 16-bit
TIM2 32-bit
TIM3 16-bit
TIM14 16-bit Up
TIM15 16-bit Up
TIM16
TIM17
TIM6
TIM7
16-bit Up
16-bit Up
Table 7. Timer feature comparison
Counter
type
Up, down,
up/down
Up, down,
up/down
Up, down,
up/down
Prescaler
factor
integer from
1 to 65536
integer from
1 to 65536
integer from
1 to 65536
integer from
1 to 65536
integer from
1 to 65536
integer from
1 to 65536
integer from
1 to 65536
DMA
request
generation
Yes 4 3
Yes 4 -
Yes 4 -
No 1 -
Yes 2 1
Yes 1 1
Yes - -
Capture/compare
channels
Complementary
outputs
DS9826 Rev 6 21/128
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Functional overview STM32F072x8 STM32F072xB
3.14.1 Advanced-control timer (TIM1)
The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on six
channels. It has complementary PWM outputs with programmable inserted dead times. It
can also be seen as a complete general-purpose timer. The four independent channels can
be used for:
• input capture
• output compare
• PWM generation (edge or center-aligned modes)
• one-pulse mode output
If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If
configured as the 16-bit PWM generator, it has full modulation capability (0-100%).
The counter can be frozen in debug mode.
Many features are shared with those of the standard timers which have the same
architecture. The advanced control timer can therefore work together with the other timers
via the Timer Link feature for synchronization or event chaining.
3.14.2 General-purpose timers (TIM2, 3, 14, 15, 16, 17)
There are six synchronizable general-purpose timers embedded in the STM32F072x8/xB
devices (see
PWM outputs, or as simple time base.
Tabl e 7 for differences). Each general-purpose timer can be used to generate
TIM2, TIM3
STM32F072x8/xB devices feature two synchronizable 4-channel general-purpose timers.
TIM2 is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TIM3 is based
on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. They feature 4 independent
channels each for input capture/output compare, PWM or one-pulse mode output. This
gives up to 12 input captures/output compares/PWMs on the largest packages.
The TIM2 and TIM3 general-purpose timers can work together or with the TIM1 advancedcontrol timer via the Timer Link feature for synchronization or event chaining.
TIM2 and TIM3 both have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
Their counters can be frozen in debug mode.
TIM14
This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM14 features one single channel for input capture/output compare, PWM or one-pulse
mode output.
Its counter can be frozen in debug mode.
TIM15, TIM16 and TIM17
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
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STM32F072x8 STM32F072xB Functional overview
TIM15 has two independent channels, whereas TIM16 and TIM17 feature one single
channel for input capture/output compare, PWM or one-pulse mode output.
The TIM15, TIM16 and TIM17 timers can work together, and TIM15 can also operate
withTIM1 via the Timer Link feature for synchronization or event chaining.
TIM15 can be synchronized with TIM16 and TIM17.
TIM15, TIM16 and TIM17 have a complementary output with dead-time generation and
independent DMA request generation.
Their counters can be frozen in debug mode.
3.14.3 Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger generation. They can also be used as generic
16-bit time bases.
3.14.4 Independent watchdog (IWDG)
The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with
user-defined refresh window. It is clocked from an independent 40 kHz internal RC and as it
operates independently from the main clock, it can operate in Stop and Standby modes. It
can be used either as a watchdog to reset the device when a problem occurs, or as a free
running timer for application timeout management. It is hardware or software configurable
through the option bytes. The counter can be frozen in debug mode.
3.14.5 System window watchdog (WWDG)
The system window watchdog is based on a 7-bit downcounter that can be set as free
running. It can be used as a watchdog to reset the device when a problem occurs. It is
clocked from the APB clock (PCLK). It has an early warning interrupt capability and the
counter can be frozen in debug mode.
3.14.6 SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
• a 24-bit down counter
• autoreload capability
• maskable system interrupt generation when the counter reaches 0
• programmable clock source (HCLK or HCLK/8)
3.15 Real-time clock (RTC) and backup registers
The RTC and the five backup registers are supplied through a switch that takes power either
on V
registers used to store 20 bytes of user application data when V
They are not reset by a system or power reset, or at wake up from Standby mode.
supply when present or through the V
DD
pin. The backup registers are five 32-bit
BAT
power is not present.
DD
DS9826 Rev 6 23/128
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Functional overview STM32F072x8 STM32F072xB
The RTC is an independent BCD timer/counter. Its main features are the following:
• calendar with subseconds, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format
• automatic correction for 28, 29 (leap year), 30, and 31 day of the month
• programmable alarm with wake up from Stop and Standby mode capability
• Periodic wakeup unit with programmable resolution and period.
• on-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize the RTC with a master clock
• digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal
inaccuracy
• Three anti-tamper detection pins with programmable filter. The MCU can be woken up
from Stop and Standby modes on tamper event detection
• timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be
woken up from Stop and Standby modes on timestamp event detection
• reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision
The RTC clock sources can be:
• a 32.768 kHz external crystal
• a resonator or oscillator
• the internal low-power RC oscillator (typical frequency of 40 kHz)
• the high-speed external clock divided by 32
3.16 Inter-integrated circuit interface (I2C)
Up to two I2C interfaces (I2C1 and I2C2) can operate in multimaster or slave modes. Both
can support Standard mode (up to 100 kbit/s), Fast mode (up to 400 kbit/s) and Fast Mode
Plus (up to 1 Mbit/s) with 20
Both support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (two
addresses, one with configurable mask). They also include programmable analog and
digital noise filters.
Aspect Analog filter Digital filter
Pulse width of
suppressed spikes
Benefits Available in Stop mode
Drawbacks
Table 8. Comparison of I2C analog and digital filters
In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP
capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts
mA output drive on most of the associated I/Os.
50 ns
Variations depending on
temperature, voltage, process
Programmable length from 1 to 15
I2Cx peripheral clocks
–Extra filtering capability vs.
standard requirements
–Stable length
Wakeup from Stop on address
match is not available when digital
filter is enabled.
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STM32F072x8 STM32F072xB Functional overview
verifications and ALERT protocol management. I2C1 also has a clock domain independent
from the CPU clock, allowing the I2C1 to wake up the MCU from Stop mode on address
match.
The I2C peripherals can be served by the DMA controller.
Refer to Tab le 9 for the differences between I2C1 and I2C2.
Table 9. STM32F072x8/xB I2C implementation
I2C features
7-bit addressing mode X X
10-bit addressing mode X X
Standard mode (up to 100 kbit/s) X X
Fast mode (up to 400 kbit/s) X X
Fast Mode Plus (up to 1 Mbit/s) with 20 mA output drive I/Os X X
Independent clock X -
SMBus X -
Wakeup from STOP X -
1. X = supported.
(1)
I2C1 I2C2
3.17 Universal synchronous/asynchronous receiver/transmitter (USART)
The device embeds four universal synchronous/asynchronous receivers/transmitters
(USART1, USART2, USART3, USART4) which communicate at speeds of up to 6
They provide hardware management of the CTS, RTS and RS485 DE signals,
multiprocessor communication mode, master synchronous communication and single-wire
half-duplex communication mode. USART1 and USART2 support also SmartCard
communication (ISO 7816), IrDA SIR ENDEC, LIN Master/Slave capability and auto baud
rate feature, and have a clock domain independent of the CPU clock, allowing to wake up
the MCU from Stop mode.
The USART interfaces can be served by the DMA controller.
Table 10. STM32F072x8/xB USART implementation
USART modes/features
Hardware flow control for modem X X
Continuous communication using DMA X X
Multiprocessor communication X X
Synchronous mode X X
Smartcard mode X -
Single-wire half-duplex communication X X
(1)
USART1 and
USART2
Mbit/s.
USART3 and
USART4
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Functional overview STM32F072x8 STM32F072xB
Table 10. STM32F072x8/xB USART implementation (continued)
USART modes/features
IrDA SIR ENDEC block X -
LIN mode X -
Dual clock domain and wakeup from Stop mode X -
Receiver timeout interrupt X -
Modbus communication X -
Auto baud rate detection X -
Driver Enable X X
1. X = supported.
(1)
USART1 and
USART2
USART3 and
USART4
3.18 Serial peripheral interface (SPI) / Inter-integrated sound
interface (I
Two SPIs are able to communicate up to 18 Mbit/s in slave and master modes in full-duplex
and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame size is configurable from 4 bits to 16 bits.
Two standard I2S interfaces (multiplexed with SPI1 and SPI2 respectively) supporting four
different audio standards can operate as master or slave at half-duplex communication
mode. They can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data
resolution and synchronized by a specific signal. Audio sampling frequency from 8 kHz up to
192 kHz can be set by an 8-bit programmable linear prescaler. When operating in master
mode, they can output a clock for an external audio component at 256 times the sampling
frequency.
2
S)
Table 11. STM32F072x8/xB SPI/I2S implementation
SPI features
(1)
SPI1 and SPI2
Hardware CRC calculation X
Rx/Tx FIFO X
NSS pulse mode X
2
S mode X
I
TI mode X
1. X = supported.
3.19 High-definition multimedia interface (HDMI) - consumer electronics control (CEC)
The device embeds a HDMI-CEC controller that provides hardware support for the
Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
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STM32F072x8 STM32F072xB Functional overview
overhead. It has a clock domain independent from the CPU clock, allowing the HDMI_CEC
controller to wakeup the MCU from Stop mode on data reception.
3.20 Controller area network (CAN)
The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It
can receive and transmit standard frames with 11-bit identifiers as well as extended frames
with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and
14 scalable filter banks.
3.21 Universal serial bus (USB)
The STM32F072x8/xB embeds a full-speed USB device peripheral compliant with the USB
specification version 2.0. The internal USB PHY supports USB FS signaling, embedded DP
pull-up and also battery charging detection according to Battery Charging Specification
Revision 1.2. The USB interface implements a full-speed (12 Mbit/s) function interface with
added support for USB 2.0 Link Power Management. It has software-configurable endpoint
setting with packet memory up-to 1 KB (the last 256 byte are used for CAN peripheral if
enabled) and suspend/resume support. It requires a precise 48 MHz clock which can be
generated from the internal main PLL (the clock source must use an HSE crystal oscillator)
or by the internal 48 MHz oscillator in automatic trimming mode. The synchronization for this
oscillator can be taken from the USB data stream itself (SOF signalization) which allows
crystal-less operation.
3.22 Clock recovery system (CRS)
The STM32F072x8/xB embeds a special block which allows automatic trimming of the
internal 48
operational range. This automatic trimming is based on the external synchronization signal,
which could be either derived from USB SOF signalization, from LSE oscillator, from an
external signal on CRS_SYNC pin or generated by user software. For faster lock-in during
startup it is also possible to combine automatic trimming with manual trimming action.
MHz oscillator to guarantee its optimal accuracy over the whole device
3.23 Serial wire debug port (SW-DP)
An Arm SW-DP interface is provided to allow a serial wire debugging tool to be connected to
the MCU.
DS9826 Rev 6 27/128
27
MS31409V2
AHB2
0
1
2
3
4
5
6
7
0xFFFF FFFF
Peripherals
SRAM
Flash memory
Reserved
System memory
Option Bytes
0xE010 0000
Flash, system
memory or SRAM,
depending on BOOT
configuration
0x0000 0000
0xE000 0000
0xC000 0000
0xA000 0000
0x8000 0000
0x6000 0000
0x4000 0000
0x2000 0000
0x0000 0000
0x0800 0000
0x0802 0000
0x1FFF C800
0x1FFF F800
0x1FFF FFFF
0x0002 0000
Reserved
CODE
APB
APB
Reserved
0x4000 0000
0x4000 8000
0x4001 0000
0x4001 8000
Reserved
0x4002 0000
AHB1
0x4800 0000
Reserved
0x4800 17FF
0x4002 43FF
Cortex-M0 internal
peripherals
Reserved
0x1FFF FC00
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Memory mapping STM32F072x8 STM32F072xB
4 Memory mapping
To the difference of STM32F072xB memory map in Figure 3, the two bottom code memory
spaces of STM32F072x8 end at 0x0000 FFFF and 0x0800 FFFF, respectively.
Figure 3. STM32F072xB memory map
28/128 DS9826 Rev 6
STM32F072x8 STM32F072xB Memory mapping
Table 12. Peripheral register boundary addresses
Bus Boundary address Size Peripheral
- 0x4800 1800 - 0x5FFF FFFF ~384 MB Reserved
0x4800 1400 - 0x4800 17FF 1 KB GPIOF
0x4800 1000 - 0x4800 13FF 1 KB GPIOE
0x4800 0C00 - 0x4800 0FFF 1 KB GPIOD
AHB2
0x4800 0800 - 0x4800 0BFF 1 KB GPIOC
0x4800 0400 - 0x4800 07FF 1 KB GPIOB
0x4800 0000 - 0x4800 03FF 1 KB GPIOA
- 0x4002 4400 - 0x47FF FFFF ~128 MB Reserved
0x4002 4000 - 0x4002 43FF 1 KB TSC
0x4002 3400 - 0x4002 3FFF 3 KB Reserved
0x4002 3000 - 0x4002 33FF 1 KB CRC
0x4002 2400 - 0x4002 2FFF 3 KB Reserved
AHB1
0x4002 2000 - 0x4002 23FF 1 KB Flash memory interface
0x4002 1400 - 0x4002 1FFF 3 KB Reserved
0x4002 1000 - 0x4002 13FF 1 KB RCC
0x4002 0400 - 0x4002 0FFF 3 KB Reserved
0x4002 0000 - 0x4002 03FF 1 KB DMA
- 0x4001 8000 - 0x4001 FFFF 32 KB Reserved
0x4001 5C00 - 0x4001 7FFF 9 KB Reserved
0x4001 5800 - 0x4001 5BFF 1 KB DBGMCU
0x4001 4C00 - 0x4001 57FF 3 KB Reserved
0x4001 4800 - 0x4001 4BFF 1 KB TIM17
0x4001 4400 - 0x4001 47FF 1 KB TIM16
0x4001 4000 - 0x4001 43FF 1 KB TIM15
0x4001 3C00 - 0x4001 3FFF 1 KB Reserved
0x4001 3800 - 0x4001 3BFF 1 KB USART1
0x4001 3400 - 0x4001 37FF 1 KB Reserved
APB
0x4001 3000 - 0x4001 33FF 1 KB SPI1/I2S1
0x4001 2C00 - 0x4001 2FFF 1 KB TIM1
0x4001 2800 - 0x4001 2BFF 1 KB Reserved
0x4001 2400 - 0x4001 27FF 1 KB ADC
0x4001 0800 - 0x4001 23FF 7 KB Reserved
0x4001 0400 - 0x4001 07FF 1 KB EXTI
0x4001 0000 - 0x4001 03FF 1 KB SYSCFG + COMP
- 0x4000 8000 - 0x4000 FFFF 32 KB Reserved
DS9826 Rev 6 29/128
30
Memory mapping STM32F072x8 STM32F072xB
Table 12. Peripheral register boundary addresses (continued)
Bus Boundary address Size Peripheral
0x4000 7C00 - 0x4000 7FFF 1 KB Reserved
0x4000 7800 - 0x4000 7BFF 1 KB CEC
0x4000 7400 - 0x4000 77FF 1 KB DAC
0x4000 7000 - 0x4000 73FF 1 KB PWR
0x4000 6C00 - 0x4000 6FFF 1 KB CRS
0x4000 6800 - 0x4000 6BFF 1 KB Reserved
0x4000 6400 - 0x4000 67FF 1 KB BxCAN
0x4000 6000 - 0x4000 63FF 1 KB USB/CAN RAM
0x4000 5C00 - 0x4000 5FFF 1 KB USB
0x4000 5800 - 0x4000 5BFF 1 KB I2C2
0x4000 5400 - 0x4000 57FF 1 KB I2C1
0x4000 5000 - 0x4000 53FF 1 KB Reserved
0x4000 4C00 - 0x4000 4FFF 1 KB USART4
0x4000 4800 - 0x4000 4BFF 1 KB USART3
0x4000 4400 - 0x4000 47FF 1 KB USART2
APB
0x4000 3C00 - 0x4000 43FF 2 KB Reserved
0x4000 3800 - 0x4000 3BFF 1 KB SPI2
0x4000 3400 - 0x4000 37FF 1 KB Reserved
0x4000 3000 - 0x4000 33FF 1 KB IWDG
0x4000 2C00 - 0x4000 2FFF 1 KB WWDG
0x4000 2800 - 0x4000 2BFF 1 KB RTC
0x4000 2400 - 0x4000 27FF 1 KB Reserved
0x4000 2000 - 0x4000 23FF 1 KB TIM14
0x4000 1800 - 0x4000 1FFF 2 KB Reserved
0x4000 1400 - 0x4000 17FF 1 KB TIM7
0x4000 1000 - 0x4000 13FF 1 KB TIM6
0x4000 0800 - 0x4000 0FFF 2 KB Reserved
0x4000 0400 - 0x4000 07FF 1 KB TIM3
0x4000 0000 - 0x4000 03FF 1 KB TIM2
30/128 DS9826 Rev 6
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