ST MICROELECTRONICS STM32F072CBT6 Datasheet

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STM32F072x8 STM32F072xB

LQFP100 14x14 mm

LQFP64 10x10 mm

LQFP48 7x7 mm

UFQFPN48

7x7 mm

UFBGA100

7x7 mm

UFBGA64

5x5 mm

WLCSP49

3.3x3.1 mm

Arm®-based 32-bit MCU, up to 128 KB Flash, crystal-less USB

FS 2.0, CAN, 12 timers, ADC, DAC & comm. interfaces, 2.0 - 3.6 V

Datasheet - production data

Features

• Core: Arm® 32-bit Cortex®-M0 CPU, frequency up to 48 MHz

• Memories – 64 to 128 Kbytes of Flash memory – 16 Kbytes of SRAM with HW parity

• CRC calculation unit

• Reset and power management

– Digital and I/O supply: V – Analog supply: V – Selected I/Os: V

DDA

DDIO2

– Power-on/Power down reset (POR/PDR) – Programmable voltage detector (PVD) – Low power modes: Sleep, Stop, Standby –V

supply for RTC and backup registers

BAT

• Clock management – 4 to 32 MHz crystal oscillator – 32 kHz oscillator for RTC with calibration – Internal 8 MHz RC with x6 PLL option – Internal 40 kHz RC oscillator – Internal 48 MHz oscillator with automatic

trimming based on ext. synchronization

• Up to 87 fast I/Os – All mappable on external interrupt vectors – Up to 68 I/Os with 5V tolerant capability

and 19 with independent supply V

• 7-channel DMA controller

• One 12-bit, 1.0 µs ADC (up to 16 channels)

– Conversion range: 0 to 3.6 V – Separate analog supply: 2.4 V to 3.6 V

• One 12-bit D/A converter (with 2 channels)

• 2 fast low-power analog comparators with

programmable input and output

• Up to 24 capacitive sensing channels for touchkey, linear and rotary touch sensors

= 2.0 V to 3.6 V

= VDD to 3.6 V

= 1.65 V to 3.6 V

DDIO2

FBGA

• Calendar RTC with alarm and periodic wakeup from Stop/Standby

• 12 timers – One 16-bit advanced-control timer for

six-channel PWM output

– One 32-bit and seven 16-bit timers, with up

to four IC/OC, OCN, usable for IR control

decoding or DAC control – Independent and system watchdog timers – SysTick timer

• Communication interfaces

–2 I

C interfaces supporting Fast Mode Plus (1 Mbit/s) with 20 mA current sink, one supporting SMBus/PMBus and wakeup

– 4 USARTs supporting master synchronous

SPI and modem control, two with ISO7816 interface, LIN, IrDA, auto baud rate detection and wakeup feature

– 2 SPIs (18 Mbit/s) with 4 to 16

programmable bit frames, and with I

interface multiplexed

– CAN interface – USB 2.0 full-speed interface, able to run

from internal 48 MHz oscillator and with BCD and LPM support

• HDMI CEC wakeup on header reception

• Serial wire debug (SWD)

• 96-bit unique ID

• All packages ECOPACK

Reference Part number

STM32F072x8 STM32F072xB

Table 1. Device summary

STM32F072C8, STM32F072R8, STM32F072V8, STM32F072CB, STM32F072RB, STM32F072VB

September 2019 DS9826 Rev 6 1/128

This is information on a product in full production.

www.st.com

Contents STM32F072x8 STM32F072xB

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.1 Arm®-Cortex®-M0 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.2 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.3 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.4 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 14

3.5 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.5.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.5.2 Power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.5.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.5.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.6 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.7 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.8 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.9 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.9.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 17

3.9.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 18

3.10 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.10.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.10.2 Internal voltage reference (V

3.10.3 V

battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

BAT

) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

REFINT

3.11 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.12 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.13 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.14 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.14.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.14.2 General-purpose timers (TIM2, 3, 14, 15, 16, 17) . . . . . . . . . . . . . . . . . 22

3.14.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.14.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.14.5 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Contents

3.14.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.15 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 23

3.16 Inter-integrated circuit interface (I

C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.17 Universal synchronous/asynchronous receiver/transmitter (USART) . . . 25

3.18 Serial peripheral interface (SPI) / Inter-integrated sound interface (I

S) . 26

3.19 High-definition multimedia interface (HDMI) - consumer

electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.20 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.21 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.22 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.23 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5 Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 54

6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 54

6.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

6.3.6 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

DS9826 Rev 6 3/128

Contents STM32F072x8 STM32F072xB

6.3.10 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

6.3.16 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

6.3.17 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

6.3.18 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

6.3.19 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

6.3.20 V

6.3.21 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

6.3.22 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

BAT

7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

7.1 UFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

7.2 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

7.3 UFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

7.4 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

7.5 WLCSP49 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

7.6 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

7.7 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118

7.8 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

7.8.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

7.8.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 121

8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

4/128 DS9826 Rev 6

STM32F072x8 STM32F072xB List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. STM32F072x8/xB family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . 11

Table 3. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 4. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 5. Capacitive sensing GPIOs available on STM32F072x8/xB devices. . . . . . . . . . . . . . . . . . 20

Table 6. Number of capacitive sensing channels available

on STM32F072x8/xB devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 7. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 8. Comparison of I Table 9. STM32F072x8/xB I

Table 10. STM32F072x8/xB USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 11. STM32F072x8/xB SPI/I

Table 12. Peripheral register boundary addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 13. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 14. STM32F072x8/xB pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 15. Alternate functions selected through GPIOA_AFR registers for port A . . . . . . . . . . . . . . . 44

Table 16. Alternate functions selected through GPIOB_AFR registers for port B . . . . . . . . . . . . . . . 45

Table 17. Alternate functions selected through GPIOC_AFR registers for port C . . . . . . . . . . . . . . . 46

Table 18. Alternate functions selected through GPIOD_AFR registers for port D . . . . . . . . . . . . . . . 46

Table 19. Alternate functions selected through GPIOE_AFR registers for port E . . . . . . . . . . . . . . . 47

Table 20. Alternate functions available on port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 21. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 22. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 23. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 24. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 25. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 26. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 27. Programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 28. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 29. Typical and maximum current consumption from V Table 30. Typical and maximum current consumption from the V

Table 31. Typical and maximum consumption in Stop and Standby modes . . . . . . . . . . . . . . . . . . . 59

Table 32. Typical and maximum current consumption from the V Table 33. Typical current consumption, code executing from Flash memory,

running from HSE 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 34. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 35. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 36. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 37. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 38. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 39. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 40. LSE oscillator characteristics (f

Table 41. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 42. HSI14 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 43. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 44. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 45. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 46. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

S implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

supply at VDD = 3.6 V . . . . . . . . . . 56

= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

LSE

supply . . . . . . . . . . . . . . . . . 58

DDA

supply. . . . . . . . . . . . . . . . . . . 60

BAT

DS9826 Rev 6 5/128

List of tables STM32F072x8 STM32F072xB

Table 47. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 48. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 49. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 50. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 51. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 52. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 53. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 54. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 55. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 56. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 57. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 58. R

max for f

AIN

= 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

ADC

Table 59. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 60. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 61. Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 62. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 63. V

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

BAT

Table 64. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 65. IWDG min/max timeout period at 40 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 66. WWDG min/max timeout value at 48 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 67. I

Table 68. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 69. I

C analog filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 70. USB electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 71. UFBGA100 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 72. UFBGA100 recommended PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Table 73. LQPF100 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 74. UFBGA64 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Table 75. UFBGA64 recommended PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 76. LQFP64 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 77. WLCSP49 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 78. LQFP48 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Table 79. UFQFPN48 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Table 80. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Table 81. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

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STM32F072x8 STM32F072xB List of figures

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 3. STM32F072xB memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 4. UFBGA100 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 5. LQFP100 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 6. UFBGA64 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 7. LQFP64 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 8. LQFP48 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 9. UFQFPN48 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 10. WLCSP49 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 11. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 12. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 13. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 14. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 15. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 16. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 17. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 18. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 19. HSI oscillator accuracy characterization results for soldered parts . . . . . . . . . . . . . . . . . . 71

Figure 20. HSI14 oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 21. HSI48 oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 22. TC and TTa I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 23. Five volt tolerant (FT and FTf) I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 24. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 25. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 26. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 27. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 28. 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 29. Maximum V

Figure 30. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 31. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 32. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 33. I Figure 34. I

S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

S master timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Figure 35. UFBGA100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 36. Recommended footprint for UFBGA100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Figure 37. UFBGA100 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 38. LQFP100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Figure 39. Recommended footprint for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Figure 40. LQFP100 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Figure 41. UFBGA64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 42. Recommended footprint for UFBGA64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 43. UFBGA64 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 44. LQFP64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Figure 45. Recommended footprint for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Figure 46. LQFP64 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Figure 47. WLCSP49 package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 48. WLCSP49 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

scaler startup time from power down . . . . . . . . . . . . . . . . . . . . . . . . . . 91

REFINT

DS9826 Rev 6 7/128

List of figures STM32F072x8 STM32F072xB

Figure 49. LQFP48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 50. Recommended footprint for LQFP48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 51. LQFP48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 52. UFQFPN48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 53. Recommended footprint for UFQFPN48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 54. UFQFPN48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 55. LQFP64 P

max versus TA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

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STM32F072x8 STM32F072xB Introduction

1 Introduction

This datasheet provides characteristics and ordering information of the STM32F072x8/xB microcontrollers.

This document should be read in conjunction with the STM32F0xxxx reference manual (RM0091). The reference manual is available from the STMicroelectronics website

www.st.com.

For information on the Arm Technical Reference Manual, available from the www.arm.com website.

®(a)

Cortex®-M0 core, please refer to the Arm® Cortex®-M0

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

DS9826 Rev 6 9/128

Description STM32F072x8 STM32F072xB

2 Description

The STM32F072x8/xB microcontrollers incorporate the high-performance Arm®Cortex®-M0 32-bit RISC core operating at up to 48 MHz frequency, high-speed embedded memories (up to 128 extensive range of enhanced peripherals and I/Os. All devices offer standard communication interfaces (two I USB Full-speed device (crystal-less), one CAN, one 12-bit ADC, one 12-bit DAC with two channels, seven 16-bit timers, one 32-bit timer and an advanced-control PWM timer.

The STM32F072x8/xB microcontrollers operate in the -40 to +85 °C and -40 to +105 °C temperature ranges, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving modes allows the design of low-power applications.

The STM32F072x8/xB microcontrollers include devices in seven different packages ranging from 48 pins to 100 pins with a die form also available upon request. Depending on the device chosen, different sets of peripherals are included.

These features make the STM32F072x8/xB microcontrollers suitable for a wide range of applications such as application control and user interfaces, hand-held equipment, A/V receivers and digital TV, PC peripherals, gaming and GPS platforms, industrial applications, PLCs, inverters, printers, scanners, alarm systems, video intercoms and HVACs.

Kbytes of Flash memory and 16 Kbytes of SRAM), and an

Cs, two SPI/I2S, one HDMI CEC and four USARTs), one

10/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Description

Table 2. STM32F072x8/xB family device features and peripheral counts

Peripheral STM32F072Cx STM32F072Rx STM32F072Vx

Flash memory (Kbyte) 64 128 64 128 64 128

SRAM (Kbyte) 16

Timers

Advanced

control

General

purpose

Basic 2 (16-bit)

2S](1)

SPI [I

1 (16-bit)

5 (16-bit) 1 (32-bit)

2 [2]

Comm.

interfaces

USART 4

CAN 1

USB 1

CEC 1

12-bit ADC

(number of channels)

(10 ext. + 3 int.)

12-bit DAC

(number of channels)

Analog comparator 2

GPIOs 37 51 87

Capacitive sensing

channels

17 18 24

Max. CPU frequency 48 MHz

Operating voltage 2.0 to 3.6 V

Operating temperature

Packages

1. The SPI interface can be used either in SPI mode or in I2S audio mode.

Ambient operating temperature: -40°C to 85°C / -40°C to 105°C

Junction temperature: -40°C to 105°C / -40°C to 125°C

LQFP48

UFQFPN48

WLCSP49

LQFP64

UFBGA64

(16 ext. + 3 int.)

(2)

LQFP100

UFBGA100

DS9826 Rev 6 11/128

Description STM32F072x8 STM32F072xB

MSv31404V4

Power domain of analog blocks :

BAT

DDIO2

4 channels 3 compl. channels BRK, ETR input as AF

@ V

DDA

System and peripheral

clocks

PA[15:0]

PB[15:0]

PC[15:0]

PF[10:9], PF6

PF[3:0]

8 groups of

4 channels

SYNC

87 AF

MOSI/SD

MISO/MCK

SCK/CK

NSS/WS as AF

@ V

DDA

SSA

SWCLK

SWDIO

as AF

16x

AD input

OSC_IN OSC_OUT

BAT

= 1.65 to 3.6 V

OSC32_IN OSC32_OUT

3 TAMPER-RTC (ALARM OUT)

@ V

BAT

SYNC

MOSI/SD

MISO/MCK

SCK/CK

NSS/WS as AF

HSI14

HSI

LSI

HSI48

PLLCLK

IR_OUT as AF

1 channel 1 compl, BRK as AF

1 channel as AF

4 ch., ETR as AF

GP DMA

7 channels

CORTEX-M0 CPU

MAX

= 48 MHz

Serial Wire

Debug

NVIC

Touch

Sensing

Controller

PAD

Analog

switches

EXT. IT WKUP

SPI1/I2S1

SPI2/I2S2

SYSCFG IF

DBGMCU

Window WDG

APB

AHB

CRC

RESET & CLOCK

CONTROL

Power

Controller

XTAL OSC

4-32 MHz

Ind. Window WDG

SRAM 16 KB

Temp. sensor

12-bit ADC

RTC

Backup

reg

RTC interface

CRS

RC 14 MHz

RC 8 MHz

RC 40 kHz

PLL

RC 48MHz

AHB decoder

XTAL32 kHz

SRAM

controller

Bus matrix

Flash

memory

interface

Flash GPL

up to 128 KB

32-bit

Obl

2 channels 1 compl, BRK as AF

RX, TX,CTS, RTS, CK as AF

SCL, SDA (20 mA FM+) as AF

SCL, SDA, SMBA (20 mA FM+) as AF

CEC as AF

I2C1

I2C2

12-bit DAC

DAC_OUT1

DAC_OUT2

@ V

DDA

TIMER 6

TIMER 7

GP comparator 1

GP comparator 2

INPUT +

INPUT -

OUTPUT

as AF

@ V

DDA

GPIO port F

GPIO port E

GPIO port D

GPIO port C

GPIO port B

GPIO port A

PD[15:0]

PE[15:0]

DDA

SUPPLY

SUPERVISION

POWER

@ V

DDA

@ V

DD18

POR

Reset

Int

= 2 to 3.6 V

NRST V

DDA

SSA

DDIO2

OKIN

PVD

POR/PDR

VOLT.REG

3.3 V to 1.8 V

USART4

USART3

USART2

USART1

HDMI-CEC

TIMER 17

TIMER 16

TIMER 15

TIMER 14

TIMER 3

TIMER 2 32-bit

PWM TIMER 1

TX, RX as AF

D+, D-

@ V

DDIO2

BxCAN

USB PHY

USB

SRAM 768B

SRAM 256B

Figure 1. Block diagram

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STM32F072x8 STM32F072xB Functional overview

3 Functional overview

Figure 1 shows the general block diagram of the STM32F072x8/xB devices.

3.1 Arm®-Cortex®-M0 core

The Arm® Cortex®-M0 is a generation of Arm 32-bit RISC processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.

The Arm® Cortex®-M0 processors feature exceptional code-efficiency, delivering the high performance expected from an Arm core, with memory sizes usually associated with 8- and 16-bit devices.

The STM32F072x8/xB devices embed Arm core and are compatible with all Arm tools and software.

3.2 Memories

The device has the following features:

• 16 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states and featuring embedded parity checking with exception generation for fail-critical applications.

• The non-volatile memory is divided into two arrays:

– 64 to 128 Kbytes of embedded Flash memory for programs and data

– Option bytes

The option bytes are used to write-protect the memory (with 4 KB granularity) and/or readout-protect the whole memory with the following options:

– Level 0: no readout protection

– Level 1: memory readout protection, the Flash memory cannot be read from or

written to if either debug features are connected or boot in RAM is selected

– Level 2: chip readout protection, debug features (Arm

and boot in RAM selection disabled

3.3 Boot modes

At startup, the boot pin and boot selector option bit are used to select one of the three boot options:

• boot from User Flash memory

• boot from System Memory

• boot from embedded SRAM

Cortex®-M0 serial wire)

The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART on pins PA14/PA15, or PA9/PA10 or I DFU interface.

DS9826 Rev 6 13/128

C on pins PB6/PB7 or through the USB

Functional overview STM32F072x8 STM32F072xB

3.4 Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.

3.5 Power management

3.5.1 Power supply schemes

• VDD = V

= 2.0 to 3.6 V: external power supply for I/Os (V

DDIO1

regulator. It is provided externally through VDD pins.

• V

= from VDD to 3.6 V: external analog power supply for ADC, DAC, Reset blocks,

DDA

RCs and PLL (minimum voltage to be applied to V are used). It is provided externally through VDDA pin. The V always greater or equal to the V

• V

= 1.65 to 3.6 V: external power supply for marked I/Os. V

DDIO2

externally through the VDDIO2 pin. The V from V V

DDIO2

REFINT

or V

, but it must not be provided without a valid supply on VDD. The

DDA

supply is monitored and compared with the internal reference voltage

). When the V

DDIO2

are disabled by hardware. The output of this comparator is connected to EXTI line 31 and it can be used to generate an interrupt. Refer to the pinout diagrams or tables for concerned I/Os list.

• V

= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and

BAT

backup registers (through power switch) when V

For more details on how to connect power pins, refer to Figure 13: Power supply scheme.

3.5.2 Power supply supervisors

The device has integrated power-on reset (POR) and power-down reset (PDR) circuits. They are always active, and ensure proper operation above a threshold of 2 V. The device remains in reset mode when the monitored supply voltage is below a specified threshold, V

POR/PDR

• The POR monitors only the VDD supply voltage. During the startup phase it is required

• The PDR monitors both the V

The device features an embedded programmable voltage detector (PVD) that monitors the V

when V

, without the need for an external reset circuit.

that V

should arrive first and be greater than or equal to VDD.

DDA

supply supervisor can be disabled (by programming a dedicated Option bit) to reduce the power consumption if the application design ensures that V equal to V

power supply and compares it to the V

drops below the V

PVD

) and the internal

DDIO1

is 2.4 V when the ADC or DAC

DDA

voltage level and must be established first.

voltage level is completely independent

DDIO2

voltage level must be

DDA

is provided

DDIO2

is below this threshold, all the I/Os supplied from this rail

is not present.

and V

threshold and/or when VDD is higher than the V

supply voltages, however the V

DDA

is higher than or

DDA

threshold. An interrupt can be generated

PVD

DDA

power

PVD

14/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Functional overview

threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

3.5.3 Voltage regulator

The regulator has two operating modes and it is always enabled after reset.

• Main (MR) is used in normal operating mode (Run).

• Low power (LPR) can be used in Stop mode where the power demand is reduced.

In Standby mode, it is put in power down mode. In this mode, the regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost).

3.5.4 Low-power modes

The STM32F072x8/xB microcontrollers support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

• Stop mode

Stop mode achieves very low power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low power mode.

The device can be woken up from Stop mode by any of the EXTI lines. The EXTI line source can be one of the 16 external lines, the PVD output, RTC, I2C1, USART1, USART2, USB, COMPx, V

The CEC, USART1, USART2 and I2C1 peripherals can be configured to enable the HSI RC oscillator so as to get clock for processing incoming data. If this is used when the voltage regulator is put in low power mode, the regulator is first switched to normal mode before the clock is provided to the given peripheral.

• Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the RTC domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pins, or an RTC event occurs.

supply comparator or the CEC.

DDIO2

Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop

or Standby mode.

3.6 Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches

DS9826 Rev 6 15/128

Functional overview STM32F072x8 STM32F072xB

MSv31418V2

OSC_IN

OSC_OUT

OSC32_IN

OSC32_OUT

IWDG

PLLMUL

MCO

Main clock

output

PLLCLK

HSI

HSE

PLLCLK

ADC asynchronous clock input

LSE

LSI

HSI

HSE

RTC

PLLSRC

MCO

RTCCLK

RTCSEL

SYSCLK

TIM1,2,3,6,7, 14,15,16,17

FLITFCLK

Flash memory programming interface

HSI14

LSE

I2C1

USART1

LSE

HSI

SYSCLK

PCLK

SYSCLK

HSI

PCLK

I2S1/SPI1 I2S2/SPI2

CEC

APB peripherals

LSI

LSE

PREDIV

HSI48

PLLNODIV

MCOPRE

TIM14

LSE

HSE

SYNC

CSS

Trim

Legend

white

clock tree control element clock line control line

black

clock tree element

/32

4-32 MHz

HSE OSC

/1,/2,/4,

/8,/16

/1,/2

14 MHz RC

HSI14

/1,/2,…

…/512

8 MHz

HSI RC

/1,/2,..

../16

32.768 kHz LSE OSC

40 kHz LSI RC

PLL

x2,x3,..

...x16

48 MHz HSI RC

x1, x2

/1,/2,/4,..

../128

USARTxSW

PPRE

PPREHPRE

CECSW

/244

I2C1SW

SYSCLK

CRS

HSI

HSI48

HSI

SYNCSRC

USART2

HCLK

AHB, core, memory, DMA, Cortex FCLK free-run clock

Cortex system timer

USB

HSI48

USBSW

LSE

USB SOF

back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example on failure of an indirectly used external crystal, resonator or oscillator).

Figure 2. Clock tree

16/128 DS9826 Rev 6

Several prescalers allow the application to configure the frequency of the AHB and the APB domains. The maximum frequency of the AHB and the APB domains is 48 MHz.

STM32F072x8 STM32F072xB Functional overview

Additionally, also the internal RC 48 MHz oscillator can be selected for system clock or PLL input source. This oscillator can be automatically fine-trimmed by the means of the CRS peripheral using the external synchronization.

3.7 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions.

The I/O configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.

3.8 Direct memory access controller (DMA)

The 7-channel general-purpose DMAs manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers.

The DMA supports circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent.

DMA can be used with the main peripherals: SPIx, I2Sx, I2Cx, USARTx, all TIMx timers (except TIM14), DAC and ADC.

3.9 Interrupts and events

3.9.1 Nested vectored interrupt controller (NVIC)

The STM32F0xx family embeds a nested vectored interrupt controller able to handle up to 32 maskable interrupt channels (not including the 16 interrupt lines of Cortex priority levels.

• Closely coupled NVIC gives low latency interrupt processing

• Interrupt entry vector table address passed directly to the core

• Closely coupled NVIC core interface

• Allows early processing of interrupts

• Processing of late arriving higher priority interrupts

• Support for tail-chaining

• Processor state automatically saved

• Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt latency.

-M0) and 4

DS9826 Rev 6 17/128

Functional overview STM32F072x8 STM32F072xB

3.9.2 Extended interrupt/event controller (EXTI)

The extended interrupt/event controller consists of 32 edge detector lines used to generate interrupt/event requests and wake-up the system. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the internal clock period. Up to 87 GPIOs can be connected to the 16 external interrupt lines.

3.10 Analog-to-digital converter (ADC)

The 12-bit analog-to-digital converter has up to 16 external and 3 internal (temperature sensor, voltage reference, VBAT voltage measurement) channels and performs conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs.

The ADC can be served by the DMA controller.

An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

3.10.1 Temperature sensor

The temperature sensor (TS) generates a voltage V temperature.

The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only.

To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode.

Calibration value name Description Memory address

TS_CAL1

TS_CAL2

Table 3. Temperature sensor calibration values

SENSE

TS ADC raw data acquired at a temperature of 30 °C (± 5 °C), V

= 3.3 V (± 10 mV)

DDA

TS ADC raw data acquired at a temperature of 110 °C (± 5 °C), V

= 3.3 V (± 10 mV)

DDA

that varies linearly with

0x1FFF F7B8 - 0x1FFF F7B9

0x1FFF F7C2 - 0x1FFF F7C3

3.10.2 Internal voltage reference (V

The internal voltage reference (V ADC and comparators. V

18/128 DS9826 Rev 6

REFINT

) provides a stable (bandgap) voltage output for the

REFINT

is internally connected to the ADC_IN17 input channel. The

)

STM32F072x8 STM32F072xB Functional overview

precise voltage of V

is individually measured for each part by ST during production

REFINT

test and stored in the system memory area. It is accessible in read-only mode.

3.10.3 V

Calibration value name Description Memory address

VREFINT_CAL

battery voltage monitoring

BAT

Table 4. Internal voltage reference calibration values

Raw data acquired at a temperature of 30 °C (± 5 °C), V

= 3.3 V (± 10 mV)

DDA

This embedded hardware feature allows the application to measure the V using the internal ADC channel ADC_IN18. As the V and thus outside the ADC input range, the V

pin is internally connected to a bridge

BAT

divider by 2. As a consequence, the converted digital value is half the V

3.11 Digital-to-analog converter (DAC)

The two 12-bit buffered DAC channels can be used to convert digital signals into analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in non-inverting configuration.

This digital Interface supports the following features:

• 8-bit or 12-bit monotonic output

• Left or right data alignment in 12-bit mode

• Synchronized update capability

• Noise-wave generation

• Triangular-wave generation

• Dual DAC channel independent or simultaneous conversions

• DMA capability for each channel

• External triggers for conversion

0x1FFF F7BA - 0x1FFF F7BB

battery voltage

voltage may be higher than V

BAT

voltage.

BAT

DDA

Six DAC trigger inputs are used in the device. The DAC is triggered through the timer trigger outputs and the DAC interface is generating its own DMA requests.

3.12 Comparators (COMP)

The device embeds two fast rail-to-rail low-power comparators with programmable reference voltage (internal or external), hysteresis and speed (low speed for low power) and with selectable output polarity.

The reference voltage can be one of the following:

• External I/O

• DAC output pins

• Internal reference voltage or submultiple (1/4, 1/2, 3/4).Refer to Table 28: Embedded

internal reference voltage for the value and precision of the internal reference voltage.

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Functional overview STM32F072x8 STM32F072xB

Both comparators can wake up from STOP mode, generate interrupts and breaks for the timers and can be also combined into a window comparator.

3.13 Touch sensing controller (TSC)

The STM32F072x8/xB devices provide a simple solution for adding capacitive sensing functionality to any application. These devices offer up to 24 capacitive sensing channels distributed over 8 analog I/O groups.

Capacitive sensing technology is able to detect the presence of a finger near a sensor which is protected from direct touch by a dielectric (glass, plastic...). The capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. It consists in charging the sensor capacitance and then transferring a part of the accumulated charges into a sampling capacitor until the voltage across this capacitor has reached a specific threshold. To limit the CPU bandwidth usage, this acquisition is directly managed by the hardware touch sensing controller and only requires few external components to operate. For operation, one capacitive sensing GPIO in each group is connected to an external capacitor and cannot be used as effective touch sensing channel.

The touch sensing controller is fully supported by the STMTouch touch sensing firmware library, which is free to use and allows touch sensing functionality to be implemented reliably in the end application.

Table 5. Capacitive sensing GPIOs available on STM32F072x8/xB devices

Group

Capacitive sensing

signal name

TSC_G1_IO1 PA0

TSC_G1_IO2 PA1 TSC_G5_IO2 PB4

TSC_G1_IO3 PA2 TSC_G5_IO3 PB6

TSC_G1_IO4 PA3 TSC_G5_IO4 PB7

TSC_G2_IO1 PA4

TSC_G2_IO2 PA5 TSC_G6_IO2 PB12

TSC_G2_IO3 PA6 TSC_G6_IO3 PB13

TSC_G2_IO4 PA7 TSC_G6_IO4 PB14

TSC_G3_IO1 PC5

TSC_G3_IO2 PB0 TSC_G7_IO2 PE3

TSC_G3_IO3 PB1 TSC_G7_IO3 PE4

TSC_G3_IO4 PB2 TSC_G7_IO4 PE5

TSC_G4_IO1 PA9

TSC_G4_IO2 PA10 TSC_G8_IO2 PD13

TSC_G4_IO3 PA11 TSC_G8_IO3 PD14

TSC_G4_IO4 PA12 TSC_G8_IO4 PD15

name

Group

Capacitive sensing

signal name

TSC_G5_IO1 PB3

TSC_G6_IO1 PB11

TSC_G7_IO1 PE2

TSC_G8_IO1 PD12

name

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STM32F072x8 STM32F072xB Functional overview

Table 6. Number of capacitive sensing channels available

on STM32F072x8/xB devices

Analog I/O group

STM32F072Vx STM32F072Rx STM32F072Cx

G1 3 3 3

G2 3 3 3

G3 3 3 2

G4 3 3 3

G5 3 3 3

G6 3 3 3

G7 3 0 0

G8 3 0 0

Number of capacitive

sensing channels

3.14 Timers and watchdogs

The STM32F072x8/xB devices include up to six general-purpose timers, two basic timers and an advanced control timer.

Number of capacitive sensing channels

24 18 17

Timer

type

Advanced

control

General

purpose

Basic

Tab le 7 compares the features of the different timers.

Timer

Counter

resolution

TIM1 16-bit

TIM2 32-bit

TIM3 16-bit

TIM14 16-bit Up

TIM15 16-bit Up

TIM16 TIM17

TIM6 TIM7

16-bit Up

Table 7. Timer feature comparison

Counter

type

Up, down,

up/down

Up, down,

up/down

Up, down,

up/down

Prescaler

factor

integer from

1 to 65536

integer from

1 to 65536

integer from

1 to 65536

integer from

1 to 65536

integer from

1 to 65536

integer from

1 to 65536

integer from

1 to 65536

DMA

request

generation

Yes 4 3

Yes 4 -

No 1 -

Yes 2 1

Yes 1 1

Yes - -

Capture/compare

channels

Complementary

outputs

DS9826 Rev 6 21/128

Functional overview STM32F072x8 STM32F072xB

3.14.1 Advanced-control timer (TIM1)

The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on six channels. It has complementary PWM outputs with programmable inserted dead times. It can also be seen as a complete general-purpose timer. The four independent channels can be used for:

• input capture

• output compare

• PWM generation (edge or center-aligned modes)

• one-pulse mode output

If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If configured as the 16-bit PWM generator, it has full modulation capability (0-100%).

The counter can be frozen in debug mode.

Many features are shared with those of the standard timers which have the same architecture. The advanced control timer can therefore work together with the other timers via the Timer Link feature for synchronization or event chaining.

3.14.2 General-purpose timers (TIM2, 3, 14, 15, 16, 17)

There are six synchronizable general-purpose timers embedded in the STM32F072x8/xB devices (see PWM outputs, or as simple time base.

Tabl e 7 for differences). Each general-purpose timer can be used to generate

TIM2, TIM3

STM32F072x8/xB devices feature two synchronizable 4-channel general-purpose timers. TIM2 is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TIM3 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. They feature 4 independent channels each for input capture/output compare, PWM or one-pulse mode output. This gives up to 12 input captures/output compares/PWMs on the largest packages.

The TIM2 and TIM3 general-purpose timers can work together or with the TIM1 advancedcontrol timer via the Timer Link feature for synchronization or event chaining.

TIM2 and TIM3 both have independent DMA request generation.

These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors.

Their counters can be frozen in debug mode.

TIM14

This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler.

TIM14 features one single channel for input capture/output compare, PWM or one-pulse mode output.

Its counter can be frozen in debug mode.

TIM15, TIM16 and TIM17

These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.

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STM32F072x8 STM32F072xB Functional overview

TIM15 has two independent channels, whereas TIM16 and TIM17 feature one single channel for input capture/output compare, PWM or one-pulse mode output.

The TIM15, TIM16 and TIM17 timers can work together, and TIM15 can also operate withTIM1 via the Timer Link feature for synchronization or event chaining.

TIM15 can be synchronized with TIM16 and TIM17.

TIM15, TIM16 and TIM17 have a complementary output with dead-time generation and independent DMA request generation.

Their counters can be frozen in debug mode.

3.14.3 Basic timers TIM6 and TIM7

These timers are mainly used for DAC trigger generation. They can also be used as generic 16-bit time bases.

3.14.4 Independent watchdog (IWDG)

The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with user-defined refresh window. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.

3.14.5 System window watchdog (WWDG)

The system window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the APB clock (PCLK). It has an early warning interrupt capability and the counter can be frozen in debug mode.

3.14.6 SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features:

• a 24-bit down counter

• autoreload capability

• maskable system interrupt generation when the counter reaches 0

• programmable clock source (HCLK or HCLK/8)

3.15 Real-time clock (RTC) and backup registers

The RTC and the five backup registers are supplied through a switch that takes power either on V registers used to store 20 bytes of user application data when V They are not reset by a system or power reset, or at wake up from Standby mode.

supply when present or through the V

pin. The backup registers are five 32-bit

BAT

power is not present.

DS9826 Rev 6 23/128

Functional overview STM32F072x8 STM32F072xB

The RTC is an independent BCD timer/counter. Its main features are the following:

• calendar with subseconds, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format

• automatic correction for 28, 29 (leap year), 30, and 31 day of the month

• programmable alarm with wake up from Stop and Standby mode capability

• Periodic wakeup unit with programmable resolution and period.

• on-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to

synchronize the RTC with a master clock

• digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal inaccuracy

• Three anti-tamper detection pins with programmable filter. The MCU can be woken up from Stop and Standby modes on tamper event detection

• timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be woken up from Stop and Standby modes on timestamp event detection

• reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision

The RTC clock sources can be:

• a 32.768 kHz external crystal

• a resonator or oscillator

• the internal low-power RC oscillator (typical frequency of 40 kHz)

• the high-speed external clock divided by 32

3.16 Inter-integrated circuit interface (I2C)

Up to two I2C interfaces (I2C1 and I2C2) can operate in multimaster or slave modes. Both can support Standard mode (up to 100 kbit/s), Fast mode (up to 400 kbit/s) and Fast Mode Plus (up to 1 Mbit/s) with 20

Both support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (two addresses, one with configurable mask). They also include programmable analog and digital noise filters.

Aspect Analog filter Digital filter

Pulse width of

suppressed spikes

Benefits Available in Stop mode

Drawbacks

Table 8. Comparison of I2C analog and digital filters

In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts

mA output drive on most of the associated I/Os.

 50 ns

Variations depending on

temperature, voltage, process

Programmable length from 1 to 15

I2Cx peripheral clocks

–Extra filtering capability vs.

standard requirements

–Stable length

Wakeup from Stop on address

match is not available when digital

filter is enabled.

24/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Functional overview

verifications and ALERT protocol management. I2C1 also has a clock domain independent from the CPU clock, allowing the I2C1 to wake up the MCU from Stop mode on address match.

The I2C peripherals can be served by the DMA controller.

Refer to Tab le 9 for the differences between I2C1 and I2C2.

Table 9. STM32F072x8/xB I2C implementation

I2C features

7-bit addressing mode X X

10-bit addressing mode X X

Standard mode (up to 100 kbit/s) X X

Fast mode (up to 400 kbit/s) X X

Fast Mode Plus (up to 1 Mbit/s) with 20 mA output drive I/Os X X

Independent clock X -

SMBus X -

Wakeup from STOP X -

1. X = supported.

(1)

I2C1 I2C2

3.17 Universal synchronous/asynchronous receiver/transmitter (USART)

The device embeds four universal synchronous/asynchronous receivers/transmitters (USART1, USART2, USART3, USART4) which communicate at speeds of up to 6

They provide hardware management of the CTS, RTS and RS485 DE signals, multiprocessor communication mode, master synchronous communication and single-wire half-duplex communication mode. USART1 and USART2 support also SmartCard communication (ISO 7816), IrDA SIR ENDEC, LIN Master/Slave capability and auto baud rate feature, and have a clock domain independent of the CPU clock, allowing to wake up the MCU from Stop mode.

The USART interfaces can be served by the DMA controller.

Table 10. STM32F072x8/xB USART implementation

USART modes/features

Hardware flow control for modem X X

Continuous communication using DMA X X

Multiprocessor communication X X

Synchronous mode X X

Smartcard mode X -

Single-wire half-duplex communication X X

(1)

USART1 and

USART2

Mbit/s.

USART3 and

USART4

DS9826 Rev 6 25/128

Functional overview STM32F072x8 STM32F072xB

Table 10. STM32F072x8/xB USART implementation (continued)

USART modes/features

IrDA SIR ENDEC block X -

LIN mode X -

Dual clock domain and wakeup from Stop mode X -

Receiver timeout interrupt X -

Modbus communication X -

Auto baud rate detection X -

Driver Enable X X

1. X = supported.

(1)

USART1 and

USART2

USART3 and

USART4

3.18 Serial peripheral interface (SPI) / Inter-integrated sound interface (I

Two SPIs are able to communicate up to 18 Mbit/s in slave and master modes in full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits.

Two standard I2S interfaces (multiplexed with SPI1 and SPI2 respectively) supporting four different audio standards can operate as master or slave at half-duplex communication mode. They can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data resolution and synchronized by a specific signal. Audio sampling frequency from 8 kHz up to 192 kHz can be set by an 8-bit programmable linear prescaler. When operating in master mode, they can output a clock for an external audio component at 256 times the sampling frequency.

Table 11. STM32F072x8/xB SPI/I2S implementation

SPI features

(1)

SPI1 and SPI2

Hardware CRC calculation X

Rx/Tx FIFO X

NSS pulse mode X

S mode X

TI mode X

1. X = supported.

3.19 High-definition multimedia interface (HDMI) - consumer electronics control (CEC)

The device embeds a HDMI-CEC controller that provides hardware support for the Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).

This protocol provides high-level control functions between all audiovisual products in an environment. It is specified to operate at low speeds with minimum processing and memory

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STM32F072x8 STM32F072xB Functional overview

overhead. It has a clock domain independent from the CPU clock, allowing the HDMI_CEC controller to wakeup the MCU from Stop mode on data reception.

3.20 Controller area network (CAN)

The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and 14 scalable filter banks.

3.21 Universal serial bus (USB)

The STM32F072x8/xB embeds a full-speed USB device peripheral compliant with the USB specification version 2.0. The internal USB PHY supports USB FS signaling, embedded DP pull-up and also battery charging detection according to Battery Charging Specification Revision 1.2. The USB interface implements a full-speed (12 Mbit/s) function interface with added support for USB 2.0 Link Power Management. It has software-configurable endpoint setting with packet memory up-to 1 KB (the last 256 byte are used for CAN peripheral if enabled) and suspend/resume support. It requires a precise 48 MHz clock which can be generated from the internal main PLL (the clock source must use an HSE crystal oscillator) or by the internal 48 MHz oscillator in automatic trimming mode. The synchronization for this oscillator can be taken from the USB data stream itself (SOF signalization) which allows crystal-less operation.

3.22 Clock recovery system (CRS)

The STM32F072x8/xB embeds a special block which allows automatic trimming of the internal 48 operational range. This automatic trimming is based on the external synchronization signal, which could be either derived from USB SOF signalization, from LSE oscillator, from an external signal on CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also possible to combine automatic trimming with manual trimming action.

MHz oscillator to guarantee its optimal accuracy over the whole device

3.23 Serial wire debug port (SW-DP)

An Arm SW-DP interface is provided to allow a serial wire debugging tool to be connected to the MCU.

DS9826 Rev 6 27/128

MS31409V2

AHB2

0xFFFF FFFF

Peripherals

SRAM

Flash memory

Reserved

System memory

Option Bytes

0xE010 0000

Flash, system

memory or SRAM,

depending on BOOT

configuration

0x0000 0000

0xE000 0000

0xC000 0000

0xA000 0000

0x8000 0000

0x6000 0000

0x4000 0000

0x2000 0000

0x0000 0000

0x0800 0000

0x0802 0000

0x1FFF C800

0x1FFF F800

0x1FFF FFFF

0x0002 0000

Reserved

CODE

APB

Reserved

0x4000 0000

0x4000 8000

0x4001 0000

0x4001 8000

Reserved

0x4002 0000

AHB1

0x4800 0000

Reserved

0x4800 17FF

0x4002 43FF

Cortex-M0 internal

peripherals

Reserved

0x1FFF FC00

Reserved

Memory mapping STM32F072x8 STM32F072xB

4 Memory mapping

To the difference of STM32F072xB memory map in Figure 3, the two bottom code memory spaces of STM32F072x8 end at 0x0000 FFFF and 0x0800 FFFF, respectively.

Figure 3. STM32F072xB memory map

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STM32F072x8 STM32F072xB Memory mapping

Table 12. Peripheral register boundary addresses

Bus Boundary address Size Peripheral

- 0x4800 1800 - 0x5FFF FFFF ~384 MB Reserved

0x4800 1400 - 0x4800 17FF 1 KB GPIOF

0x4800 1000 - 0x4800 13FF 1 KB GPIOE

0x4800 0C00 - 0x4800 0FFF 1 KB GPIOD

AHB2

0x4800 0800 - 0x4800 0BFF 1 KB GPIOC

0x4800 0400 - 0x4800 07FF 1 KB GPIOB

0x4800 0000 - 0x4800 03FF 1 KB GPIOA

- 0x4002 4400 - 0x47FF FFFF ~128 MB Reserved

0x4002 4000 - 0x4002 43FF 1 KB TSC

0x4002 3400 - 0x4002 3FFF 3 KB Reserved

0x4002 3000 - 0x4002 33FF 1 KB CRC

0x4002 2400 - 0x4002 2FFF 3 KB Reserved

AHB1

0x4002 2000 - 0x4002 23FF 1 KB Flash memory interface

0x4002 1400 - 0x4002 1FFF 3 KB Reserved

0x4002 1000 - 0x4002 13FF 1 KB RCC

0x4002 0400 - 0x4002 0FFF 3 KB Reserved

0x4002 0000 - 0x4002 03FF 1 KB DMA

- 0x4001 8000 - 0x4001 FFFF 32 KB Reserved

0x4001 5C00 - 0x4001 7FFF 9 KB Reserved

0x4001 5800 - 0x4001 5BFF 1 KB DBGMCU

0x4001 4C00 - 0x4001 57FF 3 KB Reserved

0x4001 4800 - 0x4001 4BFF 1 KB TIM17

0x4001 4400 - 0x4001 47FF 1 KB TIM16

0x4001 4000 - 0x4001 43FF 1 KB TIM15

0x4001 3C00 - 0x4001 3FFF 1 KB Reserved

0x4001 3800 - 0x4001 3BFF 1 KB USART1

0x4001 3400 - 0x4001 37FF 1 KB Reserved

APB

0x4001 3000 - 0x4001 33FF 1 KB SPI1/I2S1

0x4001 2C00 - 0x4001 2FFF 1 KB TIM1

0x4001 2800 - 0x4001 2BFF 1 KB Reserved

0x4001 2400 - 0x4001 27FF 1 KB ADC

0x4001 0800 - 0x4001 23FF 7 KB Reserved

0x4001 0400 - 0x4001 07FF 1 KB EXTI

0x4001 0000 - 0x4001 03FF 1 KB SYSCFG + COMP

- 0x4000 8000 - 0x4000 FFFF 32 KB Reserved

DS9826 Rev 6 29/128

Memory mapping STM32F072x8 STM32F072xB

Table 12. Peripheral register boundary addresses (continued)

Bus Boundary address Size Peripheral

0x4000 7C00 - 0x4000 7FFF 1 KB Reserved

0x4000 7800 - 0x4000 7BFF 1 KB CEC

0x4000 7400 - 0x4000 77FF 1 KB DAC

0x4000 7000 - 0x4000 73FF 1 KB PWR

0x4000 6C00 - 0x4000 6FFF 1 KB CRS

0x4000 6800 - 0x4000 6BFF 1 KB Reserved

0x4000 6400 - 0x4000 67FF 1 KB BxCAN

0x4000 6000 - 0x4000 63FF 1 KB USB/CAN RAM

0x4000 5C00 - 0x4000 5FFF 1 KB USB

0x4000 5800 - 0x4000 5BFF 1 KB I2C2

0x4000 5400 - 0x4000 57FF 1 KB I2C1

0x4000 5000 - 0x4000 53FF 1 KB Reserved

0x4000 4C00 - 0x4000 4FFF 1 KB USART4

0x4000 4800 - 0x4000 4BFF 1 KB USART3

0x4000 4400 - 0x4000 47FF 1 KB USART2

APB

0x4000 3C00 - 0x4000 43FF 2 KB Reserved

0x4000 3800 - 0x4000 3BFF 1 KB SPI2

0x4000 3400 - 0x4000 37FF 1 KB Reserved

0x4000 3000 - 0x4000 33FF 1 KB IWDG

0x4000 2C00 - 0x4000 2FFF 1 KB WWDG

0x4000 2800 - 0x4000 2BFF 1 KB RTC

0x4000 2400 - 0x4000 27FF 1 KB Reserved

0x4000 2000 - 0x4000 23FF 1 KB TIM14

0x4000 1800 - 0x4000 1FFF 2 KB Reserved

0x4000 1400 - 0x4000 17FF 1 KB TIM7

0x4000 1000 - 0x4000 13FF 1 KB TIM6

0x4000 0800 - 0x4000 0FFF 2 KB Reserved

0x4000 0400 - 0x4000 07FF 1 KB TIM3

0x4000 0000 - 0x4000 03FF 1 KB TIM2

30/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Pinouts and pin descriptions

MSv33167V4

Top view

I/O supplied from VDDIO2

87654321 1211109

PE3

PE4

PC0

PF2

VSSA

PF3

VDDA

PE1

PE5

PE2

PE6

VBAT

PF9

PF10

NRST

PC1

PC3

PA0

PA1

PB8

PE0

PB9

VSS

VDD

PC2

PA2

PA3

PA4

BOOT0

PB7

VDD

PA5

PA6

PA7

PD7

PB6

PB5

PC4

PC5

PB0

PD5

PD6

PB2

PB1

PB4

PD4

PE8

PE7

PB3

PD3

PD2

PD9

PE10

PE9

PA15

PD1

PD0

PD8

PE12

PE11

PA14

PC12

PC11

PC8

PA9

PD15

PD12

PB15

PB10

PE13

PA13

PC10

PF6

PA8

PC7

PD14

PD11

PB14

PB11

PE14

VDDIO2

PA12

PA11

PA10

PC9

PC6

PD13

PD10

PB13

PB12

PE15

VSS

VDD

PC13

PC14-

OSC32_

PC15-

OSC32_

OUT

PF0-

OSC_

PF1-

OSC_

OUT

VSS

UFBGA100

5 Pinouts and pin descriptions

Figure 4. UFBGA100 package pinout

DS9826 Rev 6 31/128

Pinouts and pin descriptions STM32F072x8 STM32F072xB

MSv31410V2

Top view

I/O supplied from VDDIO2

LQFP100

787679

878685

384037

293031

919089

464845

444943

969594

100

VDDIO2 VSS PF6 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12

PA3

VSS

VDD

PA4

PA5

PA6

PA7

PC4

PC5

PB0

PB1

PB2

PE7

PE8

PE9

PE10

PE11

PE12

PE13

PE14

PE15

PB10

PB11

VSS

VDD

PE2 PE3 PE4 PE5 PE6

VBAT

PC14-OSC32_IN

PC15-OSC32_OUT

PF9

PF10

PF0-OSC_IN

NRST

PC0 PC1 PC2 PC3

PF2

VSSA

PF3

VDDA

PA0 PA1 PA2

PC13

PF1-OSC_OUT

VDD

VSS

PE1

PE0

PB9

PB8

BOOT0

PB7

PB6

PB5

PB4

PB3

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

PC12

PC11

PC10

PA15

PA14

Figure 5. LQFP100 package pinout

32/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Pinouts and pin descriptions

MSv39735V1

Top view

UFBGA64

I/O supplied from VDDIO2

87654321

PC14-

OSC32_

VDDA

PC15-

OSC32_

OUT

PF0-

OSC_

PF1-

OSC_

OUT

PC3

NRST

VSSA

VDD

PC2

PC13

PC1

PA1

PA0

VSS

VBAT

PA4

PA3

PB6

PB9

PB7

PC0

PB8

PA2

PA7

PA6

BOOT0

PB4

PB5

VSS

PA5

VDD

PB1

PC4

PB3

PB0

VDD

VSS

PD2

PC12

PC5

PA10

VDDIO2

VSS

PB2

PA15

PC11

PC6

PB11

PB10

PB15

PA14

PC10

PA9

PA8

PC7

PB14

PB13

PB12

PA13

PA12

PA11

PC9

PC8

Figure 6. UFBGA64 package pinout

DS9826 Rev 6 33/128

Pinouts and pin descriptions STM32F072x8 STM32F072xB

MSv31411V2

Top view

LQFP64

514952

605958

222421

252627

293031

646362

VBAT

PC14-OSC32_IN

PF0-OSC_IN

NRST

PC0 PC1 PC2 PC3

VSSA

VDDA

PA0 PA1 PA2

VDD

PB9

PB8

BOOT0

PB7

PB6

PB5

PB4

PB3

PD2

PC12

PC11

PC10

PA15

PA14

VDDIO2 VSS PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12

PC13

VSS

PF1-OSC_OUT

PC15-OSC32_OUT

PA5

PA7

PC4

PC5

PB0

PB1

PB2

PB10

PB11

VSS

VDD

PA6

PA4

VDD

VSS

PA3

I/O supplied from VDDIO2

MSv31412V2

PA3

PA4

PA5

PA6

PA7

PB0

PB1

PB2

PB10

PB11

VSS

VDD

VBAT

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

PF0-OSC_IN

PF1-OSC_OUT

NRST VSSA VDDA

PA0 PA1 PA2

VDDIO2 VSS PA13 PA12 PA11 PA10 PA9 PA8 PB15 PB14 PB13 PB12

PA14

PA15

PB3

PB4

PB5

PB6

PB7

BOOT0

PB8

PB9

VSS

VDD

Top view

LQFP48

393740

484746

222421

131415

I/O supplied from VDDIO2

Figure 7. LQFP64 package pinout

Figure 8. LQFP48 package pinout

34/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Pinouts and pin descriptions

MSv32166V2

I/O supplied from VDDIO2

Top view

Exposed pad

UFQFPN48

484746454443424140

131415161718192021

222324

393837

VBAT

NRST

VSSA

VDDA

PA0

PA1

PC13

PC14-OSC32_IN

PF0-OSC_IN

PF1-OSC_OUT

PC15-OSC32_OUT

PA3

PA4

PA5

PA6

PA7

PB0

PB1

PB2

PB10

PB11

VSS

VDD

VDDIO2

VSS

PA13

PA12

PA11

PA10

PA9

PA8

PB15

PB14

PB13

PB12

VDD

VSS

PB9

PB8

BOOT0

PB7

PB6

PB5

PB4

PB3

PA15

PA14

PA2

MSv32165V4

54321

Top view

WLCSP49

I/O supplied from VDDIO2

VDDVSS

VBAT

PC14-

OSC32_

PC15-

OSC32_

OUT

PF0-

OSC_

PF1-

OSC_

OUT

BOOT0PB4PB3PA15PA14

VSS VDDIO2 PA13 PB5 PB8

PB9PB6PA12PA10PA11

PC13PB7VSSPA 9PA8

VSSA

PA2PA 3PB10PB12PB15

NRST

PB14 VDD PA7 PA6 PA5 PA0 VDDA

PB13 PB11 PB2 PB1 PB0 PA4 PA1

Figure 9. UFQFPN48 package pinout

xposed pa

Figure 10. WLCSP49 package pinout

1. The above figure shows the package in top view, changing from bottom view in the previous document

versions.

DS9826 Rev 6 35/128

Pinouts and pin descriptions STM32F072x8 STM32F072xB

Pin name

I/O structure

functions

Table 13. Legend/abbreviations used in the pinout table

Name Abbreviation Definition

Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name

S Supply pin

Pin type

I Input-only pin

I/O Input / output pin

FT 5 V-tolerant I/O

FTf 5 V-tolerant I/O, FM+ capable

TTa 3.3 V-tolerant I/O directly connected to ADC

TC Standard 3.3 V I/O

B Dedicated BOOT0 pin

RST Bidirectional reset pin with embedded weak pull-up resistor

Notes

Alternate functions

Additional

functions

Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset.

Functions selected through GPIOx_AFR registers

Functions directly selected/enabled through peripheral registers

UFBGA100

Pin numbers

LQFP100

UFBGA64

LQFP64

Table 14. STM32F072x8/xB pin definitions

Pin name

(function upon

reset)

WLCSP49

type

Notes

Alternate functions

I/O structure

Pin functions

Additional

functions

LQFP48/UFQFPN48

B2 1 - - - - PE2 I/O FT -

A1 2 - - - - PE3 I/O FT -

B1 3 - - - - PE4 I/O FT -

C2 4 - - - - PE5 I/O FT -

D2 5 - - - - PE6 I/O FT - TIM3_CH4

TSC_G7_IO1,

TIM3_ETR

TSC_G7_IO2,

TIM3_CH1

TSC_G7_IO3,

TIM3_CH2

TSC_G7_IO4,

TIM3_CH3

WKUP3,

RTC_TAMP3

E26B21 1B7 VBAT S - - Backup power supply

36/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Pinouts and pin descriptions

Table 14. STM32F072x8/xB pin definitions (continued)

UFBGA100

Pin numbers

LQFP100

UFBGA64

Pin name

(function upon

reset)

LQFP64

WLCSP49

type

I/O structure

Notes

Alternate functions

Pin functions

Additional

functions

LQFP48/UFQFPN48

WKUP2,

RTC_TAMP1,

RTC_TS,

C1 7 A2 2 2 D5 PC13 I/O TC

(1)

(2)

RTC_OUT

D1 8 A1 3 3 C7

PC14-

OSC32_IN

I/O TC

(1)

(2)

- OSC32_IN

(PC14)

E1 9 B1 4 4 C6

PC15-

OSC32_OUT

I/O TC

(1)

(2)

- OSC32_OUT

(PC15)

F2 10 - - - - PF9 I/O FT - TIM15_CH1 -

G2 11 - - - PF10 I/O FT - TIM15_CH2 -

F1 12 C1 5 5 D7

PF0-OSC_IN

(PF0)

I/O FT - CRS_ SYNC OSC_IN

G1 13 D1 6 6 D6

H2 14 E1 7 7 E7 NRST I/O RST -

PF1-OSC_OUT

(PF1)

I/O FT - - OSC_OUT

Device reset input / internal reset output

(active low)

H1 15 E3 8 - - PC0 I/O TTa - EVENTOUT ADC_IN10

J2 16 E2 9 - - PC1 I/O TTa - EVENTOUT ADC_IN11

J3 17 F2 10 - - PC2 I/O TTa -

K2 18 G1 11 - - PC3 I/O TTa -

SPI2_MISO, I2S2_MCK,

EVENTOUT

SPI2_MOSI, I2S2_SD,

EVENTOUT

ADC_IN12

ADC_IN13

J1 19 - - - - PF2 I/O FT - EVENTOUT WKUP8

K1 20 F1 12 8 E6 VSSA S - - Analog ground

21 H1 13 9 F7 VDDA S - - Analog power supply

L1 22 - - - - PF3 I/O FT - EVENTOUT

L2 23 G2 14 10 F6 PA0 I/O TTa -

USART2_CTS,

TIM2_CH1_ETR,

COMP1_OUT, TSC_G1_IO1,

USART4_TX

RTC_ TAMP2,

WKUP1,

ADC_IN0,

COMP1_INM6

DS9826 Rev 6 37/128

Pinouts and pin descriptions STM32F072x8 STM32F072xB

Table 14. STM32F072x8/xB pin definitions (continued)

Pin numbers

Pin name

(function upon

reset)

LQFP100

UFBGA100

M2 24 H2 15 11 G7 PA1 I/O TTa -

K3 25 F3 16 12 E5 PA2 I/O TTa -

L3 26 G3 17 13 E4 PA3 I/O TTa -

LQFP64

UFBGA64

WLCSP49

LQFP48/UFQFPN48

type

I/O structure

Pin functions

Notes

Alternate functions

USART2_RTS,

TIM2_CH2, TIM15_CH1N, TSC_G1_IO2,

USART4_RX,

EVENTOUT

USART2_TX,

COMP2_OUT,

TIM2_CH3,

TIM15_CH1,

TSC_G1_IO3

USART2_RX,TIM2_CH4,

TIM15_CH2,

TSC_G1_IO4

Additional

functions

ADC_IN1,

COMP1_INP

ADC_IN2,

COMP2_INM6,

WKUP4

ADC_IN3,

COMP2_INP

D3 27 C2 18 - - VSS S - - Ground

H3 28 D2 19 - - VDD S - - Digital power supply

M3 29 H3 20 14 G6 PA4 I/O TTa -

K4 30 F4 21 15 F5 PA5 I/O TTa -

L4 31 G4 22 16 F4 PA6 I/O TTa -

M4 32 H4 23 17 F3 PA7 I/O TTa -

SPI1_NSS, I2S1_WS,

TIM14_CH1,

TSC_G2_IO1,

USART2_CK

SPI1_SCK, I2S1_CK,

CEC,

TIM2_CH1_ETR,

TSC_G2_IO2

SPI1_MISO, I2S1_MCK,

TIM3_CH1, TIM1_BKIN,

TIM16_CH1, COMP1_OUT, TSC_G2_IO3,

EVENTOUT,

USART3_CTS

SPI1_MOSI, I2S1_SD,

TIM3_CH2, TIM14_CH1,

TIM1_CH1N,

TIM17_CH1, COMP2_OUT, TSC_G2_IO4,

EVENTOUT

COMP1_INM4, COMP2_INM4,

DAC_OUT1

COMP1_INM5, COMP2_INM5,

DAC_OUT2

ADC_IN4,

ADC_IN5,

ADC_IN6

ADC_IN7

38/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Pinouts and pin descriptions

Table 14. STM32F072x8/xB pin definitions (continued)

UFBGA100

Pin numbers

LQFP100

UFBGA64

Pin name

(function upon

reset)

LQFP64

WLCSP49

type

I/O structure

Notes

Alternate functions

Pin functions

Additional

functions

LQFP48/UFQFPN48

K5 33 H5 24 - - PC4 I/O TTa -

L5 34 H6 25 - - PC5 I/O TTa -

EVENTOUT,

USART3_TX

TSC_G3_IO1,

USART3_RX

ADC_IN14

ADC_IN15,

WKUP5

TIM3_CH3, TIM1_CH2N,

M5 35 F5 26 18 G5 PB0 I/O TTa -

TSC_G3_IO2,

EVENTOUT,

ADC_IN8

USART3_CK

TIM3_CH4,

USART3_RTS,

M6 36 G5 27 19 G4 PB1 I/O TTa -

TIM14_CH1,

ADC_IN9

TIM1_CH3N,

TSC_G3_IO3

L6 37 G6 28 20 G3 PB2 I/O FT - TSC_G3_IO4 -

M7 38 - - - - PE7 I/O FT - TIM1_ETR -

L7 39 - - - - PE8 I/O FT - TIM1_CH1N -

M840---- PE9 I/OFT- TIM1_CH1 -

L8 41 - - - - PE10 I/O FT - TIM1_CH2N -

M942---- PE11 I/OFT- TIM1_CH2 -

L9 43 - - - - PE12 I/O FT -

M10 44 - - - - PE13 I/O FT -

M11 45 - - - - PE14 I/O FT -

M12 46 - - - - PE15 I/O FT -

SPI1_NSS, I2S1_WS,

TIM1_CH3N

SPI1_SCK, I2S1_CK,

TIM1_CH3

SPI1_MISO, I2S1_MCK,

TIM1_CH4

SPI1_MOSI, I2S1_SD,

TIM1_BKIN

SPI2_SCK, I2C2_SCL,

L10 47 G7 29 21 E3 PB10 I/O FT -

USART3_TX, CEC,

TSC_SYNC, TIM2_CH3

USART3_RX,

TIM2_CH4,

L1148H730 22G2 PB11 I/O FT -

EVENTOUT,

TSC_G6_IO1,

I2C2_SDA

F1249D531 23D3 VSS S - - Ground

DS9826 Rev 6 39/128

Pinouts and pin descriptions STM32F072x8 STM32F072xB

Table 14. STM32F072x8/xB pin definitions (continued)

UFBGA100

Pin numbers

LQFP100

UFBGA64

Pin name

(function upon

reset)

LQFP64

WLCSP49

type

I/O structure

Notes

Alternate functions

Pin functions

Additional

LQFP48/UFQFPN48

G12 50 E5 32 24 F2 VDD S - - Digital power supply

TIM1_BKIN,

TIM15_BKIN,

L12 51 H8 33 25 E2 PB12 I/O FT -

SPI2_NSS, I2S2_WS,

USART3_CK,

TSC_G6_IO2,

EVENTOUT

SPI2_SCK, I2S2_CK,

I2C2_SCL,

K12 52 G8 34 26 G1 PB13 I/O FTf -

USART3_CTS,

TIM1_CH1N,

TSC_G6_IO3

SPI2_MISO, I2S2_MCK,

I2C2_SDA,

K11 53 F8 35 27 F1 PB14 I/O FTf -

USART3_RTS,

TIM1_CH2N,

TIM15_CH1,

TSC_G6_IO4

SPI2_MOSI, I2S2_SD,

K10 54 F7 36 28 E1 PB15 I/O FT -

TIM1_CH3N, TIM15_CH1N,

RTC_REFIN

TIM15_CH2

functions

WKUP7,

K9 55 - - - - PD8 I/O FT - USART3_TX -

K8 56 - - - - PD9 I/O FT - USART3_RX -

J12 57 - - - - PD10 I/O FT - USART3_CK -

J11 58 - - - - PD11 I/O FT - USART3_CTS -

J10 59 - - - - PD12 I/O FT -

USART3_RTS,

TSC_G8_IO1

H12 60 - - - - PD13 I/O FT - TSC_G8_IO2 -

H11 61 - - - - PD14 I/O FT - TSC_G8_IO3 -

H10 62 - - - - PD15 I/O FT -

E12 63 F6 37 - - PC6 I/O FT

E1164E738 - - PC7 I/O FT

E1065E839 - - PC8 I/O FT

D1266D840 - - PC9 I/O FT

(3)

TSC_G8_IO4,

CRS_SYNC

TIM3_CH1 -

TIM3_CH2 -

TIM3_CH3 -

TIM3_CH4 -

40/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Pinouts and pin descriptions

Table 14. STM32F072x8/xB pin definitions (continued)

UFBGA100

Pin numbers

LQFP100

UFBGA64

Pin name

(function upon

reset)

LQFP64

WLCSP49

type

I/O structure

Notes

Alternate functions

Pin functions

LQFP48/UFQFPN48

USART1_CK,

D1167D741 29D1 PA8 I/O FT

(3)

TIM1_CH1,

EVENTOUT, MCO,

CRS_SYNC

USART1_TX,

D1068C74230D2 PA9 I/O FT

(3)

TIM1_CH2,

TIM15_BKIN,

TSC_G4_IO1

USART1_RX,

C1269C64331C2 PA10 I/O FT

(3)

TIM1_CH3,

TIM17_BKIN,

TSC_G4_IO2

CAN_RX,

USART1_CTS,

B1270C844 32C1 PA11 I/O FT

(3)

TIM1_CH4, COMP1_OUT, TSC_G4_IO3,

EVENTOUT

CAN_TX, USART1_RTS,

TIM1_ETR, COMP2_OUT,

A1271B84533C3 PA12 I/O FT

(3)

TSC_G4_IO4,

EVENTOUT

A1172A84634B3 PA13 I/O FT

C11 73 - - - - PF6 I/O FT

(3)

(4)

(3)

IR_OUT, SWDIO,

USB_NOE

F1174D64735B1 VSS S - - Ground

G11 75 E6 48 36 B2 VDDIO2 S - - Digital power supply

(3)

A1076A74937A1 PA14 I/O FT

USART2_TX, SWCLK -

(4)

Additional

functions

USB_DM

USB_DP

A9 77 A6 50 38 A2 PA15 I/O FT

B1178B751 - - PC10 I/O FT

DS9826 Rev 6 41/128

SPI1_NSS, I2S1_WS,

(3)

USART2_RX,

USART4_RTS,

TIM2_CH1_ETR,

EVENTOUT

(3)

USART3_TX,

USART4_TX

Pinouts and pin descriptions STM32F072x8 STM32F072xB

Table 14. STM32F072x8/xB pin definitions (continued)

Pin numbers

UFBGA100

LQFP100

LQFP64

UFBGA64

Pin name

(function upon

reset)

WLCSP49

type

Notes

I/O structure

LQFP48/UFQFPN48

C1079B652 - - PC11 I/O FT

B1080C553 - - PC12 I/O FT

C981---- PD0 I/OFT

B982---- PD1 I/OFT

C8 83 B5 54 - - PD2 I/O FT

(3)

B884---- PD3 I/OFT-

B785---- PD4 I/OFT-

Pin functions

Alternate functions

USART3_RX,

USART4_RX

USART3_CK,

USART4_CK

SPI2_NSS, I2S2_WS,

CAN_RX

SPI2_SCK, I2S2_CK,

CAN_TX

USART3_RTS,

TIM3_ETR

SPI2_MISO, I2S2_MCK,

USART2_CTS

SPI2_MOSI, I2S2_SD,

USART2_RTS

Additional

functions

A6 86 - - - - PD5 I/O FT - USART2_TX -

B6 87 - - - - PD6 I/O FT - USART2_RX -

A5 88 - - - - PD7 I/O FT - USART2_CK -

SPI1_SCK, I2S1_CK,

A8 89 A5 55 39 A3 PB3 I/O FT -

TIM2_CH2, TSC_G5_IO1,

EVENTOUT

SPI1_MISO, I2S1_MCK,

TIM17_BKIN,

A7 90 A4 56 40 A4 PB4 I/O FT -

TIM3_CH1, TSC_G5_IO2,

EVENTOUT

SPI1_MOSI, I2S1_SD,

C5 91 C4 57 41 B4 PB5 I/O FT -

I2C1_SMBA,

TIM16_BKIN,

WKUP6

TIM3_CH2

I2C1_SCL, USART1_TX,

B5 92 D3 58 42 C4 PB6 I/O FTf -

TIM16_CH1N,

TSC_G5_I03

42/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Pinouts and pin descriptions

Table 14. STM32F072x8/xB pin definitions (continued)

UFBGA100

Pin numbers

LQFP100

UFBGA64

Pin name

(function upon

reset)

LQFP64

WLCSP49

type

I/O structure

Notes

Alternate functions

Pin functions

Additional

functions

LQFP48/UFQFPN48

I2C1_SDA,

USART1_RX,

B4 93 C3 59 43 D4 PB7 I/O FTf -

USART4_CTS,

TIM17_CH1N,

TSC_G5_IO4

A4 94 B4 60 44 A5 BOOT0 I B - Boot memory selection

I2C1_SCL, CEC,

A3 95 B3 61 45 B5 PB8 I/O FTf -

TIM16_CH1, TSC_SYNC,

CAN_RX

SPI2_NSS, I2S2_WS,

I2C1_SDA, IR_OUT,

B3 96 A3 62 46 C5 PB9 I/O FTf -

TIM17_CH1,

EVENTOUT,

CAN_TX

C3 97 - - - - PE0 I/O FT - EVENTOUT, TIM16_CH1 -

A2 98 - - - - PE1 I/O FT - EVENTOUT, TIM17_CH1 -

D3 99 D4 63 47 A6 VSS S - - Ground

C4 100 E4 64 48 A7 VDD S - - Digital power supply

1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:

- The speed should not exceed 2 MHz with a maximum load of 30 pF.

- These GPIOs must not be used as current sources (e.g. to drive an LED).

2. After the first RTC domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to the RTC domain and RTC register descriptions in the reference manual.

3. PC6, PC7, PC8, PC9, PA8, PA9, PA10, PA11, PA12, PA13, PF6, PA14, PA15, PC10, PC11, PC12, PD0, PD1 and PD2 I/Os are supplied by VDDIO2.

4. After reset, these pins are configured as SWDIO and SWCLK alternate functions, and the internal pull-up on the SWDIO pin and the internal pull-down on the SWCLK pin are activated.

DS9826 Rev 6 43/128

44/128 DS9826 Rev 6

Table 15. Alternate functions selected through GPIOA_AFR registers for port A

Pin name AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

PA0 - USART2_CTS TIM2_CH1_ETR TSC_G1_IO1 USART4_TX - - COMP1_OUT

PA1 EVENTOUT USART2_RTS TIM2_CH2 TSC_G1_IO2 USART4_RX TIM15_CH1N - -

PA2 TIM15_CH1 USART2_TX TIM2_CH3 TSC_G1_IO3 - - - COMP2_OUT

PA3 TIM15_CH2 USART2_RX TIM2_CH4 TSC_G1_IO4 - - - -

PA4 SPI1_NSS, I2S1_WS USART2_CK - TSC_G2_IO1 TIM14_CH1 - - -

PA5 SPI1_SCK, I2S1_CK CEC TIM2_CH1_ETR TSC_G2_IO2 - - - -

PA6 SPI1_MISO, I2S1_MCK TIM3_CH1 TIM1_BKIN TSC_G2_IO3 USART3_CTS TIM16_CH1 EVENTOUT COMP1_OUT

PA7 SPI1_MOSI, I2S1_SD TIM3_CH2 TIM1_CH1N TSC_G2_IO4 TIM14_CH1 TIM17_CH1 EVENTOUT COMP2_OUT

PA8 MCO USART1_CK TIM1_CH1 EVENTOUT CRS_SYNC - - -

PA9 TIM15_BKIN USART1_TX TIM1_CH2 TSC_G4_IO1 - - - -

PA10 TIM17_BKIN USART1_RX TIM1_CH3 TSC_G4_IO2 - - - -

PA11 EVENTOUT USART1_CTS TIM1_CH4 TSC_G4_IO3 CAN_RX - - COMP1_OUT

PA12 EVENTOUT USART1_RTS TIM1_ETR TSC_G4_IO4 CAN_TX - - COMP2_OUT

PA13 SWDIO IR_OUT USB_NOE - - - - -

PA14 SWCLK USART2_TX - - - - - -

PA15 SPI1_NSS, I2S1_WS USART2_RX TIM2_CH1_ETR EVENTOUT USART4_RTS - - -

STM32F072x8 STM32F072xB

DS9826 Rev 6 45/128

Table 16. Alternate functions selected through GPIOB_AFR registers for port B

Pin name AF0 AF1 AF2 AF3 AF4 AF5

PB0 EVENTOUT TIM3_CH3 TIM1_CH2N TSC_G3_IO2 USART3_CK -

PB1 TIM14_CH1 TIM3_CH4 TIM1_CH3N TSC_G3_IO3 USART3_RTS -

PB2 - - - TSC_G3_IO4 - -

PB3 SPI1_SCK, I2S1_CK EVENTOUT TIM2_CH2 TSC_G5_IO1 - -

PB4 SPI1_MISO, I2S1_MCK TIM3_CH1 EVENTOUT TSC_G5_IO2 - TIM17_BKIN

PB5 SPI1_MOSI, I2S1_SD TIM3_CH2 TIM16_BKIN I2C1_SMBA - -

PB6 USART1_TX I2C1_SCL TIM16_CH1N TSC_G5_IO3 - -

PB7 USART1_RX I2C1_SDA TIM17_CH1N TSC_G5_IO4 USART4_CTS -

PB8 CEC I2C1_SCL TIM16_CH1 TSC_SYNC CAN_RX -

PB9 IR_OUT I2C1_SDA TIM17_CH1 EVENTOUT CAN_TX SPI2_NSS, I2S2_WS

PB10 CEC I2C2_SCL TIM2_CH3 TSC_SYNC USART3_TX SPI2_SCK, I2S2_CK

PB11 EVENTOUT I2C2_SDA TIM2_CH4 TSC_G6_IO1 USART3_RX -

PB12 SPI2_NSS, I2S2_WS EVENTOUT TIM1_BKIN TSC_G6_IO2 USART3_CK TIM15_BKIN

PB13 SPI2_SCK, I2S2_CK - TIM1_CH1N TSC_G6_IO3 USART3_CTS I2C2_SCL

PB14 SPI2_MISO, I2S2_MCK TIM15_CH1 TIM1_CH2N TSC_G6_IO4 USART3_RTS I2C2_SDA

PB15 SPI2_MOSI, I2S2_SD TIM15_CH2 TIM1_CH3N TIM15_CH1N - -

STM32F072x8 STM32F072xB

Table 17. Alternate functions selected through GPIOC_AFR registers for port C

Pin name AF0 AF1

PC0 EVENTOUT -

PC1 EVENTOUT -

PC2 EVENTOUT SPI2_MISO, I2S2_MCK

PC3 EVENTOUT SPI2_MOSI, I2S2_SD

PC4 EVENTOUT USART3_TX

PC5 TSC_G3_IO1 USART3_RX

PC6 TIM3_CH1 -

PC7 TIM3_CH2 -

PC8 TIM3_CH3 -

PC9 TIM3_CH4 -

PC10 USART4_TX USART3_TX

PC11 USART4_RX USART3_RX

PC12 USART4_CK USART3_CK

PC13 - -

PC14 - -

PC15 - -

Table 18. Alternate functions selected through GPIOD_AFR registers for port D

Pin name AF0 AF1

PD0 CAN_RX SPI2_NSS, I2S2_WS

PD1 CAN_TX SPI2_SCK, I2S2_CK

PD2 TIM3_ETR USART3_RTS

PD3 USART2_CTS SPI2_MISO, I2S2_MCK

PD4 USART2_RTS SPI2_MOSI, I2S2_SD

PD5 USART2_TX -

PD6 USART2_RX -

PD7 USART2_CK -

PD8 USART3_TX -

PD9 USART3_RX -

PD10 USART3_CK -

PD11 USART3_CTS -

PD12 USART3_RTS TSC_G8_IO1

PD13 - TSC_G8_IO2

PD14 - TSC_G8_IO3

PD15 CRS_SYNC TSC_G8_IO4

46/128 DS9826 Rev 6

STM32F072x8 STM32F072xB

Table 19. Alternate functions selected through GPIOE_AFR registers for port E

Pin name AF0 AF1

PE0 TIM16_CH1 EVENTOUT

PE1 TIM17_CH1 EVENTOUT

PE2 TIM3_ETR TSC_G7_IO1

PE3 TIM3_CH1 TSC_G7_IO2

PE4 TIM3_CH2 TSC_G7_IO3

PE5 TIM3_CH3 TSC_G7_IO4

PE6 TIM3_CH4 -

PE7 TIM1_ETR -

PE8 TIM1_CH1N -

PE9 TIM1_CH1 -

PE10 TIM1_CH2N -

PE11 TIM1_CH2 -

PE12 TIM1_CH3N SPI1_NSS, I2S1_WS

PE13 TIM1_CH3 SPI1_SCK, I2S1_CK

PE14 TIM1_CH4 SPI1_MISO, I2S1_MCK

PE15 TIM1_BKIN SPI1_MOSI, I2S1_SD

Table 20. Alternate functions available on port F

Pin name AF

PF0 CRS_SYNC

PF1 -

PF2 EVENTOUT

PF3 EVENTOUT

PF6 -

PF9 TIM15_CH1

PF10 TIM15_CH2

DS9826 Rev 6 47/128

Electrical characteristics STM32F072x8 STM32F072xB

MS19210V1

MCU pin

C = 50 pF

MS19211V1

MCU pin

6 Electrical characteristics

6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

6.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at T the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3

6.1.2 Typical values

= 25 °C and TA = TAmax (given by

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = V are given only as design guidelines and are not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ±2).

6.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 11.

6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 12.

Figure 11. Pin loading conditions Figure 12. Pin input voltage

= 3.3 V. Th ey

DDA

48/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Electrical characteristics

DDIO2

MSv32190V1

Level shifter

logic

Kernel logic (CPU, Digital & Memories)

Backup circuitry

(LSE, RTC,

Backup registers)

OUT

Regulator

GPIOs

1.65 – 3.6 V

OUT

GPIOs

3 x 100 nF

+1 x 4.7 μF

100 nF

Level shifter

logic

+4.7 μF

DDIO2

3 x V

BAT

CORE

Power switch

DDIO2

DDIO1

ADC/ DAC

Analog:

(RCs, PLL, …)

REF+

REF-

DDA

10 nF +1 μF

DDA

SSA

6.1.6 Power supply scheme

Figure 13. Power supply scheme

Caution: Each power supply pair (V

capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device.

DD/VSS

, V

DDA/VSSA

etc.) must be decoupled with filtering ceramic

DS9826 Rev 6 49/128

Electrical characteristics STM32F072x8 STM32F072xB

MS31999V2

BAT

DDA

DD_VBAT

DDIO2

6.1.7 Current consumption measurement

Figure 14. Current consumption measurement scheme

50/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Electrical characteristics

6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Tab le 21: Voltage characteristics,

Tab le 22: Current characteristics and Table 23: Thermal characteristics may cause

permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 21. Voltage characteristics

Symbol Ratings Min Max Unit

(1)

DD–VSS

DDIO2–VSS

DDA–VSS

DD–VDDA

BAT–VSS

(2)

External main supply voltage - 0.3 4.0 V

External I/O supply voltage - 0.3 4.0 V

External analog supply voltage - 0.3 4.0 V

Allowed voltage difference for VDD > V

-0.4V

DDA

External backup supply voltage - 0.3 4.0 V

Input voltage on FT and FTf pins V

Input voltage on TTa pins V

- 0.3 V

- 0.3 4.0 V

DDIOx

+ 4.0

(3)

BOOT0 0 9.0 V

Input voltage on any other pin VSS - 0.3 4.0 V

| Variations between different V

|V

DDx

- VSS|

SSx

ESD(HBM)

1. All main power (VDD, V supply, in the permitted range.

2. VIN maximum must always be respected. Refer to Table 22: Current characteristics for the maximum allowed injected current values.

3. Valid only if the internal pull-up/pull-down resistors are disabled. If internal pull-up or pull-down resistor is enabled, the maximum limit is 4 V.

Variations between all the different ground pins

Electrostatic discharge voltage (human body model)

) and ground (VSS, V

DDA

power pins - 50 mV

-50mV

see Section 6.3.12: Electrical

sensitivity characteristics

) pins must always be connected to the external power

SSA

DS9826 Rev 6 51/128

Electrical characteristics STM32F072x8 STM32F072xB

Table 22. Current characteristics

Symbol Ratings Max. Unit

(1)

120

-120

100

-100

I

VDD

I

VSS

VDD(PIN)

VSS(PIN)

Total current into sum of all VDD power lines (source)

Total current out of sum of all VSS ground lines (sink)

Maximum current into each VDD power pin (source)

Maximum current out of each VSS ground pin (sink)

Output current sunk by any I/O and control pin 25

IO(PIN)

I

IO(PIN)

Output current source by any I/O and control pin -25

Total output current sunk by sum of all I/Os and control pins

Total output current sourced by sum of all I/Os and control pins

(2)

-80

Total output current sourced by sum of all I/Os supplied by VDDIO2 -40

Injected current on B, FT and FTf pins -5/+0

(3)

INJ(PIN)

I

INJ(PIN)

1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range.

2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.

3. A positive injection is induced by V exceeded. Refer to Table 21: Voltage characteristics for the maximum allowed input voltage values.

4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.

5. On these I/Os, a positive injection is induced by V device. See note

6. When several inputs are submitted to a current injection, the maximum negative injected currents (instantaneous values).

Injected current on TC and RST pin ± 5

Injected current on TTa pins

Total injected current (sum of all I/O and control pins)

> V

DDIOx

(2)

below Table 59: ADC accuracy.

(5)

(6)

while a negative injection is induced by VIN < VSS. I

> V

. Negative injection disturbs the analog performance of the

DDA

I

is the absolute sum of the positive and

INJ(PIN)

(4)

± 5

± 25

must never be

Table 23. Thermal characteristics

Symbol Ratings Value Unit

STG

Storage temperature range –65 to +150 °C

Maximum junction temperature 150 °C

52/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Electrical characteristics

6.3 Operating conditions

6.3.1 General operating conditions

Table 24. General operating conditions

Symbol Parameter Conditions Min Max Unit

HCLK

PCLK

DDIO2

DDA

BAT

Internal AHB clock frequency - 0 48

MHz

Internal APB clock frequency - 0 48

Standard operating voltage - 2.0 3.6 V

I/O supply voltage

Analog operating voltage (ADC and DAC not used)

Analog operating voltage (ADC and DAC used)

Must not be supplied if V is not present

Must have a potential equal to or higher than V

1.65 3.6 V

3.6

2.4 3.6

Backup operating voltage - 1.65 3.6 V

TC and RST I/O –0.3 V

TTa I/O –0.3 V

I/O input voltage

FT and FTf I/O –0.3 5.5

DDIOx

DDA

+0.3

(1)

BOOT0 0 5.5

UFBGA100 - 364

LQFP100 - 476

Power dissipation at T

for suffix 6 or T

(2)

suffix 7

= 85 °C

= 105 °C for

UFBGA64 - 308

LQFP64 - 455

LQFP48 - 370

UFQFPN48 - 625

WLCSP49 - 408

Ambient temperature for the suffix 6 version

Ambient temperature for the suffix 7 version

Maximum power dissipation –40 85

Low power dissipation

Maximum power dissipation –40 105

Low power dissipation

Suffix 6 version –40 105

J Junction temperature range

Suffix 7 version –40 125

1. For operation with a voltage higher than V

is lower, higher PD values are allowed as long as TJ does not exceed T

2. If T

3. In low power dissipation state, T

Thermal characteristics).

can be extended to this range as long as TJ does not exceed T

+ 0.3 V, the internal pull-up resistor must be disabled.

DDIOx

DS9826 Rev 6 53/128

(3)

. See Section 7.8: Thermal characteristics.

Jmax

–40 105

–40 125

(see Section 7.8:

Jmax

°C

Electrical characteristics STM32F072x8 STM32F072xB

6.3.2 Operating conditions at power-up / power-down

The parameters given in Tab le 25 are derived from tests performed under the ambient temperature condition summarized in Tab le 24.

Symbol Parameter Conditions Min Max Unit

Table 25. Operating conditions at power-up / power-down

VDD

VDDA

VDD rise time rate

fall time rate 20

rise time rate

DDA

fall time rate 20

DDA

6.3.3 Embedded reset and power control block characteristics

The parameters given in Tab le 26 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 24: General operating

conditions.

RSTTEMPO

1. The PDR detector monitors VDD and also V monitors only VDD.

2. The product behavior is guaranteed by design down to the minimum V

3. Data based on characterization results, not tested in production.

4. Guaranteed by design, not tested in production.

Table 26. Embedded reset and power control block characteristics

Symbol Parameter Conditions Min Typ Max Unit

POR/PDR

PDRhyst

Power on/power down

(1)

reset threshold

Falling edge

Rising edge 1.84

(2)

PDR hysteresis - - 40 - mV

(4)

Reset temporization - 1.50 2.50 4.50 ms

(if kept enabled in the option bytes). The POR detector

DDA

1.80 1.88

(3)

value.

POR/PDR

1.92 2.00 V



1.96

(3)

µs/V

Table 27. Programmable voltage detector characteristics

Symbol Parameter Conditions Min Typ Max Unit

PVD0

PVD1

PVD2

PVD3

PVD threshold 0

PVD threshold 1

PVD threshold 2

PVD threshold 3

54/128 DS9826 Rev 6

Rising edge 2.1 2.18 2.26 V

Falling edge 2 2.08 2.16 V

Rising edge 2.19 2.28 2.37 V

Falling edge 2.09 2.18 2.27 V

Rising edge 2.28 2.38 2.48 V

Falling edge 2.18 2.28 2.38 V

Rising edge 2.38 2.48 2.58 V

Falling edge 2.28 2.38 2.48 V

STM32F072x8 STM32F072xB Electrical characteristics

Table 27. Programmable voltage detector characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit

PVD4

PVD5

PVD6

PVD7

PVDhyst

DD(PVD)

1. Guaranteed by design, not tested in production.

PVD threshold 4

PVD threshold 5

PVD threshold 6

PVD threshold 7

(1)

PVD hysteresis - - 100 - mV

PVD current consumption - - 0.15 0.26

6.3.4 Embedded reference voltage

The parameters given in Tab le 28 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 24: General operating

conditions.

Symbol Parameter Conditions Min Typ Max Unit

Table 28. Embedded internal reference voltage

Rising edge 2.47 2.58 2.69 V

Falling edge 2.37 2.48 2.59 V

Rising edge 2.57 2.68 2.79 V

Falling edge 2.47 2.58 2.69 V

Rising edge 2.66 2.78 2.9 V

Falling edge 2.56 2.68 2.8 V

Rising edge 2.76 2.88 3 V

Falling edge 2.66 2.78 2.9 V

(1)

µA

REFINT

START

Internal reference voltage –40 °C < TA < +105 °C 1.2 1.23 1.25 V

ADC_IN17 buffer startup time

ADC sampling time when

S_vrefint

reading the internal reference voltage

Internal reference voltage

V

REFINT

spread over the temperature range

Coeff

1. Guaranteed by design, not tested in production.

Temperature coefficient -

6.3.5 Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.

The current consumption is measured as described in Figure 14: Current consumption

measurement scheme.

100

(1)

---10

= 3 V - -

DDA

- 100

(1)

-- µs

(1)

µs

ppm/°C

DS9826 Rev 6 55/128

Electrical characteristics STM32F072x8 STM32F072xB

All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to CoreMark code.

Typical and maximum current consumption

The MCU is placed under the following conditions:

• All I/O pins are in analog input mode

• All peripherals are disabled except when explicitly mentioned

• The Flash memory access time is adjusted to the f

– 0 wait state and Prefetch OFF from 0 to 24 MHz

– 1 wait state and Prefetch ON above 24 MHz

• When the peripherals are enabled f

PCLK

= f

HCLK

The parameters given in Tab le 29 to Ta bl e 31 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Tab le 24: General

operating conditions.

Table 29. Typical and maximum current consumption from VDD supply at VDD = 3.6 V

All peripherals enabled All peripherals disabled

HCLK

frequency:

Symbol

Conditions f

Parameter

HSE bypass,

HSI clock,

Supply current in Run mode,

code executing from Flash memory

HSI clock,

HCLK

Typ

Max @ T

(1)

Max @ T

Typ

(1)

25 °C 85 °C 105 °C 25 °C 85 °C 105 °C

HSI48 48 MHz 24.3 26.9 27.2 27.9 13.1 14.8 14.9 15.5

48 MHz 24.1 26.8 27.0 27.7 13.0 14.6 14.8 15.4

PLL on

32 MHz 16.0 18.3 18.6 19.2 8.76 9.56 9.73 10.6

24 MHz 12.3 13.7 14.3 14.7 7.36 7.94 8.37 8.81

8 MHz 4.52 5.25 5.28 5.61 2.89 3.17 3.26 3.34

PLL off

1 MHz 1.25 1.39 1.58 1.87 0.93 1.06 1.15 1.34

48 MHz 24.1 27.1 27.6 27.8 12.9 14.7 14.9 15.5

PLL on

32 MHz 16.1 18.2 18.9 19.3 8.82 9.69 9.83 10.7

24 MHz 12.4 14.0 14.4 14.8 7.31 7.92 8.34 8.75

PLL off

8 MHz 4.52 5.25 5.35 5.61 2.87 3.16 3.25 3.33

Unit

56/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Electrical characteristics

Table 29. Typical and maximum current consumption from VDD supply at VDD = 3.6 V (continued)

All peripherals enabled All peripherals disabled

Symbol

Conditions f

Parameter

HSE bypass,

HSI clock,

code executing from RAM

Supply current in Run mode,

HSI clock,

HSE bypass,

HCLK

Typ

Max @ T

(1)

Max @ T

Typ

(1)

25 °C 85 °C 105 °C 25 °C 85 °C 105 °C

HSI48 48 MHz 23.1 25.4 25.8 26.6 12.8 13.5 13.7 13.9

PLL on

(2)

48 MHz 23.0 25.3

25.7 26.5

32 MHz 15.4 17.3 17.8 18.3 7.96 8.92 9.17 9.73

(2)

12.6 13.3

(2)

13.5 13.8

24 MHz 11.4 12.9 13.5 13.7 6.48 8.04 8.23 8.41

8 MHz 4.21 4.6 4.89 5.25 2.07 2.3 2.35 2.94

PLL off

1 MHz 0.78 0.9 0.92 1.15 0.36 0.48 0.59 0.82

48 MHz 23.1 24.5 25.0 25.2 12.6 13.7 13.9 14.0

PLL on

32 MHz 15.4 17.4 17.7 18.2 8.05 8.85 9.16 9.94

24 MHz 11.5 13.0 13.6 13.9 6.49 8.06 8.21 8.47

PLL off

8 MHz 4.34 4.75 5.03 5.41 2.11 2.36 2.38 2.98

HSI48 48 MHz 15.1 16.6 16.8 17.5 3.08 3.43 3.56 3.61

PLL on

(2)

48 MHz 15.0 16.5

16.7 17.3

32 MHz 9.9 11.4 11.6 11.9 2.0 2.24 2.32 2.49

(2)

2.93 3.28

(2)

3.41 3.46

24 MHz 7.43 8.17 8.71 8.82 1.63 1.82 1.88 1.9

8 MHz 2.83 3.09 3.26 3.66 0.76 0.88 0.91 0.93

PLL off

1 MHz 0.42 0.54 0.55 0.67 0.28 0.39 0.41 0.43

Unit

(2)

48 MHz 15.0 17.2 17.3 17.9 3.04 3.37 3.41 3.46

HSI clock,

PLL on

Supply current in Sleep mode

HSI clock,

PLL off

1. Data based on characterization results, not tested in production unless otherwise specified.

2. Data based on characterization results and tested in production (using one common test limit for sum of I

32 MHz 9.93 11.3 11.6 11.7 2.11 2.35 2.44 2.65

24 MHz 7.53 8.45 8.87 8.95 1.64 1.83 1.9 1.93

8 MHz 2.95 3.24 3.41 3.8 0.8 0.92 0.94 0.97

DS9826 Rev 6 57/128

and I

DDA

Electrical characteristics STM32F072x8 STM32F072xB

Symbol

DDA

Table 30. Typical and maximum current consumption from the V

= 2.4 V V

DDA

Para-

meter

Supply

current in

Run or

Sleep

mode,

code

executing

from

Flash

memory

or RAM

Conditions

(1)

HCLK

Max @ T

Typ

(2)

Typ

25 °C 85 °C 105 °C 25 °C 85 °C 105 °C

HSI48 48 MHz 311 326 334 343 322 337 345 354

HSE

bypass,

PLL on

HSE

(3)

48 MHz 152 170

178 182

32 MHz 105 121 126 128 113 129 136 138

24 MHz 81.9 95.9 99.5 101 88.7 102 107 108

8 MHz 2.7 3.8 4.3 4.6 3.6 4.7 5.2 5.5

(3)

165 184

bypass,

PLL off

1 MHz 2.7 3.8 4.3 4.6 3.6 4.7 5.2 5.5

48 MHz 223 244 255 260 245 265 279 284

HSI clock,

PLL on

32 MHz 176 195 203 206 193 212 221 224

24 MHz 154 171 178 181 168 185 192 195

supply

DDA

Max @ T

(3)

= 3.6 V

196 200

(2)

Unit

(3)

µA

HSI clock,

PLL off

1. Current consumption from the V in Run or Sleep mode or executing from Flash memory or RAM. Furthermore, when the PLL is off, I the frequency.

2. Data based on characterization results, not tested in production unless otherwise specified.

3. Data based on characterization results and tested in production (using one common test limit for sum of I

8 MHz 74.2 83.4 86.4 87.3 83.4 92.5 95.3 96.6

supply is independent of whether the digital peripherals are enabled or disabled, being

DDA

is independent from

DDA

and I

DDA

58/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Electrical characteristics

Table 31. Typical and maximum consumption in Stop and Standby modes

TA =

85 °C

(1)

TA =

105 °C

Unit

Sym-

bol

Para-

meter

Conditions

Typ @V

= V

)Max

DDA

2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V

25 °C

Supply current in Stop mode

Supply current in Standby mode

Regulator in run mode, all oscillators OFF

Regulator in lowpower mode, all oscillators OFF

LSI ON and IWDG ON

LSI OFF and IWDG OFF

15.4 15.5 15.6 15.7 15.8 15.9 23

3.2 3.3 3.4 3.5 3.6 3.7 8

0.8 1.0 1.1 1.2 1.3 1.4 - - -

0.6 0.7 0.9 0.9 1.0 1.1 2.1

(2)

2.6 3.1

Regulator in

Supply

run mode, all oscillators OFF

2.1 2.2 2.3 2.5 2.6 2.8 3.5

(2)

3.6 4.6

current in Stop mode

Regulator in low-power mode, all

2.1 2.2 2.3 2.5 2.6 2.8 3.5

(2)

3.6 4.6

oscillators

monitoring ON

OFF

DDA

LSI ON and

IWDG ON

LSI OFF and IWDG OFF

Regulator in run mode, all oscillators OFF

2.5 2.7 2.8 3.0 3.2 3.5 - - -

(2)

1.9 2.1 2.2 2.3 2.5 2.6 3.5

3.6 4.6

1.3 1.3 1.4 1.4 1.5 1.5 - - -

DDA

Supply current in Standby mode

Supply current in Stop mode

Regulator in low-power mode, all

1.3 1.3 1.4 1.4 1.5 1.5 - - oscillators OFF

monitoring OFF

DDA

Supply current in Standby mode

1. Data based on characterization results, not tested in production unless otherwise specified.

2. Data based on characterization results and tested in production (using one common test limit for sum of I

LSI ON and

IWDG ON

LSI OFF and IWDG OFF

1.7 1.8 1.9 2.0 2.1 2.2 - - -

1.2 1.2 1.2 1.3 1.3 1.4 - - -

49 68

33 51

and I

(2)

DDA

µA

DS9826 Rev 6 59/128

Electrical characteristics STM32F072x8 STM32F072xB

Table 32. Typical and maximum current consumption from the V

Symbol Parameter Conditions

1.8 V

1.65 V

LSE & RTC ON; “Xtal mode”: lower driving

RTC

DD_VBAT

1. Data based on characterization results, not tested in production.

domain supply current

capability; LSEDRV[1:0] = '00'

LSE & RTC ON; “Xtal mode” higher driving capability; LSEDRV[1:0] = '11'

0.5 0.6 0.7 0.8 1.1 1.2 1.3 1.7 2.3

0.8 0.9 1.1 1.2 1.4 1.6 1.7 2.1 2.8

Typical current consumption

The MCU is placed under the following conditions:

• VDD = V

• All I/O pins are in analog input configuration

• The Flash memory access time is adjusted to f

– 0 wait state and Prefetch OFF from 0 to 24 MHz

– 1 wait state and Prefetch ON above 24 MHz

• When the peripherals are enabled, f

• PLL is used for frequencies greater than 8 MHz

• AHB prescaler of 2, 4, 8 and 16 is used for the frequencies 4 MHz, 2 MHz, 1 MHz and

500 kHz respectively

DDA

= 3.3 V

Typ @ V

2.4 V

= f

PCLK

BAT

2.7 V

HCLK

TA =

3.6 V

25 °C

3.3 V

frequency:

BAT

supply

(1)

Max

TA =

85 °C

TA =

105 °C

Unit

µA

60/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Electrical characteristics

Table 33. Typical current consumption, code executing from Flash memory,

running from HSE

8 MHz crystal

Symbol Parameter f

48 MHz 24.1 13.5 14.6 3.5

36 MHz 18.3 10.5 11.1 2.9

32 MHz 16.5 9.6 10.0 2.7

24 MHz 12.9 7.6 7.8 2.2

Current

consumption

from V

16 MHz 8.9 5.3 5.5 1.7

supply

500 kHz 1.3 1.2 1.2 1.0

48 MHz 163.3

36 MHz 124.3

32 MHz 111.9

24 MHz 87.1

DDA

Current

consumption

from V

16 MHz 62.5

DDA

supply

HCLK

Typical consumption in

Run mode

Peripherals

enabled

Peripherals

disabled

Typical consumption in

Sleep mode

Peripherals

enabled

Peripherals

disabled

8 MHz 4.8 3.1 3.1 1.2

4 MHz 3.1 2.1 2.2 1.1

2 MHz 2.1 1.6 1.6 1.0

1 MHz 1.6 1.3 1.4 1.0

8 MHz 2.5

4 MHz 2.5

2 MHz 2.5

1 MHz 2.5

Unit

A

500 kHz 2.5

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in

For the output pins, any external pull-down or external load must also be considered to estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt

DS9826 Rev 6 61/128

Tab le 53: I/O static characteristics.

Electrical characteristics STM32F072x8 STM32F072xB

DDIOxfSW

C××=

trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs.

Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,

as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption measured previously (see

Tab le 35: Peripheral current consumption), the I/Os used by an application also contribute

to the current consumption. When an I/O pin switches, it uses the current from the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin:

where

ISW is the current sunk by a switching I/O to charge/discharge the capacitive load

C is the total capacitance seen by the I/O pin: C = C

is the I/O supply voltage

DDIOx

is the I/O switching frequency

INT

+ C

EXT

+ C

CS is the PCB board capacitance including the pad pin.

The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.

62/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Electrical characteristics

Table 34. Switching output I/O current consumption

Symbol Parameter Conditions

DDIOx

C =C

DDIOx

EXT

C = C

INT

DDIOx

EXT

C = C

INT

= 3.3 V

INT

= 3.3 V

= 0 pF

+ C

EXT

= 3.3 V

= 10 pF

+ C

EXT

(1)

+ C

frequency (fSW)

I/O toggling

4 MHz 0.07

8 MHz 0.15

16 MHz 0.31

24 MHz 0.53

48 MHz 0.92

4 MHz 0.18

8 MHz 0.37

16 MHz 0.76

24 MHz 1.39

48 MHz 2.188

4 MHz 0.32

8 MHz 0.64

16 MHz 1.25

24 MHz 2.23

Typ U n it

1. CS = 7 pF (estimated value).

I/O current

consumption

C = C

DDIOx

EXT

INT

DDIOx

EXT

INT

DDIOx

EXT

INT

C = C

DDIOx

EXT

INT

C = C

= 3.3 V

= 22 pF

+ C

EXT

= 3.3 V

= 33 pF

+ C

EXT

= 3.3 V

= 47 pF

+ C

EXT

int

= 2.4 V

= 47 pF

+ C

EXT

int

+ C

48 MHz 4.442

4 MHz 0.49

8 MHz 0.94

16 MHz 2.38

24 MHz 3.99

4 MHz 0.64

8 MHz 1.25

16 MHz 3.24

24 MHz 5.02

4 MHz 0.81

8 MHz 1.7

16 MHz 3.67

4 MHz 0.66

8 MHz 1.43

16 MHz 2.45

24 MHz 4.97

DS9826 Rev 6 63/128

Electrical characteristics STM32F072x8 STM32F072xB

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in Tabl e 35. The MCU is placed under the following conditions:

• All I/O pins are in analog mode

• All peripherals are disabled unless otherwise mentioned

• The given value is calculated by measuring the current consumption

– with all peripherals clocked off

– with only one peripheral clocked on

• Ambient operating temperature and supply voltage conditions summarized in Table 21:

Voltage characteristics

• The power consumption of the digital part of the on-chip peripherals is given in

Table 35. The power consumption of the analog part of the peripherals (where

applicable) is indicated in each related section of the datasheet.

Table 35. Peripheral current consumption

Peripheral Typical consumption at 25 °C Unit

BusMatrix

CRC 1.6

DMA 5.7

(1)

2.2

AHB

Flash memory interface 13.0

GPIOA 8.2

GPIOB 8.5

GPIOC 2.3

GPIOD 1.9

GPIOE 2.2

GPIOF 1.2

SRAM 0.9

TSC 5.0

All AHB peripherals 52.6

µA/MHz

64/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Electrical characteristics

Table 35. Peripheral current consumption (continued)

Peripheral Typical consumption at 25 °C Unit

(3)

(2)

2.8

4.1

4.7

APB-Bridge

ADC

CAN 12.4

CEC 1.5

CRS 0.8

DAC

DEBUG (MCU debug feature) 0.1

I2C1 3.9

I2C2 4.0

PWR 1.3

SPI1 8.7

SPI2 8.5

SYSCFG & COMP 1.7

TIM1 14.9

TIM2 15.5

APB

TIM3 11.4

TIM6 2.5

TIM7 2.3

TIM14 5.3

TIM15 9.1

TIM16 6.6

TIM17 6.8

USART1 17.0

USART2 16.7

USART3 5.4

USART4 5.4

USB 7.2

WWDG 1.4

All APB peripherals 182

1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA).

2. The APB Bridge is automatically active when at least one peripheral is ON on the Bus.

3. The power consumption of the analog part (I included. Refer to the tables of characteristics in the subsequent sections.

) of peripherals such as ADC, DAC, Comparators, is not

DDA

µA/MHz

DS9826 Rev 6 65/128

Electrical characteristics STM32F072x8 STM32F072xB

6.3.6 Wakeup time from low-power mode

The wakeup times given in Table 36 are the latency between the event and the execution of the first user instruction. The device goes in low-power mode after the WFE (Wait For Event) instruction, in the case of a WFI (Wait For Interruption) instruction, 16 CPU cycles must be added to the following timings due to the interrupt latency in the Cortex M0 architecture.

The SYSCLK clock source setting is kept unchanged after wakeup from Sleep mode. During wakeup from Stop or Standby mode, SYSCLK takes the default setting: HSI 8 MHz.

The wakeup source from Sleep and Stop mode is an EXTI line configured in event mode. The wakeup source from Standby mode is the WKUP1 pin (PA0).

All timings are derived from tests performed under the ambient temperature and supply voltage conditions summarized in

Table 36. Low-power mode wakeup timings

Symbol Parameter Conditions

Tab le 24: General operating conditions.

Typ @VDD = VDDA

Max Unit

= 2.0 V = 2.4 V = 2.7 V = 3 V = 3.3 V

WUSTOP

WUSTANDBY

WUSLEEP

Wakeup from Stop mode

Wakeup from Standby mode

Wakeup from Sleep mode

Regulator in run mode

Regulator in low power mode

- 60.4 55.6 53.5 52 51 -

- 4 SYSCLK cycles -

3.23.12.92.92.85

7.05.85.24.94.69

6.3.7 External clock source characteristics

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the recommended clock input waveform is shown in Figure 15: High-speed external clock

source AC timing diagram.

Symbol Parameter

HSE_ext

HSEH

HSEL

w(HSEH)

w(HSEL)

r(HSE)

f(HSE)

Table 37. High-speed external user clock characteristics

(1)

User external clock source frequency - 8 32 MHz

OSC_IN input pin high level voltage 0.7 V

OSC_IN input pin low level voltage V

OSC_IN high or low time 15 - -

OSC_IN rise or fall time - - 20

µs

Min Typ Max Unit

DDIOx

-V

- 0.3 V

DDIOx

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STM32F072x8 STM32F072xB Electrical characteristics

MS19215V2

LSEH

f(LSE)

90%

10%

LSE

r(LSE)

LSEL

w(LSEH)

w(LSEL)

1. Guaranteed by design, not tested in production.

Figure 15. High-speed external clock source AC timing diagram

w(HSEH)

HSEH

HSEL

90%

10%

r(HSE)

HSE

f(HSE)

w(HSEL)

MS19214V2

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 6.3.14. However, the recommended clock input waveform is shown in Figure 16.

Symbol Parameter

LSE_ext

LSEH

LSEL

w(LSEH)

w(LSEL)

r(LSE)

f(LSE)

1. Guaranteed by design, not tested in production.

Table 38. Low-speed external user clock characteristics

(1)

User external clock source frequency - 32.768 1000 kHz

OSC32_IN input pin high level voltage 0.7 V

OSC32_IN input pin low level voltage V

OSC32_IN high or low time 450 - -

OSC32_IN rise or fall time - - 50

Min Typ Max Unit

DDIOx

-V

- 0.3 V

DDIOx

Figure 16. Low-speed external clock source AC timing diagram

DS9826 Rev 6 67/128

Electrical characteristics STM32F072x8 STM32F072xB

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Symbol Parameter Conditions

Table 39. HSE oscillator characteristics

(1)

Min

Table 39. In the

(2)

Typ M a x

(2)

Unit

OSC_IN

Oscillator frequency - 4 8 32 MHz

Feedback resistor - - 200 - k

During startup

= 3.3 V,

Rm = 30 ,

(3)

--8.5

-0.4-

CL = 10 pF@8 MHz

= 3.3 V,

Rm = 45 ,

-0.5-

CL = 10 pF@8 MHz

= 3.3 V,

HSE current consumption

Rm = 30 ,

-0.8-

CL = 5 pF@32 MHz

= 3.3 V,

Rm = 30 ,

-1-

CL = 10 pF@32 MHz

= 3.3 V,

Rm = 30 ,

-1.5-

CL = 20 pF@32 MHz

SU(HSE)

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

2. Guaranteed by design, not tested in production.

3. This consumption level occurs during the first 2/3 of the t

4. t

SU(HSE)

oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer

Oscillator transconductance Startup 10 - - mA/V

(4)

Startup time VDD is stabilized - 2 - ms

startup time

SU(HSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz

For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5

pF to 20 pF range (Typ.), designed for high-frequency applications, and selected to match

the requirements of the crystal or resonator (see

Figure 17). CL1 and C

are usually the

same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C

and CL2. PCB and MCU pin capacitance must be included (10 pF

can be used as a rough estimate of the combined pin and board capacitance) when sizing C

and CL2.

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator

design guide for ST microcontrollers” available from the ST website www.st.com.

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STM32F072x8 STM32F072xB Electrical characteristics

MS19876V1

(1)

OSC_IN

OSC_OUT

Bias

controlled

gain

HSE

EXT

8 MHz

resonator

Resonator with integrated capacitors

Figure 17. Typical application with an 8 MHz crystal

1. R

value depends on the crystal characteristics.

EXT

Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Table 40. LSE oscillator characteristics (f

Symbol Parameter Conditions

low drive capability - 0.5 0.9

LSE current consumption

Oscillator

transconductance

medium-low drive capability - - 1

medium-high drive capability - - 1.3

high drive capability - - 1.6

low drive capability 5 - -

medium-low drive capability 8 - -

medium-high drive capability 15 - -

(1)

Tabl e 40. In the application, the

= 32.768 kHz)

LSE

(2)

Min

Typ Ma x

(2)

Unit

µA

µA/V

SU(LSE)

1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST microcontrollers”.

2. Guaranteed by design, not tested in production.

3. t

SU(LSE)

reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer

high drive capability 25 - -

(3)

is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is

Startup time V

is stabilized - 2 - s

DDIOx

DS9826 Rev 6 69/128

Electrical characteristics STM32F072x8 STM32F072xB

MS30253V2

OSC32_IN

OSC32_OUT

Drive

programmable

amplifier

LSE

32.768 kHz resonator

Resonator with integrated capacitors

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator

design guide for ST microcontrollers” available from the ST website www.st.com.

Figure 18. Typical application with a 32.768 kHz crystal

Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden

to add one.

6.3.8 Internal clock source characteristics

The parameters given in Tab le 41 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 24: General operating

conditions. The provided curves are characterization results, not tested in production.

70/128 DS9826 Rev 6

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MS30985V4

T [ºC]

MAX

MIN

-40 -20 0 20 40 60 80 100 120

-1%

-2%

-3%

-4%

High-speed internal (HSI) RC oscillator

Table 41. HSI oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

(1)

HSI

Frequency - - 8 - MHz

TRIM HSI user trimming step - - - 1

DuCy

ACC

(HSI)

HSI

Duty cycle - 45

= -40 to 105°C -2.8

= -10 to 85°C -1.9

Accuracy of the HSI oscillator

TA = 0 to 85°C -1.9

TA = 0 to 70°C -1.3

TA = 0 to 55°C -1

TA = 25°C

su(HSI)

DDA(HSI)

1. V

2. Guaranteed by design, not tested in production.

3. Data based on characterization results, not tested in production.

4. Factory calibrated, parts not soldered.

= 3.3 V, TA = -40 to 105°C unless otherwise specified.

DDA

HSI oscillator startup time - 1

HSI oscillator power consumption

(4)

- - 80 100

(2)

(3)

-55

-3.8

-2.3

-2

-1 - 1

(2)

-2

Figure 19. HSI oscillator accuracy characterization results for soldered parts

(2)

(3)

(2)

(3)

(2)

µs

µA

DS9826 Rev 6 71/128

Electrical characteristics STM32F072x8 STM32F072xB

MS30986V2

-5%

-4%

-40 -20 0 20 40 60 80 100 120

MAX

MIN

T [°C]

High-speed internal 14 MHz (HSI14) RC oscillator (dedicated to ADC)

Table 42. HSI14 oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

(1)

HSI14

Frequency - - 14 - MHz

TRIM HSI14 user-trimming step - - - 1

DuCy

(HSI14)

Duty cycle - 45

TA = –40 to 105 °C –4.2

= –10 to 85 °C –3.2

ACC

su(HSI14)

DDA(HSI14)

1. V

DDA

HSI14

Accuracy of the HSI14 oscillator (factory calibrated)

HSI14 oscillator startup time - 1

HSI14 oscillator power consumption

= 3.3 V, TA = –40 to 105 °C unless otherwise specified.

2. Guaranteed by design, not tested in production.

3. Data based on characterization results, not tested in production.

= 0 to 70 °C –2.5

= 25 °C –1 - 1 %

--100150

(2)

(3)

(2)

Figure 20. HSI14 oscillator accuracy characterization results

(2)

-55

-5.1

-3.1

-2.3

-2

(2)

(3)

(2)

µs

µA

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MS34206V1

-5%

-4%

-40 -20 0 20 40 60 80 100 120

MAX

MIN

T [°C]

High-speed internal 48 MHz (HSI48) RC oscillator

Table 43. HSI48 oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

(1)

HSI48

Frequency - - 48 - MHz

TRIM HSI48 user-trimming step - 0.09

DuCy

(HSI48)

Duty cycle - 45

TA = –40 to 105 °C -4.9

= –10 to 85 °C -4.1

ACC

su(HSI48)

DDA(HSI48)

1. V

DDA

HSI48

Accuracy of the HSI48 oscillator (factory calibrated)

HSI48 oscillator startup time - - - 6

HSI48 oscillator power consumption

= 3.3 V, TA = –40 to 105 °C unless otherwise specified.

= 0 to 70 °C -3.8

= 25 °C -2.8 - 2.9 %

- - 312 350

2. Guaranteed by design, not tested in production.

3. Data based on characterization results, not tested in production.

Figure 21. HSI48 oscillator accuracy characterization results

(2)

(3)

0.14 0.2

-55

-4.7

-3.7

-3.4

(2)

(3)

(2)

µs

µA

DS9826 Rev 6 73/128

Electrical characteristics STM32F072x8 STM32F072xB

Low-speed internal (LSI) RC oscillator

Table 44. LSI oscillator characteristics

Symbol Parameter Min Typ Max Unit

(1)

LSI

su(LSI)

DDA(LSI)

1. V

DDA

2. Guaranteed by design, not tested in production.

Frequency 30 40 50 kHz

(2)

LSI oscillator startup time - - 85 µs

(2)

LSI oscillator power consumption - 0.75 1.2 µA

= 3.3 V, TA = –40 to 105 °C unless otherwise specified.

6.3.9 PLL characteristics

The parameters given in Tab le 45 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 24: General operating

conditions.

Symbol Parameter

PLL_IN

PLL_OUT

LOCK

Jitter

PLL

1. Take care to use the appropriate multiplier factors to obtain PLL input clock values compatible with the range defined by f

2. Guaranteed by design, not tested in production.

PLL input clock

PLL input clock duty cycle 40

PLL multiplier output clock 16

PLL lock time - - 200

Cycle-to-cycle jitter - - 300

PLL_OUT

Table 45. PLL characteristics

(1)

Value

Min Typ Max

(2)

8.0 24

-60

-48MHz

(2)

Unit

MHz

µs

6.3.10 Memory characteristics

Flash memory

The characteristics are given at TA = –40 to 105 °C unless otherwise specified.

Symbol Parameter Conditions Min Typ Max

ERASE

1. Guaranteed by design, not tested in production.

16-bit programming time TA = - 40 to +105 °C 40 53.5 60 µs

prog

Page (2 KB) erase time TA = - 40 to +105 °C 20 - 40 ms

Mass erase time TA = - 40 to +105 °C 20 - 40 ms

Supply current

74/128 DS9826 Rev 6

Table 46. Flash memory characteristics

Write mode - - 10 mA

Erase mode - - 12 mA

(1)

Unit

STM32F072x8 STM32F072xB Electrical characteristics

Table 47. Flash memory endurance and data retention

Symbol Parameter Conditions Min

END

RET

1. Data based on characterization results, not tested in production.

2. Cycling performed over the whole temperature range.

Endurance TA = –40 to +105 °C

Data retention

6.3.11 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until

a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

• FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V

through a 100 pF capacitor, until a functional disturbance occurs. This test is

compliant with the IEC 61000-4-4 standard.

1 kcycle

10 kcycle

(2)

at TA = 85 °C

(2)

at TA = 105 °C 10

(2)

at TA = 55 °C 20

(1)

kcycle

Unit

Yea r1 kcycle

and

A device reset allows normal operations to be resumed.

The test results are given in Tab le 48. They are based on the EMS levels and classes defined in application note AN1709.

Symbol Parameter Conditions

FESD

Voltage limits to be applied on any I/O pin to induce a functional disturbance

Fast transient voltage burst limits to be

EFTB

applied through 100 pF on VDD and V pins to induce a functional disturbance

Table 48. EMS characteristics

= 3.3 V, LQFP100, TA = +25 °C,

= 48 MHz,

HCLK

conforming to IEC 61000-4-2

= 3.3 V, LQFP100, TA = +25°C,

= 48 MHz,

HCLK

conforming to IEC 61000-4-4

Level/ Class

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

DS9826 Rev 6 75/128

Electrical characteristics STM32F072x8 STM32F072xB

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• Corrupted program counter

• Unexpected reset

• Critical Data corruption (for example control registers)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC

61967-2 standard which specifies the test board and the pin loading.

Table 49. EMI characteristics

Symbol Parameter Conditions

= 3.6 V, TA = 25 °C,

EMI

Peak level

LQFP100 package compliant with IEC 61967-2

6.3.12 Electrical sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the standards stated in the following table.

Monitored

frequency band

0.1 to 30 MHz -2

130 MHz to 1 GHz 17

EMI Level 4 -

Max vs. [f

HSE/fHCLK

8/48 MHz

]

Unit

dBµV30 to 130 MHz 27

76/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Electrical characteristics

Symbol Ratings Conditions Packages Class

ESD(HBM)

ESD(CDM)

1. Data based on characterization results, not tested in production.

Electrostatic discharge voltage (human body model)

Electrostatic discharge voltage (charge device model)

Table 50. ESD absolute maximum ratings

TA = +25 °C, conforming to ANSI/ESDA/JEDEC JS-001

TA = +25 °C, conforming to ANSI/ESDA/JEDEC JS-002

All 2 2000 V

WLCSP49 C1 250

All others C2a 500

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up performance:

• A supply overvoltage is applied to each power supply pin.

• A current injection is applied to each input, output and configurable I/O pin.

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Symbol Parameter Conditions Class

LU Static latch-up class T

Table 51. Electrical sensitivities

= +105 °C conforming to JESD78A II level A

Maximum

(1)

value

Unit

6.3.13 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or above V product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of the -5 oscillator frequency deviation).

The characterization results are given in Tab le 52.

Negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection.

(for standard, 3.3 V-capable I/O pins) should be avoided during normal

DDIOx

µA/+0 µA range) or other functional failure (for example reset occurrence or

DS9826 Rev 6 77/128

Electrical characteristics STM32F072x8 STM32F072xB

Table 52. I/O current injection susceptibility

Symbol Description

Injected current on BOOT0 and PF1 pins –0 NA

Injected current on PC0 pin –0 +5

Injected current on PA11 and PA12 pins with induced

INJ

leakage current on adjacent pins less than -1 mA

Injected current on all other FT and FTf pins –5 NA

Injected current on all other TTa, TC and RST pins –5 +5

6.3.14 I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Tab le 53 are derived from tests performed under the conditions summarized in Table 24: General operating conditions. All I/Os are designed as CMOS- and TTL-compliant (except BOOT0).

Functional

susceptibility

Negative injection

–5 NA

Unit

Positive

injection

Table 53. I/O static characteristics

Symbol Parameter Conditions Min Typ Max Unit

(1)

TC and TTa I/O - - 0.3 V

FT and FTf I/O - - 0.475 V

Low level input

voltage

High level input

voltage

Schmitt trigger

hys

hysteresis

BOOT0 - - 0.3 V

All I/Os except BOOT0 pin

TC and TTa I/O 0.445 V

FT and FTf I/O 0.5 V

BOOT0 0.2 V

All I/Os except BOOT0 pin

TC and TTa I/O - 200

BOOT0 - 300

--0.3 V

(1)

DDIOx

0.7 V

+0.398

+0.2

+0.95

DDIOx

(1)

DDIOx

+0.07

–0.3

DDIOx

–0.2

(1)

mVFT and FTf I/O - 100

78/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Electrical characteristics

Table 53. I/O static characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit

TC, FT and FTf I/O TTa in digital mode

 V

DDIOx

TTa in digital mode

lkg

Input leakage

(2)

current

DDIOx

 V

DDA

TTa in analog mode V

 V

DDA

FT and FTf I/O V

DDIOx

 V

 5 V

Weak pull-up

equivalent resistor

(3)

VIN = V

Weak pull-down

1. Data based on design simulation only. Not tested in production.

2. The leakage could be higher than the maximum value, if negative current is injected on adjacent pins. Refer to Table 52:

3. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

equivalent

I/O current injection susceptibility.

PMOS/NMOS contribution to the series resistance is minimal (~10% order).

(3)

resistor

I/O pin capacitance - - 5 - pF

VIN = - V

DDIOx

--± 0.1

--1 µA

--± 0.2

--10

25 40 55 k

All I/Os are CMOS- and TTL-compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in

Figure 22 for standard I/Os, and in Figure 23 for

5 V-tolerant I/Os. The following curves are design simulation results, not tested in production.

DS9826 Rev 6 79/128

Electrical characteristics STM32F072x8 STM32F072xB

MSv32130V4

1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6

0.5

1.5

2.5

TESTED RANGE

IHmin

= 0.7 V

DDIOx

(CMOS standard requirement)

ILmax

= 0.3 V

DDIOx

(CMOS standard requirement)

UNDEFINED INPUT RANGE

IHmin

= 0.445 V

DDIOx

+ 0.398

ILmax

= 0.3 V

DDIOx

+ 0.07

(V)

DDIOx

(V)

TTL standard requirement

MSv32131V4

1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6

0.5

1.5

2.5

TESTED RANGE

IHmin

= 0.7 V

DDIOx

(CMOS standard requirement)

ILmax

= 0.3 V

DDIOx

(CMOS standard requirement)

UNDEFINED INPUT RANGE

IHmin

= 0.5 V

DDIOx

+ 0.2

ILmax

= 0.475 V

DDIOx

- 0.2

(V)

DDIOx

(V)

TTL standard requirement

Figure 22. TC and TTa I/O input characteristics

Figure 23. Five volt tolerant (FT and FTf) I/O input characteristics

80/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Electrical characteristics

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or source up to +/- 20

mA (with a relaxed VOL/VOH).

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in

• The sum of the currents sourced by all the I/Os on V consumption of the MCU sourced on V

I

(see Table 21: Voltage characteristics).

VDD

• The sum of the currents sunk by all the I/Os on V the MCU sunk on V

, cannot exceed the absolute maximum rating I

Section 6.2:

, plus the maximum

, cannot exceed the absolute maximum rating

DDIOx

, plus the maximum consumption of

VSS

(see

Table 21: Voltage characteristics).

Output voltage levels

Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in

Tab le 24: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT, TTa or

TC unless otherwise specified).

Table 54. Output voltage characteristics

(1)

Symbol Parameter Conditions Min Max Unit

Output low level voltage for an I/O pin CMOS port

(2)

-0.4

|IIO| = 8 mA

Output high level voltage for an I/O pin V

Output low level voltage for an I/O pin TTL port

DDIOx

 2.7 V

(2)

–0.4 -

DDIOx

-0.4

|IIO| = 8 mA

OLFm+

1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 21:

Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always

respect the absolute maximum ratings

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

3. Data based on characterization results. Not tested in production.

4. Data based on characterization results. Not tested in production.

Output high level voltage for an I/O pin 2.4 -

(3)

Output low level voltage for an I/O pin

(3)

Output high level voltage for an I/O pin V

(3)

Output low level voltage for an I/O pin

(3)

Output high level voltage for an I/O pin V

(4)

Output low level voltage for an I/O pin

(4)

Output high level voltage for an I/O pin V

Output low level voltage for an FTf I/O pin in

(3)

Fm+ mode

I

 2.7 V

DDIOx

| = 20 mA

 2.7 V

DDIOx

| = 6 mA

 2 V

DDIOx

| = 4 mA

| = 20 mA

 2.7 V

DDIOx

| = 10 mA - 0.4 V

DDIOx

-1.3

–1.3 -

-0.4

–0.4 -

-0.4V

–0.4 - V

-0.4V

DS9826 Rev 6 81/128

Electrical characteristics STM32F072x8 STM32F072xB

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in Figure 24 and

Tab le 55, respectively. Unless otherwise specified, the parameters given are derived from

tests performed under the ambient temperature and supply voltage conditions summarized in

Tab le 24: General operating conditions.

Table 55. I/O AC characteristics

(1)(2)

OSPEEDRy

[1:0] value

Symbol Parameter Conditions Min Max Unit

(1)

max(IO)out

f(IO)out

r(IO)out

max(IO)out

f(IO)out

r(IO)out

max(IO)out

f(IO)out

r(IO)out

max(IO)out

f(IO)out

r(IO)out

max(IO)out

f(IO)out

r(IO)out

Maximum frequency

Output fall time - 125

(3)

CL = 50 pF, V

DDIOx

 2 V

Output rise time - 125

Maximum frequency

Output fall time - 125

(3)

CL = 50 pF, V

DDIOx

< 2 V

Output rise time - 125

Maximum frequency

Output fall time - 25

(3)

CL = 50 pF, V

DDIOx

 2 V

Output rise time - 25

Maximum frequency

Output fall time - 62.5

(3)

CL = 50 pF, V

DDIOx

< 2 V

Output rise time - 62.5

Maximum frequency

Output fall time

Output rise time

(3)

CL = 30 pF, V

= 50 pF, V

= 50 pF, 2 V  V

= 50 pF, V

= 30 pF, V

= 50 pF, V

= 50 pF, 2 V  V

= 50 pF, V

= 30 pF, V

= 50 pF, V

= 50 pF, 2 V  V

= 50 pF, V

 2.7 V - 50

DDIOx

 2.7 V - 30

DDIOx

< 2.7 V - 20

DDIOx

< 2 V - 10

DDIOx

 2.7 V - 5

DDIOx

 2.7 V - 8

DDIOx

< 2.7 V - 12

DDIOx

< 2 V - 25

DDIOx

 2.7 V - 5

DDIOx

 2.7 V - 8

DDIOx

< 2.7 V - 12

DDIOx

< 2 V - 25

DDIOx

-2MHz

-1MHz

-10MHz

-4MHz

MHz

82/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Electrical characteristics

MS32132V3

10%

50%

90%

10%

50%

90%

Maximum frequency is achieved if (t + t ) ≤

when loaded by C (see the table I/O AC characteristics definition)

r(IO)out

f(IO)out

2 3

T and if the duty cycle is (45-55%)

(1)(2)

(continued)

DDIOx

-2MHz

 2 V

-0.5MHz

< 2 V

OSPEEDRy

[1:0] value

Fm+

configuration

(4)

Table 55. I/O AC characteristics

Symbol Parameter Conditions Min Max Unit

(1)

max(IO)out

f(IO)out

r(IO)out

max(IO)out

f(IO)out

r(IO)out

Maximum frequency

Output fall time - 12

Output rise time - 34

Maximum frequency

Output fall time - 16

Output rise time - 44

(3)

CL = 50 pF, V

(3)

CL = 50 pF, V

Pulse width of external

-t

EXTIpw

signals detected by the

-10-ns

EXTI controller

1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32F0xxxx RM0091 reference manual for a description of GPIO Port configuration register.

2. Guaranteed by design, not tested in production.

3. The maximum frequency is defined in Figure 24.

4. When Fm+ configuration is set, the I/O speed control is bypassed. Refer to the STM32F0xxxx reference manual RM0091 for a detailed description of Fm+ I/O configuration.

Figure 24. I/O AC characteristics definition

6.3.15 NRST pin characteristics

The NRST pin input driver uses the CMOS technology. It is connected to a permanent pullup resistor, R

Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in

Tab le 24: General operating conditions.

Symbol Parameter Conditions Min Typ Max Unit

IL(NRST)

IH(NRST)

NRST input low level voltage - - - 0.3 VDD+0.07

NRST input high level voltage - 0.445 VDD+0.398

Table 56. NRST pin characteristics

(1)

DS9826 Rev 6 83/128

Electrical characteristics STM32F072x8 STM32F072xB

MS19878V3

Internal reset

External

reset circuit

(1)

NRST

(2)

Filter

0.1 μF

Table 56. NRST pin characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit

hys(NRST)

F(NRST)

NF(NRST)

1. Data based on design simulation only. Not tested in production.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimal (~10% order).

3. Data based on design simulation only. Not tested in production.

NRST Schmitt trigger voltage hysteresis

Weak pull-up equivalent

(2)

resistor

NRST input filtered pulse - - - 100

NRST input not filtered pulse

--200-mV

VIN = V

2.7 < V

2.0 < V

< 3.6 300

< 3.6 500

25 40 55 k

(3)

(1)

Figure 25. Recommended NRST pin protection

1. The external capacitor protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the V

Table 56: NRST pin characteristics. Otherwise the reset will not be taken into account by the device.

6.3.16 12-bit ADC characteristics

Unless otherwise specified, the parameters given in Tab le 57 are derived from tests performed under the conditions summarized in Table 24: General operating conditions.

Note: It is recommended to perform a calibration after each power-up.

Symbol Parameter Conditions Min Typ

DDA

DDA (ADC)

ADC

(2)

84/128 DS9826 Rev 6

Analog supply voltage for ADC ON

Current consumption of the ADC

(1)

ADC clock frequency - 0.6 - 14 MHz

Sampling rate 12-bit resolution 0.043 - 1 MHz

Table 57. ADC characteristics

- 2.4 - 3.6 V

= 3.3 V - 0.9 - mA

DDA

max level specified in

IL(NRST)

Max Unit

STM32F072x8 STM32F072xB Electrical characteristics

Table 57. ADC characteristics (continued)

Symbol Parameter Conditions Min Typ

= 14 MHz,

TRIG

(2)

External trigger frequency

ADC

12-bit resolution

--823kHz

12-bit resolution - - 17 1/f

CAL

AIN

ADC

(2)

(2)(3)

Conversion voltage range - 0 - V

External input impedance

Sampling switch

(2)

resistance

Internal sample and hold

(2)

capacitor

Calibration time

See Equation 1 and

Table 58 for details

--50k

---1k

---8pF

= 14 MHz 5.9 µs

ADC

-831/f

1.5 ADC

LATENCY

ADC_DR register ready

(2)(4)

latency

ADC clock = HSI14

ADC clock = PCLK/2 - 4.5 -

cycles + 2

cycles

PCLK

ADC clock = PCLK/4 - 8.5 -

latr

Jitter

STAB

CONV

(2)

ADC

(2)

= f

ADC

Trigger conversion latency

ADC

= f

ADC

ADC jitter on trigger conversion

Sampling time

(2)

Stabilization time - 14 1/f

Total conversion time

(2)

12-bit resolution

(including sampling time)

12-bit resolution

/2 = 14 MHz 0.196 µs

PCLK

= f

ADC

PCLK

= f

ADC

= f

HSI14

ADC

= 14 MHz 0.107 - 17.1 µs

ADC

/2 5.5 1/f

PCLK

/4 = 12 MHz 0.219 µs

/4 10.5 1/f

PCLK

= 14 MHz 0.179 - 0.250 µs

= f

HSI14

-1-1/f

- 1.5 - 239.5 1/f

= 14 MHz,

ADC

1-18µs

14 to 252 (t

successive approximation)

for sampling +12.5 for

Max Unit

DDA

1.5 ADC

cycles + 3

cycles

PCLK

cycle

PCLK

cycle

PCLK

HSI14

1/f

ADC

1. During conversion of the sampled value (12.5 x ADC clock period), an additional consumption of 100 µA on I on IDD should be taken into account.

2. Guaranteed by design, not tested in production.

3. Specified value includes only ADC timing. It does not include the latency of the register access.

4. This parameter specify latency for transfer of the conversion result to the ADC_DR register. EOC flag is set at this time.

and 60 µA

DDA

DS9826 Rev 6 85/128

Electrical characteristics STM32F072x8 STM32F072xB

AIN

ADCCADC

N2+

()ln××

---------------------------------------------------------------- R

ADC

–<

Equation 1: R

max formula

AIN

The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).

Ts (cycles) tS (µs) R

1.5 0.11 0.4

7.5 0.54 5.9

13.5 0.96 11.4

28.52.0425.2

41.52.9637.2

55.5 3.96 50

71.5 5.11 NA

239.5 17.1 NA

1. Guaranteed by design, not tested in production.

Table 58. R

max for f

AIN

= 14 MHz

ADC

max (k)

AIN

(1)

Table 59. ADC accuracy

(1)(2)(3)

Symbol Parameter Test conditions Typ Max

ET Total unadjusted error

= 48 MHz,

EO Offset error ±1 ±1.5

EG Gain error ±0.5 ±1.5

ED Differential linearity error ±0.7 ±1

PCLK

= 14 MHz, R

ADC

= 3 V to 3.6 V

DDA

TA = 25 °C

< 10 k

AIN

±1.3 ±2

EL Integral linearity error ±0.8 ±1.5

ET Total unadjusted error

= 48 MHz,

EO Offset error ±1.9 ±2.8

EG Gain error ±2.8 ±3

ED Differential linearity error ±0.7 ±1.3

PCLK

= 14 MHz, R

ADC

= 2.7 V to 3.6 V

DDA

= - 40 to 105 °C

< 10 k

AIN

±3.3 ±4

EL Integral linearity error ±1.2 ±1.7

ET Total unadjusted error

= 48 MHz,

EO Offset error ±1.9 ±2.8

EG Gain error ±2.8 ±3

ED Differential linearity error ±0.7 ±1.3

PCLK

= 14 MHz, R

ADC

= 2.4 V to 3.6 V

DDA

= 25 °C

< 10 k

AIN

±3.3 ±4

EL Integral linearity error ±1.2 ±1.7

(4)

Unit

LSB

1. ADC DC accuracy values are measured after internal calibration.

86/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Electrical characteristics

ET = total unajusted error: maximum deviation between the actual and ideal transfer curves.

= offset error: maximum deviation between the first actual transition and the first ideal one.

= gain error: deviation between the last ideal transition and the last actual one.

ED = differential linearity error: maximum

deviation between actual steps and the ideal ones.

= integral linearity error: maximum deviation between any actual transition and the end point correlation line.

(1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line

4095

4094

4093

23456

7 4093

4094 4095

4096

DDA

SSA

1 LSB IDEAL

(1)

(3)

(2)

MS19880V2

2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for I accuracy.

3. Better performance may be achieved in restricted V

, frequency and temperature ranges.

DDA

INJ(PIN)

and I

in Section 6.3.14 does not affect the ADC

INJ(PIN)

4. Data based on characterization results, not tested in production.

Figure 26. ADC accuracy characteristics

Figure 27. Typical connection diagram using the ADC

DDA

(1)

AIN

1. Refer to Table 57: ADC characteristics for the values of R

2. C

pad capacitance (roughly 7 pF). A high C this, f

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

parasitic

should be reduced.

ADC

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 13: Power supply

scheme. The 10 nF capacitor should be ceramic (good quality) and it should be placed as

close as possible to the chip.

AINx

parasitic

(2)

value will downgrade conversion accuracy. To remedy

parasitic

±1 μA

AIN

, R

DS9826 Rev 6 87/128

Sample and hold ADC

ADC

and C

ADC

converter

ADC

12-bit

MS33900V2

Electrical characteristics STM32F072x8 STM32F072xB

6.3.17 DAC electrical specifications

Table 60. DAC characteristics

Symbol Parameter Min Typ Max Unit Comments

Analog supply voltage for DAC ON

Resistive load with buffer

(1)

2.4 - 3.6 V -

5- - k Load connected to V

25 - - k Load connected to V

DDA

LOAD

When the buffer is OFF, the

buffer OFF

-- 15 k

Impedance output with

(1)

Minimum resistive load between DAC_OUT and V

1% accuracy is 1.5 M

Maximum capacitive load at DAC_OUT pin (when the buffer

LOAD

(1)

Capacitive load - - 50 pF

is ON).

DAC_OUT

(1)

min

Lower DAC_OUT voltage with buffer ON

0.2 - - V

It gives the maximum output excursion of the DAC.

It corresponds to 12-bit input code (0x0E0) to (0xF1C) at

DAC_OUT

max

DAC_OUT

min

DAC_OUT

max

DDA

Higher DAC_OUT voltage

(1)

with buffer ON

Lower DAC_OUT voltage

(1)

with buffer OFF

Higher DAC_OUT voltage

(1)

with buffer OFF

DAC DC current

(1)

consumption in quiescent

(2)

mode

--V

– 0.2 V

DDA

(0xEAB) at V

-0.5 - mV It gives the maximum output

excursion of the DAC.

--V

-- 600 µA

-- 700 µA

– 1LSB V

DDA

With no load, middle code (0x800) on the input

With no load, worst code (0xF1C) on the input

= 3.6 V and (0x155) and

= 2.4 V

DDA

SSA

DDA

to have a

-- ±0.5 LSB

-- ±2 LSB

-- ±1 LSB

-- ±4 LSB

DNL

INL

Differential non linearity

(3)

Difference between two consecutive code-1LSB)

Integral non linearity (difference between measured value at Code i

(3)

and the value at Code i on a line drawn between Code 0 and last Code 1023)

-- ±10 mV -

-- ±3 LSB

Offset

Offset error (difference between

(3)

measured value at Code (0x800) and the ideal value = V

DDA

/2)

-- ±12LSB

88/128 DS9826 Rev 6

Given for the DAC in 10-bit configuration

Given for the DAC in 12-bit configuration

Given for the DAC in 10-bit configuration

Given for the DAC in 12-bit configuration

Given for the DAC in 10-bit at V

= 3.6 V

DDA

Given for the DAC in 12-bit at

= 3.6 V

DDA

STM32F072x8 STM32F072xB Electrical characteristics

Table 60. DAC characteristics (continued)

Symbol Parameter Min Typ Max Unit Comments

Gain error

(3)

Gain error - - ±0.5 %

Given for the DAC in 12-bit configuration

Settling time (full scale: for a 10-bit input code transition

SETTLING

(3)

highest input codes when

-3 4 µsC

LOAD

 50 pF, R

LOAD

 5 k

between the lowest and the

DAC_OUT reaches final value ±1LSB

Max frequency for a correct

Update

rate

DAC_OUT change when

(3)

small variation in the input

-- 1 MS/sC

LOAD

 50 pF, R

LOAD

 5 k

code (from code i to i+1LSB)

WAKEUP

PSRR+

Wakeup time from off state

(3)

(Setting the ENx bit in the DAC Control register)

Power supply rejection ratio

(1)

(to V

) (static DC

DDA

-6.5 10 µs

- –67 –40 dB No R

LOAD

 50 pF, R

LOAD

 5 k

input code between lowest and highest possible ones.

LOAD

, C

LOAD

= 50 pF

measurement

1. Guaranteed by design, not tested in production.

2. The DAC is in “quiescent mode” when it keeps the value steady on the output so no dynamic consumption is involved.

3. Data based on characterization results, not tested in production.

Figure 28. 12-bit buffered / non-buffered DAC

Buffered/Non-buffered DAC

(1)

Buffer

12-bit digital to analog converter

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register.

DAC_OUTx

MS39009V1

DS9826 Rev 6 89/128

Electrical characteristics STM32F072x8 STM32F072xB

6.3.18 Comparator characteristics

Table 61. Comparator characteristics

Symbol Parameter Conditions Min

(1)

Typ Max

(1)

Unit

DDA

S_SC

START

offset

Analog supply voltage - V

Comparator input voltage range

REFINT

scaler offset

voltage

REFINT

scaler startup

First V power on

scaler activation after device

REFINT

-0-V

- - ±5 ±10 mV

time from power down

-3.6 V

1000

DDA

(2)

Next activations - - 0.2

Comparator startup time

Startup time to reach propagation delay specification

--60µs

Ultra-low power mode - 2 4.5

Propagation delay for 200 mV step with 100 mV overdrive

Medium power mode - 0.3 0.6

 2.7 V - 50 100

High speed mode

DDA

< 2.7 V - 100 240

DDA

µsLow power mode - 0.7 1.5

Ultra-low power mode - 2 7

Propagation delay for full range step with 100 mV overdrive

Medium power mode - 0.3 1.2

 2.7 V - 90 180

High speed mode

DDA

< 2.7 V - 110 300

DDA

µsLow power mode - 0.7 2.1

Comparator offset error - - ±4 ±10 mV

Offset error

/dT

temperature coefficient

--18-µV/°C

Ultra-low power mode - 1.2 1.5

DD(COMP)

COMP current consumption

Low power mode - 3 5

Medium power mode - 10 15

High speed mode - 75 100

90/128 DS9826 Rev 6

µA

STM32F072x8 STM32F072xB Electrical characteristics

100

1000

-40 -20 0 20 40 60 80 100

S_SC(max)

(ms)

Temperature (°C)

2.0V ≤ V

DDA

< 2.4V

2.4V ≤ V

DDA

< 3.0V

3.0V ≤ V

DDA

< 3.6V

Table 61. Comparator characteristics (continued)

Symbol Parameter Conditions Min

(1)

Typ Max

(1)

Unit

No hysteresis (COMPxHYST[1:0]=00)

Low hysteresis (COMPxHYST[1:0]=01)

hys

Comparator hysteresis

Medium hysteresis (COMPxHYST[1:0]=10)

High hysteresis (COMPxHYST[1:0]=11)

1. Data based on characterization results, not tested in production.

2. For more details and conditions see Figure 29: Maximum V

Figure 29. Maximum V

REFINT

--0-

High speed mode 3

All other power modes

510

High speed mode 7

All other power modes

919

High speed mode 18

All other power modes

scaler startup time from power down.

19 40

scaler startup time from power down

DS9826 Rev 6 91/128

Electrical characteristics STM32F072x8 STM32F072xB

6.3.19 Temperature sensor characteristics

Table 62. TS characteristics

Symbol Parameter Min Typ Max Unit

(1)

Avg_Slope

START

S_temp

1. Guaranteed by design, not tested in production.

2. Measured at V

Temperature sensor calibration values.

6.3.20 V

(1)

Average slope 4.0 4.3 4.6 mV/°C

Voltage at 30 °C (± 5 °C)

(1)

ADC_IN16 buffer startup time - - 10 µs

ADC sampling time when reading the

(1)

temperature

DDA

BAT

linearity with temperature - ± 1 ± 2 °C

SENSE

(2)

1.34 1.43 1.52 V

4--µs

= 3.3 V ± 10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte. Refer to Table 3:

monitoring characteristics

Table 63. V

monitoring characteristics

BAT

Symbol Parameter Min Typ Max Unit

R Resistor bridge for V

(1)

S_vbat

1. Guaranteed by design, not tested in production.

Ratio on V

BAT

Error on Q –1 - +1 %

ADC sampling time when reading the V

BAT

measurement - 2 - -

BAT

-2 x 50- k

4--µs

6.3.21 Timer characteristics

The parameters given in the following tables are guaranteed by design.

Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output).

Symbol Parameter Conditions Min Typ Max Unit

res(TIM)

Timer resolution time

Timer external clock

EXT

frequency on CH1 to CH4

16-bit timer maximum period

MAX_COUNT

32-bit counter maximum period

92/128 DS9826 Rev 6

Table 64. TIMx characteristics

TIMxCLK

= 48 MHz - 20.8 - ns

TIMxCLK

= 48 MHz - 24 - MHz

= 48 MHz - 1365 - µs

TIMxCLK

= 48 MHz - 89.48 - s

TIMxCLK

--1-

TIMxCLK

-MHz

TIMxCLK

STM32F072x8 STM32F072xB Electrical characteristics

Prescaler divider PR[2:0] bits

/16 2 0.4 1638.4

/32 3 0.8 3276.8

/64 4 1.6 6553.6

/128 5 3.2 13107.2

/256 6 or 7 6.4 26214.4

1. These timings are given for a 40 kHz clock but the microcontroller internal RC frequency can vary from 30

to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.

Prescaler WDGTB Min timeout value Max timeout value Unit

1 0 0.0853 5.4613

2 1 0.1706 10.9226

4 2 0.3413 21.8453

Table 65. IWDG min/max timeout period at 40 kHz (LSI)

Min timeout RL[11:0]=

0x000

/4 0 0.1 409.6

/8 1 0.2 819.2

Max timeout RL[11:0]=

Table 66. WWDG min/max timeout value at 48 MHz (PCLK)

0xFFF

(1)

Unit

8 3 0.6826 43.6906

6.3.22 Communication interfaces

I2C interface characteristics

The I2C interface meets the timings requirements of the I2C-bus specification and user manual rev. 03 for:

• Standard-mode (Sm): with a bit rate up to 100 kbit/s

• Fast-mode (Fm): with a bit rate up to 400 kbit/s

• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.

The I2C timings requirements are guaranteed by design when the I2Cx peripheral is properly configured (refer to Reference manual).

The SDA and SCL I/O requirements are met with the following restrictions: the SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and V support Fm+ low level output current maximum requirement. Refer to

port characteristics for the I2C I/Os characteristics.

All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog filter characteristics:

is disabled, but is still present. Only FTf I/O pins

DDIOx

Section 6.3.14: I/O

DS9826 Rev 6 93/128

Electrical characteristics STM32F072x8 STM32F072xB

Table 67. I2C analog filter characteristics

(1)

Symbol Parameter Min Max Unit

1. Guaranteed by design, not tested in production.

2. Spikes with widths below t

3. Spikes with widths above t

Maximum width of spikes that are suppressed by the analog filter

are filtered.

AF(min)

are not filtered

AF(max)

(2)

260

(3)

SPI/I2S characteristics

Unless otherwise specified, the parameters given in Tab le 68 for SPI or in Ta bl e 69 for I2S are derived from tests performed under the ambient temperature, f supply voltage conditions summarized in

Tabl e 24: General operating conditions.

Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S).

Table 68. SPI characteristics

Symbol Parameter Conditions Min Max Unit

SCK

1/t

c(SCK)

r(SCK)

f(SCK)

su(NSS)

h(NSS)

w(SCKH)

w(SCKL)

su(MI)

su(SI)

h(MI)

h(SI)

(2)

a(SO)

(3)

dis(SO)

v(SO)

v(MO)

h(SO)

h(MO)

DuCy(SCK)

SPI clock frequency

SPI clock rise and fall time

NSS setup time Slave mode 4Tpclk -

NSS hold time Slave mode 2Tpclk + 10 -

SCK high and low time

Data input setup time

Data input hold time

Data output access time Slave mode, f

Data output disable time Slave mode 0 18

Data output valid time Slave mode (after enable edge) - 22.5

Data output valid time Master mode (after enable edge) - 6

Data output hold time

SPI slave input clock duty cycle

Master mode - 18

Slave mode - 18

Capacitive load: C = 15 pF - 6 ns

Master mode, f

= 36 MHz,

PCLK

presc = 4

Master mode 4 -

Slave mode 5 -

Master mode 4 -

Slave mode 5 -

= 20 MHz 0 3Tpclk

PCLK

Slave mode (after enable edge) 11.5 -

Master mode (after enable edge) 2 -

Slave mode 25 75 %

(1)

Tpclk/2 -2 Tpclk/2 + 1

frequency and

PCLKx

MHz

1. Data based on characterization results, not tested in production.

2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.

3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z

94/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Electrical characteristics

MSv41658V1

NSS input

CPHA=0 CPOL=0

SCK input

CPHA=0 CPOL=1

MISO output

MOSI input

su(SI)

h(SI)

w(SCKL)

w(SCKH)

c(SCK)

r(SCK)

h(NSS)

dis(SO)

su(NSS)

a(SO)

v(SO)

Next bits IN

Last bit OUT

First bit IN

First bit OUT Next bits OUT

h(SO)

f(SCK)

Last bit IN

MSv41659V1

NSS input

CPHA=1 CPOL=0

SCK input

CPHA=1 CPOL=1

MISO output

MOSI input

su(SI)

h(SI)

w(SCKL)

w(SCKH)

su(NSS)

c(SCK)

a(SO)

v(SO)

First bit OUT Next bits OUT

Next bits IN

Last bit OUT

h(SO)

r(SCK)

f(SCK)

h(NSS)

dis(SO)

First bit IN Last bit IN

Figure 30. SPI timing diagram - slave mode and CPHA = 0

Figure 31. SPI timing diagram - slave mode and CPHA = 1

1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 V

DS9826 Rev 6 95/128

Electrical characteristics STM32F072x8 STM32F072xB

Figure 32. SPI timing diagram - master mode

High

NSS input

c(SCK)

CPHA=0 CPOL=0

CPHA=0 CPOL=1

SCK Output

CPHA=1 CPOL=0

CPHA=1 CPOL=1

SCK Output

MISO

INP U T

MOSI

OUTPUT

1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 V

su(MI)

w(SCKH)

w(SCKL)

MSB IN

MSB OUT

v(MO)

h(MI)

BIT6 IN

B I T1 OUT

h(MO)

r(SCK)

f(SCK)

LSB IN

LSB OUT

ai14136c

Table 69. I2S characteristics

(1)

Symbol Parameter Conditions Min Max Unit

1/t

c(CK)

r(CK)

f(CK)

w(CKH)

w(CKL)

v(WS)

h(WS)

su(WS)

h(WS)

DuCy(SCK)

Master mode (data: 16 bits, Audio

I2S clock frequency

frequency = 48 kHz)

Slave mode 0 6.5

I2S clock rise time

I2S clock fall time - 12

Capacitive load C

I2S clock high time

I2S clock low time 312 -

Master f

PCLK

frequency = 48 kHz

= 15 pF

= 16 MHz, audio

WS valid time Master mode 2 -

WS hold time Master mode 2 -

WS setup time Slave mode 7 -

WS hold time Slave mode 0 -

S slave input clock duty

cycle

Slave mode 25 75 %

1.597 1.601

-10

306 -

MHz

96/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Electrical characteristics

MSv39721V1

CK Input

CPOL = 0

CPOL = 1

tc(CK)

WS input

SDtransmit

SDreceive

tw(CKH)

tw(CKL)

tsu(WS)

tv(SD_ST) th(SD_ST)

th(WS)

tsu(SD_SR) th(SD_SR)

MSB receive Bitn receive LSB receive

MSB transmit Bitn transmit

LSB receive(2)

LSB transmit(2)

Table 69. I2S characteristics

(1)

(continued)

Symbol Parameter Conditions Min Max Unit

su(SD_MR)

su(SD_SR)

h(SD_MR)

h(SD_SR)

v(SD_MT)

v(SD_ST)

h(SD_MT)

h(SD_ST)

1. Data based on design simulation and/or characterization results, not tested in production.

2. Depends on f

Data input setup time

(2)

Data input hold time

(2)

Data output valid time

(2)

Data output hold time

. For example, if f

PCLK

Master receiver 6 -

Slave receiver 2 -

Master receiver 4 -

Slave receiver 0.5 -

Master transmitter - 4

Slave transmitter - 20

Master transmitter 0 -

Slave transmitter 13 -

= 8 MHz, then T

PCLK

= 1/f

PLCLK

= 125 ns.

Figure 33. I2S slave timing diagram (Philips protocol)

1. Measurement points are done at CMOS levels: 0.3 × V

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

DS9826 Rev 6 97/128

DDIOx

and 0.7 × V

DDIOx

Electrical characteristics STM32F072x8 STM32F072xB

MSv39720V1

CK output

CPOL = 0

CPOL = 1

tc(CK)

WS output

SDreceive

SDtransmit

tw(CKH)

tw(CKL)

tsu(SD_MR)

tv(SD_MT) th(SD_MT)

th(WS)

th(SD_MR)

MSB receive Bitn receive LSB receive

MSB transmit Bitn transmit LSB transmit

tf(CK)

tr(CK)

tv(WS)

LSB receive(2)

LSB transmit(2)

10%

90%

Figure 34. I2S master timing diagram (Philips protocol)

1. Data based on characterization results, not tested in production.

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

98/128 DS9826 Rev 6

STM32F072x8 STM32F072xB Electrical characteristics

USB characteristics

The STM32F072x8/xB USB interface is fully compliant with the USB specification version

2.0 and is USB-IF certified (for Full-speed device operation).

Symbol Parameter Conditions Min. Typ Max. Unit

Table 70. USB electrical characteristics

DDIO2

STARTUP

PUI

USB transceiver operating voltage

(2)

USB transceiver startup time - - - 1.0 µs

Embedded USB_DP pull-up value during idle

-3.0

- 1.1 1.26 1.5

(1)

-3.6V

k

PUR

DRV

1. The STM32F072x8/xB USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics which are degraded in the 2.7-to-3.0 V voltage range.

2. Guaranteed by design, not tested in production.

3. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-); the matching impedance is already included in the embedded driver.

Embedded USB_DP pull-up value during reception

(2)

Output driver impedance

(3)

- 2.0 2.26 2.6

Driving high and low

28 40 44 

CAN (controller area network) interface

Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (CAN_TX and CAN_RX).

DS9826 Rev 6 99/128

Package information STM32F072x8 STM32F072xB

A0C2_ME_V5

Seating plane

Øb (100 balls)

TOP VIEWBOTTOM VIEW

112

A1 ball

identifier

ddd Z

eee

ZYX

fffØØ

M M

A1 ball

index area

7 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK

packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: ECOPACK® is an ST trademark.

7.1 UFBGA100 package information

UFBGA100 is a 100-ball, 7 × 7 mm, 0.50 mm pitch, ultra-fine-profile ball grid array package.

Figure 35. UFBGA100 package outline

www.st.com.

1. Drawing is not to scale.

Table 71. UFBGA100 package mechanical data

millimeters inches

Symbol

Min. Typ. Max. Min. Typ. Max.

A - - 0.600 - - 0.0236

A1 - - 0.110 - - 0.0043

A2 - 0.450 - - 0.0177 -

A3 - 0.130 - - 0.0051 0.0094

A4 - 0.320 - - 0.0126 -

100/128 DS9826 Rev 6

(1)

ST MICROELECTRONICS STM32F072CBT6 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Table 1. Device summary

1 Introduction

2 Description

Table 2. STM32F072x8/xB family device features and peripheral counts

Figure 1. Block diagram

3 Functional overview

3.1 Arm®-Cortex®-M0 core

3.2 Memories

3.3 Boot modes

3.4 Cyclic redundancy check calculation unit (CRC)

3.5 Power management

3.5.1 Power supply schemes

3.5.2 Power supply supervisors

3.5.3 Voltage regulator

3.5.4 Low-power modes

3.6 Clocks and startup

Figure 2. Clock tree

3.7 General-purpose inputs/outputs (GPIOs)

3.8 Direct memory access controller (DMA)

3.9 Interrupts and events

3.9.1 Nested vectored interrupt controller (NVIC)

3.9.2 Extended interrupt/event controller (EXTI)

3.10 Analog-to-digital converter (ADC)

3.10.1 Temperature sensor

Table 3. Temperature sensor calibration values

Table 4. Internal voltage reference calibration values

3.11 Digital-to-analog converter (DAC)

3.12 Comparators (COMP)

3.13 Touch sensing controller (TSC)

Table 5. Capacitive sensing GPIOs available on STM32F072x8/xB devices

3.14 Timers and watchdogs

Table 7. Timer feature comparison

3.14.1 Advanced-control timer (TIM1)

3.14.2 General-purpose timers (TIM2, 3, 14, 15, 16, 17)

3.14.3 Basic timers TIM6 and TIM7

3.14.4 Independent watchdog (IWDG)

3.14.5 System window watchdog (WWDG)

3.14.6 SysTick timer

3.15 Real-time clock (RTC) and backup registers

3.16 Inter-integrated circuit interface (I2C)

Table 8. Comparison of I2C analog and digital filters

Table 9. STM32F072x8/xB I2C implementation

3.17 Universal synchronous/asynchronous receiver/transmitter (USART)

Table 11. STM32F072x8/xB SPI/I2S implementation

3.19 High-definition multimedia interface (HDMI) - consumer electronics control (CEC)

3.20 Controller area network (CAN)

3.21 Universal serial bus (USB)

3.22 Clock recovery system (CRS)

3.23 Serial wire debug port (SW-DP)

4 Memory mapping

Figure 3. STM32F072xB memory map

Table 12. Peripheral register boundary addresses

5 Pinouts and pin descriptions

Figure 4. UFBGA100 package pinout

Figure 5. LQFP100 package pinout

Figure 6. UFBGA64 package pinout

Figure 7. LQFP64 package pinout

Figure 8. LQFP48 package pinout

Figure 9. UFQFPN48 package pinout

Figure 10. WLCSP49 package pinout

Table 13. Legend/abbreviations used in the pinout table

Table 15. Alternate functions selected through GPIOA_AFR registers for port A

Table 16. Alternate functions selected through GPIOB_AFR registers for port B

Table 17. Alternate functions selected through GPIOC_AFR registers for port C

Table 18. Alternate functions selected through GPIOD_AFR registers for port D

Table 19. Alternate functions selected through GPIOE_AFR registers for port E

Table 20. Alternate functions available on port F

6 Electrical characteristics

6.1 Parameter conditions

6.1.1 Minimum and maximum values

6.1.2 Typical values

6.1.3 Typical curves

6.1.4 Loading capacitor

6.1.5 Pin input voltage

Figure 11. Pin loading conditions Figure 12. Pin input voltage

6.1.6 Power supply scheme