STMicroelectronics STM32F05 series Reference Manual

RM0091

Reference manual

STM32F05xxx advanced ARM-based 32-bit MCUs

Introduction

This reference manual targets application developers. It provides complete information on
how to use the STM32F05xxx microcontroller memory and peripherals.

The STM32F05xxx is a family of microcontrollers with different memory sizes, packages and
peripherals.

For ordering information, mechanical and electrical device characteristics please refer to the
corresponding datasheet.

For information on the ARM C
reference manual.

Table 1. Applicable products

Typ e Part numbers

Microcontrollers STM32F051x4, STM32F051x6 , STM32F051x8

ORTEX™-M0 core, please refer to the Cortex-M0 technical

Related documents

■ Cortex-M0 technical reference manual, available from:

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/
DDI0432C_cortex_m0_r0p0_trm.pdf

■ STM32F05xxx datasheets available from your nearest ST sales office.

April 2012 Doc ID 018940 Rev 1 1/742

www.st.com

Contents RM0091

Contents

1 Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

1.1 List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

1.2 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

1.3 Peripheral availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2 System and memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2.1 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2.2 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2.2.2 Memory map and register boundary addresses . . . . . . . . . . . . . . . . . . 37

2.3 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

2.4 Flash memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

2.5 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.1 Flash main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.2 Flash memory functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.2.1 Flash memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.2.2 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.2.3 Flash program and erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.3 Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.3.1 Read protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.3.2 Write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.3.3 Option byte write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.4 Flash interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.5 Flash register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.5.1 Flash access control register (FLASH_ACR) . . . . . . . . . . . . . . . . . . . . . 53

3.5.2 Flash key register (FLASH_KEYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.5.3 Flash option key register (FLASH_OPTKEYR) . . . . . . . . . . . . . . . . . . . 54

3.5.4 Flash status register (FLASH_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.5.5 Flash control register (FLASH_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.5.6 Flash address register (FLASH_AR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.5.7 Option byte register (FLASH_OBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

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3.5.8 Write protection register (FLASH_WRPR) . . . . . . . . . . . . . . . . . . . . . . . 58

3.6 Flash register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

4 Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

5 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . 62

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5.2 CRC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5.3 CRC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.4 CRC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.4.1 Data register (CRC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.4.2 Independent data register (CRC_IDR) . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.4.3 Control register (CRC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.4.4 Initial CRC value (CRC_INIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.4.5 CRC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

6 Power control (PWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

6.1 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

6.1.1 Independent A/D and D/A converter supply and reference voltage . . . . 67

6.1.2 Battery backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

6.1.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

6.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

6.2.1 Power on reset (POR) / power down reset (PDR) . . . . . . . . . . . . . . . . . 69

6.2.2 Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . . 70

6.3 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6.3.1 Slowing down system clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6.3.2 Peripheral clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

6.3.3 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

6.3.4 Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

6.3.5 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

6.3.6 Auto-wakeup from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

6.4 Power control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

6.4.1 Power control register (PWR_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

6.4.2 Power control/status register (PWR_CSR) . . . . . . . . . . . . . . . . . . . . . . 79

6.4.3 PWR register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

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7 Reset and clock control (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

7.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

7.1.1 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

7.1.2 Power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

7.1.3 Backup domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

7.2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

7.2.1 HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

7.2.2 HSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

7.2.3 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

7.2.4 LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

7.2.5 LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

7.2.6 System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

7.2.7 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

7.2.8 ADC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

7.2.9 RTC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

7.2.10 Watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

7.2.11 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

7.3 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

7.4 RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

7.4.1 Clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

7.4.2 Clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . . . . . . 94

7.4.3 Clock interrupt register (RCC_CIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

7.4.4 APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . . . . . . 99

7.4.5 APB1 peripheral reset register (RCC_APB1RSTR) . . . . . . . . . . . . . . 101

7.4.6 AHB peripheral clock enable register (RCC_AHBENR) . . . . . . . . . . . 102

7.4.7 APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . . . . . . 104

7.4.8 APB1 peripheral clock enable register (RCC_APB1ENR) . . . . . . . . . . 105

7.4.9 Backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . . . . . 108

7.4.10 Control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

7.4.11 AHB peripheral reset register (RCC_AHBRSTR) . . . . . . . . . . . . . . . . 112

7.4.12 Clock configuration register 2 (RCC_CFGR2) . . . . . . . . . . . . . . . . . . . 113

7.4.13 Clock configuration register 3 (RCC_CFGR3) . . . . . . . . . . . . . . . . . . . 114

7.4.14 Clock control register 2 (RCC_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 115

7.4.15 RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

8 General-purpose I/Os (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

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8.1 GPIO introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

8.2 GPIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

8.3 GPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

8.3.1 General-purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

8.3.2 I/O pin alternate function multiplexer and mapping . . . . . . . . . . . . . . . 121

8.3.3 I/O port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

8.3.4 I/O port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

8.3.5 I/O data bitwise handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

8.3.6 GPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

8.3.7 I/O alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

8.3.8 External interrupt/wakeup lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

8.3.9 Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

8.3.10 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

8.3.11 Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

8.3.12 Analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

8.3.13 Using the HSE or LSE oscillator pins as GPIOs . . . . . . . . . . . . . . . . . 126

8.3.14 Using the GPIO pins in the backup supply domain . . . . . . . . . . . . . . . 126

8.4 GPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

8.4.1 GPIO port mode register (GPIOx_MODER) (x = A..D, F) . . . . . . . . . . 127

8.4.2 GPIO port output type register (GPIOx_OTYPER) (x = A..D, F) . . . . . 127

8.4.3 GPIO port output speed register (GPIOx_OSPEEDR)

(x = A..D, F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

8.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR)

(x = A..D, F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

8.4.5 GPIO port input data register (GPIOx_IDR) (x = A..D, F) . . . . . . . . . . 129

8.4.6 GPIO port output data register (GPIOx_ODR) (x = A..D, F) . . . . . . . . 129

8.4.7 GPIO port bit set/reset register (GPIOx_BSRR) (x = A..D, F) . . . . . . . 130

8.4.8 GPIO port configuration lock register (GPIOx_LCKR) (x = A..B) . . . . . 131

8.4.9 GPIO alternate function low register (GPIOx_AFRL) (x = A..B) . . . . . 132

8.4.10 GPIO alternate function high register (GPIOx_AFRH)

(x = A..B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

8.4.11 Port bit reset register (GPIOx_BRR) (x=A..D, F) . . . . . . . . . . . . . . . . . 133

8.4.12 GPIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

9 System configuration controller (SYSCFG) . . . . . . . . . . . . . . . . . . . . 135

9.1 SYSCFG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

9.1.1 SYSCFG configuration register 1 (SYSCFG_CFGR1) . . . . . . . . . . . . 135

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9.1.2 SYSCFG external interrupt configuration register 1

(SYSCFG_EXTICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

9.1.3 SYSCFG external interrupt configuration register 2

(SYSCFG_EXTICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

9.1.4 SYSCFG external interrupt configuration register 3

(SYSCFG_EXTICR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

9.1.5 SYSCFG external interrupt configuration register 4

(SYSCFG_EXTICR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

9.1.6 SYSCFG configuration register 2 (SYSCFG_CFGR2) . . . . . . . . . . . . 139

9.1.7 SYSCFG register maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

10 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . 142

10.1 DMA introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

10.2 DMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

10.3 DMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

10.3.1 DMA transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

10.3.2 Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

10.3.3 DMA channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

10.3.4 Programmable data width, data alignment and endians . . . . . . . . . . . 146

10.3.5 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

10.3.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

10.3.7 DMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

10.4 DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

10.4.1 DMA interrupt status register (DMA_ISR) . . . . . . . . . . . . . . . . . . . . . . 150

10.4.2 DMA interrupt flag clear register (DMA_IFCR) . . . . . . . . . . . . . . . . . . 151

10.4.3 DMA channel x configuration register (DMA_CCRx) (x = 1..5,

where x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

10.4.4 DMA channel x number of data register (DMA_CNDTRx) (x = 1..5),

where x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

10.4.5 DMA channel x peripheral address register (DMA_CPARx) (x = 1..5),

where x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

10.4.6 DMA channel x memory address register (DMA_CMARx) (x = 1..5),

where x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

10.4.7 DMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

11 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

11.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 157

11.1.1 NVIC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

11.1.2 SysTick calibration value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

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11.1.3 Interrupt and exception vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

11.2 Extended interrupts and events controller (EXTI) . . . . . . . . . . . . . . . . . 159

11.2.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

11.2.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

11.2.3 Wakeup event management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

11.2.4 Asynchronous Internal Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

11.2.5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

11.2.6 External and internal interrupt/event line mapping . . . . . . . . . . . . . . . 161

11.3 EXTI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

11.3.1 Interrupt mask register (EXTI_IMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

11.3.2 Event mask register (EXTI_EMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

11.3.3 Rising trigger selection register (EXTI_RTSR) . . . . . . . . . . . . . . . . . . 164

11.3.4 Falling trigger selection register (EXTI_FTSR) . . . . . . . . . . . . . . . . . . 164

11.3.5 Software interrupt event register (EXTI_SWIER) . . . . . . . . . . . . . . . . . 165

11.3.6 Pending register (EXTI_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

11.3.7 EXTI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

12 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

12.2 ADC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

12.3 ADC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

12.4 ADC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

12.4.1 Calibration (ADCAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

12.4.2 ADC on-off control (ADEN, ADDIS, ADRDY) . . . . . . . . . . . . . . . . . . . . 172

12.4.3 ADC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

12.4.4 Configuring the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

12.4.5 Channel selection (CHSEL, SCANDIR) . . . . . . . . . . . . . . . . . . . . . . . . 174

12.4.6 Programmable sampling time (SMP) . . . . . . . . . . . . . . . . . . . . . . . . . . 175

12.4.7 Single conversion mode (CONT=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

12.4.8 Continuous conversion mode (CONT=1) . . . . . . . . . . . . . . . . . . . . . . . 176

12.4.9 Starting conversions (ADSTART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

12.4.10 Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

12.4.11 Stopping an ongoing conversion (ADSTP) . . . . . . . . . . . . . . . . . . . . . 177

12.5 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN) . 178

12.5.1 Discontinuous mode (DISCEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

12.5.2 Programmable resolution (RES) - fast conversion mode . . . . . . . . . . . 179

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12.5.3 End of conversion, end of sampling phase (EOC, EOSMP flags) . . . . 180

12.5.4 End of conversion sequence (EOSEQ flag) . . . . . . . . . . . . . . . . . . . . . 180

12.5.5 Example timing diagrams (single/continuous modes . . . . . . . . . . . . . . . . .

hardware/software triggers) 181

12.6 Data management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

12.6.1 Data register & data alignment (ADC_DR, ALIGN) . . . . . . . . . . . . . . . 183

12.6.2 ADC overrun (OVR, OVRMOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

12.6.3 Managing a sequence of data converted without using the DMA . . . . 184

12.6.4 Managing converted data without using the DMA without overrun . . . 184

12.6.5 Managing converted data using the DMA . . . . . . . . . . . . . . . . . . . . . . 184

12.7 Low power features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

12.7.1 Wait mode conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

12.7.2 Auto-off mode (AUTOFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

12.8 Analog window watchdog (AWDEN, AWDSGL, AWDCH,

AWD_HTR/LTR, AWD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

12.9 Temperature sensor and internal reference voltage . . . . . . . . . . . . . . . . 189

12.10 Battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

12.11 ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

12.12 ADC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

12.12.1 ADC interrupt and status register (ADC_ISR) . . . . . . . . . . . . . . . . . . . 192

12.12.2 ADC interrupt enable register (ADC_IER) . . . . . . . . . . . . . . . . . . . . . . 193

12.12.3 ADC control register (ADC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

12.12.4 ADC configuration register 1 (ADC_CFGR1) . . . . . . . . . . . . . . . . . . . 196

12.12.5 ADC configuration register 2 (ADC_CFGR2) . . . . . . . . . . . . . . . . . . . 199

12.12.6 ADC sampling time register (ADC_SMPR) . . . . . . . . . . . . . . . . . . . . . 200

12.12.7 ADC watchdog threshold register (ADC_TR) . . . . . . . . . . . . . . . . . . . 200

12.12.8 ADC channel selection register (ADC_CHSELR) . . . . . . . . . . . . . . . . 201

12.12.9 ADC data register (ADC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

12.12.10 ADC common configuration register (ADC_CCR) . . . . . . . . . . . . . . . . 202

12.12.11 ADC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

13 Digital-to-analog converter (DAC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

13.1 DAC1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

13.2 DAC1 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

13.3 Single mode functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

13.3.1 DAC channel enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

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13.3.2 DAC output buffer enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

13.3.3 DAC data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

13.3.4 DAC conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

13.3.5 DAC output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

13.3.6 DAC trigger selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

13.4 DMA request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

13.5 DAC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

13.5.1 DAC control register (DAC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

13.5.2 DAC software trigger register (DAC_SWTRIGR) . . . . . . . . . . . . . . . . . 211

13.5.3 DAC channel1 12-bit right-aligned data holding register

(DAC_DHR12R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

13.5.4 DAC channel1 12-bit left aligned data holding register

(DAC_DHR12L1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

13.5.5 DAC channel1 8-bit right aligned data holding register

(DAC_DHR8R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

13.5.6 DAC channel1 data output register (DAC_DOR1) . . . . . . . . . . . . . . . . 212

13.5.7 DAC status register (DAC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

13.5.8 DAC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

14 Comparator (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

14.1 COMP introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

14.2 COMP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

14.3 COMP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

14.3.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

14.3.2 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

14.3.3 Comparator inputs and output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

14.3.4 Interrupt and wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

14.3.5 Power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

14.3.6 Comparator LOCK mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

14.3.7 Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

14.4 COMP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

14.4.1 COMP control and status register (COMP_CSR) . . . . . . . . . . . . . . . . 219

14.4.2 COMP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

15 Advanced-control timers (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

15.1 TIM1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

15.2 TIM1 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

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15.3 TIM1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

15.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

15.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

15.3.3 Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

15.3.4 Clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

15.3.5 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

15.3.6 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

15.3.7 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

15.3.8 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

15.3.9 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

15.3.10 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

15.3.11 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . . 248

15.3.12 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

15.3.13 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 253

15.3.14 6-step PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

15.3.15 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

15.3.16 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

15.3.17 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

15.3.18 Interfacing with Hall sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

15.3.19 TIMx and external trigger synchronization . . . . . . . . . . . . . . . . . . . . . . 261

15.3.20 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

15.3.21 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

15.4 TIM1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

15.4.1 TIM1 control register 1 (TIM1_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 265

15.4.2 TIM1 control register 2 (TIM1_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 266

15.4.3 TIM1 slave mode control register (TIM1_SMCR) . . . . . . . . . . . . . . . . 268

15.4.4 TIM1 DMA/interrupt enable register (TIM1_DIER) . . . . . . . . . . . . . . . 270

15.4.5 TIM1 status register (TIM1_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

15.4.6 TIM1 event generation register (TIM1_EGR) . . . . . . . . . . . . . . . . . . . . 273

15.4.7 TIM1 capture/compare mode register 1 (TIM1_CCMR1) . . . . . . . . . . 275

15.4.8 TIM1 capture/compare mode register 2 (TIM1_CCMR2) . . . . . . . . . . 278

15.4.9 TIM1 capture/compare enable register (TIM1_CCER) . . . . . . . . . . . . 279

15.4.10 TIM1 counter (TIM1_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

15.4.11 TIM1 prescaler (TIM1_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

15.4.12 TIM1 auto-reload register (TIM1_ARR) . . . . . . . . . . . . . . . . . . . . . . . . 283

15.4.13 TIM1 repetition counter register (TIM1_RCR) . . . . . . . . . . . . . . . . . . . 284

15.4.14 TIM1 capture/compare register 1 (TIM1_CCR1) . . . . . . . . . . . . . . . . . 284

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15.4.15 TIM1 capture/compare register 2 (TIM1_CCR2) . . . . . . . . . . . . . . . . . 285

15.4.16 TIM1 capture/compare register 3 (TIM1_CCR3) . . . . . . . . . . . . . . . . . 285

15.4.17 TIM1 capture/compare register 4 (TIM1_CCR4) . . . . . . . . . . . . . . . . . 286

15.4.18 TIM1 break and dead-time register (TIM1_BDTR) . . . . . . . . . . . . . . . 286

15.4.19 TIM1 DMA control register (TIM1_DCR) . . . . . . . . . . . . . . . . . . . . . . . 288

15.4.20 TIM1 DMA address for full transfer (TIM1_DMAR) . . . . . . . . . . . . . . . 289

15.4.21 TIM1 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

16 General-purpose timers (TIM2 and TIM3) . . . . . . . . . . . . . . . . . . . . . . 292

16.1 TIM2 and TIM3 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

16.2 TIM2 and TIM3 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

16.3 TIM2 and TIM3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . 293

16.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

16.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

16.3.3 Clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

16.3.4 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

16.3.5 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

16.3.6 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

16.3.7 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

16.3.8 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

16.3.9 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

16.3.10 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

16.3.11 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 316

16.3.12 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

16.3.13 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

16.3.14 Timers and external trigger synchronization . . . . . . . . . . . . . . . . . . . . 320

16.3.15 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

16.3.16 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

16.4 TIM2 and TIM3 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329

16.4.1 TIM2 and TIM3 control register 1 (TIM2_CR1 and TIM3_CR1) . . . . . 329

16.4.2 TIM2 and TIM3 control register 2 (TIM2_CR2 and TIM3_CR2) . . . . . 331

16.4.3 TIM2 and TIM3 slave mode control register (TIM2_SMCR and

TIM3_SMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

16.4.4 TIM2 and TIM3 DMA/Interrupt enable register (TIM2_DIER and

TIM3_DIER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

16.4.5 TIM2 and TIM3 status register (TIM2_SR and TIM3_SR) . . . . . . . . . . 336

16.4.6 TIM2 and TIM3 event generation register (TIM2_EGR and TIM3_EGR) .

338

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16.4.7 TIM2 and TIM3 capture/compare mode register 1 (TIM2_CCMR1 and

TIM3_CCMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339

16.4.8 TIM2 and TIM3 capture/compare mode register 2 (TIM2_CCMR2 and

TIM3_CCMR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

16.4.9 TIM2 and TIM3 capture/compare enable register (TIM2_CCER and

TIM3_CCER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343

16.4.10 TIM2 and TIM3 counter (TIM2_CNT and TIM3_CNT) . . . . . . . . . . . . . 345

16.4.11 TIM2 and TIM3 prescaler (TIM2_PSC and TIM3_PSC) . . . . . . . . . . . 345

16.4.12 TIM2 and TIM3 auto-reload register (TIM2_ARR and TIM3_ARR) . . . 345

16.4.13 TIM2 and TIM3 capture/compare register 1 (TIM2_CCR1 and

TIM3_CCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346

16.4.14 TIM2 and TIM3 capture/compare register 2 (TIM2_CCR2 and

TIM3_CCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346

16.4.15 TIM2 and TIM3 capture/compare register 3 (TIM2_CCR3 and

TIM3_CCR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348

16.4.16 TIM2 and TIM3 capture/compare register 4 (TIM2_CCR4 and

TIM3_CCR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348

16.4.17 TIM2 and TIM3 DMA control register (TIM2_DCR and TIM3_DCR) . . 349

16.4.18 TIM2 and TIM3 DMA address for full transfer (TIM2_DMAR and

TIM3_DMAR) 349

16.4.19 TIM2 and TIM3 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351

17 General-purpose timer (TIM14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353

17.1 TIM14 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353

17.2 TIM14 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353

17.3 TIM14 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354

17.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354

17.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356

17.3.3 Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359

17.3.4 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359

17.3.5 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

17.3.6 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362

17.3.7 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362

17.3.8 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

17.3.9 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364

17.4 TIM14 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365

17.4.1 TIM14 control register 1 (TIM14_CR1) . . . . . . . . . . . . . . . . . . . . . . . . 365

17.4.2 TIM14 interrupt enable register (TIM14_DIER) . . . . . . . . . . . . . . . . . . 366

17.4.3 TIM14 status register (TIM14_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 366

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17.4.4 TIM14 event generation register (TIM14_EGR) . . . . . . . . . . . . . . . . . . 367

17.4.5 TIM14 capture/compare mode register 1 (TIM14_CCMR1) . . . . . . . . 368

17.4.6 TIM14 capture/compare enable register (TIM14_CCER) . . . . . . . . . . 370

17.4.7 TIM14 counter (TIM14_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371

17.4.8 TIM14 prescaler (TIM14_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371

17.4.9 TIM14 auto-reload register (TIM14_ARR) . . . . . . . . . . . . . . . . . . . . . . 371

17.4.10 TIM14 capture/compare register 1 (TIM14_CCR1) . . . . . . . . . . . . . . . 372

17.4.11 TIM14 option register (TIM14_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 372

17.4.12 TIM14 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373

18 General-purpose timers (TIM15/16/17) . . . . . . . . . . . . . . . . . . . . . . . . 375

18.1 TIM15/16/17 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375

18.2 TIM15 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375

18.3 TIM16 and TIM17 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376

18.4 TIM15/16/17 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379

18.4.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379

18.4.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380

18.4.3 Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383

18.4.4 Clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384

18.4.5 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386

18.4.6 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388

18.4.7 PWM input mode (only for TIM15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389

18.4.8 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390

18.4.9 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390

18.4.10 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391

18.4.11 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . . 393

18.4.12 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394

18.4.13 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

18.4.14 TIM15 external trigger synchronization . . . . . . . . . . . . . . . . . . . . . . . . 399

18.4.15 Timer synchronization (TIM15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401

18.4.16 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401

18.5 TIM15 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402

18.5.1 TIM15 control register 1 (TIM15_CR1) . . . . . . . . . . . . . . . . . . . . . . . . 402

18.5.2 TIM15 control register 2 (TIM15_CR2) . . . . . . . . . . . . . . . . . . . . . . . . 403

18.5.3 TIM15 slave mode control register (TIM15_SMCR) . . . . . . . . . . . . . . 404

18.5.4 TIM15 DMA/interrupt enable register (TIM15_DIER) . . . . . . . . . . . . . 406

18.5.5 TIM15 status register (TIM15_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 407

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18.5.6 TIM15 event generation register (TIM15_EGR) . . . . . . . . . . . . . . . . . . 408

18.5.7 TIM15 capture/compare mode register 1 (TIM15_CCMR1) . . . . . . . . 409

18.5.8 TIM15 capture/compare enable register (TIM15_CCER) . . . . . . . . . . 412

18.5.9 TIM15 counter (TIM15_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415

18.5.10 TIM15 prescaler (TIM15_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415

18.5.11 TIM15 auto-reload register (TIM15_ARR) . . . . . . . . . . . . . . . . . . . . . . 415

18.5.12 TIM15 repetition counter register (TIM15_RCR) . . . . . . . . . . . . . . . . . 416

18.5.13 TIM15 capture/compare register 1 (TIM15_CCR1) . . . . . . . . . . . . . . . 416

18.5.14 TIM15 capture/compare register 2 (TIM15_CCR2) . . . . . . . . . . . . . . . 417

18.5.15 TIM15 break and dead-time register (TIM15_BDTR) . . . . . . . . . . . . . 417

18.5.16 TIM15 DMA control register (TIM15_DCR) . . . . . . . . . . . . . . . . . . . . . 419

18.5.17 TIM15 DMA address for full transfer (TIM15_DMAR) . . . . . . . . . . . . . 420

18.5.18 TIM15 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420

18.6 TIM16 and TIM17 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422

18.6.1 TIM16 and TIM17 control register 1 (TIM16_CR1 and TIM17_CR1) . 422

18.6.2 TIM16 and TIM17 control register 2 (TIM16_CR2 and TIM17_CR2) . 423

18.6.3 TIM16 and TIM17 DMA/interrupt enable register (TIM16_DIER and

TIM17_DIER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424

18.6.4 TIM16 and TIM17 status register (TIM16_SR and TIM17_SR) . . . . . . 425

18.6.5 TIM16 and TIM17 event generation register (TIM16_EGR and

TIM17_EGR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426

18.6.6 TIM16 and TIM17 capture/compare mode register 1 (TIM16_CCMR1 and

TIM17_CCMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427

18.6.7 TIM16 and TIM17 capture/compare enable register (TIM16_CCER and

TIM17_CCER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430

18.6.8 TIM16 and TIM17 counter (TIM16_CNT and TIM17_CNT) . . . . . . . . . 432

18.6.9 TIM16 and TIM17 prescaler (TIM16_PSC and TIM17_PSC) . . . . . . . 432

18.6.10 TIM16 and TIM17 auto-reload register (TIM16_ARR and TIM17_ARR) . .

432

18.6.11 TIM16 and TIM17 repetition counter register (TIM16_RCR and

TIM17_RCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433

18.6.12 TIM16 and TIM17 capture/compare register 1 (TIM16_CCR1 and

TIM17_CCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433

18.6.13 TIM16 and TIM17 break and dead-time register (TIM16_BDTR and

TIM17_BDTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434

18.6.14 TIM16 and TIM17 DMA control register (TIM16_DCR and TIM17_DCR) .

436

18.6.15 TIM16 and TIM17 DMA address for full transfer (TIM16_DMAR and

TIM17_DMAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436

18.6.16 TIM16 and TIM17 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438

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19 Basic timer (TIM6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440

19.1 TIM6 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440

19.2 TIM6 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440

19.3 TIM6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441

19.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441

19.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443

19.3.3 Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446

19.3.4 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446

19.4 TIM6 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447

19.4.1 TIM6 control register 1 (TIM6_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 447

19.4.2 TIM6 control register 2 (TIM6_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 448

19.4.3 TIM6 DMA/Interrupt enable register (TIM6_DIER) . . . . . . . . . . . . . . . 448

19.4.4 TIM6 status register (TIM6_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449

19.4.5 TIM6 event generation register (TIM6_EGR) . . . . . . . . . . . . . . . . . . . . 449

19.4.6 TIM6 counter (TIM6_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449

19.4.7 TIM6 prescaler (TIM6_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450

19.4.8 TIM6 auto-reload register (TIM6_ARR) . . . . . . . . . . . . . . . . . . . . . . . . 450

19.4.9 TIM6 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451

20 Infrared (IRTIM) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452

20.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452

21 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453

21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453

21.2 IWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453

21.3 IWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453

21.3.1 Window option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453

21.3.2 Hardware watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454

21.3.3 Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454

21.3.4 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454

21.4 IWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455

21.4.1 Key register (IWDG_KR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455

21.4.2 Prescaler register (IWDG_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456

21.4.3 Reload register (IWDG_RLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457

21.4.4 Status register (IWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458

21.4.5 Window register (IWDG_WINR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459

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21.4.6 IWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460

22 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . 461

22.1 WWDG introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461

22.2 WWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461

22.3 WWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461

22.4 How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . . 463

22.5 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464

22.6 WWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465

22.6.1 Control register (WWDG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465

22.6.2 Configuration register (WWDG_CFR) . . . . . . . . . . . . . . . . . . . . . . . . . 466

22.6.3 Status register (WWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466

22.6.4 WWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467

23 Inter-integrated circuit (I2C) interface . . . . . . . . . . . . . . . . . . . . . . . . . 468

23.1 I2C introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468

23.2 I

2

C main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468

23.3 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469

23.4 I

2

C functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469

23.4.1 I2C1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470

23.4.2 I2C2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471

23.4.3 I

23.4.4 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472

23.4.5 I

23.4.6 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476

23.4.7 Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477

23.4.8 I2C slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479

23.4.9 I2C master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487

23.4.10 I2Cx_TIMINGR register configuration examples . . . . . . . . . . . . . . . . . 499

23.4.11 SMBus specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501

23.4.12 SMBus initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504

23.4.13 SMBus: I2Cx_TIMEOUTR register configuration examples . . . . . . . . 505

2

C clock requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471

2

C initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473

23.4.14 SMBus slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506

23.4.15 Wakeup from STOP on address match . . . . . . . . . . . . . . . . . . . . . . . . 513

23.4.16 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514

23.4.17 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516

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23.5 I2C interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517

23.6 I

23.7 I

2

C debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519

2

C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519

23.7.1 Control register 1 (I2Cx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519

23.7.2 Control register 2 (I2Cx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522

23.7.3 Own address 1 register (I2Cx_OAR1) . . . . . . . . . . . . . . . . . . . . . . . . . 524

23.7.4 Own address 2 register (I2Cx_OAR2) . . . . . . . . . . . . . . . . . . . . . . . . . 525

23.7.5 Timing register (I2Cx_TIMINGR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526

23.7.6 Timeout register (I2Cx_TIMEOUTR) . . . . . . . . . . . . . . . . . . . . . . . . . . 527

23.7.7 Interrupt and Status register (I2Cx_ISR) . . . . . . . . . . . . . . . . . . . . . . . 528

23.7.8 Interrupt clear register (I2Cx_ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531

23.7.9 PEC register (I2Cx_PECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532

23.7.10 Receive data register (I2Cx_RXDR) . . . . . . . . . . . . . . . . . . . . . . . . . . 532

23.7.11 Transmit data register (I2Cx_TXDR) . . . . . . . . . . . . . . . . . . . . . . . . . . 533

23.8 I2C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534

24 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535

24.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535

24.2 RTC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535

24.3 RTC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536

24.3.1 RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536

24.3.2 GPIOs controlled by the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537

24.3.3 Clock and prescalers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538

24.3.4 Real-time clock and calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539

24.3.5 Programmable alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539

24.3.6 RTC initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 540

24.3.7 Reading the calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541

24.3.8 Resetting the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542

24.3.9 RTC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542

24.3.10 RTC reference clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543

24.3.11 RTC smooth digital calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544

24.3.12 Time-stamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546

24.3.13 Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546

24.3.14 Calibration clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548

24.3.15 Alarm output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548

24.4 RTC low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548

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24.5 RTC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549

24.6 RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550

24.6.1 RTC time register (RTC_TR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550

24.6.2 RTC date register (RTC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551

24.6.3 RTC control register (RTC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552

24.6.4 RTC initialization and status register (RTC_ISR) . . . . . . . . . . . . . . . . . 555

24.6.5 RTC prescaler register (RTC_PRER) . . . . . . . . . . . . . . . . . . . . . . . . . 557

24.6.6 RTC alarm A register (RTC_ALRMAR) . . . . . . . . . . . . . . . . . . . . . . . . 557

24.6.7 RTC write protection register (RTC_WPR) . . . . . . . . . . . . . . . . . . . . . 559

24.6.8 RTC sub second register (RTC_SSR) . . . . . . . . . . . . . . . . . . . . . . . . . 560

24.6.9 RTC shift control register (RTC_SHIFTR) . . . . . . . . . . . . . . . . . . . . . . 561

24.6.10 RTC timestamp time register (RTC_TSTR) . . . . . . . . . . . . . . . . . . . . . 562

24.6.11 RTC timestamp date register (RTC_TSDR) . . . . . . . . . . . . . . . . . . . . 562

24.6.12 RTC time-stamp sub second register (RTC_TSSSR) . . . . . . . . . . . . . 563

24.6.13 RTC calibration register (RTC_CALR) . . . . . . . . . . . . . . . . . . . . . . . . . 564

24.6.14 RTC tamper and alternate function configuration register

(RTC_TAFCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565

24.6.15 RTC alarm A sub second register (RTC_ALRMASSR) . . . . . . . . . . . . 568

24.6.16 RTC backup registers (RTC_BKPxR) . . . . . . . . . . . . . . . . . . . . . . . . . 569

24.6.17 RTC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569

25 Universal synchronous asynchronous receiver

transmitter (USART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571

25.1 USART introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571

25.2 USART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571

25.3 USART extended features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572

25.4 USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573

25.5 USART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573

25.5.1 USART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576

25.5.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577

25.5.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579

25.5.4 Baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585

25.5.5 Tolerance of the USART receiver to clock deviation . . . . . . . . . . . . . . 587

25.5.6 Auto baud rate detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588

25.5.7 Multiprocessor communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589

25.5.8 ModBus communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590

25.5.9 Parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591

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25.5.10 LIN (local interconnection network) mode . . . . . . . . . . . . . . . . . . . . . . 592

25.5.11 USART synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594

25.5.12 Single-wire half-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . 596

25.5.13 Smartcard mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597

25.5.14 IrDA SIR ENDEC block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601

25.5.15 Continuous communication using DMA . . . . . . . . . . . . . . . . . . . . . . . . 604

25.5.16 Hardware flow control and RS485 Driver Enable . . . . . . . . . . . . . . . . 606

25.5.17 Wakeup from Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608

25.6 USART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609

25.7 USART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611

25.7.1 Control register 1 (USART_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611

25.7.2 Control register 2 (USART_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614

25.7.3 Control register 3 (USART_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618

25.7.4 Baud rate register (USART_BRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621

25.7.5 Guard time and prescaler register (USART_GTPR) . . . . . . . . . . . . . . 622

25.7.6 Receiver timeout register (USART_RTOR) . . . . . . . . . . . . . . . . . . . . . 623

25.7.7 Request register (USART_RQR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624

25.7.8 Interrupt & status register (USART_ISR) . . . . . . . . . . . . . . . . . . . . . . . 625

25.7.9 Interrupt flag clear register (USART_ICR) . . . . . . . . . . . . . . . . . . . . . . 629

25.7.10 Receive data register (USART_RDR) . . . . . . . . . . . . . . . . . . . . . . . . . 631

25.7.11 Transmit data register (USART_TDR) . . . . . . . . . . . . . . . . . . . . . . . . . 632

25.7.12 USART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633

26 Serial peripheral interface / inter-IC sound (SPI/I2S) . . . . . . . . . . . . . 634

26.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634

26.1.1 SPI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634

26.1.2 SPI extended features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635

26.1.3 I²S features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635

26.2 SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635

26.3 SPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635

26.3.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635

26.3.2 Communications between one master and one slave . . . . . . . . . . . . . 636

26.3.3 Standard multi-slave communication . . . . . . . . . . . . . . . . . . . . . . . . . . 638

26.3.4 Slave select (NSS) pin management . . . . . . . . . . . . . . . . . . . . . . . . . . 639

26.3.5 Communication formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640

26.3.6 Initialize SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642

26.3.7 Data transmission and reception procedures . . . . . . . . . . . . . . . . . . . 643

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26.3.8 SPI Status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646

26.3.9 SPI error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647

26.4 SPI special features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648

26.4.1 NSS pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648

26.4.2 TI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649

26.4.3 CRC calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650

26.5 SPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652

26.6 I2S functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652

26.6.1 I2S general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652

26.6.2 Supported audio protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654

26.6.3 Clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660

26.6.4 I

26.6.5 I

26.6.6 I

26.6.7 I

26.6.8 I

26.6.9 DMA features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669

2

S master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663

2

S slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664

2

S status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667

2

S error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668

2

S interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669

26.7 SPI and I2S registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670

26.7.1 SPI control register 1 (SPIx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670

26.7.2 SPI control register 2 (SPIx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672

26.7.3 SPI status register (SPIx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674

26.7.4 SPI data register (SPIx_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676

26.7.5 SPI CRC polynomial register (SPIx_CRCPR) . . . . . . . . . . . . . . . . . . . 676

26.7.6 SPI Rx CRC register (SPIx_RXCRCR) . . . . . . . . . . . . . . . . . . . . . . . . 677

26.7.7 SPI Tx CRC register (SPIx_TXCRCR) . . . . . . . . . . . . . . . . . . . . . . . . 677

26.7.8 SPIx_I

26.7.9 SPIx_I

2

S configuration register (SPIx_I2SCFGR) . . . . . . . . . . . . . . . . 678

2

S prescaler register (SPIx_I2SPR) . . . . . . . . . . . . . . . . . . . . . 679

26.7.10 SPI/I2S register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680

27 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681

27.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681

27.2 TSC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681

27.3 TSC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682

27.3.1 TSC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682

27.3.2 Surface charge transfer acquisition overview . . . . . . . . . . . . . . . . . . . 682

27.3.3 Reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684

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27.3.4 Charge transfer acquisition sequence . . . . . . . . . . . . . . . . . . . . . . . . . 685

27.3.5 Spread spectrum feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686

27.3.6 Max count error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686

27.3.7 Sampling capacitor I/O and channel I/O mode selection . . . . . . . . . . . 687

27.3.8 Acquisition mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688

27.3.9 I/O hysteresis and analog switch control . . . . . . . . . . . . . . . . . . . . . . . 688

27.3.10 Capacitive sensing GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689

27.4 TSC low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689

27.5 TSC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689

27.6 TSC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690

27.6.1 TSC control register (TSC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690

27.6.2 TSC interrupt enable register (TSC_IER) . . . . . . . . . . . . . . . . . . . . . . 693

27.6.3 TSC interrupt clear register (TSC_ICR) . . . . . . . . . . . . . . . . . . . . . . . . 693

27.6.4 TSC interrupt status register (TSC_ISR) . . . . . . . . . . . . . . . . . . . . . . . 694

27.6.5 TSC I/O hysteresis control register (TSC_IOHCR) . . . . . . . . . . . . . . . 694

27.6.6 TSC I/O analog switch control register (TSC_IOASCR) . . . . . . . . . . . 695

27.6.7 TSC I/O sampling control register (TSC_IOSCR) . . . . . . . . . . . . . . . . 695

27.6.8 TSC I/O channel control register (TSC_IOCCR) . . . . . . . . . . . . . . . . . 696

27.6.9 TSC I/O group control status register (TSC_IOGCSR) . . . . . . . . . . . . 696

27.6.10 TSC I/O group x counter register (TSC_IOGxCR) (x=1..6) . . . . . . . . . 697

27.6.11 TSC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697

28 HDMI-CEC controller (HDMI-CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699

28.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699

28.2 HDMI-CEC controller main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699

28.3 HDMI-CEC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700

28.3.1 HDMI-CEC pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700

28.3.2 Message description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701

28.3.3 Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701

28.4 Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702

28.4.1 SFT option bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703

28.5 Error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704

28.5.1 Bit error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704

28.5.2 Message error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704

28.5.3 Bit Rising Error (BRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704

28.5.4 Short Bit Period Error (SBPE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705

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28.5.5 Long Bit Period Error (LBPE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705

28.5.6 Transmission Error Detection (TXERR) . . . . . . . . . . . . . . . . . . . . . . . . 707

28.6 HDMI-CEC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708

28.7 HDMI-CEC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709

28.7.1 CEC control register (CEC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709

28.7.2 CEC configuration register (CEC_CFGR) . . . . . . . . . . . . . . . . . . . . . . 711

28.7.3 CEC Tx data register (CEC_TXDR) . . . . . . . . . . . . . . . . . . . . . . . . . . 713

28.7.4 CEC Rx Data Register (CEC_RXDR) . . . . . . . . . . . . . . . . . . . . . . . . . 713

28.7.5 CEC Interrupt and Status Register (CEC_ISR) . . . . . . . . . . . . . . . . . . 713

28.7.6 CEC interrupt enable register (CEC_IER)* . . . . . . . . . . . . . . . . . . . . . 715

28.7.7 HDMI-CEC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717

29 Debug support (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718

29.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718

29.2 Reference ARM documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719

29.3 Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719

29.3.1 SW debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720

29.3.2 Flexible SW-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720

29.3.3 Internal pull-up & pull-down on SW pins . . . . . . . . . . . . . . . . . . . . . . . 720

29.4 ID codes and locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720

29.4.1 MCU device ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721

29.5 SW debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721

29.5.1 SW protocol introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721

29.5.2 SW protocol sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722

29.5.3 SW-DP state machine (reset, idle states, ID code) . . . . . . . . . . . . . . . 723

29.5.4 DP and AP read/write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723

29.5.5 SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723

29.5.6 SW-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725

29.6 Core debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725

29.7 BPU (Break Point Unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726

29.7.1 BPU functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726

29.8 DWT (Data Watchpoint) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726

29.8.1 DWT functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726

29.8.2 DWT Program Counter Sample Register . . . . . . . . . . . . . . . . . . . . . . . 726

29.9 MCU debug component (DBGMCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 726

29.9.1 Debug support for low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 727

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29.9.2 Debug support for timers, watchdog and I2C . . . . . . . . . . . . . . . . . . . . 727

29.9.3 Debug MCU configuration register (DBGMCU_CR) . . . . . . . . . . . . . . 728

29.9.4 Debug MCU APB low freeze register (DBGMCU_APB1_FZ) . . . . . . . 729

29.9.5 Debug MCU APB2 freeze register (DBGMCU_APB2_FZ) . . . . . . . . . 731

29.10 DBG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732

30 Device electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733

30.1 Unique device ID register (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733

30.2 Memory size data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735

30.2.1 Flash size data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735

31 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741

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List of tables RM0091

List of tables

Table 1. Applicable products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. STM32F05xxx memory map and peripheral register boundary addresses . . . . . . . . . . . . 37

Table 3. Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 4. Flash module organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 5. Flash memory read protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 6. Access status versus protection level and execution modes . . . . . . . . . . . . . . . . . . . . . . . 51

Table 7. Flash interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 8. Flash interface - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 9. Option byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 10. Option byte organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 11. Description of the option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 12. CRC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 13. Low-power mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 14. Sleep-now . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 15. Sleep-on-exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 16. Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 17. Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 18. PWR register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 19. RCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Table 20. Port bit configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Table 21. GPIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Table 22. SYSCFG register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Table 23. Programmable data width & endian behavior (when bits PINC = MINC = 1) . . . . . . . . . . 146

Table 24. DMA interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Table 25. Summary of DMA requests for each channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Table 26. DMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Table 27. Vector table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Table 28. External interrupt/event controller register map and reset values. . . . . . . . . . . . . . . . . . . 167

Table 29. ADC internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Table 30. ADC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Table 31. Latency between trigger and start of conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Table 32. Configuring the trigger polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Table 33. External triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Table 34. tSAR timings depending on resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Table 35. Analog watchdog comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Table 36. Analog watchdog channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Table 37. ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Table 38. ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Table 39. DAC1 pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Table 40. External triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

Table 41. DAC register map and reset values.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Table 42. COMP register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

Table 43. Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

Table 44. TIMx Internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

Table 45. Output control bits for complementary OCx and OCxN channels with

break feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

Table 46. TIM1 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

Table 47. Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318

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Table 48. TIM2 and TIM3 internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334

Table 49. Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344

Table 50. TIM2 and TIM3 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351

Table 51. Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370

Table 52. TIM14 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373

Table 53. TIMx Internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405

Table 54. Output control bits for complementary OCx and OCxN channels with break feature. . . . 414

Table 55. TIM15 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420

Table 56. Output control bits for complementary OCx and OCxN channels with break feature. . . . 431

Table 57. TIM16 and TIM17 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438

Table 58. TIM6 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451

Table 59. IWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460

Table 60. WWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467

Table 61. I2C Configurations in Goldfish and Manta edge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468

Table 62. STM32F05xxx I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469

Table 63. Comparison of analog vs. digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473

Table 64. I2C-SMBUS specification data setup and hold times . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475

Table 66. I2C-SMBUS specification clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488

Table 67. Examples of timings settings for fI2CCLK = 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499

Table 68. Examples of timings settings for fI2CCLK = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499

Table 69. Examples of timings settings for fI2CCLK = 48 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500

Table 70. SMBus timeout specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503

Table 71. SMBUS with PEC configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504

Table 72. Examples of TIMEOUTA settings for various I2CCLK frequencies . . . . . . . . . . . . . . . . . 506

Table 73. Examples of TIMEOUTB settings for various I2CCLK frequencies . . . . . . . . . . . . . . . . . 506

Table 74. Examples of TIMEOUTA settings for various I2CCLK frequencies . . . . . . . . . . . . . . . . . 506

Table 75. I2C Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517

Table 76. I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534

Table 77. RTC pin PC13 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537

Table 78. LSE pin PC14 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538

Table 79. LSE pin PC15 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538

Table 80. Effect of low power modes on RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548

Table 81. Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549

Table 82. RTC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569

Table 83. STM32F05xxx USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573

Table 84. Noise detection from sampled data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583

Table 85. Error calculation for programmed baud rates at f

= 48 MHz

CK

for oversampling by 16 and by 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586

Table 86. Tolerance of the USART receiver when BRR[3:0] = 0000 . . . . . . . . . . . . . . . . . . . . . . . . 587

Table 87. Tolerance of the USART receiver when BRR[3:0]

is different from 0000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588

Table 88. Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591

Table 89. USART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609

Table 90. USART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633

Table 91. SPI interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652

Table 92. Audio-frequency precision using standard 8 MHz HSE . . . . . . . . . . . . . . . . . . . . . . . . . . 662

Table 93. I

2

S interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669

Table 94. SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680

Table 95. Acquisition sequence summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684

Table 96. Spread spectrum deviation versus AHB clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . 686

Table 97. I/O state depending on its mode and IODEF bit value . . . . . . . . . . . . . . . . . . . . . . . . . . . 687

Table 98. Capacitive sensing GPIOs available on STM32F05xxx devices . . . . . . . . . . . . . . . . . . . 689

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List of tables RM0091

Table 99. Effect of low power modes on TSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689

Table 100. Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689

Table 101. TSC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697

Table 102. HDMI pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700

Table 103. Error handling timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706

Table 104. TXERR timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707

Table 105. HDMI-CEC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708

Table 106. HDMI-CEC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717

Table 107. SW debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720

Table 108. Packet request (8-bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722

Table 109. ACK response (3 bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722

Table 110. DATA transfer (33 bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722

Table 111. SW-DP registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723

Table 112. 32-bit debug port registers addressed through the shifted value A[3:2] . . . . . . . . . . . . . . 725

Table 113. Core debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725

Table 114. DBG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732

Table 115. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741

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List of figures

Figure 1. System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 2. Programming procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 3. Flash memory Page Erase procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 4. Flash memory Mass Erase procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 5. CRC calculation unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 6. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 7. Power on reset/power down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 8. PVD thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 9. Simplified diagram of the reset circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 10. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 11. HSE/ LSE clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 12. Basic structure of a standard I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 13. Basic structure of a five-volt tolerant I/O port bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 14. Input floating/pull up/pull down configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 15. Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Figure 16. Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Figure 17. High impedance-analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Figure 18. DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Figure 19. DMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Figure 20. EXTI external interrupt/event block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Figure 21. External interrupt/event GPIO mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Figure 22. ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Figure 23. ADC calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Figure 24. Enabling/disabling the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Figure 25. Analog to digital conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Figure 26. Stopping an ongoing conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Figure 27. Single conversions of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Figure 28. Continuous conversion of a sequence, software trigger. . . . . . . . . . . . . . . . . . . . . . . . . . 181

Figure 29. Single conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Figure 30. Continuous conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . 182

Figure 31. Data alignment and resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Figure 32. Example of overrun (OVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Figure 33. Wait mode conversion (continuous mode, software trigger). . . . . . . . . . . . . . . . . . . . . . . 186

Figure 34. Behavior withWAIT=0, AUTOFF=1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Figure 35. Behavior with WAIT=1, AUTOFF=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Figure 36. Analog watchdog guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Figure 37. Temperature sensor and VREFINT channel block diagram . . . . . . . . . . . . . . . . . . . . . . 189

Figure 38. DAC1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Figure 39. Data registers in single DAC channel mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Figure 40. Timing diagram for conversion with trigger disabled TEN = 0 . . . . . . . . . . . . . . . . . . . . . 208

Figure 41. Comparators block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Figure 42. Comparator hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Figure 43. Advanced-control timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Figure 44. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 226

Figure 45. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 226

Figure 46. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

Figure 47. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

Figure 48. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

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Figure 49. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

Figure 50. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . . 229

Figure 51. Counter timing diagram, update event when ARPE=1

(TIMx_ARR preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

Figure 52. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

Figure 53. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

Figure 54. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

Figure 55. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

Figure 56. Counter timing diagram, update event when repetition counter

is not used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

Figure 57. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . . 233

Figure 58. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

Figure 59. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 233

Figure 60. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

Figure 61. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . . . . . . . . . 234

Figure 62. Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . . . . . . . . . . 235

Figure 63. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 236

Figure 64. Control circuit in normal mode, internal clock divided by 1. . . . . . . . . . . . . . . . . . . . . . . . 237

Figure 65. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

Figure 66. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

Figure 67. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

Figure 68. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

Figure 69. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 240

Figure 70. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

Figure 71. Output stage of capture/compare channel (channel 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . 241

Figure 72. Output stage of capture/compare channel (channel 4). . . . . . . . . . . . . . . . . . . . . . . . . . . 241

Figure 73. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

Figure 74. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Figure 75. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Figure 76. Center-aligned PWM waveforms (ARR=8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

Figure 77. Complementary output with dead-time insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

Figure 78. Dead-time waveforms with delay greater than the negative pulse. . . . . . . . . . . . . . . . . . 249

Figure 79. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 249

Figure 80. Output behavior in response to a break.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

Figure 81. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

Figure 82. 6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

Figure 83. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Figure 84. Example of counter operation in encoder interface mode. . . . . . . . . . . . . . . . . . . . . . . . . 258

Figure 85. Example of encoder interface mode with TI1FP1 polarity inverted. . . . . . . . . . . . . . . . . . 258

Figure 86. Example of hall sensor interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

Figure 87. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

Figure 88. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

Figure 89. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

Figure 90. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 264

Figure 91. General-purpose timer block diagram (TIM2 and TIM3) . . . . . . . . . . . . . . . . . . . . . . . . . 293

Figure 92. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 294

Figure 93. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 295

Figure 94. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

Figure 95. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

Figure 96. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

Figure 97. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

Figure 98. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . . 297

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Figure 99. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . 298

Figure 100. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

Figure 101. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

Figure 102. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

Figure 103. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

Figure 104. Counter timing diagram, Update event when repetition counter is not used . . . . . . . . . . 300

Figure 105. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . . 301

Figure 106. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

Figure 107. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 302

Figure 108. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

Figure 109. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . . 303

Figure 110. Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . . . . . . . . . . 303

Figure 111. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 304

Figure 112. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

Figure 113. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

Figure 114. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

Figure 115. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

Figure 116. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 307

Figure 117. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

Figure 118. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 308

Figure 119. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

Figure 120. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

Figure 121. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

Figure 122. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

Figure 123. Example of one-pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

Figure 124. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

Figure 125. Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . 318

Figure 126. Example of encoder interface mode with TI1FP1 polarity inverted . . . . . . . . . . . . . . . . . 319

Figure 127. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

Figure 128. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

Figure 129. Control circuit in trigger mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

Figure 130. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 323

Figure 131. Master/Slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

Figure 132. Gating timer 2 with OC1REF of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

Figure 133. Gating timer 2 with Enable of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

Figure 134. Triggering timer 2 with update of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

Figure 135. Triggering timer 2 with Enable of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

Figure 136. Triggering timer 1 and 2 with timer 1 TI1 input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

Figure 137. General-purpose timer block diagram (TIM14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354

Figure 138. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 355

Figure 139. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 355

Figure 140. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356

Figure 141. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357

Figure 142. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357

Figure 143. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357

Figure 144. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not

preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358

Figure 145. Counter timing diagram, update event when ARPE=1 (TIMx_ARR

preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358

Figure 146. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 359

Figure 147. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 359

Figure 148. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360

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List of figures RM0091

Figure 149. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 360

Figure 150. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

Figure 151. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364

Figure 152. TIM15 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377

Figure 153. TIM16 and TIM17 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378

Figure 154. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 380

Figure 155. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 380

Figure 156. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381

Figure 157. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381

Figure 158. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382

Figure 159. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382

Figure 160. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not

preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382

Figure 161. Counter timing diagram, update event when ARPE=1 (TIMx_ARR

preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383

Figure 162. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 384

Figure 163. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 385

Figure 164. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385

Figure 165. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386

Figure 166. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 386

Figure 167. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387

Figure 168. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 387

Figure 169. Output stage of capture/compare channel (channel 2 for TIM15) . . . . . . . . . . . . . . . . . . 387

Figure 170. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389

Figure 171. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391

Figure 172. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392

Figure 173. Complementary output with dead-time insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393

Figure 174. Dead-time waveforms with delay greater than the negative pulse. . . . . . . . . . . . . . . . . . 393

Figure 175. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 394

Figure 176. Output behavior in response to a break.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396

Figure 177. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

Figure 178. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399

Figure 179. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400

Figure 180. Control circuit in trigger mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401

Figure 181. Basic timer block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440

Figure 182. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 442

Figure 183. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 442

Figure 184. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443

Figure 185. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444

Figure 186. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444

Figure 187. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444

Figure 188. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not

preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445

Figure 189. Counter timing diagram, update event when ARPE=1 (TIMx_ARR

preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445

Figure 190. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 446

Figure 191. IR internal hardware connections with TIM16 and TIM17. . . . . . . . . . . . . . . . . . . . . . . . . 452

Figure 192. Independent watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455

Figure 193. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462

Figure 194. Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463

Figure 195. I2C1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470

Figure 196. I2C2 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471

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Figure 197. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472

Figure 198. Setup and hold timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474

Figure 199. I2C initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476

Figure 200. Data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477

Figure 201. Data transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478

Figure 202. Slave initialization flowchart.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481

Figure 203. Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH=0 . . . . . . . . . . . . . 483

Figure 204. Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH=1 . . . . . . . . . . . . . 483

Figure 205. Transfer bus diagrams for I2C slave transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484

Figure 206. Transfer sequence flowchart for slave receiver with NOSTRETCH=0 . . . . . . . . . . . . . . . 485

Figure 207. Transfer sequence flowchart for slave receiver with NOSTRETCH=1 . . . . . . . . . . . . . . . 486

Figure 208. Transfer bus diagrams for I2C slave receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486

Figure 209. Master clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488

Figure 210. Master initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490

Figure 211. 10-bit address read access with HEAD10R=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490

Figure 212. 10-bit address read access with HEAD10R=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491

Figure 213. Transfer sequence flowchart for I2C master transmitter for N<=255 bytes . . . . . . . . . . . 492

Figure 214. Transfer sequence flowchart for I2C master transmitter for N>255 bytes . . . . . . . . . . . . 493

Figure 215. Transfer bus diagrams for I2C master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494

Figure 216. Transfer sequence flowchart for I2C master receiver for N<=255 bytes . . . . . . . . . . . . . 496

Figure 217. Transfer sequence flowchart for I2C master receiver for N>255 bytes . . . . . . . . . . . . . . 497

Figure 218. Transfer bus diagrams for I2C master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498

Figure 219. Timeout intervals for t

LOW:SEXT

, t

LOW:MEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503

Figure 220. Transfer sequence flowchart for SMBus slave transmitter N bytes + PEC. . . . . . . . . . . . 507

Figure 221. Transfer bus diagrams for SMBus slave transmitter (SBC=1) . . . . . . . . . . . . . . . . . . . . . 507

Figure 222. Transfer sequence flowchart for SMBus slave receiver N Bytes + PEC . . . . . . . . . . . . . 509

Figure 223. Bus transfer diagrams for SMBus slave receiver (SBC=1) . . . . . . . . . . . . . . . . . . . . . . . 510

Figure 224. Bus transfer diagrams for SMBus master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511

Figure 225. Bus transfer diagrams for SMBus master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513

Figure 226. I2C interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518

Figure 227. RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536

Figure 228. USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575

Figure 229. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576

Figure 230. Configurable stop bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577

Figure 231. TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579

Figure 232. Start bit detection when oversampling by 16 or 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580

Figure 233. Data sampling when oversampling by 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583

Figure 234. Data sampling when oversampling by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583

Figure 235. Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589

Figure 236. Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590

Figure 237. Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . . . . . . . . . . . . . . 593

Figure 238. Break detection in LIN mode vs. Framing error detection. . . . . . . . . . . . . . . . . . . . . . . . . 594

Figure 239. USART example of synchronous transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595

Figure 240. USART data clock timing diagram (M=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595

Figure 241. USART data clock timing diagram (M=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596

Figure 242. RX data setup/hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596

Figure 243. ISO 7816-3 asynchronous protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597

Figure 244. Parity error detection using the 1.5 stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599

Figure 245. IrDA SIR ENDEC- block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603

Figure 246. IrDA data modulation (3/16) -Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603

Figure 247. Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605

Figure 248. Reception using DMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606

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List of figures RM0091

Figure 249. Hardware flow control between 2 USARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606

Figure 250. RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607

Figure 251. CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607

Figure 252. USART interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610

Figure 253. SPI block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636

Figure 254. Full-duplex single master/ single slave application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637

Figure 255. Half-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637

Figure 256. Simplex single master/single slave application (master in transmit-only/

slave in receive-only mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638

Figure 257. Master and three independent slaves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639

Figure 258. Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640

Figure 259. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641

Figure 260. Data alignment when data length is not equal to 8-bit or 16-bit . . . . . . . . . . . . . . . . . . . . 642

Figure 261. Packing data in FIFO for transmission and reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645

Figure 262. NSSP pulse generation in Motorola SPI master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 649

Figure 263. TI mode transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650

Figure 264. I
Figure 265. I
Figure 266. I

2

S block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653

2

S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0). . . . . . . . . . . . . . . . . 655

2

S Philips standard waveforms (24-bit frame with CPOL = 0) . . . . . . . . . . . . . . . . . . . . . 655

Figure 267. Transmitting 0x8EAA33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655

Figure 268. Receiving 0x8EAA33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656

Figure 269. I

2

S Philips standard (16-bit extended to 32-bit packet frame

with CPOL = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656

Figure 270. Example of 16-bit data frame extended to 32-bit channel frame . . . . . . . . . . . . . . . . . . . 656

Figure 271. MSB Justified 16-bit or 32-bit full-accuracy length with CPOL = 0 . . . . . . . . . . . . . . . . . . 657

Figure 272. MSB justified 24-bit frame length with CPOL = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657

Figure 273. MSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . . . . . . . . . . . . . 657

Figure 274. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0 . . . . . . . . . . . . . . . . . . . . . . . . 658

Figure 275. LSB justified 24-bit frame length with CPOL = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658

Figure 276. Operations required to transmit 0x3478AE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658

Figure 277. Operations required to receive 0x3478AE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659

Figure 278. LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . . . . . . . . . . . . . 659

Figure 279. Example of 16-bit data frame extended to 32-bit channel frame . . . . . . . . . . . . . . . . . . . 659

Figure 280. PCM standard waveforms (16-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660

Figure 281. PCM standard waveforms (16-bit extended to 32-bit packet frame). . . . . . . . . . . . . . . . . 660

Figure 282. Audio sampling frequency definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661

Figure 283. I

2

S clock generator architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661

Figure 284. TSC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682

Figure 285. Surface charge transfer analog I/O group structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683

Figure 286. Sampling capacitor voltage variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684

Figure 287. Charge transfer acquisition sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685

Figure 288. Spread spectrum variation principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686

Figure 289. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700

Figure 290. Message structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701

Figure 291. Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701

Figure 292. Bit timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702

Figure 293. Signal free time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702

Figure 294. Arbitration phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702

Figure 295. SFT of three nominal bit periods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703

Figure 296. Error bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704

Figure 297. Error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705

Figure 298. TXERR detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707

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Figure 299. Block diagram of STM32F05xxx MCU and Cortex-M0-level debug support . . . . . . . . . . 718

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Documentation conventions RM0091

1 Documentation conventions

1.1 List of abbreviations for registers

The following abbreviations are used in register descriptions:

read/write (rw) Software can read and write to these bits.

read-only (r) Software can only read these bits.

write-only (w) Software can only write to this bit. Reading the bit returns the reset value.

read/clear (rc_w1) Software can read as well as clear this bit by writing 1. Writing ‘0’ has no effect on

the bit value.

read/clear (rc_w0) Software can read as well as clear this bit by writing 0. Writing ‘1’ has no effect on

the bit value.

read/clear by read
(rc_r)

Software can read this bit. Reading this bit automatically clears it to ‘0’. Writing ‘0’
has no effect on the bit value.

read/set (rs) Software can read as well as set this bit. Writing ‘0’ has no effect on the bit value.

read-only write
trigger (rt_w)

Software can read this bit. Writing ‘0’ or ‘1’ triggers an event but has no effect on
the bit value.

toggle (t) Software can only toggle this bit by writing ‘1’. Writing ‘0’ has no effect.

Reserved (Res.) Reserved bit, must be kept at reset value.

1.2 Glossary

This section gives a brief definition of acronyms and abbreviations used in this document:

● The Cortex-M0 core integrates one debug port: SWD debug port (SWD-DP) provides a

2-pin (clock and data) interface based on the Serial Wire Debug (SWD) protocol.
Please refer to the Cortex-M0 technical reference manual.

● Word: data/instruction of 32-bit length

● Half word: data/instruction of 16-bit length

● Byte: data of 8-bit length

● IAP (in-application programming): IAP is the ability to re-program the Flash memory of

a microcontroller while the user program is running.

● ICP (in-circuit programming): ICP is the ability to program the Flash memory of a

microcontroller using the JTAG protocol, the SWD protocol or the bootloader while the
device is mounted on the user application board.

● Option bytes: product configuration bits stored in the Flash memory

● OBL: option byte loader.

● AHB: advanced high-performance bus.

1.3 Peripheral availability

For peripheral availability and number across all sales types, please refer to the datasheet.

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RM0091 System and memory overview

2 System and memory overview

2.1 System architecture

The main system consists of:

● Two masters:

– Cortex-M0 core AHB bus
– GP-DMA (general-purpose DMA)

● Four slaves:

– Internal SRAM
– Internal Flash memory
– AHB to APB, which connects all the APB peripherals
– AHB dedicated to GPIO ports

These are interconnected using a multilayer AHB bus architecture as shown in Figure 1:

Figure 1. System architecture

Cortex

M0

DMA

Controller

(Channels

1 to 5)

System bus

DMA

Busmatrix

AHB1 bus

DMA request

AHB2 bus

AHB2APB

Bridge

Reset and

clock

controller

(RCC)

Touch

sensing

controller

(TSC)

CRC

FLITF

Flash interface

SRAM

GPIO Ports

A,B,C,D,F

APB bus

Flash memory

SYSCFG

ADC
DAC

COMP

TIM1

TIM2,TIM3

TIM14,TIM15,TIM16,TIM17

TIM6

IWWDG

WWDG

RTC

I2C1, I2C2

USART1, USART2

SPI1/I2S1, SPI2

HDMI-CEC

DBGMCU

MS19217V1

System bus

This bus connects the system bus of the Cortex-M0 core (peripherals bus) to a BusMatrix
which manages the arbitration between the core and the DMA.

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DMA bus

This bus connects the AHB master interface of the DMA to the BusMatrix which manages
the access of CPU DCode and DMA to SRAM, Flash memory and peripherals.

BusMatrix

The BusMatrix manages the access arbitration between the core system bus and the DMA
master bus. The arbitration uses a Round Robin algorithm. The BusMatrix is composed of
two masters (CPU AHB, System bus) and four slaves (FLITF, SRAM, AHB2GPIO and
AHB2APB bridges).

AHB peripherals are connected on system bus through a BusMatrix to allow DMA access.

AHB2APB bridges (APB)

The AHB2APB bridges provide full synchronous connections between the AHB and the
APB bus.

Refer to Table 2.2.2 on page 37 for the address mapping of the peripherals connected to
this bridge.

After each device reset, all peripheral clocks are disabled (except for the SRAM and FLITF).
Before using a peripheral you have to enable its clock in the RCC_AHBENR,
RCC_APB2ENR or RCC_APB1ENR register.

Note: When a 16- or 8-bit access is performed on an APB register, the access is transformed into

a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.

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2.2 Memory organization

2.2.1 Introduction

Program memory, data memory, registers and I/O ports are organized within the same linear
4-Gbyte address space.

The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word
is considered the word’s least significant byte and the highest numbered byte the most
significant.

The addressable memory space is divided into 8 main blocks, each of 512 MB.

All the memory areas that are not allocated to on-chip memories and peripherals are
considered “Reserved”). For the detailed mapping of available memory and register areas,
please refer to the Memory map and register boundary addresses chapter and peripheral
chapters.

2.2.2 Memory map and register boundary addresses

The following table gives the memory map and boundary addresses of the peripherals
available in all STM32F05xxx devices.

Table 2. STM32F05xxx memory map and peripheral register boundary addresses

Bus Boundary address Size Peripheral Peripheral register map

Cortex M0 internal
peripherals

AHB2

AHB1

0xE000 0000 - 0xE00F FFFF 1MB

0x4800 1800 - 0x5FFF FFFF ~384 MB Reserved

0x4800 1400 - 0x4800 17FF 1KB GPIOF Section 8.4.11 on page 133

0x4800 1000 - 0x4800 13FF 1KB Reserved

0x4800 0C00 - 0x4800 0FFF 1KB GPIOD Section 8.4.11 on page 133

0x4800 0800 - 0x4800 0BFF 1KB GPIOC Section 8.4.11 on page 133

0x4800 0400 - 0x4800 07FF 1KB GPIOB Section 8.4.11 on page 133

0x4800 0000 - 0x4800 03FF 1KB GPIOA Section 8.4.11 on page 133

0x4002 4400 - 0x47FF FFFF ~128 MB Reserved

0x4002 4000 - 0x4002 43FF 1 KB TSC Section 27.6.11 on page 697

0x4002 3400 - 0x4002 3FFF 3 KB Reserved

0x4002 3000 - 0x4002 33FF 1 KB CRC Section 5.4.5 on page 66

0x4002 2400 - 0x4002 2FFF 3 KB Reserved

0x4002 2000 - 0x4002 23FF 1 KB FLASH interface Section 3.6 on page 58

0x4002 1400 - 0x4002 1FFF 3KB Reserved

0x4002 1000 - 0x4002 13FF 1 KB RCC Section 7.4.15 on page 116

0x4002 0400 - 0x4002 0FFF 3KB Reserved

0x4002 0000 - 0x4002 03FF 1 KB DMA Section 10.4.7 on page 155

0x4001 8000 - 0x4001 FFFF 32 KB Reserved

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Table 2. STM32F05xxx memory map and peripheral register boundary addresses

Bus Boundary address Size Peripheral Peripheral register map

0x4001 5C00 - 0x4001 7FFF 9KB Reserved

0x4001 5800 - 0x4001 5BFF 1 KB DBGMCU

0x4001 4C00 - 0x4001 57FF 3KB Reserved

0x4001 4800 - 0x4001 4BFF 1 KB TIM17 Section 18.6.16 on page 438

0x4001 4400 - 0x4001 47FF 1 KB TIM16 Section 18.6.16 on page 438

0x4001 4000 - 0x4001 43FF 1 KB TIM15 Section 18.5.18 on page 420

0x4001 3C00 - 0x4001 3FFF 1KB Reserved

RM0091

APB

0x4001 3800 - 0x4001 3BFF 1 KB USART1 Section 25.7.12 on page 633

0x4001 3400 - 0x4001 37FF 1KB Reserved

0x4001 3000 - 0x4001 33FF 1 KB SPI1/I2S1 Section 26.7.10 on page 680

0x4001 2C00 - 0x4001 2FFF 1 KB TIM1 Section 15.4.21 on page 290

0x4001 2800 - 0x4001 2BFF 1KB Reserved

0x4001 2400 - 0x4001 27FF 1 KB ADC Section 12.12.11 on page 203

0x4001 0800 - 0x4001 23FF 7KB Reserved

0x4001 0400 - 0x4001 07FF 1 KB EXTI Section 11.3.7 on page 181

Section 9.1.7 on page 140

0x4001 0000 - 0x4001 03FF 1 KB SYSCFG + COMP

Section 14.4.2 on page 222

0x4000 8000 - 0x4000 FFFF 32 KB Reserved

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Table 2. STM32F05xxx memory map and peripheral register boundary addresses

Bus Boundary address Size Peripheral Peripheral register map

0x4000 7C00 - 0x4000 7FFF 1KB Reserved

0x4000 7800 - 0x4000 7BFF 1 KB CEC Section 28.7.7 on page 717

0x4000 7400 - 0x4000 77FF 1 KB DAC Section 13.5.8 on page 214

0x4000 7000 - 0x4000 73FF 1 KB PWR Section 6.4.3 on page 81

0x4000 5C00 - 0x4000 6FFF 5KB Reserved

0x4000 5800 - 0x4000 5BFF 1 KB I2C2 Section 23.8 on page 534

0x4000 5400 - 0x4000 57FF 1 KB I2C1 Section 23.8 on page 534

0x4000 4800 - 0x4000 53FF 3KB Reserved

0x4000 4400 - 0x4000 47FF 1 KB USART2 Section 25.7.12 on page 633

0x4000 3C00 - 0x4000 43FF 2KB Reserved

APB

0x4000 3800 - 0x4000 3BFF 1 KB SPI2 Section 26.7.10 on page 680

0x4000 3400 - 0x4000 37FF 1KB Reserved

0x4000 3000 - 0x4000 33FF 1 KB IWWDG Section 21.4.6 on page 460

0x4000 2C00 - 0x4000 2FFF 1 KB WWDG Section 22.6.4 on page 467

0x4000 2800 - 0x4000 2BFF 1 KB RTC Section 24.6.17 on page 569

0x4000 2400 - 0x4000 27FF 1KB Reserved

0x4000 2000 - 0x4000 23FF 1 KB TIM14 Section 17.4.12 on page 373

0x4000 1400 - 0x4000 1FFF 3KB Reserved

0x4000 1000 - 0x4000 13FF 1 KB TIM6 Section 19.4.9 on page 451

0x4000 0800 - 0x4000 0FFF 2KB Reserved

0x4000 0400 - 0x4000 07FF 1 KB TIM3 Section 16.4.19 on page 351

0x4000 0000 - 0x4000 03FF 1 KB TIM2 Section 16.4.19 on page 351

0x2000 2000 - 0x3FFF FFFF ~512 MB Reserved

0x2000 0000 - 0x2000 1FFF 8 KB SRAM Section 4 on page 59

0x1FFF FC00 - 0x1FFF FFFF 1 KB

0x1FFF F800 - 0x1FFF FBFF 1 KB Option bytes Section 3.5.7 on page 57

0x1FFF EC00 - 0x1FFF F7FF 3 KB System memory

0x0801 0000 - 0x1FFF EBFF ~384 MB Reserved

0x0800 0000 - 0x0800 FFFF 64 KB Main Flash memory Section 3.6 on page 58

0x0001 0000 - 0x07FF FFFF 128 MB Reserved

Reserved

0x0000 000 - 0x0000 FFFF 64 KB

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Main Flash memory,
system memory or SRAM
depending on BOOT
configuration

2.3 Embedded SRAM

The STM32F05xxx features up to 8 Kbytes of static SRAM. It can be accessed as bytes,
half-words (16 bits) or full words (32 bits). This memory can be addressed at maximum
system clock frequency without wait state and thus by both CPU and DMA.

Parity check

The user can enable the parity check using the option bit RAM_PARITY_CHECK in the user
option byte (refer to Table 11 on page 60).

The data bus width is 36 bits because 4 bits are available for parity check (1 bit per byte) in
order to increase memory robustness, as required for instance by Class B or SIL norms.

The parity bits are computed and stored when writing into the SRAM. Then, they are
automatically checked when reading. If one bit fails, an NMI is generated. The same error
can also be linked to the BRK_IN Break input of TIMER15/TIM16/TIM7, with the
SRAM_PARITY_LOCK control bit in the SYSCFG configuration register 2

(SYSCFG_CFGR2). The SRAM Parity Error flag (SRAM_PEF) is available in the SYSCFG
configuration register 2 (SYSCFG_CFGR2).

2.4 Flash memory overview

RM0091

The Flash memory is composed of two distinct physical areas:

● The main Flash memory block. It contains the application program and user data if

necessary.

● The information block. It is composed of two parts:

– Option bytes for hardware and memory protection user configuration.
– System memory which contains the proprietary boot loader code.

Please, refer to Section 3: Embedded Flash memory for more details.

The Flash interface implements instruction access and data access based on the AHB
protocol. It implements the prefetch buffer that speeds up CPU code execution. It also
implements the logic necessary to carry out the Flash memory operations (Program/Erase)
controlled through the Flash registers.

2.5 Boot configuration

In the STM32F05xxx, three different boot modes can be selected through the BOOT0 pin
and nBOOT1 bit in in the User option byte, as shown in the following table.

Table 3. Boot modes

Boot mode selection

BOOT1 BOOT0

Boot mode Aliasing

x 0 Main Flash memory Main Flash memory is selected as boot space

0 1 System memory System memory is selected as boot space

1 1 Embedded SRAM Embedded SRAM is selected as boot space

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RM0091

The values on both BOOT0 pin and nBOOT1 bit are latched on the 4th rising edge of
SYSCLK after a reset. It is up to the user to set nBOOT1 and BOOT0 to select the required
boot mode.

The BOOT0 pin and nBOOT1 bit are also re-sampled when exiting from Standby mode.
Consequently they must be kept in the required Boot mode configuration in Standby mode.
After this startup delay has elapsed, the CPU fetches the top-of-stack value from address
0x0000 0000, then starts code execution from the boot memory at 0x0000 0004.

Depending on the selected boot mode, main Flash memory, system memory or SRAM is
accessible as follows:

● Boot from main Flash memory: the main Flash memory is aliased in the boot memory

space (0x0000 0000), but still accessible from its original memory space
(0x0800 0000). In other words, the Flash memory contents can be accessed starting
from address 0x0000 0000 or 0x0800 0000.

● Boot from system memory: the system memory is aliased in the boot memory space

(0x0000 0000), but still accessible from its original memory space (0x

● Boot from the embedded SRAM: the SRAM is aliased in the boot memory space

1FFF EC00).

(0x0000 0000), but it is still accessible from its original memory space (0x2000 0000).

Embedded boot loader

The embedded boot loader is located in the System memory, programmed by ST during
production. It is used to reprogram the Flash memory with the USART1 interface.

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Embedded Flash memory RM0091

3 Embedded Flash memory

3.1 Flash main features

● Up to 64 Kbytes of Flash memory

● Memory organization:

– Main Flash memory block:

16 Kwords (16K × 32 bits)

– Information block:

1 Kword (1K × 32 bits)

Flash memory interface features:

● Read interface with prefetch buffer (1 × 32-bit words)

● Option byte Loader

● Flash Program / Erase operation

● Read / Write protection

● Low-power mode

3.2 Flash memory functional description

3.2.1 Flash memory organization

The Flash memory is organized as 32-bit wide memory cells that can be used for storing
both code and data constants.

The memory organization is based on a main Flash memory block containing 64 pages of
1 Kbyte or 16 sectors of 4 Kbytes (4 pages). The sector is the granularity of the write
protection (see Memory protection on page 49).

Table 4. Flash module organization

Flash area Flash memory addresses

Main Flash

memory

Size

(bytes)

0x0800 0000 - 0x0800 03FF 1 Kbyte Page 0

0x0800 0400 - 0x0800 07FF 1 Kbyte Page 1

0x0800 0800 - 0x0800 0BFF 1 Kbyte Page 2

0x0800 0C00 - 0x0800 0FFF 1 Kbyte Page 3

.
.
.

.
.
.

0x0800 7000 - 0x0800 73FF 1 Kbyte Page 60

0x0800 7400 - 0x0800 77FF 1 Kbyte Page 61

0x0800 7800 - 0x0800 7BFF 1 Kbyte Page 62

0x0800 7C00 - 0x0800 7FFF 1 Kbyte Page 63

Name Description

Sector 0

.
.
.

.
.
.

Sector 15

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RM0091 Embedded Flash memory

Table 4. Flash module organization (continued)

Flash area Flash memory addresses

Information block

Flash memory

interface
registers

0x1FFF EC00- 0x1FFF F7FF 3 Kbytes System memory

0x1FFF F800 - 0x1FFF F80B 6 Option bytes

0x4002 2000 - 0x4002 2003 4 FLASH_ACR

0x4002 2004 - 0x4002 2007 4 FLASH_KEYR

0x4002 2008 - 0x4002 200B 4 FLASH_OPTKEYR

0x4002 200C - 0x4002 200F 4 FLASH_SR

0x4002 2010 - 0x4002 2013 4 FLASH_CR

0x4002 2014 - 0x4002 2017 4 FLASH_AR

0x4002 2018 - 0x4002 201B 4 Reserved

0x4002 201C - 0x4002 201F 4 FLASH_OBR

0x4002 2020 - 0x4002 2023 4 FLASH_WRPR

3.2.2 Read operations

The embedded Flash module can be addressed directly, as a common memory space. Any
data read operation accesses the content of the Flash module through dedicated read
senses and provides the requested data.

Size

(bytes)

Name Description

The instruction fetch and the data access are both done through the same AHB bus. Read
accesses can be performed with the following options managed through the Flash access
control register (FLASH_ACR):

● Instruction fetch: Prefetch buffer enabled for a faster CPU execution.

● Latency: number of wait states for a correct read operation (from 0 to 1)

Instruction fetch

The Cortex-M0 fetches the instruction over the AHB bus. The prefetch block aims at
increasing the efficiency of instruction fetching.

Prefetch buffer

The prefetch buffer is 3 blocks wide where each block consists of 8 bytes. The prefetch
blocks are direct-mapped. A block can be completely replaced on a single read to the Flash
memory as the size of the block matches the bandwidth of the Flash memory.

The implementation of this prefetch buffer makes a faster CPU execution possible as the
CPU fetches one word at a time with the next word readily available in the prefetch buffer.
This implies that the acceleration ratio will be of the order of 2 assuming that the code is
aligned at a 64-bit boundary for the jumps.

Prefetch controller

The prefetch controller decides to access the Flash memory depending on the available
space in the prefetch buffer. The Controller initiates a read request when there is at least
one block free in the prefetch buffer.

After reset, the state of the prefetch buffer is on.
The prefetch buffer should be switched on/off only when SYSCLK is lower than 24 MHz and

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Embedded Flash memory RM0091

no prescaler is applied on the AHB clock (SYSCLK must be equal to HCLK). The prefetch
buffer is usually switched on/off during the initialization routine, while the microcontroller is
running on the internal 8 MHz RC (HSI) oscillator.

Note: The prefetch buffer must be kept on (FLASH_ACR[4]=’1’) when using a prescaler different

from 1 on the AHB clock.

Access latency

In order to maintain the control signals to read the Flash memory, the ratio of the prefetch
controller clock period to the access time of the Flash memory has to be programmed in the
Flash access control register with the LATENCY[2:0] bits. This value gives the number of
cycles needed to maintain the control signals of the Flash memory and correctly read the
required data. After reset, the value is zero and only one cycle without additional wait states
is required to access the Flash memory.

3.2.3 Flash program and erase operations

The STM32F05xxx embedded Flash memory can be programmed using in-circuit
programming or in-application programming.

The in-circuit programming (ICP) method is used to update the entire contents of the
Flash memory, using the SWD protocol or the boot loader to load the user application into
the microcontroller. ICP offers quick and efficient design iterations and eliminates
unnecessary package handling or socketing of devices.

In contrast to the ICP method, in-application programming (IAP) can use any
communication interface supported by the microcontroller (I/Os, USB, CAN, UART, I

2

C, SPI,
etc.) to download programming data into memory. IAP allows the user to re-program the
Flash memory while the application is running. Nevertheless, part of the application has to
have been previously programmed in the Flash memory using ICP.

The program and erase operations can be performed over the whole product voltage range.
They are managed through the following seven Flash registers:

● Key register (FLASH_KEYR)

● Option byte key register (FLASH_OPTKEYR)

● Flash control register (FLASH_CR)

● Flash status register (FLASH_SR)

● Flash address register (FLASH_AR)

● Option byte register (FLASH_OBR)

● Write protection register (FLASH_WRPR)

An ongoing Flash memory operation will not block the CPU as long as the CPU does not
access the Flash memory.

On the contrary, during a program/erase operation to the Flash memory, any attempt to read
the Flash memory will stall the bus. The read operation will proceed correctly once the
program/erase operation has completed. This means that code or data fetches cannot be
made while a program/erase operation is ongoing.

For program and erase operations on the Flash memory (write/erase), the internal RC
oscillator (HSI) must be ON.

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RM0091 Embedded Flash memory

Unlocking the Flash memory

After reset, the Flash memory is protected against unwanted write or erase operations. The
FLASH_CR register is not accessible in write mode. An unlocking sequence should be
written to the FLASH_KEYR register to open the access to the FLASH_CR register. This
sequence consists of two write operations:

● Write KEY1 = 0x45670123

● Write KEY2 = 0xCDEF89AB

Any wrong sequence locks up the FLASH_CR register until the next reset.

In the case of a wrong key sequence, a bus error is detected and a Hard Fault interrupt is
generated. This is done after the first write cycle if KEY1 does not match, or during the
second write cycle if KEY1 has been correctly written but KEY2 does not match.

The FLASH_CR register can be locked again by user software by writing the LOCK bit in the
FLASH_CR register to 1.

Main Flash memory programming

The main Flash memory can be programmed 16 bits at a time. The program operation is
started when the CPU writes a half-word into a main Flash memory address with the PG bit
of the FLASH_CR register set. Any attempt to write data that are not half-word long will
result in a bus error generating a Hard Fault interrupt.

Figure 2. Programming procedure

Read LOCK bit in

FLASH_CR

LOCK bit in FLASH_CR

= 1

No

Write PG bit in FLASH_CR to 1

Perform half-word write at the

desired address

BSY bit in FLASH_SR

= 1

Yes

Perform unlock sequence

Yes

No

Check the programmed value

by reading the programmed

address

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Embedded Flash memory RM0091

The Flash memory interface preliminarily reads the value at the addressed main Flash
memory location and checks that it has been erased. If not, the program operation is
skipped and a warning is issued by the PGERR bit in FLASH_SR register. The only
exception to this is when 0x0000 is programmed. In this case, the location is correctly
programmed to 0x0000 and the PGERR bit is not set.

If the addressed main Flash memory location is write-protected by the FLASH_WRPR
register, the program operation is skipped and a warning is issued by the WRPRTERR bit in
the FLASH_SR register. The end of the program operation is indicated by the EOP bit in the
FLASH_SR register.

The main Flash memory programming sequence in standard mode is as follows:

1. Check that no main Flash memory operation is ongoing by checking the BSY bit in the

FLASH_SR register.

2. Sett the PG bit in the FLASH_CR register.

3. Perform the data write (half-word) at the desired address.

4. Wait until the BSY bit is reset in the FLASH_SR register.

5. Read the programmed value and verify.

Note: The registers are not accessible in write mode when the BSY bit of the FLASH_SR register

is set.

Flash memory erase

The Flash memory can be erased page by page or completely (Mass Erase).

Page Erase

To erase a page, the procedure below should be followed:

1. Check that no Flash memory operation is ongoing by checking the BSY bit in the

FLASH_CR register

2. Set the PER bit in the FLASH_CR register.

3. Program the FLASH_AR register to select a page to erase.

4. Set the STRT bit in the FLASH_CR register.

5. Wait for the BSY bit to be reset.

6. Read the erased page and verify.

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RM0091 Embedded Flash memory

Read LOCK bit in

FLASH_CR

LOCK bit in FLASH_CR

=1

Yes

No

Yes

No

Perform unlock sequence

Write into FAR an address

within the page to erase

Write PER bit in FLASH_CR

Write STRT bit in FLASH_CR

to 1

BSY bit in FLASH_SR

= 1

Check the page is erased by

reading all the addresses in

the page

MS19221V1

Figure 3. Flash memory Page Erase procedure

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Embedded Flash memory RM0091

Mass Erase

The Mass Erase command can be used to completely erase the user pages of the Flash
memory. The information block is unaffected by this procedure. The following sequence is
recommended:

1. Check that no Flash memory operation is ongoing by checking the BSY bit in the

FLASH_SR register.

2. Set the MER bit in the FLASH_CR register.

3. Set the STRT bit in the FLASH_CR register.

4. Wait for the BSY bit to be reset.

5. Read all the pages and verify.

Figure 4. Flash memory Mass Erase procedure

Read LOCK bit in

FLASH_CR

LOCK bit in FLASH_CR

in FLASH_CR to 1

Write STRT bit in FLASH_CR

Check the erase operation by

reading all the addresses in

the user memory

Option byte programming

=1

No

Write MER bit

to 1

BSY bit in

FLASH_SR

=1

No

Yes

Yes

Perform unlock sequency

MS19222V1

The option bytes are programmed differently from normal user addresses. The number of
option bytes is limited to 6 (2 for write protection, 1 for read protection, 1 for hardware
configuration and 2 free bytes for user data). After unlocking the Flash access, the user has
to authorize the programming of the option bytes by writing the same set of KEYS (KEY1
and KEY2) to the FLASH_OPTKEYR register to set the OPTWRE bit in the FLASH_CR
register (refer to Unlocking the Flash memory for key values). Then the user has to set the
OPTPG bit in the FLASH_CR register and perform a half-word write operation at the desired
Flash address.

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RM0091 Embedded Flash memory

The value of the addressed option byte is first read to check it is really erased. If not, the
program operation is skipped and a warning is issued by the WRPRTERR bit in the
FLASH_SR register. The end of the program operation is indicated by the EOP bit in the
FLASH_SR register.

The LSB value is automatically complemented into the MSB before the programming
operation starts. This guarantees that the option byte and its complement are always
correct.

The sequence is as follows:

1. Check that no Flash memory operation is ongoing by checking the BSY bit in the

FLASH_SR register.

2. Unlock the OPTWRE bit in the FLASH_CR register.

3. Set the OPTPG bit in the FLASH_CR register

4. Write the data (half-word) to the desired address

5. Wait for the BSY bit to be reset.

6. Read the programmed value and verify.

When the Flash memory read protection option is changed from protected to unprotected, a
Mass Erase of the main Flash memory is performed before reprogramming the read
protection option. If the user wants to change an option other than the read protection
option, then the mass erase is not performed. The erased state of the read protection option
byte protects the Flash memory.

Erase procedure

The option byte erase sequence is as follows:

1. Check that no Flash memory operation is ongoing by reading the BSY bit in the

FLASH_SR register

2. Unlock the OPTWRE bit in the FLASH_CR register

3. Set the OPTER bit in the FLASH_CR register

4. Set the STRT bit in the FLASH_CR register

5. Wait for BSY to reset

6. Read the erased option bytes and verify

3.3 Memory protection

The user area of the Flash memory can be protected against read by untrusted code. The
pages of the Flash memory can also be protected against unwanted write due to loss of
program counter contexts. The write-protection granularity is one sector (four pages).

3.3.1 Read protection

The read protection is activated by setting the RDP option byte and then, by applying a
system reset to reload the new RDP option byte.

Note: If the read protection is set while the debugger is still connected through SWD, apply a POR

(power-on reset) instead of a system reset.

There are three levels of read protection from no protection (level 0) to maximum protection
or no debug (level 2). Refer to Table 6: Access status versus protection level and execution

modes.

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Embedded Flash memory RM0091

The Flash memory is protected when the RDP option byte and its complement contain the
pair of values shown in Ta bl e 5 .

Table 5. Flash memory read protection status

RDP byte value RDP complement value Read protection level

0xAA 0x55

Any value
except 0xAA or 0xCC

0xCC 0x33 Level 2

Any value
(not necessarily complementary)
except 0x55 and 0x33

Level 0 (ST production
configuration)

Level 1

The System memory area is read accessible whatever the protection level. It is never
accessible for program/erase operation

Level 0: no protection

Read, program and erase operations into the main Flash memory area are possible.

The option bytes are as well accessible by all operations.

Level 1: read protection

This is the default protection level when RDP option byte is erased. It is defined as well
when RDP value is at any value different from 0xAA and 0xCC, or even if the complement is
not correct.

● User mode: Code executing in user mode can access main Flash memory and option

bytes with all operations.

● Debug, boot RAM and boot loader modes: In debug mode (with SWD) or when code

is running from boot RAM or boot loader, the main Flash memory and the backup
registers (RTC_BKPxR in the RTC) are totally inaccessible.
In these modes, even a simple read access generates a bus error and a Hard Fault
interrupt. The main Flash memory is program/erase protected to prevent malicious or
unauthorized users from reprogramming any of the user code with a dump routine. Any
attempted program/erase operation sets the PGERR flag of Flash status register
(FLASH_SR).

When the RPD is reprogrammed to the value 0xAA to move back to Level 0, a mass
erase of the main Flash memory is performed and the backup registers (RTC_BKPxR
in the RTC) are reset.

Level 2: no debug

In this level, the protection level 1 is guaranteed. In addition, the CortexM0 debug
capabilities are disabled. Consequently, the debug port (SWD), the boot from RAM (boot
RAM mode) and the boot from System memory (boot loader mode) are no more available.

In user execution mode, all operations are allowed on the Main Flash memory. On the
contrary, only read and program operations can be performed through option bytes. Option
bytes are accessible for erase operations.

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RM0091 Embedded Flash memory

Moreover, the RDP bytes cannot be programmed. Thus, the level 2 cannot be removed at
all: it is an irreversible operation. When attempting to program the RDP byte, the protection
error flag WRPRTERR is set in the Flash_SR register and an interrupt can be generated.

Note: 1 The debug feature is also disabled under reset.

2 STMicroelectronics is not able to perform analysis on defective parts on which the level 2

protection has been set.

Table 6. Access status versus protection level and execution modes

Debug/ BootFromRam/

BootFromLoader

Area

Protection

level

User execution

Read Write Erase Read Write Erase

Main Flash

memory

System

memory

(2)

Option bytes

Backup

registers

1. When the protection level 2 is active, the Debug port, the boot from RAM and the boot from system memory are disabled.

2. The system memory is only read-accessible, whatever the protection level (0, 1 or 2) and execution mode.

3. The main Flash memory is erased when the RDP option byte is programmed with all level protections disabled (0xAA).

4. All option bytes can be programmed, except the RDP byte.

1 Ye s Ye s Ye s N o No N o

2 Yes Yes Yes N/A

(1)

N/A

(1)

1 Yes No No Yes No No

2 Yes No No NA

1Yes Yes

2Yes Yes

(3)

(4)

Yes Yes Yes

No N/A

(1)

(1)

N/A

(1)

N/A

N/A

(3)

Yes

(1)

N/A

1 Ye s Ye s N/ A N o No Yes

(1)

2Yes YesN/A N/A

N/A

(1)

N/A

(3)

N/A

Changing read protection level

It is easy to move from level 0 to level 1 by changing the value of the RDP byte to any value
(except 0xCC).

(1)

(1)

(1)

(1)

By programming the 0xCC value in the RDP byte, it is possible to go to level 2 either directly
from level 0 or from level 1.

On the contrary, the change to level 0 (no protection) is not possible without a main Flash
memory Mass erase operation. This Mass erase is generated as soon as 0xAA is
programmed in the RDP byte.

Note: When the Mass Erase command is used, the backup registers (RTC_BKPxR in the RTC)

are also reset.

To validate the protection level change, the option bytes must be reloaded through the
"OBL_LAUNCH" bit in Flash control register.

3.3.2 Write protection

The write protection is implemented with a granularity of one sector, i.e. four pages. It is
activated by configuring the WRP[1:0] option bytes, and then by reloading them by setting
the OBL_LAUNCH bit in the FLASH_CR register.

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Embedded Flash memory RM0091

If a program or an erase operation is performed on a protected sector, the Flash memory
returns a WRPRTERR protection error flag in the Flash memory Status Register
(FLASH_SR).

Write unprotection

To disable the write protection, two application cases are provided:

● Case 1: Read protection disabled after the write unprotection:

– Erase the entire option byte area by using the OPTER bit in the Flash memory

control register (FLASH_CR)

– Program the code 0xAA in the RDP byte to unprotect the memory. This operation

forces a Mass Erase of the main Flash memory.

– Set the OBL_LAUNCH bit in the Flash control register (FLASH_CR) to reload the

option bytes (and the new WRP[1:0] bytes), and to disable the write protection

● Case 2: Read protection maintained active after the write unprotection, useful for in-

application programming with a user boot loader:
– Erase the entire option byte area by using the OPTER bit in the Flash memory

control register (FLASH_CR)

– Set the OBL_LAUNCH bit in the Flash control register (FLASH_CR) to reload the

option bytes (and the new WRP[1:0] bytes), and to disable the write protection.

3.3.3 Option byte write protection

The option bytes are always read-accessible and write-protected by default. To gain write
access (Program/Erase) to the option bytes, a sequence of keys (same as for lock) has to
be written into the OPTKEYR. A correct sequence of keys gives write access to the option
bytes and this is indicated by OPTWRE in the FLASH_CR register being set. Write access
can be disabled by resetting the bit through software.

3.4 Flash interrupts

Table 7. Flash interrupt request

Interrupt event Event flag Enable control bit

End of operation EOP EOPIE

Write protection error WRPRTERR ERRIE

Programming error PGERR ERRIE

3.5 Flash register description

The Flash memory registers have to be accessed by 32-bit words (half-word and byte
accesses are not allowed).

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RM0091 Embedded Flash memory

3.5.1 Flash access control register (FLASH_ACR)

Address offset: 0x00
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 PRFTBS: Prefetch buffer status

This bit provides the status of the prefetch buffer.
0: Prefetch buffer is disabled
1: Prefetch buffer is enabled

Bit 4 PRFTBE: Prefetch buffer enable

0: Prefetch is disabled
1: Prefetch is enabled

PRFTBSPRFT

rrw rwrwrw

Res. LATENCY[2:0]

BE

Bit 3 Reserved, must be kept at reset value.

Bits 1:0 LATENCY[2:0]: Latency

These bits represent the ratio of the SYSCLK (system clock) period to the Flash
access time.

000: Zero wait state, if 0 < SYSCLK≤ 24 MHz
001: One wait state, if 24 MHz < SYSCLK ≤ 48 MHz

3.5.2 Flash key register (FLASH_KEYR)

Address offset: 0x04
Reset value: xxxx xxxx

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

FKEYR[31:16]

wwwwwww wwwwwwwww

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FKEYR[15:0]

wwwwwww wwwwwwwww

Note: These bits are all write-only and will return a 0 when read.

Bits 31:0 FKEYR: Flash key

These bits represent the keys to unlock the Flash.

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Embedded Flash memory RM0091

3.5.3 Flash option key register (FLASH_OPTKEYR)

Address offset: 0x08
Reset value: xxxx xxxx

All the register bits are all write-only and will return a 0 when read.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

OPTKEYR[31:16]

wwwwwww wwwwwwwww

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OPTKEYR[15:0]

wwwwwww wwwwwwwww

Bits 31:0 OPTKEYR: Option byte key

These bits represent the keys to unlock the OPTWRE.

3.5.4 Flash status register (FLASH_SR)

Address offset: 0x0C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EOP

rw rw rw r

WRPRT

ERR

Res.

PG

ERR

Res. BSY

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 EOP: End of operation

Set by hardware when a Flash operation (programming / erase) is completed.
Reset by writing a 1

Note: EOP is asserted at the end of each successful program or erase operation

Bit 4 WRPRTERR: Write protection error

Set by hardware when programming a write-protected address of the Flash
memory.
Reset by writing 1.

Bit 3 Reserved, must be kept at reset value.

Bit 2 PGERR: Programming error

Set by hardware when an address to be programmed contains a value different
from '0xFFFF' before programming.

Reset by writing 1.

Note: The STRT bit in the FLASH_CR register should be reset before starting a

programming operation.

Bit 1 Reserved, must be kept at reset value

Bit 0 BSY: Busy

This indicates that a Flash operation is in progress. This is set on the beginning
of a Flash operation and reset when the operation finishes or when an error
occurs.

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RM0091 Embedded Flash memory

3.5.5 Flash control register (FLASH_CR)

Address offset: 0x10
Reset value: 0x0000 0080

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res.

FORCE_

OPTLOAD

EOPIE Res. ERRIE

rw rw rw rw rw rw rw rw rw rw rw

OPTWR

E

Res. LOCK STRT OPTER

Bits 31:14 Reserved, must be kept at reset value.

Bit 13 OBL_LAUNCH: Force option byte loading

When set to 1, this bit forces the option byte reloading. This operation generates
a system reset.

0: Inactive
1: Active

Bit 12 EOPIE: End of operation interrupt enable

This bit enables the interrupt generation when the EOP bit in the FLASH_SR
register goes to 1.

0: Interrupt generation disabled
1: Interrupt generation enabled

Bit 11 Reserved, must be kept at reset value

OPT

Res. MER PER PG

PG

Bit 10 ERRIE: Error interrupt enable

This bit enables the interrupt generation on an error when PGERR /
WRPRTERR are set in the FLASH_SR register.
0: Interrupt generation disabled
1: Interrupt generation enabled

Bit 9 OPTWRE: Option bytes write enable

When set, the option bytes can be programmed. This bit is set on writing the
correct key sequence to the FLASH_OPTKEYR register.

This bit can be reset by software

Bit 8 Reserved, must be kept at reset value.

Bit 7 LOCK: Lock

Write to 1 only. When it is set, it indicates that the Flash is locked. This bit is reset
by hardware after detecting the unlock sequence.
In the event of unsuccessful unlock operation, this bit remains set until the next
reset.

Bit 6 STRT: Start

This bit triggers an ERASE operation when set. This bit is set only by software
and reset when the BSY bit is reset.

Bit 5 OPTER: Option byte erase

Option byte erase chosen.

Bit 4 OPTPG: Option byte programming

Option byte programming chosen.

Bit 3 Reserved, must be kept at reset value.

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Embedded Flash memory RM0091

Bit 2 MER: Mass erase

Erase of all user pages chosen.

Bit 1 PER: Page erase

Page Erase chosen.

Bit 0 PG: Programming

Flash programming chosen.

3.5.6 Flash address register (FLASH_AR)

Address offset: 0x14

Reset value: 0x0000 0000

This register is updated by hardware with the currently/last used address. For Page Erase
operations, this should be updated by software to indicate the chosen page.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

FAR [31:16]

wwwwwww w wwwwwww w

1514131211109 87654321 0

FAR[15:0]

wwwwwww w wwwwwww w

Bits 31:0 FAR : Flash Address

Chooses the address to program when programming is selected, or a page to
erase when Page Erase is selected.

Note: Write access to this register is blocked when the BSY bit in the FLASH_SR

register is set.

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RM0091 Embedded Flash memory

3.5.7 Option byte register (FLASH_OBR)

Address offset 0x1C

Reset value: 0x03FF FFF2

The reset value of this register depends on the value programmed in the option byte and the
OPTERR bit reset value depends on the comparison of the option byte and its complement
during the option byte loading phase.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Data1 Data0

rrrrrrr r rrrrrrr r

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res.

VDDA_MONITOR

RAM_PARITY_CHECK

rr r r r rr r

Res.

nBOOT1

nRST_STOP

nRST_STDBY

Res.

Res.

Res.

Res.

Res.

RDPRT2

WDG_SW

RDPRT1

OPTERR

Bits 31:24 Data1

Bits 23:16 Data0

Bits 15:8 User option bytes :

Bit 15 : reserved
Bit 14 : RAM_PARITY_CHECK
Bit 13 : VDDA_MONITOR
Bit 12 : nBOOT1
Bit 11 : reserved
Bit 10 : nRST_STDBY
Bit 9 : nRST_STOP
Bit 8 : WDG_SW

Bits 7:3 Reserved, must be kept at reset value.

Bits 2:1 RDPRT[2:1]: Read protection level status

00: Read protection level 0 is enabled (ST production configuration)
01: Read protection level 1 is enabled
11: Read protection level 2 is enabled.

Bit 0 OPTERR: Option byte error

When set, this indicates that the loaded option byte and its complement do not
match. The corresponding byte and its complement are read as 0xFF in the
FLASH_OBR or FLASH_WRPR register.

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Embedded Flash memory RM0091

3.5.8 Write protection register (FLASH_WRPR)

Address offset: 0x20

Reset value: 0xFFFF FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bits 31:0 WRP: Write protect

This register contains the write-protection option bytes loaded by the OBL.

Res.

WRP[15:0]

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

3.6 Flash register map

Table 8. Flash interface - register map and reset values

Offset Register

0x000

0x004

0x008

0x00C

0x010

0x014

0x01C

0x020

313029282726252423222120191817161514131211

FLASH_ACR

Reset value 000000

FLASH_KEYR FKEYR[31:0]

Reset value xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx

FLASH_OPTKEYR OPTKEYR[31:0]

Reset Value xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx

FLASH_SR

Reset value 00 000

FLASH_CR

Reset value 00 00 1000 000
FLASH_AR FAR [3 1: 0]
Reset value 00000000000000000000000000000000

FLASH_OBR

Reset value 11111111111111111111111100

FLASH_WRPR

Reset value 11111111111111111111111111111111

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Data1

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Data0

Res.

Res.

Res.

Res.

Res.

Res.

987654321

10

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

RAM_PARITY_CHECK

Res.

EOPIE

OBL_LAUNCH

nBOOT1

VDDA_MONITOR

Res.

Res.

ERRIE

OPTWRE

nRST_STOP

nRST_STDBY

WRP[15:0]

Res.

STRT

LOCK

Res.

Res.

WDG_SW

HLFCYA

PRFTBS

PRFTBE

Res.

EOP

WRPRTERR

Res.

OPTER

OPTPG

Res.

Res.

Res.

PGERR

MER

RDPRT2

[2:0]

LATENCY

BSY

ERLYBSY

PG

PER

RDPRT1

OPTERR

0

Refer to Section 2.2.2 on page 37 for the register boundary addresses.

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RM0091 Option byte description

4 Option byte description

There are six option bytes. They are configured by the end user depending on the
application requirements. As a configuration example, the watchdog may be selected in
hardware or software mode.

A 32-bit word is split up as follows in the option bytes.

Table 9. Option byte format

31-24 23-16 15 -8 7-0

Complemented

option byte 1

Option byte 1

Complemented

option byte 0

Option byte 0

The organization of these bytes inside the information block is as shown in Tabl e 1 0 .

The option bytes can be read from the memory locations listed in Ta ble 1 0 or from the
Option byte register (FLASH_OBR).

Note: The new programmed option bytes (user, read/write protection) are loaded after a system

reset.

Table 10. Option byte organization

Address [31:24] [23:16] [15:8] [7:0]

0x1FFF F800 nUSER USER nRDP RDP

0x1FFF F804 nData1 Data1 nData0 Data0

0x1FFF F808 nWRP1 WRP1 nWRP0 WRP0

Doc ID 018940 Rev 1 59/742

Option byte description RM0091

Table 11. Description of the option bytes

Flash memory

address

0x1FFF F800

0x1FFF F804

Option bytes

Bits [31:24] nUSER
Bits [23:16] USER: User option byte (stored in FLASH_OBR[15:8])

This byte is used to configure the following features:

– Select the watchdog event: Hardware or software.
– Reset event when entering Stop mode.

– Reset event when entering Standby mode.
Bit 23 : reserved
Bit 22 : RAM_PARITY_CHECK

0 : RAM parity check enabled
1 : RAM parity check disabled

Bit 21 : VDDA_MONITOR

0 : V
1 : V

power supply supervisor disabled

DDA

power supply supervisor enabled

DDA

Bit 20 : nBOOT1

Together with the BOOT0 pin, it selects the boot mode to the main Flash memory

SRAM or to the System memory.
Refer to Section 2.5: Boot configuration for more details.
Bit 19 : reserved
Bit 18: nRST_STDBY

0: Reset generated when entering Standby mode.

1: No reset generated.
Bit 17: nRST_STOP

0: Reset generated when entering Stop mode

1: No reset generated
Bit 16: WDG_SW

0: Hardware watchdog

1: Software watchdog
Bits [15:8]: nRDP
Bits [7:0]: RDP: Read protection option byte
The value of this byte defines the Flash memory protection level

0xAA : level 0 (ST production configuration)

0xXX (except 0xAA & 0xCC) : Level 1

0xCC : Level 2
Note : The protection level 1 and 2 are stored in the FLASH_OBR Flash option

register (RDPRT1 and RDPRT2 status flags respectively). Refer to Section 3.2.2:

Read operations for more details.

Datax: Two bytes for user data storage.

These addresses can be programmed using the option byte programming

procedure.

Bits [31:24]: nData1

Bits [23:16]: Data1 (stored in FLASH_OBR[25:18])

Bits [15:8]: nData0

Bits [7:0]: Data0 (stored in FLASH_OBR[17:10])

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RM0091 Option byte description

Table 11. Description of the option bytes (continued)

Flash memory

address

0x1FFF F808

WRPx: Flash memory write protection option bytes

Bits [31:24]: nWRP1

Bits [23:16]: WRP1 (stored in FLASH_WRPR[15:8])

Bits [15:8]: nWRP0

Bits [7:0]: WRP0 (stored in FLASH_WRPR[7:0])

0: Write protection enabled

1: Write protection disabled
Refer to Section 3.3.2: Write protection for more details.

Option bytes

On every system reset, the option byte loader (OBL) reads the information block and stores
the data into the Option byte register (FLASH_OBR) and the Write protection register
(FLASH_WRPR). Each option byte also has its complement in the information block. During
option loading, by verifying the option bit and its complement, it is possible to check that the
loading has correctly taken place. If this is not the case, an option byte error (OPTERR) is
generated. When a comparison error occurs the corresponding option byte is forced to
0xFF. The comparator is disabled when the option byte and its complement are both equal
to 0xFF (Electrical Erase state).

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Cyclic redundancy check calculation unit (CRC) RM0091

5 Cyclic redundancy check calculation unit (CRC)

5.1 Introduction

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the functional safety standards, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link
time and stored at a given memory location.

5.2 CRC main features

● Uses CRC-32 (Ethernet) polynomial: 0x4C11DB7

32

. X

+ X26 + X23 + X22 + X16 + X12 + X11 + X10 +X8 + X7 + X5 + X4 + X2+ X +1

● Handles 8,16, 32 bit data size

● Programmable CRC initial value

● Single input/output 32-bit data register

● Input buffer to avoid bus stall during calculation

● CRC computation done in 4 AHB clock cycles (HCLK) for 32-bit data

● General-purpose 8-bit register (can be used for temporary storage)

● Reversibility option on I/O data

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RM0091 Cyclic redundancy check calculation unit (CRC)

MS19882V1

Data register (output)

32-bit (read access)

CRC computation

Data register (input)

32-bit (write access)

AHB bus

5.3 CRC functional description

Figure 5. CRC calculation unit block diagram

The CRC calculation unit has a single 32-bit read/write data register (CRC_DR). It is used to
input new data (write access), and holds the result of the previous CRC calculation (read
access).

Each write operation to the data register creates a combination of the previous CRC value
(stored in CRC_DR) and the new one. CRC computation is done on the whole 32-bit data
word or byte by byte depending on the format of the data being written.

The CRC_DR register can be accessed by word, right-aligned half-word and right-aligned
byte. For the other registers only 32-bit access is allowed.

The duration of the computation depends on data width:

● 4 AHB clock cycles for 32-bit

● 2 AHB clock cycles for 16-bit

● 1 AHB clock cycles for 8-bit

An input buffer allows to immediately write a second data without waiting for any wait states
due to the previous CRC calculation.

The data size can be dynamically adjusted to minimize the number of write accesses for a
given number of bytes. For instance, a CRC for 5 bytes can be computed with a word write
followed by a byte write.

The input data can be reversed, to manage the various endianness schemes. The reversing
operation can be performed on 8 bits, 16 bits and 32 bits depending on the REV_IN[1:0] bits
in the CRC_CR register.

For example: input data 0x1A2B3C4D is used for CRC calculation as:

0x58D43CB2 with bit-reversal done by byte
0xD458B23C with bit-reversal done by half-word
0xB23CD458 with bit-reversal done on the full word

The output data can also be reversed by setting the REV_OUT bit in the CRC_CR register.

The operation is done at bit level: for example, output data 0x11223344 is converted into
0x22CC4488.

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Cyclic redundancy check calculation unit (CRC) RM0091

The CRC calculator can be initialized to a programmable value using the RESET control bit
in the CRC_CR register (the default value is 0xFFFFFFFF).

The initial CRC value can be programmed with the CRC_INIT register. The CRC_DR
register is automatically initialized upon CRC_INIT register write access.

The CRC_IDR register can be used to hold a temporary value related to CRC calculation. It
is not affected by the RESET bit in the CRC_CR register.

5.4 CRC registers

5.4.1 Data register (CRC_DR)

Address offset: 0x00

Reset value: 0xFFFF FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

1514131211109876543210

Bits 31:0 DR[31:0]: Data register bits

DR[31:16]

rw

DR[15:0]

rw

This register is used to write new data to the CRC calculator.
It holds the previous CRC calculation result when it is read.
If the data size is less than 32 bits, the least significant bits are used to write/read the correct value.

5.4.2 Independent data register (CRC_IDR)

Address offset: 0x04

Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

1514131211109876543210

Res. Res. Res. Res. Res. Res. Res. Res. IDR[7:0]

Bits 31:8 Reserved, must be kept cleared.

Bits 7:0 IDR[7:0]: General-purpose 8-bit data register bits

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rw

These bits can be used as a temporary storage location for one byte.
This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register

RM0091 Cyclic redundancy check calculation unit (CRC)

5.4.3 Control register (CRC_CR)

Address offset: 0x08

Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

1514131211109876543210

Res. Res. Res. Res. Res. Res. Res. Res.

Bits 31:8 Reserved, must be kept cleared.

Bits 6:5 REV_IN[1:0]: Reverse input data

Bits 4:3 Reserved, must be kept cleared.

REV_O

UT

rw rw rw rs

Bit 7 REV_OUT: Reverse output data

This bit controls the reversal of the bit order of the output data.
0: Bit order not affected
1: Bit-reversed output format

These bits control the reversal of the bit order of the input data
00: Bit order not affected
01: Bit reversal done by byte
10: Bit reversal done by half-word
11: Bit reversal done by word

REV_IN[1:0] Res. Res. Res. RESET

Bits 4:3 These bits are generated only if the generic “full_poly” = 1 otherwise they are forced to 0

Bits 2:1 Reserved, must be kept cleared.

Bit 0 RESET: RESET bit

This bit is set by software to reset the CRC calculation unit and set the data register to the value stored
in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware

Doc ID 018940 Rev 1 65/742

Cyclic redundancy check calculation unit (CRC) RM0091

5.4.4 Initial CRC value (CRC_INIT)

Address offset: 0x10

Reset value: 0xFFFF FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bits 31:0 CRC_INIT: Programmable initial CRC value

CRC_INIT[31:16]

rw

CRC_INI[15:0]

rw

This register is used to write the CRC initial value.

5.4.5 CRC register map

Table 12. CRC register map and reset values

Offset Register

0x00

0x04

0x08

0x10

313029282726252423222120191817161514131211

CRC_DR Data register

Reset value 11111111111111111111111111111111

CRC_IDR

Reset value 00000000

CRC_CR

Reset value 000 0

CRC_INIT CRC initial value

Reset value 11111111111111111111111111111111

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Refer to Section 2.2.2 on page 37 for the register boundary addresses.

987654321

10

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Independent data register

Res.

Res.

Res.

Res.

REV_IN

REV_OUT

Res.

Res.

0

Res.

Res.

RESET

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RM0091 Power control (PWR)

A/D converter

V

DD

V

BAT

V

SS

I/O Ring

V

DDA

BKP registers

Temp. sensor
Reset block

Standby circuitry

PLL

(Wakeup logic,
IWDG)

RTC

Voltage Regulator

Core

Memories

digital

peripherals

Low voltage detector

V

DDA

domain

V

DD

domain

1.8 V domain

Backup domain

LSE crystal 32K osc

RCC BDCR register

V

SSA

D/A converter

6 Power control (PWR)

6.1 Power supplies

The device requires a 2.0 V - 3.6 V operating voltage supply (VDD) and 2.0 V - 3.6 V analog
voltage supply (V
power.

). An embedded regulator is used to supply the internal 1.8 V digital

DDA

The real-time clock (RTC) and backup registers can be powered from the V
the main V

supply is powered off.

DD

Figure 6. Power supply overview

voltage when

BAT

6.1.1 Independent A/D and D/A converter supply and reference voltage

To improve conversion accuracy and to extend the supply flexibility, the ADC and the DAC
have an independent power supply which can be separately filtered and shielded from noise
on the PCB.

● The ADC and DAC voltage supply input is available on a separate V

● An isolated supply ground connection is provided on pin V

The V

supply/reference voltage can be equal or higher than VDD.

DDA

When a single supply is used, V
external filtering circuit in order to ensure a noise free V

Doc ID 018940 Rev 1 67/742

can be externally connected to VDD, through the

DDA

DDA

SSA

/reference voltage.

DDA

.

pin.

Power control (PWR) RM0091

When V

is different from VDD, it must always be higher or equal to VDD. In order to

DDA

ensure this condition, also during power-up/power-down transitions, an external Shottky
diode may be used between V

6.1.2 Battery backup domain

To retain the content of the Backup registers and supply the RTC function when V
turned off, V
by another source.

The V

BAT

the RTC to operate even when the main power supply is turned off. The switch to the V
supply is controlled by the Power Down Reset embedded in the Reset block.

Warning: During t

pin can be connected to an optional standby voltage supplied by a battery or

BAT

pin powers the RTC unit, the LSE oscillator and the PC13 to PC15 IOs, allowing

is detected, the power switch between V

RSTTEMPO

connected to V
During the startup phase, if V
t

RSTTEMPO

and V

DD

> V
through an internal diode connected between V
power switch (V
If the power supply/battery connected to the V
support this current injection, it is strongly recommended to
connect an external low-drop diode between this power
supply and the V

DD

and V

DDA

.

(temporization at VDD startup) or after a PDR

and VDD remains

BAT

BAT

.

is established in less than

DD

(Refer to the datasheet for the value of t

+ 0.6 V, a current may be injected into V

BAT

DD

BAT

BAT

BAT

).

pin.

DD

RSTTEMPO

BAT

and the

pin cannot

is

BAT

)

If no external battery is used in the application, it is recommended to connect V

BAT

externally to VDD with a 100 nF external ceramic decoupling capacitor (for more details refer
to AN2586).

When the backup domain is supplied by V

(analog switch connected to VDD), the

DD

following functions are available:

● PC13, PC14 and PC15 can be used as GPIO pins

● PC13, PC14 and PC15 can be configured by RTC or LSE (refer to Section 24.3: RTC

functional description on page 536)

Note: Due to the fact that the switch only sinks a limited amount of current (3 mA), the use of

GPIOs PC13 to PC15 in output mode is restricted: the speed has to be limited to 2 MHz with
a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive
an LED).

When the backup domain is supplied by V
V

is not present), the following functions are available:

DD

● PC13, PC14 and PC15 can be controlled only by RTC or LSE (refer to Section 24.3:

(analog switch connected to V

BAT

because

BAT

RTC functional description on page 536)

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RM0091 Power control (PWR)

VDD/V

DDA

Reset

40 mV

hysteresis

POR

PDR

Temporization
t

RSTTEMPO

6.1.3 Voltage regulator

The voltage regulator is always enabled after Reset. It works in three different modes
depending on the application modes.

● In Run mode, the regulator supplies full power to the 1.8 V domain (core, memories

and digital peripherals).

● In Stop mode the regulator supplies low-power to the 1.8 V domain, preserving

contents of registers and SRAM

● In Standby Mode, the regulator is powered off. The contents of the registers and SRAM

are lost except for the Standby circuitry and the Backup Domain.

6.2 Power supply supervisor

6.2.1 Power on reset (POR) / power down reset (PDR)

The device has an integrated power-on reset (POR) and power-down reset (PDR) circuits
which are always active and ensure proper operation above a threshold of 2 V.

The device remains in Reset mode when the monitored supply voltage is below a specified
threshold, V

● The POR monitors only the V

POR/PDR

arrive first and be greater than or equal to V

●

The PDR monitors both the V
supply supervisor can be disabled (by programming a dedicated option bit
V

DDA_MONITOR

sure that V

For more details on the power on / power down reset threshold, refer to the electrical
characteristics section in the datasheet.

, without the need for an external reset circuit.

supply voltage. During the startup phase V

DD

DD

and V

DD.

supply voltages. However, the V

DDA

DDA

DDA

) to reduce the power consumption if the application is designed to make
is higher than or equal to VDD.

DDA

must

power

Figure 7. Power on reset/power down reset waveform

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Power control (PWR) RM0091

V

DD

PVD output

100 mV
hysteresis

PVD threshold

6.2.2 Programmable voltage detector (PVD)

You can use the PVD to monitor the VDD power supply by comparing it to a threshold
selected by the PLS[2:0] bits in the Power control register (PWR_CR).

The PVD is enabled by setting the PVDE bit.

A PVDO flag is available, in the Power control/status register (PWR_CSR), to indicate if V

DD

is higher or lower than the PVD threshold. This event is internally connected to the EXTI
line16 and can generate an interrupt if enabled through the EXTI registers. The PVD output
interrupt can be generated when V

drops below the PVD threshold and/or when VDD

DD

rises above the PVD threshold depending on EXTI line16 rising/falling edge configuration.
As an example the service routine could perform emergency shutdown tasks.

Figure 8. PVD thresholds

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RM0091 Power control (PWR)

6.3 Low-power modes

By default, the microcontroller is in Run mode after a system or a power Reset. Several low­power modes are available to save power when the CPU does not need to be kept running,
for example when waiting for an external event. It is up to the user to select the mode that
gives the best compromise between low-power consumption, short startup time and
available wakeup sources.

The device features three low-power modes:

● Sleep mode (CPU clock off, all peripherals including Cortex-M0 core peripherals like

NVIC, SysTick, etc. are kept running)

● Stop mode (all clocks are stopped)

● Standby mode (1.8V domain powered-off)

In addition, the power consumption in Run mode can be reduce by one of the following
means:

● Slowing down the system clocks

● Gating the clocks to the APB and AHB peripherals when they are unused.

Table 13. Low-power mode summary

Effect on

Mode name Entry wakeup

Effect on 1.8V

domain clocks

V

DD

domain

clocks

Volt ag e

regulator

Sleep
(Sleep now or

Sleep-on ­exit)

Stop

Standby

WFI Any interrupt CPU clock OFF

WFE Wakeup event

Any EXTI line
(configured in the

PDDS and LPDS
bits +
SLEEPDEEP bit
+ WFI or WFE

PDDS bit +
SLEEPDEEP bit
+ WFI or WFE

EXTI registers)
Specific

communication
peripherals on
reception events
(CEC, USART,
I2C)

WKUP pin rising
edge, RTC alarm,
external reset in
NRST pin,
IWDG reset

6.3.1 Slowing down system clocks

In Run mode the speed of the system clocks (SYSCLK, HCLK, PCLK) can be reduced by
programming the prescaler registers. These prescalers can also be used to slow down
peripherals before entering Sleep mode.

no effect on other
clocks or analog
clock sources

All 1.8V domain
clocks OFF

None ON

ON or in low­power mode

(depends on

HSI and
HSE
oscillators
OFF

Power control
register
(PWR_CR))

OFF

For more details refer to Section 7.4.2: Clock configuration register (RCC_CFGR).

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Power control (PWR) RM0091

6.3.2 Peripheral clock gating

In Run mode, the HCLK and PCLK for individual peripherals and memories can be stopped
at any time to reduce power consumption.

To further reduce power consumption in Sleep mode the peripheral clocks can be disabled
prior to executing the WFI or WFE instructions.

Peripheral clock gating is controlled by the AHB peripheral clock enable register

(RCC_AHBENR), the APB2 peripheral clock enable register (RCC_APB2ENR) and the
APB1 peripheral clock enable register (RCC_APB1ENR).

6.3.3 Sleep mode

Entering Sleep mode

The Sleep mode is entered by executing the WFI (Wait For Interrupt) or WFE (Wait for
Event) instructions. Two options are available to select the Sleep mode entry mechanism,
depending on the SLEEPONEXIT bit in the Cortex-M0 System Control register:

● Sleep-now: if the SLEEPONEXIT bit is cleared, the MCU enters Sleep mode as soon

as WFI or WFE instruction is executed.

● Sleep-on-exit: if the SLEEPONEXIT bit is set, the MCU enters Sleep mode as soon as

it exits the lowest priority ISR.

In the Sleep mode, all I/O pins keep the same state as in the Run mode.

Refer to Ta bl e 1 4 and Table 1 5 for details on how to enter Sleep mode.

Exiting Sleep mode

If the WFI instruction is used to enter Sleep mode, any peripheral interrupt acknowledged by
the nested vectored interrupt controller (NVIC) can wake up the device from Sleep mode.

If the WFE instruction is used to enter Sleep mode, the MCU exits Sleep mode as soon as
an event occurs. The wakeup event can be generated either by:

● enabling an interrupt in the peripheral control register but not in the NVIC, and enabling

the SEVONPEND bit in the Cortex-M0 System Control register. When the MCU
resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC IRQ
channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.

● or configuring an external or internal EXTI line in event mode. When the CPU resumes

from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC
IRQ channel pending bit as the pending bit corresponding to the event line is not set.

This mode offers the lowest wakeup time as no time is wasted in interrupt entry/exit.

Refer to Ta bl e 1 4 and Table 1 5 for more details on how to exit Sleep mode.

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RM0091 Power control (PWR)

Table 14. Sleep-now

Sleep-now mode Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

Mode entry

Mode exit

Wakeup latency None

Table 15. Sleep-on-exit

Sleep-on-exit Description

Mode entry

Mode exit Interrupt: Refer to Table 27: Vector table.

Wakeup latency None

– SLEEPDEEP = 0 and
– SLEEPONEXIT = 0
Refer to the Cortex-M0 System Control register.

If WFI was used for entry:

Interrupt: Refer to Table 27: Vector table

If WFE was used for entry

Wakeup event: Refer to Section 11.2.3: Wakeup event management

WFI (wait for interrupt) while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1
Refer to the Cortex-M0 System Control register.

6.3.4 Stop mode

The Stop mode is based on the Cortex-M0 deepsleep mode combined with peripheral clock
gating. The voltage regulator can be configured either in normal or low-power mode. In Stop
mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE oscillators
are disabled. SRAM and register contents are preserved.

In the Stop mode, all I/O pins keep the same state as in the Run mode.

Entering Stop mode

Refer to Ta bl e 1 6 for details on how to enter the Stop mode.

To further reduce power consumption in Stop mode, the internal voltage regulator can be
put in low-power mode. This is configured by the LPDS bit of the Power control register

(PWR_CR).

If Flash memory programming is ongoing, the Stop mode entry is delayed until the memory
access is finished.

If an access to the APB domain is ongoing, The Stop mode entry is delayed until the APB
access is finished.

In Stop mode, the following features can be selected by programming individual control bits:

● Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by

hardware option. Once started it cannot be stopped except by a Reset. See

Section 21.3: IWDG functional description in Section 21: Independent watchdog
(IWDG).

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Power control (PWR) RM0091

● real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control

register (RCC_BDCR)

● Internal RC oscillator (LSI): this is configured by the LSION bit in the Control/status

register (RCC_CSR).

● External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the Backup

domain control register (RCC_BDCR).

The ADC or DAC can also consume power during Stop mode, unless they are disabled
before entering this mode. Refer to ADC control register (ADC_CR) and DAC control

register (DAC_CR) for details on how to disable them.

Exiting Stop mode

Refer to Ta bl e 1 6 for more details on how to exit Stop mode.

When exiting Stop mode by issuing an interrupt or a wakeup event, the HSI oscillator is
selected as system clock.

When the voltage regulator operates in low-power mode, an additional startup delay is
incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop
mode, the consumption is higher although the startup time is reduced.

Table 16. Stop mode

Stop mode Description

Mode entry

Mode exit

Wakeup latency HSI wakeup time + regulator wakeup time from Low-power mode

6.3.5 Standby mode

WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– Set SLEEPDEEP bit in Cortex-M0 System Control register
– Clear PDDS bit in Power Control register (PWR_CR)
– Select the voltage regulator mode by configuring LPDS bit in PWR_CR

Note: To enter Stop mode, all EXTI Line pending bits (in Pending register

(EXTI_PR)) and RTC Alarm flag must be reset. Otherwise, the Stop mode

entry procedure is ignored and program execution continues.

If WFI was used for entry:
– Any EXTI Line configured in Interrupt mode (the corresponding EXTI

Interrupt vector must be enabled in the NVIC).

– Some specific communication peripherals (CEC, USART, I2C) interrupts,

when programmed in wakeup mode (the peripheral must be programmed
in wakeup mode and the corresponding interrupt vector must be enabled

in the NVIC).
Refer to Table 27: Vector table.
If WFE was used for entry:

Any EXTI Line configured in event mode. Refer to Section 11.2.3:

Wakeup event management on page 160

The Standby mode allows to achieve the lowest power consumption. It is based on the
Cortex-M0 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is
consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also
switched off. SRAM and register contents are lost except for registers in the Backup domain
and Standby circuitry (see Figure 6).

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RM0091 Power control (PWR)

Entering Standby mode

Refer to Ta bl e 1 7 for more details on how to enter Standby mode.

In Standby mode, the following features can be selected by programming individual control
bits:

● Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by

hardware option. Once started it cannot be stopped except by a reset. See

Section 21.3: IWDG functional description in Section 21: Independent watchdog
(IWDG).

● real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control

register (RCC_BDCR)

● Internal RC oscillator (LSI): this is configured by the LSION bit in the Control/status

register (RCC_CSR).

● External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the Backup

domain control register (RCC_BDCR)

Exiting Standby mode

The microcontroller exits the Standby mode when an external reset (NRST pin), an IWDG
reset, a rising edge on one of the enabled WKUPx pins or the rising edge of an RTC alarm
occurs (see Figure 227: RTC block diagram). All registers are reset after wakeup from
Standby except for Power control/status register (PWR_CSR).

After waking up from Standby mode, program execution restarts in the same way as after a
Reset (boot pin sampling, option bytes loading, reset vector is fetched, etc.). The SBF status
flag in the Power control/status register (PWR_CSR) indicates that the MCU was in Standby
mode.

Refer to Ta bl e 1 7 for more details on how to exit Standby mode.

Table 17. Standby mode

Standby mode Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

Mode entry

Mode exit

Wakeup latency Reset phase

– Set SLEEPDEEP in Cortex-M0 System Control register
– Set PDDS bit in Power Control register (PWR_CR)
– Clear WUF bit in Power Control/Status register (PWR_CSR)

WKUP pin rising edge, RTC alarm event’s rising edge, external Reset in

NRST pin, IWDG Reset.

I/O states in Standby mode

In Standby mode, all I/O pins are high impedance except:

● Reset pad (still available)

● PC13, PC14 and PC15 if configured by RTC or LSE

● WKUPx pins

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Power control (PWR) RM0091

Debug mode

By default, the debug connection is lost if the application puts the MCU in Stop or Standby
mode while the debug features are used. This is due to the fact that the Cortex-M0 core is
no longer clocked.

However, by setting some configuration bits in the DBGMCU_CR register, the software can
be debugged even when using the low-power modes extensively..

6.3.6 Auto-wakeup from low-power mode

The RTC can be used to wakeup the MCU from low-power mode without depending on an
external interrupt (Auto-wakeup mode). The RTC provides a programmable time base for
waking up from Stop or Standby mode at regular intervals. For this purpose, two of the three
alternative RTC clock sources can be selected by programming the RTCSEL[1:0] bits in the

Backup domain control register (RCC_BDCR):

● Low-power 32.768 kHz external crystal oscillator (LSE OSC).

This clock source provides a precise time base with very low-power consumption (less
than 1µA added consumption in typical conditions)

● Low-power internal RC Oscillator (LSI)

This clock source has the advantage of saving the cost of the 32.768 kHz crystal. This
internal RC Oscillator is designed to add minimum power consumption.

To wakeup from Stop mode with an RTC alarm event, it is necessary to:

● Configure the EXTI Line 17 to be sensitive to rising edge

● Configure the RTC to generate the RTC alarm

To wakeup from Standby mode, there is no need to configure the EXTI Line 17.

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RM0091 Power control (PWR)

6.4 Power control registers

The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).

6.4.1 Power control register (PWR_CR)

Address offset: 0x00

Reset value: 0x0000 0000 (reset by wakeup from Standby mode)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res

1514131211109876543210

Res Res Res Res Res Res Res DBP PLS[2:0] PVDE CSBF CWUF PDDS LPDS

rw rw rw rw rw rc_w1 rc_w1 rw rw

Bits 31:9 Reserved, must be kept at reset value..

Bit 8 DBP: Disable backup domain write protection.

In reset state, the RTC and backup registers are protected against parasitic write access.
This bit must be set to enable write access to these registers.
0: Access to RTC and Backup registers disabled
1: Access to RTC and Backup registers enabled

Bits 7:5 PLS[2:0]: PVD level selection.

These bits are written by software to select the voltage threshold detected by the Power
Voltage Detector.

Once the PVD_LOCK is enabled in the SYSCFG configuration register 2 (SYSCFG_CFGR2),
the PLS[2:0] bits cannot be programmed anymore.

000: PVD threshold 0
001: PVD threshold 1
010: PVD threshold 2
011: PVD threshold 3
100: PVD threshold 4
101: PVD threshold 5
110: PVD threshold 6
111: PVD threshold 7

Refer to the electrical characteristics of the datasheet for more details.

Bit 4 PVDE: Power voltage detector enable.

This bit is set and cleared by software. Once the PVD_LOCK is enabled in the SYSCFG

configuration register 2 (SYSCFG_CFGR2) register, the PVDE bit cannot be programmed

anymore.

0: PVD disabled
1: PVD enabled

Bit 3 CSBF: Clear standby flag.

This bit is always read as 0.

0: No effect
1: Clear the SBF Standby Flag (write).

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Power control (PWR) RM0091

Bit 2 CWUF: Clear wakeup flag.

This bit is always read as 0.

0: No effect
1: Clear the WUF Wakeup Flag after 2 System clock cycles. (write)

Bit 1 PDDS: Power down deepsleep.

This bit is set and cleared by software. It works together with the LPDS bit.

0: Enter Stop mode when the CPU enters Deepsleep. The regulator status depends on the
LPDS bit.

1: Enter Standby mode when the CPU enters Deepsleep.

Bit 0 LPDS: Low-power deepsleep.

This bit is set and cleared by software. It works together with the PDDS bit.

0: Voltage regulator on during Stop mode
1: Voltage regulator in low-power mode during Stop mode

Note: When a peripheral that can work in STOP mode requires a clock, the Power controller

automatically switch the voltage regulator from Low-power mode to Normal mode and
remains in this mode until the request disappears.

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RM0091 Power control (PWR)

6.4.2 Power control/status register (PWR_CSR)

Address offset: 0x04

Reset value: 0x0000 0000 (not reset by wakeup from Standby mode)

Additional APB cycles are needed to read this register versus a standard APB read.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res

1514131211109876543210

Res Res Res Res Res Res

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 EWUP2: Enable WKUP2 pin

This bit is set and cleared by software.

0: WKUP2 pin is used for general purpose I/O. An event on the WKUP2 pin does not wakeup
the device from Standby mode.

1: WKUP2 pin is used for wakeup from Standby mode and forced in input pull down
configuration (rising edge on WKUP1 pin wakes-up the system from Standby mode).

Note: This bit is reset by a system Reset.

Bit 8 EWUP1: Enable WKUP1 pin

This bit is set and cleared by software.

0: WKUP1 pin is used for general purpose I/O. An event on the WKUP1 pin does not wakeup
the device from Standby mode.

1: WKUP1 pin is used for wakeup from Standby mode and forced in input pull down
configuration (rising edge on WKUP1 pin wakes-up the system from Standby mode).

Note: This bit is reset by a system Reset.

Bits 7:3 Reserved, must be kept at reset value.

EWUP2EWUP

rw rw r r r

Res Res Res Res Res PVDO SBF WUF

1

Bit 2 PVDO: PVD output

This bit is set and cleared by hardware. It is valid only if PVD is enabled by the PVDE bit.

is lower than the PVD threshold selected with the PLS[2:0] bits.

0: V

DD

1: V

is higher than the PVD threshold selected with the PLS[2:0] bits.

DD

Notes:

1. The PVD is stopped by Standby mode. For this reason, this bit is equal to 0 after Standby
or reset until the PVDE bit is set.

2. Once the PVD is enabled and configured in the PWR_CR register, PVDO can be used to
generate an interrupt through the External Interrupt controller.

Bit 1 SBF: Standby flag

This bit is set by hardware when the device enters Standby mode and it is cleared only by a
POR/PDR (power on reset/power down reset) or by setting the CSBF bit in the Power control

register (PWR_CR)

0: Device has not been in Standby mode
1: Device has been in Standby mode

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Power control (PWR) RM0091

Bit 0 WUF: Wakeup flag

This bit is set by hardware to indicate that the device received a wakeup event. It is cleared
only by a POR/PDR (power on reset/power down reset) or by setting the CWUF bit in the

Power control register (PWR_CR)

0: No wakeup event occurred
1: A wakeup event was received from one of the enabled WKUPx pins or from the RTC

alarm.

Note: An additional wakeup event is detected if one WKUPx pin is enabled (by setting the

EWUP bit) when its pin level is already high.

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RM0091 Power control (PWR)

6.4.3 PWR register map

The following table summarizes the PWR registers.

Table 18. PWR register map and reset values

Offset Register

0x000

313029282726252423222120191817161514131211

PWR_CR

Reset value 000000000

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

987654321

10

Res.

Res.

PLS[2:0]

Res.

DBP

CSBF

PVDE

PDDS

CWUF

0

LPDS

0x004

PWR_CSR

Reset value 00 000

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

EWUP2

EWUP1

Res.

Res.

Res.

Res.

SBF

Res.

WUF

PVDO

Refer to Section 2.2.2 on page 37 for the register boundary addresses.

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Reset and clock control (RCC) RM0091

NRST

R

PU

V

DD

WWDG reset
IWWDG reset

Pulse

generator

Power reset

External

reset

(min 20 μs)

System reset

Filter

Software reset
Low-power management reset
Option byte loader reset

Exit from Standby mode

MS19841V1

7 Reset and clock control (RCC)

7.1 Reset

There are three types of reset, defined as system reset, power reset and backup domain
reset.

7.1.1 System reset

A system reset sets all registers to their reset values except the reset flags in the clock
controller CSR register and the registers in the Backup domain (see Figure 6 on page 74).

A system reset is generated when one of the following events occurs:

1. A low level on the NRST pin (external reset)

2. Window watchdog event (WWDG reset)

3. Independent watchdog event (IWWDG reset)

4. A software reset (SW reset) (see Software reset)

5. Low-power management reset (see Low-power management reset)

6. Option byte loader reset (see Option byte loader reset)

The reset source can be identified by checking the reset flags in the Control/Status register,
RCC_CSR (see Section 7.4.10: Control/status register (RCC_CSR)).

These sources act on the NRST pin and it is always kept low during the delay phase. The
RESET service routine vector is fixed at address 0x0000_0004 in the memory map.

The system reset signal provided to the device is output on the NRST pin. The pulse
generator guarantees a minimum reset pulse duration of 20 µs for each reset source
(external or internal reset). In case of an external reset, the reset pulse is generated while
the NRST pin is asserted low.

Figure 9. Simplified diagram of the reset circuit

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RM0091 Reset and clock control (RCC)

Software reset

The SYSRESETREQ bit in Cortex-M0 Application Interrupt and Reset Control Register
must be set to force a software reset on the device. Refer to the Cortex™-M0 technical
reference manual for more details.

Low-power management reset

There are two ways to generate a low-power management reset:

1. Reset generated when entering Standby mode:
This type of reset is enabled by resetting nRST_STDBY bit in User Option Bytes. In this

case, whenever a Standby mode entry sequence is successfully executed, the device
is reset instead of entering Standby mode.

2. Reset when entering Stop mode:
This type of reset is enabled by resetting nRST_STOP bit in User Option Bytes. In this

case, whenever a Stop mode entry sequence is successfully executed, the device is
reset instead of entering Stop mode.

For further information on the User Option Bytes, refer to Section 4 on page 64.

Option byte loader reset

The option byte loader reset is generated when the FORCE_OBL bit (bit 13) is set in the
FLASH_CR register. This bit is used to launch the option byte loading by software.

7.1.2 Power reset

A power reset is generated when one of the following events occurs:

1. Power-on/power-down reset (POR/PDR reset)

2. When exiting Standby mode

A power reset sets all registers to their reset values except the Backup domain (Figure 6 on

page 74)

7.1.3 Backup domain reset

The backup domain has two specific resets that affect only the backup domain (Figure 6 on

page 74).

A backup domain reset is generated when one of the following events occurs:

1. Software reset, triggered by setting the BDRST bit in the Backup domain control

register (RCC_BDCR).

2. V

DD

or V

power on, if both supplies have previously been powered off.

BAT

7.2 Clocks

Three different clock sources can be used to drive the system clock (SYSCLK):

● HSI 8 MHZ RC oscillator clock

● HSE oscillator clock

● PLL clock

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Reset and clock control (RCC) RM0091

The devices have the following additional clock sources:

● 40 kHz low speed internal RC (LSI RC) which drives the independent watchdog and

optionally the RTC used for Auto-wakeup from Stop/Standby mode.

● 32.768 kHz low speed external crystal (LSE crystal) which optionally drives the real-

time clock (RTCCLK)

● 14 MHz high speed internal RC (HSI14) dedicated for ADC.

Each clock source can be switched on or off independently when it is not used, to optimize
power consumption.

Several prescalers can be used to configure the frequency of the AHB and the APB
domains. The AHB and the APB domains maximum frequency is 48 MHz.

The Cortex system timer is always clocked by the AHB clock divided by 8 or directly by the
AHB clock (through Cortex Systick configuration bits).

All the peripheral clocks are derived from their bus clock (HCLK or PCLK) except:

● The Flash memory programming interface clock (FLITFCLK) which is always the HSI

clock.

● The option byte loader clock which is always the HSI clock

● The ADC clock which is derived (selected by software) from one of the two following

sources:
– dedicated HSI14 clock, to run always at the maximum sampling rate
– APB clock (PCLK) divided by 2 or 4

● The USART1 clock which is derived (selected by software) from one of the four

following sources:
– system clock
–HSI clock
– LSE clock
– APB clock (PCLK)

● The I2C1 clock which is derived (selected by software) from one of the two following

sources:
– system clock
–HSI clock

● The CEC clock which is derived from the HSI clock divided by 244 or from the LSE

clock.

● The I2S1 clock which is always the system clock.

● The RTC clock which is derived from the LSE, LSI or from the HSE clock divided by 32.

● The IWWDG clock which is always the LSI clock.

The RCC feeds the Cortex System Timer (SysTick) external clock with the AHB clock
(HCLK) divided by 8. The SysTick can work either with this clock or directly with the Cortex
clock (HCLK), configurable in the SysTick Control and Status Register.

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RM0091 Reset and clock control (RCC)

Figure 10. Clock tree

FLITFCLK
to Flash programming interface

HSI

SYSCLK

to I2C1

to I2S1

OSC_OUT

OSC_IN

OSC32_IN

OSC32_OUT

MCO

8 MHz

HSI RC

PLLSRC

/2,/3,...

/16

4-32 MHz
HSE OSC

LSE OSC

32.768kHz

LSI RC
40kHz

Main clock
output

MCO

HSI

PLLMUL

PLL

x2,x3,..

x16

/32

LSE

RTCSEL[1:0]

LSI

/2

/2

PLLCLK

PLLCLK
HSI

HSI14

HSE

SYSCLK

HSI

HSE

CSS

RTCCLK

SW

SYSCLK

14 MHz

HSI14 RC

AHB

AHB

prescaler

/1,2,..512

HSI14

to RTC

to IWWDG

IWWDGCLK

LSE

/256

HCLK

/8

APB

prescaler

/1,2,4,8,16

If (APB1 prescaler
=1) x1 else x2

ADC

Prescaler

/2,4

PCLK

SYSCLK

HSI

LSE

to CEC

to AHB bus, core,
memory and DMA

to cortex System timer
FHCLK Cortex free running clock

PCLK

to APB peripherals

to TIM1,2,3,6,
14,15,16,17

to ADC
14 MHz max

to USART1

MS19935V1

1. For full details about the internal and external clock source characteristics, please refer to the “Electrical characteristics”
section in your device datasheet.

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Reset and clock control (RCC) RM0091

OSC_OUT

External

source

GPIO

OSC_IN

OSC_IN OSC_OUT

Load

capacitors

C

L2

C

L1

The timer clock frequencies are automatically fixed by hardware. There are two cases:

1. if the APB prescaler is 1, the timer clock frequencies are set to the same frequency as
that of the APB domain.

2. otherwise, they are set to twice (×2) the frequency of the APB domain.

FCLK acts as Cortex-M0’s free-running clock. For more details refer to the ARM Cortex™-

M0 r0p0 technical reference manual(TRM).

7.2.1 HSE clock

The high speed external clock signal (HSE) can be generated from two possible clock
sources:

● HSE external crystal/ceramic resonator

● HSE user external clock

The resonator and the load capacitors have to be placed as close as possible to the
oscillator pins in order to minimize output distortion and startup stabilization time. The
loading capacitance values must be adjusted according to the selected oscillator.

Figure 11. HSE/ LSE clock sources

Clock source Hardware configuration

External clock

Crystal/Ceramic

resonators

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RM0091 Reset and clock control (RCC)

External crystal/ceramic resonator (HSE crystal)

The 4 to 32 MHz external oscillator has the advantage of producing a very accurate rate on
the main clock.

The associated hardware configuration is shown in Figure 11. Refer to the electrical
characteristics section of the datasheet for more details.

The HSERDY flag in the Clock control register (RCC_CR) indicates if the HSE oscillator is
stable or not. At startup, the clock is not released until this bit is set by hardware. An
interrupt can be generated if enabled in the Clock interrupt register (RCC_CIR).

The HSE Crystal can be switched on and off using the HSEON bit in the Clock control

register (RCC_CR).

External source (HSE bypass)

In this mode, an external clock source must be provided. It can have a frequency of up to
32 MHz. You select this mode by setting the HSEBYP and HSEON

register (RCC_CR). The external clock signal (square, sinus or triangle) with ~40-60% duty

cycle depending on the frequency (refer to the datasheet) has to drive the OSC_IN pin while
the OSC_OUT pin can be used a GPIO. See Figure 11.

bits in the Clock control

7.2.2 HSI clock

The HSI clock signal is generated from an internal 8 MHz RC Oscillator and can be used
directly as a system clock or divided by 2 to be used as PLL input.

The HSI RC oscillator has the advantage of providing a clock source at low cost (no external
components). It also has a faster startup time than the HSE crystal oscillator however, even
with calibration the frequency is less accurate than an external crystal oscillator or ceramic
resonator.

Calibration

RC oscillator frequencies can vary from one chip to another due to manufacturing process
variations, this is why each device is factory calibrated by ST for 1% accuracy at T

After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the Clock control

register (RCC_CR).

If the application is subject to voltage or temperature variations this may affect the RC
oscillator speed. You can trim the HSI frequency in the application using the HSITRIM[4:0]
bits in the Clock control register (RCC_CR).

The HSIRDY flag in the Clock control register (RCC_CR) indicates if the HSI RC is stable or
not. At startup, the HSI RC output clock is not released until this bit is set by hardware.

The HSI RC can be switched on and off using the HSION bit in the Clock control register

(RCC_CR).

The HSI signal can also be used as a backup source (Auxiliary clock) if the HSE crystal
oscillator fails. Refer to Section 7.2.7: Clock security system (CSS) on page 89.

=25°C.

A

Doc ID 018940 Rev 1 87/742

Reset and clock control (RCC) RM0091

7.2.3 PLL

The internal PLL can be used to multiply the HSI or HSE output clock frequency. Refer to

Figure 10 and Clock control register (RCC_CR).

The PLL configuration (selection of the input clock, and multiplication factor) must be done
before enabling the PLL. Once the PLL is enabled, these parameters cannot be changed.

To modify the PLL configuration, proceed as follows:

1. Disable the PLL by setting PLLON to 0.

2. Wait until PLLRDY is cleared. The PLL is now fully stopped.

3. Change the desired parameter.

4. Enable the PLL again by setting PLLON to 1.

An interrupt can be generated when the PLL is ready, if enabled in the Clock interrupt

register (RCC_CIR).

The PLL output frequency must be set in the range 16-48 MHz.

7.2.4 LSE clock

The LSE crystal is a 32.768 kHz Low Speed External crystal or ceramic resonator. It has the
advantage of providing a low-power but highly accurate clock source to the real-time clock
peripheral (RTC) for clock/calendar or other timing functions.

The LSE crystal is switched on and off using the LSEON bit in Backup domain control

register (RCC_BDCR). The crystal oscillator driving strength can be changed at runtime

using the LSEDRV[1:0] bits in the Backup domain control register (RCC_BDCR) to obtain
the best compromise between robustness and short start-up time on one side and low
power-consumption on the other.

The LSERDY flag in the Backup domain control register (RCC_BDCR) indicates whether
the LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not
released until this bit is set by hardware. An interrupt can be generated if enabled in the

Clock interrupt register (RCC_CIR).

External source (LSE bypass)

In this mode, an external clock source must be provided. It can have a frequency of up to
1 MHz. You select this mode by setting the LSEBYP and LSEON bits in the Backup domain

control register (RCC_BDCR). The external clock signal (square, sinus or triangle) with

~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin can be used as
GPIO. See Figure 11.

7.2.5 LSI clock

The LSI RC acts as an low-power clock source that can be kept running in Stop and
Standby mode for the independent window watchdog (IWWDG) and RTC. The clock
frequency is around 40 kHz (between 30 kHz and 60 kHz). For more details, refer to the
electrical characteristics section of the datasheets.

The LSI RC can be switched on and off using the LSION bit in the Control/status register

(RCC_CSR).

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RM0091 Reset and clock control (RCC)

The LSIRDY flag in the Control/status register (RCC_CSR) indicates if the LSI oscillator is
stable or not. At startup, the clock is not released until this bit is set by hardware. An
interrupt can be generated if enabled in the Clock interrupt register (RCC_CIR).

7.2.6 System clock (SYSCLK) selection

Three different clock sources can be used to drive the system clock (SYSCLK):

● HSI oscillator

● HSE oscillator

● PLL

After a system reset, the HSI oscillator is selected as system clock. When a clock source is
used directly or through the PLL as a system clock, it is not possible to stop it.

A switch from one clock source to another occurs only if the target clock source is ready
(clock stable after startup delay or PLL locked). If a clock source which is not yet ready is
selected, the switch will occur when the clock source becomes ready. Status bits in the

Clock control register (RCC_CR) indicate which clock(s) is (are) ready and which clock is

currently used as a system clock.

7.2.7 Clock security system (CSS)

Clock Security System can be activated by software. In this case, the clock detector is
enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.

If a failure is detected on the HSE clock, the HSE oscillator is automatically disabled, a clock
failure event is sent to the break input of the advanced-control timers (TIM1) and general­purpose timers (TIM15, TIM16 and TIM17) and an interrupt is generated to inform the
software about the failure (Clock Security System Interrupt CSSI), allowing the MCU to
perform rescue operations. The CSSI is linked to the Cortex-M0 NMI (Non-Maskable
Interrupt) exception vector.

Note: Once the CSS is enabled and if the HSE clock fails, the CSS interrupt occurs and an NMI is

automatically generated. The NMI will be executed indefinitely unless the CSS interrupt
pending bit is cleared. As a consequence, in the NMI ISR user must clear the CSS interrupt
by setting the CSSC bit in the Clock interrupt register (RCC_CIR).

If the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is
used as PLL input clock, and the PLL clock is used as system clock), a detected failure
causes a switch of the system clock to the HSI oscillator and the disabling of the HSE
oscillator. If the HSE clock (divided or not) is the clock entry of the PLL used as system clock
when the failure occurs, the PLL is disabled too.

7.2.8 ADC clock

The ADC clock is either the dedicated 14 MHz RC oscillator (HSI14) or PCLK divided by 2
or 4. When the ADC clock is derived from PCLK, it is in an opposite phase with PCLK. The
14 MHz RC oscillator can be configured by software either to be turned on/off (“auto-off
mode”) by the ADC interface or to be always enabled. The HSI 14 MHz RC oscillator cannot
be turned on by ADC interface when the APB clock is selected as kernel clock.

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Reset and clock control (RCC) RM0091

7.2.9 RTC clock

The RTCCLK clock source can be either the HSE/32, LSE or LSI clocks. This is selected by
programming the RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR).
This selection cannot be modified without resetting the Backup domain. The system must be
always configured in a way that the PCLK frequency is greater then or equal to the RTCCLK
frequency for proper operation of the RTC.

The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not.
Consequently:

● If LSE is selected as RTC clock:

– The RTC continues to work even if the V

V

supply is maintained.

BAT

● If LSI is selected as the RTC clock:

– The RTC state is not guaranteed if the V

● If the HSE clock divided by 32 is used as the RTC clock:

– The RTC state is not guaranteed if the V

supply is switched off, provided the

DD

supply is powered off.

DD

supply is powered off or if the internal

DD

voltage regulator is powered off (removing power from the 1.8 V domain).

7.2.10 Watchdog clock

If the Independent watchdog (IWWDG) is started by either hardware option or software
access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator
temporization, the clock is provided to the IWWDG.

7.2.11 Clock-out capability

The microcontroller clock output (MCO) capability allows the clock to be output onto the
external MCO pin. The configuration registers of the corresponding GPIO port must be
programmed in alternate function mode. One of 5 clock signals can be selected as the MCO
clock.

● HSI14

● SYSCLK

● HSI

● HSE

● PLL clock divided by 2

The selection is controlled by the MCO[2:0] bits of the Clock configuration register

(RCC_CFGR).

7.3 Low power modes

APB peripheral clocks and DMA clock can be disabled by software.

Sleep mode stops the CPU clock. The memory interface clocks (Flash and RAM interfaces)
can be stopped by software during sleep mode. The AHB to APB bridge clocks are disabled
by hardware during Sleep mode when all the clocks of the peripherals connected to them
are disabled.

Stop mode stops all the clocks in the core supply domain and disables the PLL and the HSI,
HSI14 and HSE oscillators.

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RM0091 Reset and clock control (RCC)

HDMI CEC, USART1 and I2C1 have the capability to enable the HSI oscillator even when
the MCU is in Stop mode (if HSI is selected as the clock source for that peripheral).

HDMI CEC and USART1 can also be driven by the LSE oscillator when the system is in
Stop mode (if LSE is selected as clock source for that peripheral) and the LSE oscillator is
enabled (LSEON) but they do not have the capability to turn on the LSE oscillator.

Standby mode stops all the clocks in the core supply domain and disables the PLL and the
HSI, HSI14 and HSE oscillators.

The CPU’s deepsleep mode can be overridden for debugging by setting the DBG_STOP or
DBG_STANDBY bits in the DBGMCU_CR register.

When waking up from deepsleep after an interrupt (Stop mode) or reset (Standby mode),
the HSI oscillator is selected as system clock.

If a Flash programming operation is on going, deepsleep mode entry is delayed until the
Flash interface access is finished. If an access to the APB domain is ongoing, deepsleep
mode entry is delayed until the APB access is finished.

Doc ID 018940 Rev 1 91/742

Reset and clock control (RCC) RM0091

7.4 RCC registers

Refer to Section 1.1 on page 34 for a list of abbreviations used in register descriptions.

7.4.1 Clock control register (RCC_CR)

Address offset: 0x00

Reset value: 0x0000 XX83 where X is undefined.

Access: no wait state, word, half-?word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res Res Res Res Res Res

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

HSICAL[7:0] HSITRIM[4:0] Res

rrrrrrr rrwrwrwrwrw rrw

PLL

PLLON Res Res Res Res

RDY

rrw rwrwrrw

Bits 31:26 Reserved, must be kept at reset value.

Bit 25 PLLRDY: PLL clock ready flag

Set by hardware to indicate that the PLL is locked.
0: PLL unlocked
1: PLL locked

Bit 24 PLLON: PLL enable

Set and cleared by software to enable PLL.
Cleared by hardware when entering Stop or Standby mode. This bit can not be reset if the

PLL clock is used as system clock or is selected to become the system clock.
0: PLL OFF
1: PLL ON

CSS ONHSE

BYP

HSE
RDY

HSI

RDY

HSE

ON

HSION

Bits 23:20 Reserved, must be kept at reset value.

Bit 19 CSSON: Clock security system enable

Set and cleared by software to enable the clock security system. When CSSON is set, the
clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by
hardware if a HSE clock failure is detected.

0: Clock detector OFF
1: Clock detector ON (Clock detector ON if the HSE oscillator is ready , OFF if not).

Bit 18 HSEBYP: HSE crystal oscillator bypass

Set and cleared by software to bypass the oscillator with an external clock. The external
clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit
can be written only if the HSE oscillator is disabled.
0: HSE crystal oscillator not bypassed
1: HSE crystal oscillator bypassed with external clock

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RM0091 Reset and clock control (RCC)

Bit 17 HSERDY: HSE clock ready flag

Set by hardware to indicate that the HSE oscillator is stable. This bit needs 6 cycles of the
HSE oscillator clock to fall down after HSEON reset.
0: HSE oscillator not ready
1: HSE oscillator ready

Bit 16 HSEON: HSE clock enable

Set and cleared by software.
Cleared by hardware to stop the HSE oscillator when entering Stop or Standby mode. This

bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.
0: HSE oscillator OFF
1: HSE oscillator ON

Bits 15:8 HSICAL[7:0]: HSI clock calibration

These bits are initialized automatically at startup.

Bits 7:3 HSITRIM[4:0]: HSI clock trimming

These bits provide an additional user-programmable trimming value that is added to the
HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature
that influence the frequency of the HSI.

The default value is 16, which, when added to the HSICAL value, should trim the HSI to 8
MHz ± 1%. The trimming step (F
steps.

Bit 2 Reserved, must be kept at reset value.

Bit 1 HSIRDY: HSI clock ready flag

Set by hardware to indicate that HSI oscillator is stable. After the HSION bit is cleared,
HSIRDY goes low after 6 HSI oscillator clock cycles.

0: HSI oscillator not ready
1: HSI oscillator ready

) is around 40 kHz between two consecutive HSICAL

hsitrim

Bit 0 HSION: HSI clock enable

Set and cleared by software.
Set by hardware to force the HSI oscillator ON when leaving Stop or Standby mode or in
case of failure of the HSE crystal oscillator used directly or indirectly as system clock. This

bit cannot be reset if the HSI is used directly or indirectly as system clock or is selected to
become the system clock.

0: HSI oscillator OFF
1: HSI oscillator ON

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Reset and clock control (RCC) RM0091

7.4.2 Clock configuration register (RCC_CFGR)

Address offset: 0x04

Reset value: 0x0000 0000

Access: 0 ≤ wait state ≤ 2, word, half-word and byte access

1 or 2 wait states inserted only if the access occurs during clock source switch.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res Res Res Res Res MCO[2:0] Res Res PLLMUL[3:0]

rw rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res

ADCP

Res Res Res PPRE[2:0] HPRE[3:0] SWS[1:0] SW[1:0]

RE

rw rw rw rw rw rw rw rw r r rw rw

PLL

XTPRE

Bits 31:27 Reserved, must be kept at reset value.

Bits 26:24 MCO: Microcontroller clock output

Set and cleared by software.
000: MCO output disabled, no clock on MCO
001: Reserved
010: Reserved
011: HSI14 clock selected
100: System clock (SYSCLK) selected
101: HSI clock selected
110: HSE clock selected
111: PLL clock divided by 2 selected

Note: This clock output may have some truncated cycles at startup or during MCO clock

source switching.

Bits 23:22 Reserved, must be kept at reset value.

PLL

SRC

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RM0091 Reset and clock control (RCC)

Bits 21:18 PLLMUL: PLL multiplication factor

These bits are written by software to define the PLL multiplication factor. These bits can be
written only when PLL is disabled.
Caution: The PLL output frequency must not exceed 48 MHz.
0000: PLL input clock x 2
0001: PLL input clock x 3
0010: PLL input clock x 4
0011: PLL input clock x 5
0100: PLL input clock x 6
0101: PLL input clock x 7
0110: PLL input clock x 8
0111: PLL input clock x 9
1000: PLL input clock x 10
1001: PLL input clock x 11
1010: PLL input clock x 12
1011: PLL input clock x 13
1100: PLL input clock x 14
1101: PLL input clock x 15
1110: PLL input clock x 16
1111: PLL input clock x 16

Bit 17 PLLXTPRE: HSE divider for PLL input clock

This bits is set and cleared by software to select the HSE division factor for the PLL. It can
be written only when the PLL is disabled.

Note: This bit is the same as the LSB of PREDIV in Clock configuration register 2

(RCC_CFGR2) (for compatibility with other STM32 products)

0000: HSE input to PLL not divided
0001: HSE input to PLL divided by 2

Bit 16 PLLSRC: PLL entry clock source

Set and cleared by software to select PLL clock source. This bit can be written only when
PLL is disabled.
0: HSI/2 selected as PLL input clock
1: HSE/PREDIV selected as PLL input clock (refer to Section 7.4.12: Clock configuration

register 2 (RCC_CFGR2) on page 113

Bit 15 Reserved, must be kept at reset value.

Bit 14 ADCPRE: ADC prescaler

Set and cleared by software to select the frequency of the clock to the ADC.
0: PCLK divided by 2
1: PCLK divided by 4

Bits 13:11 Reserved, must be kept at reset value.

Bits 10:8 PPRE: PCLK prescaler

Set and cleared by software to control the division factor of the APB clock (PCLK).
0xx: HCLK not divided
100: HCLK divided by 2
101: HCLK divided by 4
110: HCLK divided by 8
111: HCLK divided by 16

Doc ID 018940 Rev 1 95/742

Reset and clock control (RCC) RM0091

Bits 7:4 HPRE: HLCK prescaler

Set and cleared by software to control the division factor of the AHB clock.
0xxx: SYSCLK not divided
1000: SYSCLK divided by 2
1001: SYSCLK divided by 4
1010: SYSCLK divided by 8
1011: SYSCLK divided by 16
1100: SYSCLK divided by 64
1101: SYSCLK divided by 128
1110: SYSCLK divided by 256
1111: SYSCLK divided by 512

Bits 3:2 SWS: System clock switch status

Set and cleared by hardware to indicate which clock source is used as system clock.
00: HSI oscillator used as system clock
01: HSE oscillator used as system clock
10: PLL used as system clock
11: not applicable

Bits 1:0 SW: System clock switch

Set and cleared by software to select SYSCLK source.
Cleared by hardware to force HSI selection when leaving Stop and Standby mode or in case

of failure of the HSE oscillator used directly or indirectly as system clock (if the Clock
Security System is enabled).

00: HSI selected as system clock
01: HSE selected as system clock
10: PLL selected as system clock
11: not allowed

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RM0091 Reset and clock control (RCC)

7.4.3 Clock interrupt register (RCC_CIR)

Address offset: 0x08

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res Res Res Res Res Res Res Res CSSC Res

wwwwwww

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res Res

HSI14
RDYIE

PLL

HSE

HSI

RDYIE

RDYIE

RDYIE

rw rw rw rw rw rw r r r r r r r

LSE

RDYIE

LSI

RDYIE

CSSF Res

HSI14
RDYC

HSI14
RDYF

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 CSSC: Clock security system interrupt clear

This bit is set by software to clear the CSSF flag.
0: No effect
1: Clear CSSF flag

PLL

RDYC

PLL

RDYF

HSE

RDYC

HSE

RDYF

HSI

RDYC

HSI

RDYF

LSE

RDYC

LSE

RDYF

LSI

RDYC

LSI

RDYF

Bit 22 Reserved, must be kept at reset value.

Bit 21 HSI14RDYC: HSI 14 MHz Ready Interrupt Clear

This bit is set by software to clear the HSI14RDYF flag.
0: No effect
1: Clear HSI14RDYF flag

Bit 20 PLLRDYC: PLL ready interrupt clear

This bit is set by software to clear the PLLRDYF flag.
0: No effect
1: Clear PLLRDYF flag

Bit 19 HSERDYC: HSE ready interrupt clear

This bit is set by software to clear the HSERDYF flag.
0: No effect
1: Clear HSERDYF flag

Bit 18 HSIRDYC: HSI ready interrupt clear

This bit is set software to clear the HSIRDYF flag.
0: No effect
1: Clear HSIRDYF flag

Bit 17 LSERDYC: LSE ready interrupt clear

This bit is set by software to clear the LSERDYF flag.
0: No effect
1: LSERDYF cleared

Bit 16 LSIRDYC: LSI ready interrupt clear

This bit is set by software to clear the LSIRDYF flag.
0: No effect
1: LSIRDYF cleared

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Reset and clock control (RCC) RM0091

Bits 15:14 Reserved, must be kept at reset value.

Bit 13 HSI14RDYIE: HSI14 ready interrupt enable

Set and cleared by software to enable/disable interrupt caused by the HSI14 oscillator
stabilization.

0: HSI14 ready interrupt disabled
1: HSI14 ready interrupt enabled

Bit 12 PLLRDYIE: PLL ready interrupt enable

Set and cleared by software to enable/disable interrupt caused by PLL lock.
0: PLL lock interrupt disabled
1: PLL lock interrupt enabled

Bit 11 HSERDYIE: HSE ready interrupt enable

Set and cleared by software to enable/disable interrupt caused by the HSE oscillator
stabilization.

0: HSE ready interrupt disabled
1: HSE ready interrupt enabled

Bit 10 HSIRDYIE: HSI ready interrupt enable

Set and cleared by software to enable/disable interrupt caused by the HSI oscillator
stabilization.

0: HSI ready interrupt disabled
1: HSI ready interrupt enabled

Bit 9 LSERDYIE: LSE ready interrupt enable

Set and cleared by software to enable/disable interrupt caused by the LSE oscillator
stabilization.

0: LSE ready interrupt disabled
1: LSE ready interrupt enabled

Bit 8 LSIRDYIE: LSI ready interrupt enable

Set and cleared by software to enable/disable interrupt caused by the LSI oscillator
stabilization.
0: LSI ready interrupt disabled
1: LSI ready interrupt enabled

Bit 7 CSSF: Clock security system interrupt flag

Set by hardware when a failure is detected in the HSE oscillator.
Cleared by software setting the CSSC bit.
0: No clock security interrupt caused by HSE clock failure
1: Clock security interrupt caused by HSE clock failure

Bit 6 Reserved, must be kept at reset value.

Bit 5 HSI14RDYF: HSI14 ready interrupt flag

Set by hardware when the HSI14 becomes stable and HSI14RDYDIE is set in a response
to setting the HSI14ON bit (refer to Clock configuration register 2 (RCC_CFGR2). When
HSI14ON is not set but the HSI14 oscillator is enabled by the peripheral through a clock
request, this bit is not set and no interrupt is generated.
Cleared by software setting the HSI14RDYC bit.
0: No clock ready interrupt caused by the HSI14 oscillator
1: Clock ready interrupt caused by the HSI14 oscillator

98/742 Doc ID 018940 Rev 1

RM0091 Reset and clock control (RCC)

Bit 4 PLLRDYF: PLL ready interrupt flag

Set by hardware when the PLL locks and PLLRDYDIE is set.
Cleared by software setting the PLLRDYC bit.
0: No clock ready interrupt caused by PLL lock
1: Clock ready interrupt caused by PLL lock

Bit 3 HSERDYF: HSE ready interrupt flag

Set by hardware when the HSE clock becomes stable and HSERDYDIE is set.
Cleared by software setting the HSERDYC bit.
0: No clock ready interrupt caused by the HSE oscillator
1: Clock ready interrupt caused by the HSE oscillator

Bit 2 HSIRDYF: HSI ready interrupt flag

Set by hardware when the HSI clock becomes stable and HSIRDYDIE is set in a response
to setting the HSION (refer to Clock control register (RCC_CR)). When HSION is not set
but the HSI oscillator is enabled by the peripheral through a clock request, this bit is not set
and no interrupt is generated.
Cleared by software setting the HSIRDYC bit.
0: No clock ready interrupt caused by the HSI oscillator

1: Clock ready interrupt caused by the HSI oscillator

Bit 1 LSERDYF: LSE ready interrupt flag

Set by hardware when the LSE clock becomes stable and LSERDYDIE is set.
Cleared by software setting the LSERDYC bit.
0: No clock ready interrupt caused by the LSE oscillator
1: Clock ready interrupt caused by the LSE oscillator

Bit 0 LSIRDYF: LSI ready interrupt flag

Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set.
Cleared by software setting the LSIRDYC bit.
0: No clock ready interrupt caused by the LSI oscillator
1: Clock ready interrupt caused by the LSI oscillator

7.4.4 APB2 peripheral reset register (RCC_APB2RSTR)

Address offset: 0x0C

Reset value: 0x00000 0000

Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res Res Res Res Res Res Res Res Res

151413121110987 6 54321 0

Res

SPI1

USART1

Res

RST

rw rw rw rw rw

RST

TIM1

RST

Res

ADC

Res Res Res Res Res Res Res Res

RST

DBG MCU

RST

rw rw rw rw

Res Res Res

Bits 31:23 Reserved, must be kept at reset value.

Doc ID 018940 Rev 1 99/742

TIM17

RST

TIM16

RST

TIM15RST

SYSCFG

COMPRST

Reset and clock control (RCC) RM0091

Bits 22 DBGMCURST: Debug MCU reset

Set and cleared by software.
0: No effect
1: Resets Debug MCU

Bits 21:19 Reserved, must be kept at reset value.

Bit 18 TIM17RST: TIM17 timer reset

Set and cleared by software.
0: No effect
1: Reset TIM17 timer

Bit 17 TIM16RST: TIM16 timer reset

Set and cleared by software.
0: No effect
1: Reset TIM16 timer

Bit 16 TIM15RST: TIM15 timer reset

Set and cleared by software.
0: No effect
1: Reset TIM15 timer

Bit 15 Reserved, must be kept at reset value.

Bit 14 USART1RST: USART1 reset

Set and cleared by software.
0: No effect
1: Reset USART1

Bit 13 Reserved, must be kept at reset value.

Bit 12 SPI1RST: SPI1 reset

Set and cleared by software.
0: No effect
1: Reset SPI1

Bit 11 TIM1RST: TIM1 timer reset

Set and cleared by software.
0: No effect
1: Reset TIM1 timer

Bit 10 Reserved, must be kept at reset value.

Bit 9 ADCRST: ADC interface reset

Set and cleared by software.
0: No effect
1: Reset ADC interface

Bits 8:1 Reserved, must be kept at reset value.

Bit 0 SYSCFGCOMPRST: SYSCFG and COMP reset

Set and cleared by software.
0: No effect
1: Reset SYSCFG and COMP

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