STMicroelectronics STM32F050G6, STM32F050F6, STM32F050F4, STM32F050G4, STM32F050K4 User Manual
...
STM32F050x4 STM32F050x6
LQFP48 7x7 UFQFPN32 5x5
TSSOP20
UFQFPN28 4x4LQFP32 7x7
Low- and medium-density advanced ARM™-based 32-bit MCU with
up to 32 Kbytes Flash, timers, ADC and comm. interfaces
Datasheet production data
Features
■ Core: ARM 32-bit Cortex™-M0 CPU,
frequency up to 48 MHz
■ Memories
– 16 to 32 Kbytes of Flash memory
– 4 Kbytes of SRAM with HW parity checking
■ CRC calculation unit
■ Reset and supply management
– Voltage range: 2.0 V to 3.6 V
– Power-on/Power-down reset (POR/PDR)
– Programmable voltage detector (PVD)
– Low power modes: Sleep, Stop and
Standby
–V
■ Clock management
supply for RTC and backup registers
BAT
– 4 to 32 MHz crystal oscillator
– 32 kHz oscillator for RTC with calibration
– Internal 8 MHz RC with x6 PLL option
– Internal 40 kHz RC oscillator
■ Up to 39 fast I/Os
– All mappable on external interrupt vectors
– Up to 25 I/Os with 5 V tolerant capability
■ 5-channel DMA controller
■ 1 × 12-bit, 1.0 µs ADC (up to 10 channels)
– Conversion range: 0 to 3.6V
– Separate analog supply from 2.4 up to
3.6 V
■ Up to 9 timers
– 1 x 16-bit 7-channel advanced-control timer
for 6 channels PWM output, with deadtime
generation and emergency stop
– 1 x 32-bit and 1 x 16-bit timer, with up to 4
IC/OC, usable for IR control decoding
– 1 x 16-bit timer, with 2 IC/OC, 1 OCN,
deadtime generation and emergency stop
– 1 x 16-bit timer, with IC/OC and OCN,
deadtime generation, emergency stop and
modulator gate for IR control
– 1 x 16-bit timer with 1 IC/OC
– Independent and system watchdog timers
– SysTick timer: 24-bit downcounter
■ Calendar RTC with alarm and periodic wakeup
from Stop/Standby
■ Communication interfaces
– 1 x I
2
C interface; supporting Fast Mode
Plus (1 Mbit/s) with 20 mA current sink,
SMBus/PMBus, and wakeup from STOP
– 1 x USART supporting master synchronous
SPI and modem control; one with ISO7816
interface, LIN, IrDA capability auto baud
rate detection and wakeup feature
– 1 x SPI (18 Mbit/s) with 4 to 16
programmable bit frame, with I
2
S interface
multiplexed
■ Serial wire debug (SWD)
■ 96-bit unique ID
Table 1. Device summary
Reference Part number
STM32F050x4
STM32F050x6
STM32F050F4, STM32F050G4, STM32F050K4,
STM32F050C4
STM32F050F6, STM32F050G6, STM32F050K6,
STM32F050C6
September 2012 Doc ID 023079 Rev 3 1/98
This is information on a product in full production.
www.st.com
1
Contents STM32F050xx
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 ARM® CortexTM-M0 core with embedded Flash and SRAM . . . . . . . . . 12
3.2 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 13
3.5 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.2 Power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.7 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.8 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.9 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.9.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 16
3.9.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 16
3.10 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.10.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.10.2 Internal voltage reference (V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
REFINT
3.11 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.11.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.11.2 General-purpose timers (TIM2..3, TIM14..17) . . . . . . . . . . . . . . . . . . . . 18
3.11.3 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.11.4 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.11.5 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.12 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 20
3.13 Inter-integrated circuit interface (I
2
C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.14 Universal synchronous/asynchronous receiver transmitter (USART) . . . 21
3.15 Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I
2/98 Doc ID 023079 Rev 3
2
S) . 21
STM32F050xx Contents
3.16 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 40
6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 40
6.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.3.11 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.3.15 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.3.16 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.3.17 V
6.3.18 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
BAT
6.3.19 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Doc ID 023079 Rev 3 3/98
Contents STM32F050xx
7 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
7.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
7.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
7.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
7.2.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 93
8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4/98 Doc ID 023079 Rev 3
STM32F050xx List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. STM32F050xx family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 6. Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 8. Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 9. Alternate functions selected through GPIOA_AFR registers for port A . . . . . . . . . . . . . . . 30
Table 10. Alternate functions selected through GPIOB_AFR registers for port B . . . . . . . . . . . . . . . 31
Table 11. STM32F050x peripheral register boundary addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 12. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 13. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 14. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 15. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 16. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 17. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 18. Programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 19. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 20. Typical and maximum current consumption from V
Table 21. Typical and maximum current consumption from the V
Table 22. Typical and maximum V
Table 23. Typical and maximum V
consumption in Stop and Standby modes. . . . . . . . . . . . . . . . 45
DD
consumption in Stop and Standby modes. . . . . . . . . . . . . . . 46
DDA
Table 24. Typical and maximum current consumption from V
Table 25. Typical current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 26. Typical current consumption in Sleep mode, code running from Flash or RAM. . . . . . . . . 48
Table 27. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 28. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 29. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 30. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 31. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 32. LSE oscillator characteristics (f
= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
LSE
Table 33. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 34. HSI14 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 35. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 36. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 37. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 38. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 39. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 40. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 41. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 42. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 43. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 44. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 45. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 46. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 47. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
supply at VDD = 3.6 . . . . . . . . . . . 43
DD
BAT
supply . . . . . . . . . . . . . . . . . . 44
DDA
supply. . . . . . . . . . . . . . . . . . . . . . 46
Doc ID 023079 Rev 3 5/98
List of tables STM32F050xx
Table 48. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 49. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 50. R
max for f
AIN
= 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
ADC
Table 51. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 52. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 53. V
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
BAT
Table 54. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 55. IWDG min/max timeout period at 40 kHz (LSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 56. WWDG min-max timeout value @48 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 57. I
2
C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 58. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 59. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 60. I
2
S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 61. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . 83
Table 62. LQFP32 – 7 x 7 mm, 32-pin low-profile quad flat package mechanical data . . . . . . . . . . . 85
Table 63. UFQFPN32 – 5 x 5 mm, 32-lead ultra thin fine pitch quad flat no-lead package
mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 64. UFQFPN28 – 4 x 4 mm, 28-lead ultra thin fine pitch quad flat no-lead package
mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 65. TSSOP20 – 20-pin thin shrink small outline package mechanical data . . . . . . . . . . . . . . . 91
Table 66. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 67. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 68. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6/98 Doc ID 023079 Rev 3
STM32F050xx List of figures
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 3. LQFP48 48-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 4. LQFP32 32-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 5. UFQFPN32 32-pin package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 6. UFQFPN28 28-pin package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 7. TSSOP20 20-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 8. STM32F050xx memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 9. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 10. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 11. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 12. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 13. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 14. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 15. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 16. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 17. TC and TTa I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 18. TC and TTa I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 19. Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port. . . . . . . . . . . . . . . . . 67
Figure 20. Five volt tolerant (FT and FTf) I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . 67
Figure 21. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 22. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 23. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 24. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 25. I
Figure 26. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 27. SPI timing diagram - slave mode and CPHA = 1
Figure 28. SPI timing diagram - master mode
Figure 29. I2S slave timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 30. I2S master timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 31. LQFP48 - 7 x 7 mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 83
Figure 32. LQFP48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 33. LQFP32 - 7 x 7 mm, 32-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 85
Figure 34. LQFP32 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 35. UFQFPN32 - 5 x 5 mm, 32-lead ultra thin fine pitch quad flat no-lead package outline . . . 87
Figure 36. UFQFPN32 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 37. UFQFPN28 - 4 x 4 mm, 28-lead ultra thin fine pitch quad flat no-lead package outline . . . 89
Figure 38. UFQFPN28 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 39. TSSOP20 - 20-pin thin shrink small outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 40. TSSOP20 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
2
C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
(1)
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Doc ID 023079 Rev 3 7/98
Introduction STM32F050xx
1 Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F050x microcontrollers.
This STM32F050x4 and STM32F050x6 datasheet should be read in conjunction with the
STM32F0xxxx reference manual (RM0091). The reference manual is available from the
STMicroelectronics website www.st.com.
For information on the ARM Cortex™-M0 core, please refer to the Cortex™-M0 Technical
Reference Manual, available from the www.arm.com website at the following address:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0432c/index.html.
8/98 Doc ID 023079 Rev 3
STM32F050xx Description
2 Description
The STM32F050xx family incorporates the high-performance ARM Cortex™-M0 32-bit
RISC core operating at a 48 MHz maximum frequency, high-speed embedded memories
(Flash memory up to 32 Kbytes and SRAM up to 4 Kbytes), and an extensive range of
enhanced peripherals and I/Os. All devices offer standard communication interfaces (one
2
I
C, one SPI, one I2S, and one USART), one 12-bit ADC, up to five general-purpose 16-bit
timers, a 32-bit timer and an advanced-control PWM timer.
The STM32F050xx family operates in the -40 to +85 °C and -40 to +105 °C temperature
ranges, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving modes
allows the design of low-power applications.
The STM32F050xx family includes devices in five different packages ranging from 20 pins to
48 pins. Depending on the device chosen, different sets of peripherals are included. An
overview of the complete range of peripherals proposed in this family is provided.
These features make the STM32F050xx microcontroller family suitable for a wide range of
applications such as control application and user interfaces, handheld equipment, A/V
receivers and digital TV, PC peripherals, gaming and GPS platforms, industrial applications,
PLCs, inverters, printers, scanners, alarm systems, video intercoms, and HVACs.
Doc ID 023079 Rev 3 9/98
Description STM32F050xx
Table 2. STM32F050xx family device features and peripheral counts
Peripheral STM32F050Fx STM32F050Gx STM32F050Kx STM32F050Cx
Flash (Kbytes) 16 32 16 32 16 32 16 32
SRAM (Kbytes) 4 4 4 4
Timers
Comm.
interfaces
Advanced
control
General
purpose
SPI (I2S)
2
I
(1)
C1
1 (16-bit)
4 (16-bit)
1 (32-bit)
1
USART 1
12-bit synchronized
ADC
(number of channels)
GPIOs 13 21
1
(9 ext. + 3 int.)
1
(10 ext. + 3 int.)
25 (on LQFP32)
27 (on UFQFPN32)
39
Max. CPU frequency 48 MHz
Operating voltage 2.0 to 3.6 V
Operating temperature
Ambient operating temperature: -40 °C to 85 °C / -40 °C to 105 °C
Junction temperature: -40 °C to 125 °C
Packages TSSOP20 UFQFPN28
1. The SPI interface can be used either in SPI mode or in I2S audio mode.
LQFP32
UFQFPN32
LQFP48
10/98 Doc ID 023079 Rev 3
STM32F050xx Description
PA[ 15:0]
EXT.IT
NVIC
SWCLK
SWDAT
NRST
VDD=2 to 3.6V
39 AF
AHB
SRAM
WKUP
V
SS
GP DMA
5 channels
XTAL OSC
4-32 MHz
XTAL 32kHz
OSCIN - PF 0
OSCOUT - PF1
OSC32_OU T
OSC32_IN
AHBPCLK
HCLK
APBPCLK
FLASH
VOL T. RE G.
3.3 V T O1.8 V
V
DD18
POWER
RTC int erface
as AF
BusMatrix
32 bits
Int erfac e
4KB
RTC
CORTEX-M0 CPU
f
HCLK
= 48 MHz
obl
flash
Backup
reg
SCL,SDA,SMBal
I2C1
as AF
4channels
3 com pl . channels
BRK,ETR i nput as AF
4ch,ETRasAF
FCLK
Pow er
IWDG
@V
DD
@VSW
POR / PD R
SUPPLY
@V
DDA
V
DDA
V
BAT
=1.65 V to 3.6 V
RX,TX, CTS, RTS,
CK as A F
NVIC
SPI1/I2S1
Contr oll er
@V
DDA
SUPER VISION
PVD
Reset
Int
@V
DD
APB
POR
TAMPE R-RTC
RESET
& CLOCK
CONTROL
ADCCLK
PLL
(ALARM OUT)
Serial Wire
Debug
CECCLK
MISO/MCK,
PB[15:0]
PC[15:13]
PF[7:6, 1:0]
4ch,ETRasAF
1channelasAF
V
DD
32 KB
RC HS 14 MHz
USARTCLK
1 channel,
1compl,BRK asAF
1channel,
1compl,BRK as AF
controller
SRAM
SYSCFG IF
(20 mA f or FM+)
IR_OUT as AF
DBGMCU
AHB decoder
MS30246V2
TIMER 1
TIMER 2
TIMER 3
TIMER 14
TIMER 16
TIMER 17
USART1
GPIO port A
GPIO port B
GPIO port C
GPIO port F
12-bit ADC1
10
ADC_IN
V
DDA
Temp sensor
V
SSA
@V
DDA
IF
RC HS 8 MHz
RC LS
SCK/CK,
MOSI/SD,
NSS/WS as AF
WWDG
CRC
Figure 1. Block diagram
Doc ID 023079 Rev 3 11/98
Functional overview STM32F050xx
3 Functional overview
3.1 ARM® CortexTM-M0 core with embedded Flash and SRAM
The ARM Cortex™-M0 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex™-M0 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The STM32F050xx family has an embedded ARM core and is therefore compatible with all
ARM tools and software.
Figure 1 shows the general block diagram of the device family.
3.2 Memories
The device has the following features:
● 4 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states and featuring embedded parity checking with exception generation for fail-critical
applications.
● The non-volatile memory is divided into two arrays:
– 16 to 32 Kbytes of embedded Flash memory for programs and data
–Option bytes
The option bytes are used to write-protect the memory (with 4 KB granularity) and/or
readout-protect the whole memory with the following options:
– Level 0: no readout protection
– Level 1: memory readout protection, the Flash memory cannot be read from or
written to if either debug features are connected or boot in RAM is selected
– Level 2: chip readout protection, debug features (Cortex-M0 serial wire) and boot
in RAM selection disabled
3.3 Boot modes
At startup, the boot pin and boot selector option bit are used to select one of three boot
options:
● Boot from User Flash
● Boot from System Memory
● Boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1.
12/98 Doc ID 023079 Rev 3
STM32F050xx Functional overview
3.4 Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a CRC-32 (Ethernet) polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
3.5 Power management
3.5.1 Power supply schemes
● V
= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.
DD
Provided externally through V
● V
= 2.0 to 3.6 V: external analog power supply for ADC, Reset blocks, RCs and PLL
DDA
(minimum voltage to be applied to V
voltage level must be always greater or equal to the V
provided first.
● V
= 1.6 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup
BAT
registers (through power switch) when V
3.5.2 Power supply supervisors
The device has integrated power-on reset (POR) and power-down reset (PDR) circuits.
They are always active, and ensure proper operation above a threshold of 2 V. The device
remains in reset mode when the monitored supply voltage is below a specified threshold,
V
POR/PDR
● The POR monitors only the V
● The PDR monitors both the V
The device features an embedded programmable voltage detector (PVD) that monitors the
V
DD
when V
threshold. The interrupt service routine can then generate a warning message and/or put
the MCU into a safe state. The PVD is enabled by software.
, without the need for an external reset circuit.
that V
should arrive first and be greater than or equal to VDD.
DDA
supply supervisor can be disabled (by programming a dedicated Option bit) to reduce
the power consumption if the application design ensures that V
equal to V
DD
.
power supply and compares it to the V
drops below the V
DD
PVD
pins.
DD
is 2.4 V when the ADC is used). The V
DDA
is not present.
DD
supply voltage. During the startup phase it is required
DD
DD
and V
supply voltages, however the V
DDA
threshold. An interrupt can be generated
PVD
threshold and/or when VDD is higher than the V
voltage level and must be
DD
DDA
is higher than or
DDA
PVD
DDA
power
Doc ID 023079 Rev 3 13/98
Functional overview STM32F050xx
3.5.3 Voltage regulator
The regulator has three operating modes: main (MR), low power (LPR) and power down.
● MR is used in normal operating mode (Run)
● LPR can be used in Stop mode where the power demand is reduced
● Power down is used in Standby mode: the regulator output is in high impedance: the
kernel circuitry is powered down, inducing zero consumption (but the contents of the
registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby mode, providing high
impedance output.
3.5.4 Low-power modes
The STM32F050xx family supports three low-power modes to achieve the best compromise
between low power consumption, short startup time and available wakeup sources:
● Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
● Stop mode
Stop mode achieves very low power consumption while retaining the content of SRAM
and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the
HSE crystal oscillators are disabled. The voltage regulator can also be put either in
normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI lines. The EXTI line
source can be one of the 16 external lines, the PVD output, RTC alarm, I2C1 or
USART1.
The I2C1 and the USART1 can be configured to enable the HSI RC oscillator for
processing incoming data. If this is used, the voltage regulator should not be put in the
low-power mode but kept in normal mode.
● Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a
rising edge on the WKUP pins, or an RTC alarm occurs.
Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
14/98 Doc ID 023079 Rev 3
STM32F050xx Functional overview
3.6 Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the application to configure the frequency of the AHB and the APB
domains. The maximum frequency of the AHB and the APB domains is 48 MHz.
Figure 2. Clock tree
FLITFCLK
to Flash programming interface
HSI
SYSCLK
to I2C1
to I2S1
OSC_OUT
OSC_IN
OSC32_IN
OSC32_OUT
MCO
8 MHz
HSI RC
PLLSRC
/1,2,
3,..16
4-32 MHz
HSE OSC
LSE OSC
32.768kHz
LSI RC
40kHz
Main clock
output
HSI
PLLMUL
PLL
x2,x3,..
x16
/32
LSE
MCO
/2
HSI
PLLCLK
HSE
CSS
RTCCLK
RTCSEL[1:0]
LSI
/2
PLLCLK
HSI
HSI14
HSE
SYSCLK
SW
prescaler
/1,2,..512
SYSCLK
14 MHz
HSI14 RC
AHB
AHB
HSI14
to RTC
to IWWDG
IWWDGCLK
HCLK
/8
APB
prescaler
/1,2,4,8,16
If (APB1 prescaler
=1) x1 else x2
ADC
Prescaler
/2,4
PCLK
SYSCLK
HSI
LSE
to AHB bus, core,
memory and DMA
to cortex System timer
FHCLK Cortex free running clock
PCLK
to APB peripherals
to TIM1,2,3,
14,16,17
to ADC
14 MHz max
to USART1
MS30247V1
Doc ID 023079 Rev 3 15/98
Functional overview STM32F050xx
3.7 General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions.
The I/O configuration can be locked if needed following a specific sequence in order to avoid
spurious writing to the I/Os registers.
3.8 Direct memory access controller (DMA)
The 5-channel general-purpose DMAs manage memory-to-memory, peripheral-to-memory
and memory-to-peripheral transfers.
The DMA supports circular buffer management, removing the need for user code
intervention when the controller reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
DMA can be used with the main peripherals: SPI, I2S, I2C, USART, all TIMx timers (except
TIM14) and ADC.
3.9 Interrupts and events
3.9.1 Nested vectored interrupt controller (NVIC)
The STM32F050xx family embeds a nested vectored interrupt controller able to handle up
to 32 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M0) and 4
priority levels.
● Closely coupled NVIC gives low latency interrupt processing
● Interrupt entry vector table address passed directly to the core
● Closely coupled NVIC core interface
● Allows early processing of interrupts
● Processing of late arriving higher priority interrupts
● Support for tail-chaining
● Processor state automatically saved
● Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
3.9.2 Extended interrupt/event controller (EXTI)
The external interrupt/event controller consists of 24 edge detector lines used to generate
interrupt/event requests and wake-up the system. Each line can be independently
configured to select the trigger event (rising edge, falling edge, both) and can be masked
independently. A pending register maintains the status of the interrupt requests. The EXTI
can detect an external line with a pulse width shorter than the internal clock period. Up to 39
GPIOs can be connected to the 16 external interrupt lines.
16/98 Doc ID 023079 Rev 3
STM32F050xx Functional overview
3.10 Analog to digital converter (ADC)
The 12-bit analog to digital converter has up to 16 external and 3 internal (temperature
sensor, voltage reference, VBAT voltage measurement) channels and performs conversions
in single-shot or scan modes. In scan mode, automatic conversion is performed on a
selected group of analog inputs.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
3.10.1 Temperature sensor
The temperature sensor (TS) generates a voltage V
that varies linearly with
SENSE
temperature.
The temperature sensor is internally connected to the ADC_IN16 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy
of the temperature measurement. As the offset of the temperature sensor varies from chip
to chip due to process variation, the uncalibrated internal temperature sensor is suitable for
applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
Table 3. Temperature sensor calibration values
Calibration value name Description Memory address
TS ADC raw data acquired at
TS_CAL1
TS_CAL2
temperature of 30 °C,
V
= 3.3 V
DDA
TS ADC raw data acquired at
temperature of 110 °C
V
= 3.3 V
DDA
0x1FFF F7B8 - 0x1FFF F7B9
0x1FFF F7C2 - 0x1FFF F7C3
3.10.2 Internal voltage reference (V
The internal voltage reference (V
ADC. V
of V
REFINT
is internally connected to the ADC_IN17 input channel. The precise voltage
REFINT
is individually measured for each part by ST during production test and stored in
the system memory area. It is accessible in read-only mode.
Table 4. Temperature sensor calibration values
Calibration value name Description Memory address
VREFINT_CAL
REFINT
Raw data acquired at
temperature of 30 °C
V
DDA
Doc ID 023079 Rev 3 17/98
REFINT
)
) provides a stable (bandgap) voltage output for the
0x1FFF F7BA - 0x1FFF F7BB
= 3.3 V
Functional overview STM32F050xx
3.11 Timers and watchdogs
The STM32F050xx family devices include up to six general-purpose timers, one basic timer
and an advanced control timer.
Ta bl e 5 compares the features of the advanced-control, general-purpose and basic timers.
Table 5. Timer feature comparison
Timer
type
Advanced
control
General
purpose
Timer
TIM1 16-bit
TIM2 32-bit
TIM3 16-bit
TIM14 16-bit Up
TIM16,
TIM17
Counter
resolution
16-bit Up
Counter
type
Up, down,
up/down
Up, down,
up/down
Up, down,
up/down
Prescaler
factor
Any integer
between 1
and 65536
Any integer
between 1
and 65536
Any integer
between 1
and 65536
Any integer
between 1
and 65536
Any integer
between 1
and 65536
3.11.1 Advanced-control timer (TIM1)
The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6
channels. It has complementary PWM outputs with programmable inserted dead times. It
can also be seen as a complete general-purpose timer. The 4 independent channels can be
used for:
● Input capture
● Output compare
● PWM generation (edge or center-aligned modes)
● One-pulse mode output
DMA request
generation
Ye s 4 Ye s
Ye s 4 N o
Ye s 4 N o
No 1 No
Ye s 1 Ye s
Capture/compare
channels
Complementary
outputs
If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If
configured as the 16-bit PWM generator, it has full modulation capability (0-100%).
The counter can be frozen in debug mode.
Many features are shared with those of the standard timers which have the same
architecture. The advanced control timer can therefore work together with the other timers
via the Timer Link feature for synchronization or event chaining.
3.11.2 General-purpose timers (TIM2..3, TIM14..17)
There are six synchronizable general-purpose timers embedded in the STM32F050xx
devices (see Ta bl e 5 for differences). Each general-purpose timer can be used to generate
PWM outputs, or as simple time base.
18/98 Doc ID 023079 Rev 3
STM32F050xx Functional overview
TIM2, TIM3
STM32F050xx devices feature two synchronizable 4-channel general-purpose timers. TIM2
is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TIM3 is based on a
16-bit auto-reload up/downcounter and a 16-bit prescaler. They feature 4 independent
channels each for input capture/output compare, PWM or one-pulse mode output. This
gives up to 12 input captures/output compares/PWMs on the largest packages.
The TIM2 and TIM3 general-purpose timers can work together or with the TIM1 advanced-
control timer via the Timer Link feature for synchronization or event chaining.
TIM2 and TIM3 both have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
Their counters can be frozen in debug mode.
TIM14
This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM14 features one single channel for input capture/output compare, PWM or one-pulse
mode output.
Its counter can be frozen in debug mode.
TIM16 and TIM17
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM16 and TIM17 feature one single channel for input capture/output compare, PWM or
one-pulse mode output.
The TIM16 and TIM17 timers can work together via the Timer Link feature for
synchronization or event chaining.
TIM16, and TIM17 have a complementary output with dead-time generation and
independent DMA request generation
Their counters can be frozen in debug mode.
3.11.3 Independent watchdog (IWDG)
The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with user-
defined refresh window. It is clocked from an independent 40 kHz internal RC and as it
operates independently from the main clock, it can operate in Stop and Standby modes. It
can be used either as a watchdog to reset the device when a problem occurs, or as a free
running timer for application timeout management. It is hardware or software configurable
through the option bytes. The counter can be frozen in debug mode.
3.11.4 System window watchdog (WWDG)
The system window watchdog is based on a 7-bit downcounter that can be set as free
running. It can be used as a watchdog to reset the device when a problem occurs. It is
clocked from the APB clock (PCLK). It has an early warning interrupt capability and the
counter can be frozen in debug mode.
Doc ID 023079 Rev 3 19/98
Functional overview STM32F050xx
3.11.5 SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
● A 24-bit down counter
● Autoreload capability
● Maskable system interrupt generation when the counter reaches 0.
● Programmable clock source (HCLK or HCLK/8)
3.12 Real-time clock (RTC) and backup registers
The RTC and the 5 backup registers are supplied through a switch that takes power either
on V
registers used to store 20 bytes of user application data when V
They are not reset by a system or power reset, or when the device wakes up from Standby
mode.
The RTC is an independent BCD timer/counter. Its main features are the following:
● Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
● Automatically correction for 28, 29 (leap year), 30, and 31 day of the month.
● Programmable alarm with wake up from Stop and Standby mode capability.
● On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
● Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal
● 2 anti-tamper detection pins with programmable filter. The MCU can be woken up from
● Timestamp feature which can be used to save the calendar content. This function can
supply when present or through the V
DD
pin. The backup registers are five 32-bit
BAT
power is not present.
DD
month, year, in BCD (binary-coded decimal) format.
synchronize it with a master clock.
inaccuracy.
Stop and Standby modes on tamper event detection.
triggered by an event on the timestamp pin, or by a tamper event. The MCU can be
woken up from Stop and Standby modes on timestamp event detection.
The RTC clock sources can be:
● A 32.768 kHz external crystal
● A resonator or oscillator
● The internal low-power RC oscillator (typical frequency of 40 kHz)
● The high-speed external clock divided by 32.
3.13 Inter-integrated circuit interface (I2C)
The I2C interface (I2C1) can operate in multimaster or slave mode. It can support Standard
mode (up to 100 kbit/s), Fast mode (up to 400 kbit/s) and Fast Mode Plus (up to 1 Mbit/s)
with 20 mA output drive.
It supports 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses,
1 with configurable mask). It also includes programmable analog and digital noise filters.
20/98 Doc ID 023079 Rev 3
STM32F050xx Functional overview
Table 6. Comparison of I2C analog and digital filters
Analog filter Digital filter
Pulse width of
suppressed spikes
Benefits Available in Stop mode
Drawbacks
50 ns
Variations depending on
temperature, voltage, process
Programmable length from 1 to 15
I2C peripheral clocks
1. Extra filtering capability vs.
standard requirements.
2. Stable length
Wakeup from Stop on address
match is not available when digital
filter is enabled.
In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP
capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts
verifications and ALERT protocol management. I2C1 also has a clock domain independent
from the CPU clock, allowing the I2C1 to wake up the MCU from Stop mode on address
match.
The I2C interface can be served by the DMA controller.
3.14 Universal synchronous/asynchronous receiver transmitter
(USART)
The device embeds an universal synchronous/asynchronous receiver transmitters
(USART1), which communicates at speeds of up to 6 Mbit/s.
It provides hardware management of the CTS, RTS and RS485 DE signals, multiprocessor
communication mode, master synchronous communication and single-wire half-duplex
communication mode. It also supports SmartCard communication (ISO 7816), IrDA SIR
ENDEC, LIN Master/Slave capability, auto baud rate feature and has a clock domain
independent from the CPU clock, allowing it to wake up the MCU from Stop mode.
The USART interface can be served by the DMA controller.
3.15 Serial peripheral interface (SPI)/Inter-integrated sound
interfaces (I
The SPI (SPI1) is able to communicate up to 18 Mbits/s in slave and master modes in full-
duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame size is configurable from 4 bits to 16 bits.
One standard I
can operate as master or slave at half-duplex communication mode. It can be configured to
transfer 16 and 24 or 32 bits with16-bit or 32-bit data resolution and synchronized by a
specific signal. Audio sampling frequency from 8 kHz up to 192 kHz can be set by 8-bit
programmable linear prescaler. When operating in master mode it can output a clock for an
external audio component at 256 times the sampling frequency.
2
S)
2
S interface (multiplexed with SPI1) supporting four different audio standards
Doc ID 023079 Rev 3 21/98
Functional overview STM32F050xx
3.16 Serial wire debug port (SW-DP)
An ARM SW-DP interface is provided to allow a serial wire debugging tool to be connected
to the MCU.
22/98 Doc ID 023079 Rev 3
STM32F050xx Pinouts and pin description
44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
12
13 14 15 16 17 18
19 20 21 22
1
2
3
4
5
6
7
8
9
10
11
48 47 46 45
LQFP48
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB10
PB11
VSS
VDD
PF7
PF6
PA13
PA12
PA11
PA10
PA9
PA8
PB15
PB14
PB13
PB12
VBAT
NRST
VSSA
VDDA
PA0
PA1
PA2
VDD
VSS
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PA15
PA14
MS19842V1
PC13
PC14/OSC32_IN
PF0/OSC_IN
PF1/OSC_OUT
PC15/OSC32_OUT
MS30475V1
32 31 30 29 28 27 26 25
24
23
22
20
19
18
17
8
910111213
14 15 16
1
2
3
4
5
6
7
LQFP32
PA3
PA4
PA5
PA6
PA7
PB0
PB1
VSS
PA14
PA13
PA12
PA11
PA10
PA9
PA8
VDD
NRST
VDDA
PA0
PA1
PA2
VSS
BOOT0
PB7
PB6
PB5
PB4
PB3
PA15
PF0/OSC_IN
PF1/OSC_OUT
VDD
21
4 Pinouts and pin description
Figure 3. LQFP48 48-pin package pinout
Figure 4. LQFP32 32-pin package pinout
1. PB2 and PB8 should be treated as unconnected pins on the LQFP32 package (even when they are not
available on the package, they are not forced to a defined level by hardware).
Doc ID 023079 Rev 3 23/98
Pinouts and pin description STM32F050xx
PA5
PA6
PA7
PA7
PA2
PA3
PA4
VDDA
BOOT0
PF0/OSC_IN
NRST
VDD
VDD
VSS
PB1
PA8
PA10
PA9
PB4
PB3
PA15
PA8
PB 7
PB6
PB5
2
1
3
4
5
6
7
981011121314
20
21
19
18
17
16
15
2728 26 25 24 23 22
PF1/OSC_OUT
MS30967V1
PA0
PA1
2
1
3
4
5
67 8
9
PA0
PF0/OSC_IN
PA1
BOOT0
PA10
PA9
VDD
PB5
PA6
PA7
PB1
VSS
PA2
PA3
10
PA 4
PA13
MS30968V1
PF1/OSC_OUT
NRST
VDDA
PA13
20 19 18 17 16
15
14
13
12
11
Figure 5. UFQFPN32 32-pin package pinout
PB4
PB0
PB3
PB1
PA15
24
23
22
21
20
19
18
17
PB2
PA14
PA13
PA12
PA11
PA10
PA9
PA8
VDD
MS19844V2
VDD
PF0/OSC_IN
PF1/OSC_OUT
NRST
VDDA
PA0
PA1
PA2
PB7
VSS
VSSA
1291011
PA6
PA5
PB5
PB6
28
13 1 4 15 16
PA7
BOOT0
PB8
31 30 29
32 27 26 25
1
0
2
3
4
5
6
7
8
PA3
PA4
Figure 6. UFQFPN28 28-pin package pinout
Figure 7. TSSOP20 20-pin package pinout
24/98 Doc ID 023079 Rev 3
STM32F050xx Pinouts and pin description
Table 7. Legend/abbreviations used in the pinout table
Name Abbreviation Definition
Pin name
Pin type
I/O structure
Pin
functions
Notes
Alternate
functions
Additional
functions
Unless otherwise specified in brackets below the pin name, the pin function
during and after reset is the same as the actual pin name
S Supply pin
I Input only pin
I/O Input / output pin
FT 5 V tolerant I/O
FTf 5 V tolerant I/O, FM+ capable
TTa 3.3 V tolerant I/O directly connected to ADC
TC Standard 3.3V I/O
B Dedicated BOOT0 pin
RST Bidirectional reset pin with embedded weak pull-up resistor
Unless otherwise specified by a note, all I/Os are set as floating inputs during
and after reset
Functions selected through GPIOx_AFR registers
Functions directly selected/enabled through peripheral registers
Doc ID 023079 Rev 3 25/98
Pinouts and pin description STM32F050xx
Table 8. Pin definitions
Pin number
Pin functions
Pin name
(function after
reset)
Pin type
I/O structure
Notes
Alternate
functions
LQFP48
LQFP32
UFQFPN32
UFQFPN28
TSSOP20
1 - - - - VBAT S Backup power supply
2-- - - PC13 I/OTC
(1)(2)
PC14-
3-- - -
OSC32_IN
I/O TC
(1)(2)
(PC14)
PC15-
4-- - -
OSC32_OUT
I/O TC
(1)(2)
(PC15)
52222
PF0-OSC_IN
(PF0)
I/O FT OSC_IN
Additional
functions
RTC_TAMP1,
RTC_TS,
RTC_OUT,
WKUP2
OSC32_IN
OSC32_OUT
63333
74444 NRST I/ORST
PF1-OSC_OUT
(PF1)
I/O FT OSC_OUT
Device reset input / internal reset
output (active low)
8 - 0 - - VSSA S Analog ground
9 5 5 5 5 VDDA S Analog power supply
ADC_IN0,
10 6 6 6 6 PA0 I/O TTa TIM2_CH1_ETR
RTC_TAMP2,
WKUP1
117777 PA1 I/OTTa
TIM2_CH2,
EVENTOUT
ADC_IN1
12 8 8 8 8 PA2 I/O TTa TIM2_CH3 ADC_IN2
13 9 9 9 9 PA3 I/O TTa TIM2_CH4 ADC_IN3
14 10 10 10 10 PA4 I/O TTa
SPI1_NSS/I2S1_
WS, TIM14_CH1
ADC_IN4
SPI1_SCK/I2S1_
15 11 11 11 11 PA5 I/O TTa
CK,
ADC_IN5
TIM2_CH1_ETR
26/98 Doc ID 023079 Rev 3
STM32F050xx Pinouts and pin description
Table 8. Pin definitions (continued)
Pin number
Pin functions
Pin name
(function after
reset)
LQFP48
LQFP32
UFQFPN32
16 12 12 12 12 PA6 I/O TTa
17 13 13 13 13 PA7 I/O TTa
TSSOP20
UFQFPN28
Pin type
I/O structure
Notes
Alternate
functions
SPI1_MISO/I2S1_
MCK, TIM3_CH1,
TIM1_BKIN,
TIM16_CH1,
EVENTOUT
SPI1_MOSI/I2S1_
SD, TIM3_CH2,
TIM14_CH1,
TIM1_CH1N,
TIM17_CH1,
EVENTOUT
Additional
functions
ADC_IN6
ADC_IN7
TIM3_CH3,
18 14 14 14 14 PB0 I/O TTa
19 15 15 15 15 PB1 I/O TTa
20 - 16 - - PB2 I/O FT
21---- PB10 I/OFT TIM2_CH3
22---- PB11 I/OFT
23 16 0 16 15 VSS S Ground
24 17 17 17 16 VDD S Digital power supply
25---- PB12 I/OFT
26 - - - - PB13 I/O FT TIM1_CH1N,
27---- PB14 I/OFT TIM1_CH2N
28 - - - - PB15 I/O FT TIM1_CH3N, RTC_REFIN
29 18 18 18 - PA8 I/O FT
30 19 19 19 17 PA9 I/O FT
31 20 20 20 18 PA10 I/O FT
(3)
TIM1_CH2N,
EVENTOUT
TIM3_CH4,
TIM14_CH1,
TIM1_CH3N
TIM2_CH4,
EVENTOUT
TIM1_BKIN,
EVENTOUT
USART1_CK,
TIM1_CH1,
EVENTOUT, MCO
USART1_TX,
TIM1_CH2
USART1_RX,
TIM1_CH3,
TIM17_BKIN
ADC_IN8
ADC_IN9
Doc ID 023079 Rev 3 27/98
Pinouts and pin description STM32F050xx
Table 8. Pin definitions (continued)
Pin number
Pin functions
Pin name
(function after
LQFP48
LQFP32
UFQFPN32
UFQFPN28
reset)
TSSOP20
Pin type
32 21 21 - - PA11 I/O FT
33 22 22 - - PA12 I/O FT
I/O structure
Notes
Alternate
functions
USART1_CTS,
TIM1_CH4,
EVENTOUT
USART1_RTS,
TIM1_ETR,
EVENTOUT
Additional
functions
34 23 23 21 19
PA 13
(SWDAT)
I/O FT
(4)
IR_OUT, SWDAT
35---- PF6 I/OFT
36---- PF7 I/OFT
37 24 24 22 20
PA 14
(SWCLK)
I/O FT
(4)
SWCLK
SPI1_NSS/I2S1_
38 25 25 23 - PA15 I/O FT
WS,
TIM2_CH_ETR,
EVENTOUT
SPI1_SCK/I2S1_
39 26 26 - - PB3 I/O FT
CK, TIM2_CH2,
EVENTOUT
SPI1_MISO/I2S1_
40 27 27 - - PB4 I/O FT
MCK, TIM3_CH1,
EVENTOUT
SPI1_MOSI/I2S1_
41 28 28 24 - PB5 I/O FT
SD, I2C1_SMBA,
TIM16_BKIN,
TIM3_CH2
I2C1_SCL,
42 29 29 25 - PB6 I/O FTf
USART1_TX,
TIM16_CH1N
I2C1_SDA,
43 30 30 26 - PB7 I/O FTf
USART1_RX,
TIM17_CH1N
44 31 31 27 1 BOOT0 I B Boot memory selection
45 - 32 - - PB8 I/O FTf
28/98 Doc ID 023079 Rev 3
(3)
I2C1_SCL,
TIM16_CH1
STM32F050xx Pinouts and pin description
Table 8. Pin definitions (continued)
Pin number
Pin functions
Pin name
(function after
LQFP48
LQFP32
UFQFPN32
UFQFPN28
reset)
TSSOP20
Pin type
46---- PB9 I/OFTf
47 32 0 28 - VSS S Ground
48 1 1 1 - VDD S Digital power supply
1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIO PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF
- these GPIOs must not be used as a current sources (e.g. to drive an LED).
2. After the first backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the
content of the Backup registers which is not reset by the main reset. For details on how to manage these GPIOs, refer to
the Battery backup domain and BKP register description sections in the STM32F05xx reference manual.
3. PB2 and PB8 should be treated as unconnected pins on the LQFP32 package (even when they are not available on the
package, they are not forced to a defined level by hardware).
4. After reset, these pins are configured as SWDAT and SWCLK alternate functions, and the internal pull-up on SWDAT pin
and internal pull-down on SWCLK pin are activated.
I/O structure
Notes
Alternate
functions
I2C1_SDA,
IR_OUT,
TIM17_CH1,
EVENTOUT
Additional
functions
Doc ID 023079 Rev 3 29/98
30/98 Doc ID 023079 Rev 3
Table 9. Alternate functions selected through GPIOA_AFR registers for port A
Pin name AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
Pinouts and pin description STM32F050xx
PA 0
TIM2_CH1_
ETR
PA1 EVENTOUT TIM2_CH2
PA2 TIM2_CH3
PA3 TIM2_CH4
PA 4
PA 5
PA 6
PA 7
SPI1_NSS/
I2S1_WS
SPI1_SCK/
I2S1_CK
SPI1_MISO/
I2S1_MCK
SPI1_MOSI/
I2S1_SD
CEC
TIM2_CH1_
ETR
TIM3_CH1 TIM1_BKIN TIM16_CH1 EVENTOUT
TIM3_CH2 TIM1_CH1N TIM14_CH1 TIM17_CH1 EVENTOUT
PA8 MCO USART1_CK TIM1_CH1 EVENTOUT
PA9 USART1_TX TIM1_CH2
PA10 TIM17_BKIN USART1_RX TIM1_CH3
PA11 EVENTOUT USART1_CTS TIM1_CH4
PA12 EVENTOUT USART1_RTS TIM1_ETR
PA 13 S W DAT I R_ O U T
TIM14_CH1
PA 14 S W CL K
PA 15
SPI1_NSS/
I2S1_WS
TIM2_CH1_
ETR
EVENTOUT
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