STMicroelectronics STM32F030F4, STM32F030C6, STM32F030K6, STM32F030C8, STM32F030R8 Datasheet
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STM32F030x4/x6/x8/xC
Errata sheet
STM32F030x4/x6/x8/xC device errata
Applicability
This document applies to the part numbers of STM32F030x4/x6/x8/xC devices and the device variants as stated in this page.
It gives a summary and a description of the device errata, with respect to the device datasheet and reference manual RM0360.
Deviation of the real device behavior from the intended device behavior is considered to be a device limitation. Deviation of the
description in the reference manual or the datasheet from the intended device behavior is considered to be a documentation
erratum. The term “errata” applies both to limitations and documentation errata.
Table 1. Device summary
Reference Part numbers
STM32F030x4 STM32F030F4
STM32F030x6 STM32F030C6, STM32F030K6
STM32F030x8 STM32F030C8, STM32F030R8
STM32F030xC STM32F030CC, STM32F030RC
Table 2. Device variants
Reference
STM32F030x4
STM32F030x6 A or 1 0x1000
STM32F030x8 B, 1, or 2 0x2000
STM32F030xC A 0x1000
1. Refer to the device datasheet for how to identify this code on different types of package.
2. REV_ID[15:0] bitfield of DBGMCU_IDCODE register.
Device marking
A or 1 0x1000
Silicon revision codes
(1)
REV_ID
(2)
ES0219 - Rev 5 - October 2020
For further information contact your local STMicroelectronics sales office.
www.st.com
1 Summary of device errata
The following table gives a quick reference to the STM32F030x4/x6/x8/xC device limitations and their status:
A = limitation present, workaround available
N = limitation present, no workaround available
P = limitation present, partial workaround available
“-” = limitation absent
Applicability of a workaround may depend on specific conditions of target application. Adoption of a workaround
may cause restrictions to target application. Workaround for a limitation is deemed partial if it only reduces the
rate of occurrence and/or consequences of the limitation, or if it is fully effective for only a subset of instances on
the device or in only a subset of operating modes, of the function concerned.
Table 3. Summary of device limitations
STM32F030x4/x6/x8/xC
Summary of device errata
Status
Function Section Limitation
System
GPIO
DMA 2.4.1
ADC
TIM
IWDG
2.2.1
2.2.2 RDP Level 1 issue P P P P
2.3.1
2.3.2
2.5.1
2.5.2
2.5.3 ADEN bit cannot be set immediately after the ADC calibration A A A A
2.6.1
2.6.3 Consecutive compare event missed in specific conditions N N N N
2.6.4 Output compare clear not working with external counter reset P P P P
2.7.1 RVU flag not reset in Stop A A A A
2.7.2 PVU flag not reset in Stop A A A A
2.7.3 WVU flag not reset in Stop A A A A
2.7.4 RVU flag not cleared at low APB clock frequency A A A A
Wakeup sequence from Standby mode when using more than
one wakeup source
Extra consumption on GPIOs PB0 / PC0 to PC5 on 20/48-pin
devices
GPIOx locking mechanism not working properly for
GPIOx_OTYPER register
DMA disable failure and error flag omission upon simultaneous
transfer error and global flag clear
ADCAL bit is not cleared when successive calibrations are
performed and system clock frequency is considerably higher
than the ADC clock frequency
Overrun flag is not set if EOC reset coincides with new
conversion end
PWM re-enabled in automatic output enable mode despite of
system break
STM32F030x4 Rev. A, 1
STM32F030x6 Rev. A, 1
STM32F030x8 Rev. B, 1, 2
A A A A
A - A -
P P P P
A A A A
A A A A
P P P P
P P P P
STM32F030xC Rev. A
ES0219 - Rev 5
page 2/29
Function Section Limitation
STM32F030x4/x6/x8/xC
Summary of device errata
Status
IWDG
RTC and
TAMP
I2C
USART
SPI
STM32F030x4 Rev. A, 1
STM32F030x6 Rev. A, 1
STM32F030x8 Rev. B, 1, 2
2.7.5 PVU flag not cleared at low APB clock frequency
2.7.6 WVU flag not cleared at low APB clock frequency A A A A
2.8.1 Spurious tamper detection when disabling the tamper channel N N N N
2.8.2 RTC calendar registers are not locked properly A A A A
2.8.3 RTC interrupt can be masked by another RTC interrupt A A A A
2.8.4
2.8.5
2.8.6 A tamper event preceding the tamper detect enable not detected A A A A
2.9.1
2.9.2
2.9.3
2.9.5
2.9.6 Spurious bus error detection in master mode A A A A
2.9.7 Last-received byte loss in reload mode P P P P
2.9.8 Spurious master transfer upon own slave address match P P P P
2.9.9 OVR flag not set in underrun condition N N N N
2.9.10 Transmission stalled after first byte transfer A A A A
2.10.1
2.10.2
2.10.3
2.10.4 Break request preventing TC flag from being set A A A A
2.10.5 RTS is active while RE = 0 or UE = 0 A A A A
2.10.6 Receiver timeout counter wrong start in two-stop-bit configuration - - - A
2.10.7 Anticipated end-of-transmission signaling in SPI slave mode A A A A
2.10.8 Data corruption due to noisy receive line N N N N
2.11.1 BSY bit may stay high when SPI is disabled A A A A
Calendar initialization may fail in case of consecutive INIT mode
entry
Alarm flag may be repeatedly set when the core is stopped in
debug
10-bit slave mode: wrong direction bit value upon Read header
receipt
10-bit combined with 7-bit slave mode: ADDCODE may indicate
wrong slave address detection
10-bit master mode: new transfer cannot be launched if first part
of the address is not acknowledged by the slave
Wrong data sampling when data setup time (tSU;DAT) is shorter
than one I2C kernel clock period
Consistency not checked in mode 1 of automatic baud rate
detection
Framing error (FE) flag low upon automatic baud rate detection
error
Last byte written in TDR might not be transmitted if TE is cleared
just after writing in TDR
A A A A
A A A A
N N N N
A A A -
N N N -
A A A A
P P P P
N N N -
A A A -
A A A A
STM32F030xC Rev. A
ES0219 - Rev 5
page 3/29
Function Section Limitation
STM32F030x4/x6/x8/xC
Summary of device errata
Status
2.11.2 BSY bit may stay high at the end of data transfer in slave mode
Corrupted last bit of data and/or CRC, received in master mode
with delayed SCK feedback
SPI CRC corruption upon DMA transaction completion by another
peripheral
SPI
2.11.3
2.11.4
2.11.5 Packing mode limitation at reception P P P -
2.11.7 Data flow corruption in master receiver TI half-duplex mode P P P -
The following table gives a quick reference to the documentation errata.
Table 4. Summary of device documentation errata
Function
DMA 2.4.2 Byte and half-word accesses not supported
TIM 2.6.2 TRGO and TRGO2 trigger output failure
I2C 2.9.4 Wrong behavior in Stop mode
SPI 2.11.6 CRC error in SPI slave mode if internal NSS changes before CRC transfer
Section Documentation erratum
STM32F030x4 Rev. A, 1
STM32F030x6 Rev. A, 1
STM32F030x8 Rev. B, 1, 2
A A A A
A A A -
P P P -
STM32F030xC Rev. A
ES0219 - Rev 5
page 4/29
STM32F030x4/x6/x8/xC
Description of device errata
2 Description of device errata
The following sections describe limitations of the applicable devices with Arm® core and provide workarounds if
available. They are grouped by device functions.
Note: Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
2.1 Core
Reference manual and errata notice for the Arm® Cortex®-M0 core revision r0p0 is available from http://
infocenter.arm.com.
2.2 System
2.2.1 Wakeup sequence from Standby mode when using more than one wakeup source
Description
The various wakeup sources are logically OR-ed in front of the rising-edge detector that generates the wakeup
flag (WUF). The WUF needs to be cleared prior to Standby mode entry, otherwise the MCU wakes up
immediately.
If one of the configured wakeup sources is kept high during the clearing of the WUF (by setting the CWUF bit), it
may mask further wakeup events on the input of the edge detector. As a consequence, the MCU might not be
able to wake up from Standby mode.
Workaround
Apply the following sequence before entering Standby mode:
1. Disable all used wakeup sources
2. Clear all related wakeup flags
3. Re-enable all used wakeup sources
4. Enter Standby mode
Note: Be aware that, when applying this workaround, if one of the wakeup sources is still kept high, the MCU enters
Standby mode but then it wakes up immediately, generating a power reset.
2.2.2 RDP Level 1 issue
Description
When the RDP Level 1 protection is set, there exists a logic issue that compromises protection of the Flash
memory against debugger access. When the debugger is connected to the device, the first transaction with the
Flash memory after a power on reset/power up is granted because of a race condition existing between this
debugger access and the protection mechanism of the Flash memory. As a result, the debugger may access one
data in the Flash memory after power up.
ES0219 - Rev 5
Workaround
For customers concerned by the confidentiality of their firmware, it is recommended to use the RDP Level 2
protection.
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STM32F030x4/x6/x8/xC
2.3 GPIO
2.3.1 Extra consumption on GPIOs PB0 / PC0 to PC5 on 20/48-pin devices
Description
For lower pin count devices, some GPIOs are not available on the package. The hardware forces them to safe
configuration.
In this situation, software reconfiguration of PB0 (on STM32F030F4) and PC0 to PC5 (on STM32F030C8) to
analog mode opens a path between V
can be observed if V
Workaround
Do not reconfigure PB0 (on STM32F030F4) and PC0 to PC5 (on STM32F030C8) GPIOs to analog mode on
20/48-pin devices.
is higher than V
DDA
2.3.2 GPIOx locking mechanism not working properly for GPIOx_OTYPER register
Description
DDA
and V
DDIO
. Additional current consumption in the range of tens of μA
DDIO
.
GPIO
Locking GPIOx_OTYPER[i] with i = 15 to 8 unduly depends on GPIOx_LCKR[i-8] instead on GPIOx_LCKR[i].
GPIOx_LCKR[i-8] locks both GPIOx_OTYPER[i] and GPIOx_OTYPER[i-8]. It is not possible to lock
GPIOx_OTYPER[i] with i = 15...8 without also locking GPIOx_OTYPER[i-8].
Workaround
The only way to lock GPIOx_OTYPER[i] with i=15 to 8 is to also lock GPIOx_OTYPER[i-8].
2.4
DMA
2.4.1 DMA disable failure and error flag omission upon simultaneous transfer error and global flag
clear
Description
Upon a data transfer error in a DMA channel x, both the specific TEIFx and the global GIFx flags are raised and
the channel x is normally automatically disabled. However, if in the same clock cycle the software clears the GIFx
flag (by setting the CGIFx bit of the DMA_IFCR register), the automatic channel disable fails and the TEIFx flag is
not raised.
This issue does not occur with ST's HAL software that does not use and clear the GIFx flag when the channel is
active, but uses and clears the HTIFx, TCIFx, and TEIFx specific event flags instead.
Workaround
Do not clear GIFx flags when the channel is active. Instead, use HTIFx, TCIFx, and TEIFx specific event flags and
their corresponding clear bits.
2.4.2 Byte and half-word accesses not supported
Description
Some reference manual revisions may wrongly state that the DMA registers are byte- and half-word-accessible.
Instead, the DMA registers must always be accessed through aligned 32-bit words. Byte or half-word write
accesses cause an erroneous behavior.
ST's low-level driver and HAL software only use aligned 32-bit accesses to the DMA registers.
This is a description inaccuracy issue rather than a product limitation.
ES0219 - Rev 5
page 6/29
STM32F030x4/x6/x8/xC
Workaround
No application workaround is required.
2.5 ADC
2.5.1 ADCAL bit is not cleared when successive calibrations are performed and system clock
frequency is considerably higher than the ADC clock frequency
Description
The ADC calibration is launched by setting ADCAL bit of ADC_CR register. It can only be initiated when the ADC
is disabled (ADEN cleared in ADC_CR register). ADCAL bit stays at 1 during the whole calibration sequence and
is cleared by hardware as soon the calibration completes.
However, when at least two calibrations are performed in a row and the system clock frequency is considerably
higher than the ADC clock, the ADCAL bit is set again after being cleared by hardware when the first calibration
phase ends. The ADCAL bit remains set, waiting for the calibration to complete and hence for a hardware clear
that never occurs since the ADC clock is stopped.
Workaround
ADC
Avoid performing successive calibrations.
2.5.2 Overrun flag is not set if EOC reset coincides with new conversion end
Description
If the EOC flag is cleared by an ADC_DR register read operation or by software during the same APB cycle in
which the data from a new conversion are written in the ADC_DR register, the overrun event duly occurs (which
results in the loss of either current or new data) but the overrun flag (OVR) may stay low.
Workaround
Clear the EOC flag, by performing an ADC_DR read operation or by software within less than one ADC
conversion cycle period from the last conversion cycle end, in order to avoid the coincidence with the end of the
new conversion cycle.
2.5.3 ADEN bit cannot be set immediately after the ADC calibration
Description
At the end of the ADC calibration, an internal reset of ADEN bit occurs four ADC clock cycles after the ADCAL bit
is cleared by hardware. As a consequence, if the ADEN bit is set within those four ADC clock cycles, it is reset
shortly after by the calibration logic and the ADC remains disabled.
Workaround
Apply one of the following measures:
• When the ADC calibration is complete (ADCAL = 0), keep setting the ADEN bit until the ADRDY flag goes
high.
• After the ADCAL is cleared, wait for a minimum of four ADC clock cycles before enabling the ADC
(ADEN = 1).
• Always perform the ADC calibration with ADC clock frequency = APB frequency / 2.
ES0219 - Rev 5
page 7/29
STM32F030x4/x6/x8/xC
2.6 TIM
2.6.1 PWM re-enabled in automatic output enable mode despite of system break
Description
In automatic output enable mode (AOE bit set in TIMx_BDTR register), the break input can be used to do a cycleby-cycle PWM control for a current mode regulation. A break signal (typically a comparator with a current
threshold ) disables the PWM output(s) and the PWM is re-armed on the next counter period.
However, a system break (typically coming from the CSS Clock security System) is supposed to stop definitively
the PWM to avoid abnormal operation (for example with PWM frequency deviation).
In the current implementation, the timer system break input is not latched. As a consequence, a system break
indeed disables the PWM output(s) when it occurs, but PWM output(s) is (are) re-armed on the following counter
period.
Workaround
Preferably, implement control loops with the output clear enable function (OCxCE bit in the TIMx_CCMR1/CCMR2
register), leaving the use of break circuitry solely for internal and/or external fault protection (AOE bit reset).
2.6.2 TRGO and TRGO2 trigger output failure
TIM
Description
Some reference manual revisions may omit the following information.
The timers can be linked using ITRx inputs and TRGOx outputs. Additionally, the TRGOx outputs can be used as
triggers for other peripherals (for example ADC). Since this circuitry is based on pulse generation, care must be
taken when initializing master and slave peripherals or when using different master/slave clock frequencies:
• If the master timer generates a trigger output pulse on TRGOx prior to have the destination peripheral clock
enabled, the triggering system may fail.
• If the frequency of the destination peripheral is modified on-the-fly (clock prescaler modification), the
triggering system may fail.
As a conclusion, the clock of the slave timer or slave peripheral must be enabled prior to receiving events from
the master timer, and must not be changed on-the-fly while triggers are being received from the master timer.
This is a documentation issue rather than a product limitation.
Workaround
No application workaround is required or applicable as long as the application handles the clock as indicated.
2.6.3 Consecutive compare event missed in specific conditions
Description
Every match of the counter (CNT) value with the compare register (CCR) value is expected to trigger a compare
event. However, if such matches occur in two consecutive counter clock cycles (as consequence of the CCR
value change between the two cycles), the second compare event is missed for the following CCR value
changes:
in edge-aligned mode, from ARR to 0:
•
– first compare event: CNT = CCR = ARR
– second (missed) compare event: CNT = CCR = 0
•
in center-aligned mode while up-counting, from ARR-1 to ARR (possibly a new ARR value if the period is
also changed) at the crest (that is, when TIMx_RCR = 0):
– first compare event: CNT = CCR = (ARR-1)
– second (missed) compare event: CNT = CCR = ARR
ES0219 - Rev 5
page 8/29
• in center-aligned mode while down-counting, from 1 to 0 at the valley (that is, when TIMx_RCR = 0):
– first compare event: CNT = CCR = 1
– second (missed) compare event: CNT = CCR = 0
This typically corresponds to an abrupt change of compare value aiming at creating a timer clock single-cyclewide pulse in toggle mode.
As a consequence:
• In toggle mode, the output only toggles once per counter period (squared waveform), whereas it is expected
to toggle twice within two consecutive counter cycles (and so exhibit a short pulse per counter period).
• In center mode, the compare interrupt flag does note rise and the interrupt is not generated.
Note: The timer output operates as expected in modes other than the toggle mode.
Workaround
None.
2.6.4 Output compare clear not working with external counter reset
Description
The output compare clear event (ocref_clr) is not correctly generated when the timer is configured in the following
slave modes: Reset mode, Combined reset + trigger mode, and Combined gated + reset mode.
The PWM output remains inactive during one extra PWM cycle if the following sequence occurs:
1. The output is cleared by the ocref_clr event.
2. The timer reset occurs before the programmed compare event.
STM32F030x4/x6/x8/xC
IWDG
Workaround
Apply one of the following measures:
• Use BKIN (or BKIN2 if available) input for clearing the output, selecting the Automatic output enable mode
(AOE = 1).
• Mask the timer reset during the PWM ON time to prevent it from occurring before the compare event (for
example with a spare timer compare channel open-drain output connected with the reset signal, pulling the
timer reset line down).
2.7 IWDG
2.7.1 RVU flag not reset in Stop
Description
Successful write to the IWDG_RLR register raises the RVU flag and prevents further write accesses to the
register until the RVU flag is automatically cleared by hardware. However, if the device enters Stop mode while
the RVU flag is set, the hardware never clears that flag, and writing to the IWDG_RLR register is no longer
possible.
Workaround
Ensure that the RVU flag is cleared before entering Stop mode.
2.7.2 PVU flag not reset in Stop
Description
ES0219 - Rev 5
Successful write to the IWDG_PR register raises the PVU flag and prevents further write accesses to the register
until the PVU flag is automatically cleared by hardware. However, if the device enters Stop mode while the PVU
flag is set, the hardware never clears that flag, and writing to the IWDG_PR register is no longer possible.
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