STMicroelectronics STM32F030F4, STM32F030C6, STM32F030K6, STM32F030C8, STM32F030R8 Datasheet

STM32F030x4 STM32F030x6 STM32F030x8 STM32F030xC

Value-line ARM®-based 32-bit MCU with up to 256-KB Flash, timers, ADC, communication interfaces, 2.4-3.6 V operation

Datasheet - production data

Features

•Core: ARM® 32-bit Cortex®-M0 CPU, frequency up to 48 MHz

•Memories

–16 to 256 Kbytes of Flash memory

–4 to 32 Kbytes of SRAM with HW parity

•CRC calculation unit

•Reset and power management

–Digital & I/Os supply: VDD = 2.4 V to 3.6 V

–Analog supply: VDDA = VDD to 3.6 V

–Power-on/Power down reset (POR/PDR)

–Low power modes: Sleep, Stop, Standby

•Clock management

–4 to 32 MHz crystal oscillator

–32 kHz oscillator for RTC with calibration

–Internal 8 MHz RC with x6 PLL option

–Internal 40 kHz RC oscillator

•Up to 55 fast I/Os

–All mappable on external interrupt vectors

–Up to 55 I/Os with 5V tolerant capability

•5-channel DMA controller

•One 12-bit, 1.0 μs ADC (up to 16 channels)

–Conversion range: 0 to 3.6 V

–Separate analog supply: 2.4 V to 3.6 V

•Calendar RTC with alarm and periodic wakeup from Stop/Standby

•11 timers

–One 16-bit advanced-control timer for six-channel PWM output

–Up to seven 16-bit timers, with up to four IC/OC, OCN, usable for IR control decoding

–Independent and system watchdog timers

–SysTick timer

LQFP64 10x10 mm	TSSOP20
LQFP48 7x7 mm
LQFP32 7x7 mm

•Communication interfaces

–Up to two I2C interfaces

–one supporting Fast Mode Plus (1 Mbit/s) with 20 mA current sink,

–one supporting SMBus/PMBus.

–Up to six USARTs supporting master synchronous SPI and modem control; one with auto baud rate detection

–Up to two SPIs (18 Mbit/s) with 4 to 16 programmable bit frames

•Serial wire debug (SWD)

•All packages ECOPACK®2

Table 1. Device summary

Reference	Part number
STM32F030x4	STM32F030F4
STM32F030x6	STM32F030C6, STM32F030K6
STM32F030x8	STM32F030C8, STM32F030R8
STM32F030xC	STM32F030CC, STM32F030RC

January 2015

DocID024849 Rev 2

1/96

This is information on a product in full production.

www.st.com

STM32F030x4/6/8/C	Contents

Contents

1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 8
2	Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		9
3	Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		12
	3.1	ARM®-Cortex®-M0 core with embedded Flash and SRAM . . . . . . . . . . .	12
	3.2	Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
	3.3	Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
	3.4	Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . .	13
	3.5	Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13

3.5.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.2 Power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.6 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.7 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.8 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.9 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.9.1	Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . .	16
3.9.2	Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . .	16

3.10 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.10.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.10.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.11 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.11.1	Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
3.11.2 General-purpose timers (TIM3, TIM14..17) . . . . . . . . . . . . . . . . . . . . . .		19
3.11.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		20
3.11.4	Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
3.11.5 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . .		20
3.11.6	SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20

3.12 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.13 Inter-integrated circuit interfaces (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.14Universal synchronous/asynchronous receiver transmitters (USART) . . 22

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	3.15	Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . 23
	3.16	Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . 23
4	Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . 24
5	Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . 38
6	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . 41
	6.1	Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . 41

6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

6.2	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		43
6.3	Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		45
	6.3.1	General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	45
	6.3.2	Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . .	45
	6.3.3	Embedded reset and power control block characteristics . . . . . . . . . . .	46
	6.3.4	Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	46
	6.3.5	Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	46
	6.3.6	Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . .	53
	6.3.7	External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .	54
	6.3.8	Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .	60
	6.3.9	PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	61
	6.3.10	Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	62
	6.3.11	EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	62
	6.3.12	Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .	64
	6.3.13	I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .	65
	6.3.14	I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	65
	6.3.15	NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	71
	6.3.16	12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	73
	6.3.17	Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .	76
	6.3.18	Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	76
	6.3.19	Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	77
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7	Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		81
	7.1	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	81
	7.2	Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	93

7.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

8	Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	94
9	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	95

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STM32F030x4/6/8/C	List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. STM32F030x4/6/8/C family device features and peripheral counts . . . . . . . . . . . . . . . . . . 10 Table 3. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 4. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 5. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 6. Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 7. STM32F030x4/6/8/C I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 8. STM32F030x4/6/8/C USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 9. STM32F030x4/6/8/C SPI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 10. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 11. STM32F030x4/6/8/C pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 12. Alternate functions selected through GPIOA_AFR registers for port A . . . . . . . . . . . . . . . 34 Table 13. Alternate functions selected through GPIOB_AFR registers for port B . . . . . . . . . . . . . . . 35 Table 14. Alternate functions selected through GPIOC_AFR registers for port C . . . . . . . . . . . . . . . 37 Table 15. Alternate functions selected through GPIOD_AFR registers for port D . . . . . . . . . . . . . . . 37 Table 16. Alternate functions selected through GPIOF_AFR registers for port F. . . . . . . . . . . . . . . . 37 Table 17. STM32F030x4/6/8/C peripheral register boundary addresses . . . . . . . . . . . . . . . . . . . . . . 39 Table 18. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 19. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 20. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 21. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 22. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 23. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 24. Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 25. Typical and maximum current consumption from VDD supply at VDD = 3.6 V . . . . . . . . . . 47 Table 26. Typical and maximum current consumption from the VDDA supply . . . . . . . . . . . . . . . . . . 48 Table 27. Typical and maximum consumption in Stop and Standby modes . . . . . . . . . . . . . . . . . . . 49 Table 28. Typical current consumption in Run mode, code with data processing

running from Flash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 29. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 30. Low-power mode wakeup timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 31. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 32. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 33. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 34. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 35. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 36. HSI14 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 37. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 38. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 39. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 40. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 41. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 42. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 43. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 44. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 45. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 46. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 47. Output voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

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Table 48. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 49. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 50. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 51. RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 52. ADC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 53. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 54. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 55. IWDG min/max timeout period at 40 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 56. WWDG min/max timeout value at 48 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 57. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 58. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 59. LQFP64 - 10 x 10 mm low-profile quad flat package mechanical data. . . . . . . . . . . . . . . . 82 Table 60. LQFP48 - 7 mm x 7 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . 85 Table 61. LQFP32 - 7 x 7mm 32-pin low-profile quad flat package mechanical data. . . . . . . . . . . . . 88 Table 62. TSSOP20 - 20-pin thin shrink small outline package mechanical data . . . . . . . . . . . . . . . 91 Table 63. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 64. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Table 65. Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

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STM32F030x4/6/8/C	List of figures

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 3. LQFP64 64-pin package pinout (top view), for STM32F030x4/6/8 devices . . . . . . . . . . . . 24 Figure 4. LQFP64 64-pin package pinout (top view), for STM32F030RC devices . . . . . . . . . . . . . . 25 Figure 5. LQFP48 48-pin package pinout (top view), for STM32F030x4/6/8 devices . . . . . . . . . . . . 25 Figure 6. LQFP48 48-pin package pinout (top view), for STM32F030CC devices . . . . . . . . . . . . . . 26 Figure 7. LQFP32 32-pin package pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 8. TSSOP20 20-pin package pinout (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 9. STM32F030x4/6/8/C memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 10. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 11. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 12. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 13. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 14. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 15. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 16. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 17. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 18. TC and TTa I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Figure 19. Five volt tolerant (FT and FTf) I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 20. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Figure 21. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 22. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 23. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 24. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Figure 25. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Figure 26. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Figure 27. LQFP64 - 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 82 Figure 28. LQFP64 recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Figure 29. LQFP64 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Figure 30. LQFP48 - 7 mm x 7 mm, 48 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 85 Figure 31. LQFP48 recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 32. LQFP48 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 33. LQFP32 - 7 x 7mm 32-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . 88 Figure 34. LQFP32 recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Figure 35. LQFP32 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Figure 36. TSSOP20 - 20-pin thin shrink small outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Figure 37. TSSOP20 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Figure 38. TSSOP20 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

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STM32F030x4/6/8/C	Introduction

1 Introduction

This datasheet provides the ordering information and mechanical device characteristics of the STM32F030x4/6/8/C microcontrollers.

This document should be read in conjunction with the STM32F0x0xx reference manual (RM0360). The reference manual is available from the STMicroelectronics website www.st.com.

For information on the ARM→ Cortex→-M0 core, please refer to the Cortex→-M0 Technical Reference Manual, available from the www.arm.com website.

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Description	STM32F030x4/6/8/C

2 Description

The STM32F030x4/6/8/C microcontrollers incorporate the high-performance ARM→ Cortex→-M0 32-bit RISC core operating at a 48 MHz frequency, high-speed embedded memories (up to 256 Kbytes of Flash memory and up to 32 Kbytes of SRAM), and an extensive range of enhanced peripherals and I/Os. All devices offer standard communication interfaces (up to two I2Cs, up to two SPIs and up to six USARTs), one 12-bit ADC, seven general-purpose 16-bit timers and an advanced-control PWM timer.

The STM32F030x4/6/8/C microcontrollers operate in the -40 to +85 °C temperature range from a 2.4 to 3.6V power supply. A comprehensive set of power-saving modes allows the design of low-power applications.

The STM32F030x4/6/8/C microcontrollers include devices in four different packages ranging from 20 pins to 64 pins. Depending on the device chosen, different sets of peripherals are included. The description below provides an overview of the complete range of STM32F030x4/6/8/C peripherals proposed.

These features make the STM32F030x4/6/8/C microcontrollers suitable for a wide range of applications such as application control and user interfaces, handheld equipment, A/V receivers and digital TV, PC peripherals, gaming and GPS platforms, industrial applications, PLCs, inverters, printers, scanners, alarm systems, video intercoms, and HVACs.

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STM32F030x4/6/8/C									Description
		Table 2. STM32F030x4/6/8/C family device features and peripheral counts
	Peripheral		STM32	STM32	STM32	STM32	STM32	STM32		STM32
			F030F4	F030K6	F030C6	F030C8	F030CC	F030R8		F030RC
	Flash (Kbytes)		16	32	32	64	256	64		256
	SRAM (Kbytes)		4	4	4	8	32	8		32
		Advanced				1 (16-bit)
		control
	Timers	General	4 (16-bit)(1)	4 (16-bit)(1)	4 (16-bit)(1)		5 (16-bit)
		purpose
		Basic	-	-	-	1 (16-bit)(2)	2 (16-bit)	1 (16-bit)(2)		2 (16-bit)
	Comm.	SPI	1(3)	1(3)	1(3)	2	2	2		2
		I2C	1(4)	1(4)	1(4)	2	2	2		2
	interfaces
		USART	1(5)	1(5)	1(5)	2(6)	6	2(6)		6
	12-bit ADC		1 (11	1 (12	1 (12	1 (12	1 (12	1 (18		1 (18
	(number of channels)		channels)	channels)	channels)	channels)	channels)	channels)		channels)
	GPIOs		15	26	39	39	37	55		51
	Max. CPU frequency					48 MHz
	Operating voltage					2.4 to 3.6 V
	Operating temperature			Ambient operating temperature: -40°C to 85°C
					Junction temperature: -40°C to 105°C
	Packages		TSSOP20	LQFP32		LQFP48		LQFP64

1.TIM15 is not present.

2.TIM7 is not present.

3.SPI2 is not present.

4.I2C2 is not present.

5.USART2 to USART6 are not present.

6.USART3 to USART6 are not present

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Description	STM32F030x4/6/8/C

Figure 1. Block diagram

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1.TIMER6, TIMER15, SPI, USART2 and I2C2 are available on STM32F030x8/C devices only.

2.USART3, USART4, USART5 and USART6 are available on STM32F030xC devices only.

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STM32F030x4/6/8/C	Functional overview

3 Functional overview

3.1ARM®-Cortex®-M0 core with embedded Flash and SRAM

The ARM→ Cortex→-M0 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.

The ARM→ Cortex→-M0 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices.

The STM32F0xx family has an embedded ARM core and is therefore compatible with all ARM tools and software.

Figure 3 shows the general block diagram of the device family.

3.2Memories

The device has the following features:

•4 to 32 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states and featuring embedded parity checking with exception generation for failcritical applications.

•The non-volatile memory is divided into two arrays:

–16 to 256 Kbytes of embedded Flash memory for programs and data

–Option bytes

The option bytes are used to write-protect the memory (with 4 KB granularity) and/or readout-protect the whole memory with the following options:

–Level 0: no readout protection

–Level 1: memory readout protection, the Flash memory cannot be read from or written to if either debug features are connected or boot in RAM is selected

–Level 2: chip readout protection, debug features (Cortex®-M0 serial wire) and boot in RAM selection disabled

3.3Boot modes

At startup, the boot pin and boot selector option bit are used to select one of the three boot options:

•Boot from User Flash

•Boot from System Memory

•Boot from embedded SRAM

The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART on pins PA14/PA15 or PA9/PA10.

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Functional overview	STM32F030x4/6/8/C

3.4Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.

3.5Power management

3.5.1Power supply schemes

•VDD = 2.4 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through VDD pins.

•VDDA = from VDD to 3.6 V: external analog power supply for ADC, Reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used). The VDDA voltage level must be always greater or equal to the VDD voltage level and must be provided first.

For more details on how to connect power pins, refer to Figure 12: Power supply scheme.

3.5.2Power supply supervisors

The device has integrated power-on reset (POR) and power-down reset (PDR) circuits. They are always active, and ensure proper operation above a threshold of 2 V. The device remains in reset mode when the monitored supply voltage is below a specified threshold, VPOR/PDR, without the need for an external reset circuit.

•The POR monitors only the VDD supply voltage. During the startup phase it is required that VDDA should arrive first and be greater than or equal to VDD.

•The PDR monitors both the VDD and VDDA supply voltages, however the VDDA power supply supervisor can be disabled (by programming a dedicated Option bit) to reduce

the power consumption if the application design ensures that VDDA is higher than or equal to VDD.

3.5.3Voltage regulator

The regulator has two operating modes and it is always enabled after reset.

•Main (MR) is used in normal operating mode (Run).

•Low power (LPR) can be used in Stop mode where the power demand is reduced.

In Standby mode, it is put in power down mode. In this mode, the regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost).

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STM32F030x4/6/8/C	Functional overview

3.5.4Low-power modes

The STM32F030x4/6/8/C microcontrollers support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:

•Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

•Stop mode

Stop mode achieves very low power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low power mode.

The device can be woken up from Stop mode by any of the EXTI lines. The EXTI line source can be one of the 16 external lines and RTC.

•Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the RTC domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pins, or an RTC event occurs.

Note:	The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
	or Standby mode.

3.6Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example on failure of an indirectly used external crystal, resonator or oscillator).

Several prescalers allow the application to configure the frequency of the AHB and the APB domains. The maximum frequency of the AHB and the APB domains is 48 MHz.

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Functional overview	STM32F030x4/6/8/C

Figure 2. Clock tree

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1. LSI/LSE is not available in STM32F030x8 devices.

3.7General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions.

The I/O configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.

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3.8Direct memory access controller (DMA)

The 5-channel general-purpose DMA manages memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers.

The DMA supports circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent.

The DMA can be used with the main peripherals: SPI, I2C, USART, all TIMx timers (except TIM14) and ADC.

3.9Interrupts and events

3.9.1Nested vectored interrupt controller (NVIC)

The STM32F0xx family embeds a nested vectored interrupt controller able to handle up to 32 maskable interrupt channels (not including the 16 interrupt lines of Cortex®-M0) and 4 priority levels.

•Closely coupled NVIC gives low latency interrupt processing

•Interrupt entry vector table address passed directly to the core

•Closely coupled NVIC core interface

•Allows early processing of interrupts

•Processing of late arriving higher priority interrupts

•Support for tail-chaining

•Processor state automatically saved

•Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt latency.

3.9.2Extended interrupt/event controller (EXTI)

The extended interrupt/event controller consists of 32 edge detector lines used to generate interrupt/event requests and wake-up the system. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the internal clock period. Up to 55 GPIOs can be connected to the 16 external interrupt lines.

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Functional overview	STM32F030x4/6/8/C

3.10Analog to digital converter (ADC)

The 12-bit analog to digital converter has up to 16 external and two internal (temperature sensor, voltage reference measurement) channels and performs conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs.

The ADC can be served by the DMA controller.

An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

3.10.1Temperature sensor

The temperature sensor (TS) generates a voltage VSENSE that varies linearly with temperature.

The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only.

To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode.

Table 3. Temperature sensor calibration values

Calibration value name	Description	Memory address
	TS ADC raw data acquired at a
TS_CAL1	temperature of 30 °C (± 5 °C),	0x1FFF F7B8 - 0x1FFF F7B9
	VDDA= 3.3 V (± 10 mV)

3.10.2Internal voltage reference (VREFINT)

The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC. VREFINT is internally connected to the ADC_IN17 input channel. The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode.

Table 4. Internal voltage reference calibration values

Calibration value name	Description	Memory address
	Raw data acquired at a
VREFINT_CAL	temperature of 30 °C (± 5 °C),	0x1FFF F7BA - 0x1FFF F7BB
	VDDA= 3.3 V (± 10 mV)

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3.11Timers and watchdogs

The STM32F030x4/6/8/C devices include up to six general-purpose timers, two basic timers and one advanced control timer.

Table 5 compares the features of the different timers.

Table 5. Timer feature comparison

	Timer	Timer	Counter	Counter	Prescaler	DMA request	Capture/compare	Complementary
	type		resolution	type	factor	generation	channels	outputs
	Advanced			Up,	Any integer
		TIM1	16-bit	down,	between 1	Yes	4	Yes
	control
				up/down	and 65536
				Up,	Any integer
		TIM3	16-bit	down,	between 1	Yes	4	No
				up/down	and 65536
					Any integer
		TIM14	16-bit	Up	between 1	No	1	No
	General				and 65536
	purpose	TIM15(1)			Any integer
			16-bit	Up	between 1	Yes	2	No
					and 65536
		TIM16,			Any integer
			16-bit	Up	between 1	Yes	1	Yes
		TIM17
					and 65536
	Basic	TIM6,(1)			Any integer
			16-bit	Up	between 1	Yes	0	No
		TIM7(2)
					and 65536

1.Available on STM32F030x8 and STM32F030xB devices only.

2.Available on STM32F030xB devices only

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Functional overview	STM32F030x4/6/8/C

3.11.1Advanced-control timer (TIM1)

The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on six channels. It has complementary PWM outputs with programmable inserted dead times. It can also be seen as a complete general-purpose timer. The four independent channels can be used for:

•Input capture

•Output compare

•PWM generation (edge or center-aligned modes)

•One-pulse mode output

If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If configured as the 16-bit PWM generator, it has full modulation capability (0-100%).

The counter can be frozen in debug mode.

Many features are shared with those of the standard timers which have the same architecture. The advanced control timer can therefore work together with the other timers via the Timer Link feature for synchronization or event chaining.

3.11.2General-purpose timers (TIM3, TIM14..17)

There are five synchronizable general-purpose timers embedded in the STM32F030x4/6/8/C devices (see Table 5 for differences). Each general-purpose timer can be used to generate PWM outputs, or as simple time base.

TIM3

STM32F030x4/6/8/C devices feature one synchronizable 4-channel general-purpose timer. TIM3 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. It features four independent channels each for input capture/output compare, PWM or one-pulse mode output. This gives up to 12 input captures/output compares/PWMs on the largest packages.

The TIM3 general-purpose timer can work with the TIM1 advanced-control timer via the Timer Link feature for synchronization or event chaining.

TIM3 has an independent DMA request generation.

This timer is capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors.

The counter can be frozen in debug mode.

TIM14

This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler.

TIM14 features one single channel for input capture/output compare, PWM or one-pulse mode output.

Its counter can be frozen in debug mode.

TIM15, TIM16 and TIM17

These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.

TIM15 has two independent channels, whereas TIM16 and TIM17 feature one single channel for input capture/output compare, PWM or one-pulse mode output.

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The TIM15, TIM16 and TIM17 timers can work together, and TIM15 can also operate withTIM1 via the Timer Link feature for synchronization or event chaining.

TIM15 can be synchronized with TIM16 and TIM17.

TIM15, TIM16 and TIM17 have a complementary output with dead-time generation and independent DMA request generation.

Their counters can be frozen in debug mode.

3.11.3Basic timers TIM6 and TIM7

These timers can be used as a generic 16-bit time base.

3.11.4Independent watchdog (IWDG)

The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with user-defined refresh window. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.

3.11.5System window watchdog (WWDG)

The system window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the APB clock (PCLK). It has an early warning interrupt capability and the counter can be frozen in debug mode.

3.11.6SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features:

•A 24-bit down counter

•Autoreload capability

•Maskable system interrupt generation when the counter reaches 0

•Programmable clock source (HCLK or HCLK/8)

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3.12Real-time clock (RTC)

The RTC is an independent BCD timer/counter. Its main features are the following:

•Calendar with subseconds, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format.

•Automatic correction for 28, 29 (leap year), 30, and 31 day of the month.

•Programmable alarm with wake up from Stop and Standby mode capability.

•Periodic wakeup unit with programmable resolution and period.

•On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize the RTC with a master clock.

•Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal inaccuracy.

•Tow anti-tamper detection pins with programmable filter. The MCU can be woken up from Stop and Standby modes on tamper event detection.

•Timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be woken up from Stop and Standby modes on timestamp event detection.

•Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision.

The RTC clock sources can be:

•A 32.768 kHz external crystal

•A resonator or oscillator

•The internal low-power RC oscillator (typical frequency of 40 kHz)

•The high-speed external clock divided by 32

3.13Inter-integrated circuit interfaces (I2C)

Up to two I2C interfaces (I2C1 and I2C2) can operate in multimaster or slave modes. Both can support Standard mode (up to 100 kbit/s) or Fast mode (up to 400 kbit/s). I2C1 also supports Fast Mode Plus (up to 1 Mbit/s) with 20 mA output drive.

Both support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (two addresses, one with configurable mask). They also include programmable analog and digital noise filters.

Table 6. Comparison of I2C analog and digital filters

		Analog filter	Digital filter
	Pulse width of	≥ 50 ns	Programmable length from 1 to 15
	suppressed spikes		I2C peripheral clocks
			1. Extra filtering capability vs.
	Benefits	Available in Stop mode	standard requirements.
			2. Stable length
	Drawbacks	Variations depending on	-
		temperature, voltage, process

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In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and ALERT protocol management

The I2C interfaces can be served by the DMA controller. Refer to Table 7 for the differences between I2C1 and I2C2.

Table 7. STM32F030x4/6/8/C I2C implementation

I2C features(1)	I2C1	I2C2(2)
7-bit addressing mode	X	X
10-bit addressing mode	X	X
Standard mode (up to 100 kbit/s)	X	X
Fast mode (up to 400 kbit/s)	X	X
Fast Mode Plus (up to 1 Mbit/s) with 20mA output drive I/Os	X	-
Independent clock	X	-
SMBus	X	-
Wakeup from STOP	-	-

1.X = supported.

2.Only available on STM32F030x8/C devices.

3.14Universal synchronous/asynchronous receiver transmitters (USART)

The device embeds up to six universal synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3, USART4, USART5, USART6 on STM32F030xC devices only), which communicate at speeds of up to 6 Mbit/s.

They provide hardware management of the CTS and RTS signals, multiprocessor communication mode, master synchronous communication and single-wire half-duplex communication mode. USART1 supports also the auto baud rate feature.

The USART interfaces can be served by the DMA controller.

Table 8. STM32F030x4/6/8/C USART implementation(1)

USART modes/features	USART1	USART2	(2)	USART2(3),	USART4	(3)	USART5	(3)	USART6	(3)
				USART3(3)
Hardware flow control for modem	X	X		X	X		-		-
Continuous communication using	X	X		X	X		X		X
DMA
Multiprocessor communication	X	X		X	X		X		X
Synchronous mode	X	X		X	X		X		-
Single-wire half-duplex	X	X		X	X		X		X
communication
Receiver timeout interrupt	X	-		X	-		-		-
Auto baud rate detection	X	-		X	-		-		-
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1.Where X means supported.

2.Not available on STM32F030x4/6 devices.

3.Available only on STM32F030xC devices.

3.15Serial peripheral interface (SPI)

Up to two SPIs are able to communicate up to 18 Mbit/s in slave and master modes in fullduplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits.

SPI1 and SPI2 are identical and implement the set of features shown in the following table.

Table 9. STM32F030x4/6/8/C SPI implementation

SPI features(1)	SPI1	SPI2(2)
Hardware CRC calculation	X	X
Rx/Tx FIFO	X	X
NSS pulse mode	X	X
TI mode	X	X

1.X = supported.

2.Not available on STM32F030x4/6.

3.16Serial wire debug port (SW-DP)

An ARM SW-DP interface is provided to allow a serial wire debugging tool to be connected to the MCU.

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4 Pinouts and pin descriptions

Figure 3. LQFP64 64-pin package pinout (top view), for STM32F030x4/6/8 devices

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Figure 4. LQFP64 64-pin package pinout (top view), for STM32F030RC devices

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	Figure 6. LQFP48 48-pin package pinout (top view), for STM32F030CC devices
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Figure 8. TSSOP20 20-pin package pinout (top view)

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Table 10. Legend/abbreviations used in the pinout table

Name

Abbreviation

Definition

Pin name

Unless otherwise specified in brackets below the pin name, the pin function during and

after reset is the same as the actual pin name

S

Supply pin

Pin type

I

Input only pin

I/O

Input / output pin

FT

5 V tolerant I/O

FTf

5 V tolerant I/O, FM+ capable

I/O structure

TTa

3.3 V tolerant I/O directly connected to ADC

TC

Standard 3.3 V I/O

B

Dedicated BOOT0 pin

RST

Bidirectional reset pin with embedded weak pull-up resistor

Notes

Unless otherwise specified by a note, all I/Os are set as floating inputs during and after

reset.

Alternate

Functions selected through GPIOx_AFR registers

Pin

functions

functions

Additional

Functions directly selected/enabled through peripheral registers

functions

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					Table 11. STM32F030x4/6/8/C pin definitions
	Pin number								Pin functions
					Pin name	<![if ! IE]> <![endif]>typePin	<![if ! IE]> <![endif]>structureI/O
<![if ! IE]> <![endif]>LQFP64		<![if ! IE]> <![endif]>LQFP48	<![if ! IE]> <![endif]>LQFP32	<![if ! IE]> <![endif]>TSSOP20
					(function after			Notes	Alternate functions	Additional functions
					reset)
1		1	-	-	VDD	S			Complementary power supply
										RTC_TAMP1,
2		2	-	-	PC13	I/O	TC	(1)	-	RTC_TS,
										RTC_OUT,
										WKUP2
3		3	-	-	PC14-OSC32_IN	I/O	TC	(1)	-	OSC32_IN
					(PC14)
4		4	-	-	PC15-OSC32_OUT	I/O	TC	(1)	-	OSC32_OUT
					(PC15)
5		5	2	2	PF0-OSC_IN	I/O	FT		I2C1_SDA(5)	OSC_IN
					(PF0)
6		6	3	3	PF1-OSC_OUT	I/O	FT		I2C1_SCL(5)	OSC_OUT
					(PF1)
7		7	4	4	NRST	I/O	RST		Device reset input / internal reset output
									(active low)
									EVENTOUT,
8		-	-	-	PC0	I/O	TTa		USART6_TX(5),	ADC_IN10
									USART7_TX(5)
									EVENTOUT,
9		-	-	-	PC1	I/O	TTa		USART6_RX(5),	ADC_IN11
									USART7_RX(5)
10		-	-	-	PC2	I/O	TTa		SPI2_MISO(5),	ADC_IN12
									EVENTOUT
11		-	-	-	PC3	I/O	TTa		SPI2_MOSI(5),	ADC_IN13
									EVENTOUT
12		8	-	-	VSSA	S			Analog ground
13		9	5	5	VDDA	S			Analog power supply
									USART1_CTS(2),	ADC_IN0,
14		10	6	6	PA0	I/O	TTa		USART2_CTS(3)(5),	RTC_TAMP2,
									USART4_TX(5)	WKUP1
									USART1_RTS(2),
15		11	7	7	PA1	I/O	TTa		USART2_RTS(3)(5),	ADC_IN1
									EVENTOUT,
									USART4_RX(5)

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					Table 11. STM32F030x4/6/8/C pin definitions (continued)
	Pin number								Pin functions
					Pin name	<![if ! IE]> <![endif]>typePin	<![if ! IE]> <![endif]>structureI/O
<![if ! IE]> <![endif]>LQFP64		<![if ! IE]> <![endif]>LQFP48	<![if ! IE]> <![endif]>LQFP32	<![if ! IE]> <![endif]>TSSOP20
					(function after			Notes	Alternate functions	Additional functions
					reset)
									USART1_TX(2),
16		12	8	8	PA2	I/O	TTa		USART2_TX(3)(5),	ADC_IN2
									TIM15_CH1(3)(5)
									USART1_RX(2),
17		13	9	9	PA3	I/O	TTa		USART2_RX(3)(5),	ADC_IN3
									TIM15_CH2(3)(5)
18(4)		-	-	-	PF4	I/O	FT	(4)	EVENTOUT	-
18(5)		-	-	-	VSS	S		(5)	Ground
19(4)		-	-	-	PF5	I/O	FT	(4)	EVENTOUT	-
19(5)		-	-	-	VDD			(5)	Complementary power supply
									SPI1_NSS,
									USART1_CK(2)
20		14	10	10	PA4	I/O	TTa		USART2_CK(3)(5),	ADC_IN4
									TIM14_CH1,
									USART6_TX(5)
21		15	11	11	PA5	I/O	TTa		SPI1_SCK,	ADC_IN5
									USART6_RX(5)
									SPI1_MISO,
									TIM3_CH1,
22		16	12	12	PA6	I/O	TTa		TIM1_BKIN,	ADC_IN6
									TIM16_CH1,
									EVENTOUT
									USART3_CTS(5)
									SPI1_MOSI,
									TIM3_CH2,
23		17	13	13	PA7	I/O	TTa		TIM14_CH1,	ADC_IN7
									TIM1_CH1N,
									TIM17_CH1,
									EVENTOUT
24		-	-	-	PC4	I/O	TTa		EVENTOUT,	ADC_IN14
									USART3_TX(5)
25		-	-	-	PC5	I/O	TTa		USART3_RX(5)	ADC_IN15
									TIM3_CH3,
26		18	14	-	PB0	I/O	TTa		TIM1_CH2N,	ADC_IN8
									EVENTOUT,
									USART3_CK(5)

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