AM01475v1_noZen
D(2, TAB)
G(1)
S(3)
STD7NM60N, STF7NM60N, STU7NM60N
Datasheet
N-channel 600 V, 0.8 Ω typ., 5 A MDmesh™ II Power MOSFETs in
DPAK, TO-220FP and IPAK packages
Features
Product status link
STD7NM60N
STF7NM60N
STU7NM60N
Order code
STD7NM60N
STF7NM60N TO-220FP
STU7NM60N IPAK
V
DS
600 V 0.9 Ω 5 A
R
DS(on)
max. I
D
Package
DPAK
• 100% avalanche tested
• Low input capacitance and gate charge
• Low gate input resistance
Applications
• Switching applications
Description
These devices are N-channel Power MOSFETs developed using the second
generation of MDmesh™ technology. These revolutionary Power MOSFETs
associate a vertical structure to the company’s strip layout to yield one of the world’s
lowest on-resistance and gate charge. They are therefore suitable for the most
demanding high-efficiency converters.
DS6523 - Rev 5 - September 2018
For further information contact your local STMicroelectronics sales office.
www.st.com
1 Electrical ratings
STD7NM60N, STF7NM60N, STU7NM60N
Electrical ratings
Table 1. Absolute maximum ratings
Symbol Parameter
V
DS
V
GS
I
D
I
D
IDM
P
TOT
V
ISO
dv/dt
T
T
stg
Drain-source voltage 600 V
Gate-source voltage ±25 V
Drain current (continuous) at TC = 25 °C
Drain current (continuous) at TC = 100 °C
(2)
Drain current (pulsed) 20
Total dissipation at TC = 25 °C
Insulation withstand voltage (RMS) from all three
leads to external heat-sink (t = 1 s, TC = 25 °C)
(3)
Peak diode recovery voltage slope 15 V/ns
Operating junction temperature range
j
Storage temperature range
1. Limited by maximum junction temperature.
2. Pulse width limited by safe operating area.
3. ISD ≤ 5 A, di/dt ≤ 100 A/μs, V
Symbol
R
thj-case
R
thj-amb
R
thj-pcb
1. When mounted on 1inch² FR-4 board, 2 oz Cu.
Thermal resistance junction-case 2.78 6.25 2.78 °C/W
Thermal resistance junction-ambient 62.5 100 °C/W
(1)
Thermal resistance junction-pcb 50 °C/W
DSpeak
Parameter
≤ V
(BR)DSS
, VDD = 80% V
(BR)DSS
.
Table 2. Thermal data
DPAK TO-220FP IPAK
Value
DPAK, IPAK TO-220FP
5
3
5
3
20
(1)
(1)
(1)
45 20 W
2.5 kV
-55 to 150 °C
Value
Unit
A
A
A
Unit
DS6523 - Rev 5
Symbol
(1)
I
AS
(2)
E
AS
Avalanche current, repetitive or not-repetitive 2 A
Single pulse avalanche energy 119 mJ
Parameter Value Unit
1. Pulse width limited by Tj max.
2. Starting Tj = 25 °C, ID = IAS, VDD = 50 V.
Table 3. Avalanche characteristics
page 2/26
2 Electrical characteristics
(T
= 25 °C unless otherwise specified)
CASE
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
1. Defined by design, not subject to production test.
Drain-source
breakdown voltage
Zero gate voltage drain
current
Gate body leakage
current
Gate threshold voltage
Static drain-source on
resistance
STD7NM60N, STF7NM60N, STU7NM60N
Table 4. On/off states
ID = 1 mA, VGS = 0 V
VGS = 0 V, VDS = 600 V
VGS = 0 V, VDS = 600 V, TC = 125 °C
VDS = 0 V, VGS = ±20 V
VDS = VGS, ID = 250 µA
VGS = 10 V, ID = 2.5 A
Electrical characteristics
600 V
1 µA
(1)
100 µA
100 nA
2 3 4 V
0.8 0.9 Ω
C
1. C
Table 5. Dynamic
Symbol
C
iss
C
oss
C
rss
(1)
oss eq.
R
G
Q
g
Q
gs
Q
gd
is defined as a constant equivalent capacitance giving the same charging time as C
oss eq.
to 80% V
DSS
Parameter Test conditions Min. Typ. Max. Unit
Input capacitance
Output capacitance 24.6
VDS = 50 V, f = 1 MHz, VGS = 0 V
Reverse transfer
capacitance
Equivalent capacitance
time related
VDS = 0 to 480 V, VGS = 0 V
Intrinsic gate resistance f = 1 MHz open drain - 5.4 - Ω
Total gate charge
Gate-source charge 2.7
Gate-drain charge 7.7
VDD = 480 V, ID = 5 A, VGS = 0 to 10 V
(see Figure 14. Test circuit for gate charge
behavior)
.
Table 6. Switching times
Symbol
t
d(on)
t
r
t
d(off)
t
f
Parameter Test conditions Min. Typ. Max. Unit
Turn-on delay time
Rise time 10
Turn-off delay time 26
Fall time 12
VDD = 300 V, ID = 2.5 A,
RG = 4.7 Ω, VGS = 10 V
(see Figure 13. Test circuit for resistive load
switching times and Figure 18. Switching
time waveform)
363
-
- pF
1.1
- 130 - pF
14
-
when VDS increases from 0
oss
- nC
7
-
- ns
DS6523 - Rev 5
page 3/26
STD7NM60N, STF7NM60N, STU7NM60N
Electrical characteristics
Table 7. Source drain diode
Symbol Parameter Test conditions Min. Typ. Max. Unit
I
SD
I
SDM
VSD
t
rr
Q
I
RRM
t
rr
Q
I
RRM
1. Pulse width limited by safe operating area.
2. Pulsed: pulse duration = 300 μs, duty cycle 1.5%.
Source-drain current
Source-drain current
(1)
(pulsed)
(2)
Forward on voltage
Reverse recovery time
Reverse recovery charge 1.5 μC
rr
Reverse recovery current 14 A
Reverse recovery time
Reverse recovery charge 1.8 μC
rr
Reverse recovery current 14 A
ISD = 5 A, VGS = 0 V
ISD = 5 A, di/dt = 100 A/µs
VDD = 60 V (see Figure 15. Test circuit for
inductive load switching and diode recovery
times)
ISD = 5 A, di/dt = 100 A/µs
VDD = 60 V, Tj = 150 °C(see Figure 15. Test
circuit for inductive load switching and
diode recovery times)
-
- 1.3 V
213 ns
-
265 ns
-
5
20
A
DS6523 - Rev 5
page 4/26
2.1 Electrical characteristics curves
I
D
-2
0
-1
2
DS
Ope ration in this are a is
Limited b
y ma
x R
DS(o n)
10µs
100µs
1ms
10ms
Tj=150 °C
Tc=2 5°C
Single
puls
AM06474 v1
-1
0
I
D
10
1
10
0
10
-1
10
-2
10
-1
10
0
10
1
10
2
DS
Ope ration in this are a is
Limited b y ma x R
DS(o n)
10µs
100µs
1ms
10ms
Tj=150 °C
Tc=2 5°C
Single
pulse
AM06475 v1
GC20940
10
-1
10
-2
10
-3
10 -410 -310 -210 -110
0
K
t p (s)
I
D
5
3
1
0
0
10
V
DS
(V)
20
(A)
40
7
8
5V
6V
VGS=10 V
2
4
6
9
AM06477 v1
I
D
6
4
2
0
0
4
V
GS
(V)
8
8
1
3
5
7
9
VDS=20 V
AM06478 v1
STD7NM60N, STF7NM60N, STU7NM60N
Electrical characteristics curves
Figure 1. Safe operating area for DPAK and IPAK
Figure 3. Safe operating area for TO-220FP
Figure 2. Thermal impedance for DPAK and IPAK
Figure 4. Thermal impedance for TO-220FP
Figure 5. Output characterisics
DS6523 - Rev 5
Figure 6. Transfer characteristics
page 5/26
V
GS
6
4
2
0
0
4
Q
g
(nC)
(V)
12
8
6
8
10
VDD=48 0V
I
D
=5A
14
12
300
200
100
0
400
500
V
DS
2
10
16
V
DS
(V)
AM06479v1
R
DS(o n)
0.78
0.76
0.74
0
2
I
D
(A)
(
Ohm)
1
3
0.80
0.82
VGS=10 V
4
5
0.84
0.86
0.88
AM06480v1
10
-1
10
0
10
1
10
2
10
3
10
1
10
2
10
0
V
GS (th)
1.00
0.90
0.80
0.70
-50
0
T
J
(°C)
(norm)
-25
1.10
75
25
50
100
I
D
=25 0µA
AM06483v1
R
DS(o n)
1.9
1.3
0.9
0.5
-50
0
T
J
(°C)
(norm)
-25
75
25
50
100
0.7
1.1
1.5
1.7
2.1
AM06 484v1
ID=2.5A
V
(BR)DSS
-50
0
T
J
(°C)
(norm)
-25
75
25
50
100
0.93
0.95
0.97
0.99
1.01
1.03
1.05
1.07
AM06485v1
ID=1m A
STD7NM60N, STF7NM60N, STU7NM60N
Electrical characteristics curves
Figure 7. Gate charge vs gate-source voltage
Figure 9. Capacitance variations
Figure 8. Static drain-source on-resistance
Figure 10. Normalized gate threshold voltage vs
temperature
Figure 11. Normalized on-resistance vs temperature
DS6523 - Rev 5
Figure 12. Normalized V
vs temperature
(BR)DSS
page 6/26
3 Test circuits
AM01468v1
V
D
R
G
R
L
D.U.T.
2200
μF
V
DD
3.3
μF
+
pulse width
V
GS
AM01469v1
47 kΩ
1 kΩ
47 kΩ
2.7 kΩ
1 kΩ
12 V
IG= CONST
100 Ω
100 nF
D.U.T.
+
pulse width
V
GS
2200
μF
V
G
V
DD
AM01470v1
A
D
D.U.T.
S
B
G
25 Ω
A
A
B
B
R
G
G
D
S
100 µH
µF
3.3
1000
µF
V
DD
D.U.T.
+
_
+
fast
diode
AM01471v1
V
D
I
D
D.U.T.
L
V
DD
+
pulse width
V
i
3.3
µF
2200
µF
AM01472v1
V(BR)DSS
VDD
VDD
VD
IDM
ID
AM01473v1
0
V
GS
90%
V
DS
90%
10%
90%
10%
10%
t
on
t
d(on)
t
r
0
t
off
t
d(off)
t
f
STD7NM60N, STF7NM60N, STU7NM60N
Test circuits
Figure 13. Test circuit for resistive load switching times
Figure 15. Test circuit for inductive load switching and
diode recovery times
Figure 14. Test circuit for gate charge behavior
Figure 16. Unclamped inductive load test circuit
DS6523 - Rev 5
Figure 17. Unclamped inductive waveform
Figure 18. Switching time waveform
page 7/26
4 Package information
STD7NM60N, STF7NM60N, STU7NM60N
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK
packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions
and product status are available at: www.st.com. ECOPACK® is an ST trademark.
®
DS6523 - Rev 5
page 8/26
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