STMicroelectronics STD2NK70Z, STD2NK70Z-1 User Guide

STD2NK70Z - STD2NK70Z-1

N-CHANNEL 700 V - 6 Ω - 1.6 A DPAK/IPAK

Zener-Protected SuperMESH™ MOSFET

Table 1: General Features

Figure 1: Package

TYPE	VDSS	RDS(on)	ID	Pw
STD2NK70Z	700 V	7 Ω	1.6 A	45 W
STD2NK70Z-1	700 V	7 Ω	1.6 A	45 W

■TYPICAL RDS(on) = 6 Ω

■EXTREMELY HIGH dv/dt CAPABILITY

■ESD IMPROVED CAPABILITY

■100% AVALANCHE TESTED

■NEW HIGH VOLTAGE BENCHMARK

■GATE CHARGE MINIMIZED

DESCRIPTION

The SuperMESH™ series is obtained through an extreme optimization of ST’s well established strip-based PowerMESH™ layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding application. Such series complements ST full range of high vltage MOSFETs including revolutionary MDmesh™ products.

APPLICATIONS

■SINGLE-ENDED SMPS IN MONITORS, COMPUTER AND INDUSTRIAL APPLICATION

■WELDING EQUIPMENT

■FLYBACK CONFIGURATION FOR BATTERY CHARGER

	3
1	3
	2
	1

DPAK	IPAK

Figure 2: Internal Schematic Diagram

Table 2: Order Codes

Sales Type	Marking	Package	Packaging
STD2NK70ZT4	D2NK70Z	DPAK	TAPE & REEL
STD2NK70Z-1	D2NK70Z	IPAK	TUBE

Rev. 2

January 2005

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Table 3: Absolute Maximum ratings

	Symbol	Parameter	Value	Unit
	VDS	Drain-source Voltage (VGS = 0)	700	V
	VDGR	Drain-gate Voltage (RGS = 20 KΩ)	700	V
	VGS	Gatesource Voltage	± 30	V
	ID	Drain Current (continuous) at TC = 25°C	1.6	A
	ID	Drain Current (continuous) at TC = 100°C	1	A
	IDM(*)	Drain Current (pulsed)	6.4	A
	PTOT	Total Dissipation at TC = 25°C	45	W
		Derating Factor	0.36	W/°C
	VESD(G-S)	Gate source ESD (HBM-C = 100pF, R = 1.5 KΩ)	2000	V
	dv/dt (1)	Peak Diode Recovery voltage slope	4.5	V/ns
	Tstg	Storage Temperature	-55 to 150	°C
	Tj	Max. Operating Junction Temperature

(*) Pulse width limited by safe operating area

(1) ISD ≤ 1.6 A, di/dt ≤ 200 A/µs, VDD ≤ V(BR)DSS

Table 4: Thermal Data

Rthj-case	Thermal Resistance Junction-case Max	2.78	°C/W
Rthj-amb	Thermal Resistance Junction-ambient Max	100	°C/W
Tl	Maximum Lead Temperature For Soldering Purpose	300	°C

Table 5: Avalanche Characteristics

Symbol	Parameter	Max Value	Unit
IAR	Avalanche Current, Repetitive or Not-Repetitive	1.6	A
	(pulse width limited by Tj max)
EAS	Single Pulse Avalanche Energy	110	mJ
	(starting Tj = 25 °C, ID = IAR, VDD = 50 V)

Table 6: Gate-Source Zener Diode

Symbol	Parameter	Test Condition	Min.	Typ.	Max	Unit
BVGSO	Gate-Source Breakdown	Igs= ± 1mA (Open Drain)	30			A
	Voltage

PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES

The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components.

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TABLE 7: ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED)

On /Off

Symbol		Parameter		Test Conditions		Min.	Typ.	Max.	Unit
V(BR)DSS		Drain-source Breakdown		ID = 1 mA, VGS = 0	700				V
		Voltage
IDSS		Zero Gate Voltage		VDS = Max Rating				1	µA
		Drain Current (VGS = 0)		VDS = Max Rating, TC = 125°C				50	µA
IGSS		Gate-body Leakage		VGS = ± 20 V				± 10	µA
		Current (VDS = 0)
VGS(th)		Gate Threshold Voltage		VDS = VGS, ID = 50 µA	3		3.75	4.5	V
RDS(on)		Static Drain-source On		VGS = 10 V, ID = 0.8 A			6	7	Ω
		Resistance
Table 8: Dynamic
Symbol		Parameter		Test Conditions		Min.	Typ.	Max.	Unit
gfs (1)		Forward Transconductance		VDS = 15 V,			1.4		S
				ID = 0.8 A
Coss eq.(3)		Equivalent Output		VGS = 0 V, VDS = 0 to 560 V			17
		Capacitance
Ciss		Input Capacitance		VDS = 25 V, f = 1 MHz, VGS = 0			280		pF
Coss		Output Capacitance					35		pF
Crss		Reverse Transfer					6.5		pF
		Capacitance
td(on)		Turn-on Delay Time		VDD = 350 V, ID = 0.8 A,			7		ns
tr		Rise Time		RG = 4.7 Ω, VGS = 10 V			17		ns
td(off)		Turn-off-Delay Time		(see Figure 17)			20		ns
tf		Fall Time					35		ns
Qg		Total Gate Charge		VDD = 560 V, ID = 0.8 A,			11.4	15	nC
Qgs		Gate-Source Charge		VGS = 10 V			2		nC
Qgd		Gate-Drain Charge		(see Figure 20)			6.8		nC
Table 9: Source Drain Diode
Symbol		Parameter		Test Conditions		Min.	Typ.	Max.	Unit
ISD		Source-drain Current						1.6	A
ISDM (2)		Source-drain Current (pulsed)						6.4	A
VSD (1)		Forward On Voltage		ISD = 1.6 A, VGS = 0				1.6	V
trr		Reverse Recovery Time		ISD = 1.6, di/dt = 100 A/µs			334		ns
Qrr		Reverse Recovery Charge		VDD =50 V, Tj = 25°C			918		µC
IRRM		Reverse Recovery Current		(see Figure 18)			5.5		A
trr		Reverse Recovery Time		ISD = 1.6, di/dt = 100 A/µs			350		ns
Qrr		Reverse Recovery Charge		VDD = 50 V, Tj = 150°C			1050		µC
IRRM		Reverse Recovery Current		(see Figure 18)			6		A

(1)Pulsed: Pulse duration = 300 µs, duty cycle 1.5%

(2)Pulse width limited by safe operating area

(3)Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS

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Figure 3: Safe Operating Area

Figure 6: Thermal Impedance

Figure 4: Output Characteristics										Figure 7: Transfer Characteristics

Figure 5: Transconductance					Figure 8: Static Drain-source On Resistance

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