STMicroelectronics STD25NF10L Technical data
Low gate charge STripFET™ II Power MOSFET
General features
Type V
STD25NF10L 100V < 0.035Ω 25A
DSS
R
DS(on)
STD25NF10L
N-channel 100V - 0.030Ω - 25A - DPAK
I
D
■ Exceptional dv/dt capability
■ 100% avalanche tested
■ Low threshold device
■ Logic level device
Description
This Power MOSFET series realized with
STMicroelectronics unique STripFET process has
specifically been designed to minimize input
capacitance and gate charge. It is therefore
suitable as primary switch in advanced highefficiency isolated DC-DC converters for Telecom
and Computer application. It is also intended for
any application with low gate charge drive
requirements.
Applications
■ Switching application
3
1
DPAK
Internal schematic diagram
Order codes
Part number Marking Package Packaging
STD25NF10LT4 D25NF10L DPAK Tape & reel
July 2006 Rev 2 1/13
www.st.com
13
Contents STD25NF10L
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5 Packing mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2/13
STD25NF10L Electrical ratings
1 Electrical ratings
Table 1. Absolute maximum ratings
Symbol Parameter Value Unit
V
I
V
DGR
V
I
D
DM
P
I
DS
GS
(1)
D
(2)
tot
Drain-source voltage (VGS = 0) 100 V
Drain-gate voltage (RGS = 20 kΩ) 100 V
Gate- source voltage ± 16 V
Drain current (continuous) at TC = 25°C 25 A
Drain current (continuous) at TC = 100°C 21 A
Drain current (pulsed) 100 A
Total dissipation at TC = 25°C 100 W
Derating Factor 0.67 W/°C
(3)
dv/dt
(4)
E
AS
T
stg
T
j
1. Current limited by package
2. Pulse width limited by safe operating area.
3. ISD ≤ 25A, di/dt ≤ 300A/µs, VDD =V(
4. Starting Tj = 25 °C, ID = 12.5A VDD = 50V
Peak diode recovery avalanche energy 20 V/ns
Single pulse avalanche energy 450 mJ
Storage temperature
-55 to 175 °C
Max. operating junction temperature
, Tj ≤ T
BR)DSS
JMAX
Table 2. Thermal data
Rthj-case Thermal resistance junction-case max 1.5 °C/W
Rthj-pcb Thermal resistance junction-pcb max
T
J
1. When Mounted on 1 inch2 FR-4 board, 2 oz of Cu.
Maximum lead temperature for soldering purpose 275 °C
(1)
100 °C/W
3/13
Electrical characteristics STD25NF10L
2 Electrical characteristics
(T
=25°C unless otherwise specified)
CASE
Table 3. On/off states
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Drain-source
breakdown voltage
Zero gate voltage
drain current (V
GS
Gate-body leakage
current (V
DS
= 0)
= 0)
ID = 250µA, VGS =0 100 V
V
= Max rating
DS
VDS = Max rating,
= 125°C
T
C
1
10
VGS = ± 16V ±100 nA
Gate threshold voltage VDS = VGS, ID = 250µA 1 2.5 V
Static drain-source on
resistance
= 10V, ID = 12.5A
V
GS
= 4.5V, ID = 12.5A
V
GS
0.030
0.035
0.035
0.040
Table 4. Dynamic
Symbol Parameter Test conditions Min. Typ. Max. Unit
Forward
(1)
g
fs
transconductance
V
= 15V, ID= 12.5A 24 S
DS
µA
µA
Ω
Ω
C
C
C
t
d(on)
t
t
d(off)
t
Q
Q
Q
1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
Input capacitance
iss
Output capacitance
oss
Reverse transfer
rss
capacitance
Turn-on delay time
Rise time
r
Turn-off delay time
Fall time
f
Total gate charge
g
Gate-source charge
gs
Gate-drain charge
gd
= 25V, f = 1MHz,
V
DS
VGS = 0
= 50V, ID = 12.5A
V
DD
=4.7Ω VGS = 5V
R
G
(see Figure 13)
VDD = 80V, ID = 25A,
= 5V, RG=4.7Ω
V
GS
(see Figure 14)
1710
250
110
20
40
58
20
38
8.5
21
pF
pF
pF
ns
ns
ns
ns
52 nC
nC
nC
4/13
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