STMicroelectronics STD22NM20N Technical data

STD22NM20N

N-CHANNEL 200V - 0.088Ω - 22A DPAK ULTRA LOW GATE CHARGE MDmesh™ II MOSFET

Table 1: General Features

TYPE	VDSS	RDS(on)	ID
STD22NM20N	200 V	< 0.105 Ω	22 A

■WORLDWIDE LOWEST GATE CHARGE

■TYPICAL RDS(on) = 0.088 Ω

■HIGH dv/dt and AVALANCHE CAPABILITIES

■LOW INPUT CAPACITANCE

■LOW GATE RESISTANCE

DESCRIPTION

This 200V MOSFET with a new advanced layout brings all unique advantages of MDmesh technology to lower voltages. The device exhibits worldwide lowest gate charge for any given onresistance. Its use is therefore ideal as primary switch in isolated DC-DC converters for Telecom and Computer applications. Used in combination with secondary-side low-voltage STripFET™ products, it contributes to reducting losses and boosting effeciency.

APPLICATIONS

The MDmesh™ family is very suitable for increas - ing power density allowing system miniaturization and higher efficiencies

Figure 1: Package

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DPAK

Figure 2: Internal Schematic Diagram

Table 2: Order Codes

SALES TYPE	MARKING	PACKAGE	PACKAGING
STD22NM20NT4	D22NM20N	DPAK	TAPE & REEL

Rev. 5

November 2005

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STD22NM20N

Table 3: Absolute Maximum ratings

Symbol	Parameter	Value	Unit
VDS	Drain-source Voltage (VGS = 0)	200	V
VDGR	Drain-gate Voltage (RGS = 20 kΩ )	200	V
VGS	Gatesource Voltage	± 20	V
ID	Drain Current (continuous) at TC = 25°	22	A
	Drain Current (continuous) at TC = 100°	13.7	A
IDM (*)	Drain Current (pulsed)	88	A
PTOT	Total Dissipation at TC = 25°C	100	W
	Derating Factor	0.8	W/°C
dv/dt (2)	Peak Diode Recovery voltage slope	14	V/ns
Tj	Storage Temperature	150	°C
Tstg	Max Operating Junction Temperature	-65 to 150	°C

(*) ISD ≤ 22A, di/dt ≤ 400A/µs, VDD = 80% V(BR)DSS

Table 4: Thermal Data

Rthj-case	Thermal Resistance Junction-case Max	1.25	°C/W
Rthj-amb	Thermal Resistance Junction-ambient Max	100	°C/W
Rthj-ambTl	Thermal Resistance Junction-pcb (*)	43	°C/W
	Maximum Lead Temperature For Soldering Purpose	275	°C

(*) When mounted on 1 inch² FR-4 board, 2 oz Cu, t≤ 10 sec

Table 5: Avalanche Characteristics

Symbol	Parameter	Max Value	Unit
IAS	Avalanche Current, Repetitive or Not-Repetitive	22	A
	(pulse width limited by Tj max)
EAS	Single Pulse Avalanche Energy	380	mJ
	(starting Tj = 25 °C, ID = 22 A, VDD = 50 V)

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ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED)

Table 6: On/Off

Symbol	Parameter	Test Conditions	Min.	Typ.	Max.	Unit
V(BR)DSS	Drain-source	ID = 1mA, VGS = 0	200			V
	Breakdown Voltage
IDSS	Zero Gate Voltage	VDS = Max Rating			1	µA
	Drain Current (VGS = 0)	VDS = Max Rating, TC = 125 °C			10	µA
IGSS	Gate-body Leakage	VGS = ± 20V			100	nA
	Current (VDS = 0)
VGS(th)	Gate Threshold Voltage	VDS = VGS, ID = 250 µA	3.5	4.2	5	V
RDS(on)	Static Drain-source On	VGS = 10V, ID = 11 A		0.088	0.105	Ω
	Resistance

Table 7: Dynamic

Symbol	Parameter	Test Conditions	Min.	Typ.	Max.	Unit
gfs (2)	Forward Transconductance	VDS = 15 V, ID=11 A		8		S
Ciss	Input Capacitance	VDS = 25V, f = 1 MHz, VGS = 0		800		pF
Coss	Output Capacitance			330		pF
Crss	Reverse Transfer			130		pF
	Capacitance
Coss eq. (**)	Equivalent Output	VGS = 0 V, VDS = 0 V to 400 V		225		pF
	Capacitiance
RG	Gate Input Resistance	f= 1MHz Gate DC Bias = 0		5		Ω
		Test Sgnal Level = 20 mV
		Open Drain
td(on)	Turn-on Delay Time	VDD = 100 V, ID = 11 A		40		ns
tr	Rise Time	RG = 4.7Ω VGS = 10 V		15		ns
tr(Voff)	Turn-off Delay Time	(see Figure 15)		40		ns
tf	Fall Time			11		ns
Qg	Total Gate Charge	VDD = 100 V, ID = 20 A,		32	50	nC
Qgs	Gate-Source Charge	VGS = 10 V		6		nC
Qgd	Gate-Drain Charge	(see Figure 19)		25		nC

(**) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS

Table 8: Source Drain Diode

Symbol	Parameter	Test Conditions		Min.	Typ.	Max.	Unit
ISD	Source-drain Current					22	A
ISDM (1)	Source-drain Current (pulsed)					88	A
VSD (2)	Forward On Voltage	ISD = 20	A, VGS = 0			1.3	V
trr	Reverse Recovery Time	ISD = 20	A, di/dt = 100 A/µs		160		ns
Qrr	Reverse Recovery Charge	VDD = 100V, Tj = 25°C			960		µC
IRRM	Reverse Recovery Current	(see test circuit, Figure 17)			12.8		A
trr	Reverse Recovery Time	ISD = 20	A, di/dt = 100 A/µs		225		ns
Qrr	Reverse Recovery Charge	VDD = 100V, Tj = 150°C			1642		µC
IRRM	Reverse Recovery Current	(see test circuit, Figure 17)			15		A

(1)Pulse width limited by safe operating area.

(2)Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %

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