ST MICROELECTRONICS STD16NF06L Datasheet

N-CHANNEL 60V - 0.060 - 24A DPAK/IPAK
3
3
TYPE
V
DSS
STD16NF06L 60 V < 0.070 24 A
TYPICAL R
LOGIC LEVEL DEVICE
THROUGH-HOLE IPAK (TO-251) POWER
DS
PACKAGE IN TUBE (SUFFIX “-1")
SURFACE-MOUNTING DPAK (TO-252)
POWER PACKAGE IN TAPE & REEL (SUFFIX “T4")
DESCRIPTION
This Power MOSFET is the latest development of STMicroelectronis unique "Single Feature Size™" strip-based process. The resulting transistor shows extremely high p acking density for low on­resistance, rugged ava lanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility
R
DS(on)
I
D
STD16NF06L
STripFET™ II POWER MOSFET
Figure 1:PackageTable 1: General Features
2
1
IPAK
TO-251
(Suffix “-1”)
(Suffix “T4”)
Figure 2: Internal Schematic Diagram
1
DPAK
TO-252
APPLICATIONS
SWITCHING APPLICATIONS
Table 2: Order Codes
STD16NF06LT4 D16NF06L TO-252 TAPE & REEL STD16NF06L-1 D16NF06L TO-251 TUBE
SALES TYPE MARKING PACKAGE PACKAGING
Table 3: ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
DS
V
DGR
V
GS
I
D
I
D
(•)
I
DM
P
tot
dv/dt
E
AS
T
stg
T
j
(•) Pulse width limited by safe operating area. (1) I
Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 kΩ)
60 V
60 V Gate- source Voltage ± 18 V Drain Current (conti nuo us ) at TC = 25°C Drain Current (conti nuo us ) at TC = 100°C
24 A
17 A Drain Current (pulse d) 96 A Total Dissipation at TC = 25°C
40 W Derating Factor 0.27 W/°C
(1)
Peak Diode Recovery voltage slope 11.5 V/ns
(2)
Single Pulse Avalanche Energy 200 mJ Storage Temperature Operating Junction Temperature
16A, di/dt 200A/µs, VDD V
SD
(2) Starting Tj = 25 oC, ID = 20A, VDD= 48V
-55 to 175 °C
(BR)DSS
, Tj T
JMAX
Rev. 3.0
1/11March 2005
STD16NF06L
Table 4: THERMAL DATA
Rthj-case
Rthj-pcb
T
(*)
When Mounted on 1 inch2 FR-4 board, 2 oz of Cu
Thermal Resistance Junction-case
(*)
Thermal Resistance Junction-PCB
Maximum Lead Temperature For Soldering Purpose
l
(1.6 mm from case, for 10 sec)
Max Max
3.75 62
275
°C/W °C/W
°C
ELECTRICAL CHARACTERISTICS (T
= 25 °C UNLESS OTHERWISE SPECIFIED)
CASE
Table 5: OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
V
(BR)DSS
Drain-source
= 250 µA, VGS = 0
D
60 V
Breakdown Voltage
= Max Rating
I
DSS
I
GSS
Table 6: ON
Zero Gate Voltage Drain Current (V
Gate-body Leakage Current (V
(5)
DS
= 0)
GS
= 0)
V
DS
= Max Rating TC = 125°C
V
DS
= ± 18V
V
GS
1
10
±100 nA
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
GS(th)
R
DS(on)
Gate Threshold Voltage Static Drain-source On
Resistance
V
= VGS ID = 250 µA
DS
V
= 10 V ID = 8 A
GS
= 5 V ID = 8 A
V
GS
1V
0.060
0.070
0.070
0.085
Table 7: DYNAMIC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
(*)
g
fs
C
iss
C
oss
C
rss
Forward Transconductance Input Capacitance
Output Capacitance Reverse Transfer Capacitance
V
15 V
V
DS =
DS
ID
= 25V f = 1 MHz VGS = 0
= 12 A
12 S
370
69 30
µA µA
Ω Ω
pF pF pF
2/11
STD16NF06L
ELECTRICAL CHARACTERISTICS (continued)
Table 8: SWITCHING ON
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
t
d(on)
Q Q Q
t
r
g gs gd
Turn-on Delay Time Rise Time
Total Ga te Char ge Gate-Source Charg e Gate-Drain Charge
Table 9: SWITCHING OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
d(off)
t
f
Turn-off Delay Time Fall Time
Table 10: SOURCE DRAIN DIODE
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
SDM
V
SD
t
rr
Q
rr
I
RRM
(1 )
Pulse width limited by safe operating area.
(2)
Pulsed: Pulse duration = 300 µs , duty cycle 1.5 %.
Source-drain Curre nt
)
Source-drain Curre nt (pu lse d)
(•
(*)
Forward On Voltage Reverse Recovery Time
Reverse Recovery Charge Reverse Recovery Current
= 30 V ID = 8 A
DD
=4.7 Ω VGS = 5 V
R
G
(Resistive Load, Figu re 17)
V
= 30 V ID= 16 A VGS= 5 V
DD
V
= 30 V ID = 8 A
DD
=4.7Ω, V
R
G
GS
= 5 V
(Resistive Load, Figu re 17)
I
= 64 A VGS = 0
SD
I
=16 A di/dt = 100A/µs
SD
= 25 V Tj = 150°C
V
DD
(see test circuit, Figure 19)
12 30
7.5
2.5
4.2
20
6
16 64
1.5 V
53 85
3.2
ns ns
nC nC nC
ns ns
A A
ns
µC
A
Figure 3: Safe Operating Area Figure 4: Therm al Im pe da nce
3/11
STD16NF06L
Figure 5: Output Characteristics Figure 6: Transf er Ch ar ac ter ist ics
Figure 7: Transconductance Figure 8: Static Drain-source On Resistance
Figure 9: Gate Charge vs Gate-source Voltage Figure 10: Capacitance Variations
4/11
STD16NF06L
Figure 11: Normalized Gate Threshold Voltage vs
Temperature
Figure 13: Source-drain Diode Forward
Characteristics
Figure 12: Normalized on Resist an c e vs Te mpe r at ur e
Figure 14: Normalized Breakdown Voltage vs
Temperature.
.
.
5/11
STD16NF06L
Figure 15: Unclamped Inductive Load Test Circuit
Figure 17: Switching Times Test Circuits For Resis-
tive Load
Figure 16: Unclamped Inductive Waveform
Figure 18: Gate Charge test Circuit
Figure 19: Test C ircuit For In ductive Lo ad Switchin g
And Diode Recovery Times
6/11
TO-252 (DPAK) MECHANICAL DAT A
STD16NF06L
DIM.
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 2.2 2.4 0.086 0.094 A1 0.9 1.1 0.035 0.043 A2 0.03 0.23 0.001 0.009
B 0.64 0.9 0.025 0.035 B2 5.2 5.4 0.204 0.212
C 0.45 0.6 0.017 0.023 C2 0.48 0.6 0.019 0.023
D 6 6.2 0.236 0.244
E 6.4 6.6 0.252 0.260
G 4.4 4.6 0.173 0.181
H 9.35 10.1 0.368 0.397 L2 0.8 0.031 L4 0.6 1 0.023 0.039
A
C2
E
==
L2
B2
==
H
DETAIL "A"
D
C
B
2
1 3
L4
A1
G
==
A2
DETAIL "A"
0068772-B
7/11
STD16NF06L
TO-251 (IPAK) MECHANICAL DAT A
DIM.
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 2.2 2.4 0.086 0.094 A1 0.9 1.1 0.035 0.043 A3 0.7 1.3 0.027 0.051
B 0.64 0.9 0.025 0.031 B2 5.2 5.4 0.204 0.212 B3 0.85 0.033 B5 0.3 0.012 B6 0.95 0.037
C 0.45 0.6 0.017 0.023 C2 0.48 0.6 0.019 0.023
D 6 6.2 0.236 0.244
E 6.4 6.6 0.252 0.260
G 4.4 4.6 0.173 0.181
H 15.9 16.3 0.626 0.641
L 9 9.4 0.354 0.370 L1 0.8 1.2 0.031 0.047 L2 0.8 1 0.031 0.039
A
E
= =
C2
L2
B2
= =
H
C
A3
A1
B6
L
B
B5
G
= =
D
B3
2
1 3
L1
0068771-E
8/11
STD16NF06L
*on sales type
9/11
STD16NF06L
Table 11:Revision History
Date Revision Description of Changes
March 2005
3.0 ADDED PACKAGE TO-251
10/11
STD16NF06L
I
s
o
d
b
ct
t
ot
a
nformation furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequence
f use of such information nor for any infrin gement of patents or other rights of third parties which may resul t from its use. No license is grant e y implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subje
o change without notice. This publication supersed es and replaces all information previously supplied. ST Microelectronics products are n
uthorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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11/11
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