STMicroelectronics STB5NK50ZT4, STD5NK50ZT4 Schematic [ru]
STB5NK50Z/-1 - STD5NK50Z/-1
STP5NK50Z - STP5NK50ZFP
N-CHANNEL 500V - 1.22Ω - 4.4A TO-220/FP-D/IPAK-D2/I2PAK
Zener-Protected SuperMESH™MOSFET
Table 1: Ge neral Features
TYPE V
STB5NK50Z
STB5NK50Z-1
STD5NK50Z
STD5NK50Z-1
STP5K50Z
STP5K50ZFP
■ TYPICAL R
■ EXTREMELY HIGH dv/d t C APABILITY
■ IMPROVED ESD CAPABILITY
■ 100% AVALANCHE RATED
■ GATE CHARGE MINIMIZED
■ VERY LOW INTRINSIC CAPACITANCES
■ VERY GOOD MANUFACTURING
500 V
500 V
500 V
500 V
500 V
500 V
(on) = 1.22 Ω
DS
DSS
R
DS(on)
< 1.5 Ω
< 1.5 Ω
< 1.5 Ω
< 1.5 Ω
< 1.5 Ω
< 1.5 Ω
I
D
4.4 A
4.4 A
4.4 A
4.4 A
4.4 A
4.4 A
Pw
70 W
70 W
70 W
70 W
70 W
25 W
REPEATIBILITY
DESCRIPTION
The SuperMESH™ se ries is obtained through an
extreme optimization of ST’s well established
stripbased PowerMESH™ layout. In addition to
pushing on-resistance significantly down , special
care is taken to ensure a very good dv/dt capability
for the most demanding applications. Such series
complements ST full range of high voltage MOS FET s including revolutionary MDmesh™ products.
Figure 1: Package
3
2
1
TO-220
DPAK
I2PAK
3
1
3
1
D2PAK
TO-220FP
IPAK
Figure 2: Internal Schematic Diagram
3
2
1
3
2
1
APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ IDEAL FOR OFF-L INE POWER SUPPL IES,
ADAPTORS AND PFC
■ LIGHTING
Table 2: Order Codes
SALES TYPE MARKING PACKAGE PACKAGING
STB5NK50ZT4 B5NK50Z
STB5NK50Z-1 B5NK50Z
STD5NK50ZT4 D5NK50Z DPAK TAPE & REEL
STD5NK50Z-1 D5NK50Z IPAK TUBE
STP5NK50Z P5NK50Z TO-220 TUBE
STP5NK50ZFP P5NK50ZFP TO-220FP TUBE
2
D
PAK
2
I
PAK
TAPE & REEL
TUBE
Rev. 4
1/17June 2004
STB5NK50Z/-1 - STD5NK50Z/-1 - STP5NK50Z - STP5NK50ZFP
Table 3: Absolute Maximum ratings
Symbol Parameter Value Unit
V
I
V
V
DM
P
DS
DGR
GS
I
D
I
D
TOT
STP5NK50Z
STB5NK50Z/-1
Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)
Gate- source Voltage ± 30 V
Drain Current (continuous) at TC = 25°C
Drain Current (continuous) at TC = 100°C
()
Drain Current (pulsed) 17.6 17.6 (*) 17.6 A
Total Dissipation at TC = 25°C
4.4 4.4 (*) 4.4 A
2.7 2.7 (*) 2.7 A
70 25 70 W
STP5NK50ZFP
500 V
500 V
Derating Factor 0.56 0.2 0.56 W/°C
V
ESD(G-S)
Gate source ESD(HBM-C=100pF, R=1.5KΩ) 3000 V
dv/dt (1) Peak Diode Recovery voltage slope 4.5 V/ns
V
ISO
T
j
T
stg
() Pulse width limited by saf e operating area
≤4.4A, di/dt ≤200A/µs, VDD ≤ V
(1) I
SD
(*) Limited only by maximum temperature allowed
Insulation Withstand Voltage (DC) - 2500 - V
Operating Junction Temperature
Storage Temperature
, Tj ≤ T
(BR)DSS
JMAX.
-55 to 150
-55 to 150
Table 4: Thermal Data
TO-220
2
PAK/D2PAK
I
Rthj-case Thermal Resistance Junction-case Max 1.78 5 1.78 °C/W
Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W
T
l
Maximum Lead Temperature For Soldering Purpose
TO-220FP DPAK
300 °C
STD5NK50Z
STD5NK50Z-1
°C
°C
Table 5: Avalanche Characteristics
Symbol Parameter Max Value Unit
I
AR
E
AS
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
max)
j
Single Pulse Avalanche Energy
(starting T
= 25 °C, ID = IAR, VDD = 50 V)
j
4.4 A
130 mJ
Table 6: Gate-Source Zener Diode
Symbol Parameter Test Conditions Min. Typ. Max. Unit
BV
GSO
Gate-Source Breakdown
Igs=± 1mA (Open Drain) 30 V
Voltage
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES
The built-in back-to-back Zener diodes have specifically been designed t o enhance not only t he device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to p r otect the device’s integrity. These integrated Zener diodes thus avoid the
usage of external components.
2/17
STB5NK50Z/-1 - STD5NK50Z/-1 - STP5NK50Z - STP5NK50ZFP
ELECTRICAL CHARACTERISTICS (T
=25°C UNLESS OTHERWISE SPECIFIED)
CASE
Table 7: On /Off
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
(BR)DSS
Drain-source Breakdown
ID = 1 mA, VGS = 0 500 V
Voltage
I
I
V
GS(th)
R
DS(on
DSS
GSS
Zero Gate Voltage
Drain Current (V
GS
= 0)
Gate-body Leaka ge
Current (V
DS
= 0)
Gate Threshold Voltage
Static Drain-source On
V
= Max Rating
DS
V
= Max Rating, TC = 125°C
DS
V
= ± 20 V ± 10 µA
GS
V
= VGS, ID = 50 µA 3
DS
3.75
1
50
4.5 V
VGS = 10 V, ID = 2.2 A 1.22 1.5 Ω
Resistance
Table 8: Dynamic
Symbol Parameter Test Conditions Min. Typ. Max. Unit
g
(1) Forward Transconductance VDS = 15 V , ID = 2.2 A 3.1 S
fs
C
OSS eq
C
C
C
t
d(on)
t
d(off)
Q
Q
Q
iss
oss
rss
t
r
t
gs
gd
f
g
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
(3).Equivalent Outpu t
Capacitance
Turn-on Delay Time
Rise Time
Turn-off-Delay Time
Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
= 25 V, f = 1 MHz, VGS = 0 535
V
DS
75
17
VGS = 0 V, VDS = 0 to 400 V 45 pF
= 250 V, ID = 2.2 A,
V
DD
RG = 4.7 Ω, V
GS
(see Figure 19)
= 10 V
15
10
32
15
= 400 V, ID = 4.4 A,
V
DD
VGS = 10 V
(see Figure 22)
20
10
28 nC
4
µA
µA
pF
pF
pF
ns
ns
ns
ns
nC
nC
Table 9: Source Drain Diode
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
SDM
(1)
V
SD
t
rr
Q
rr
I
RRM
(1) Pulsed: Pulse duration = 300 µs, duty cycl e 1. 5 %.
(2) Pulse width limited by safe operating area.
(3) C
oss eq.
Source-drain Current
(2)
Source-drain Current (pulsed)
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
is defined as a constant equivalent capacitance giving the same charging time as C
ISD = 4.4 A, VGS = 0
= 4.4 A, di/dt = 100 A/µs
I
SD
VDD = 30V, Tj = 150°C
(see Figure 20)
310
1425
9.2
when VDS increase s from 0 to 80% V
oss
4.4
17.6
1.6 V
A
A
ns
nC
A
DSS
3/17
.
STB5NK50Z/-1 - STD5NK50Z/-1 - STP5NK50Z - STP5NK50ZFP
Figure 3: Safe Operating Area For DPAK/IPAK/
2
PAK/I2PAK/TO-220
D
Figure 4: Thermal Impedance For DPAK/IPAK/
2
D
PAK/I2PAK/TO-220
Figure 6: Safe Operating Area For TO-220FP
Figure 7: Thermal Impedance For TO-220FP
Figure 5: Output Characteristics
4/17
Figure 8: Transfer Characteristics
STB5NK50Z/-1 - STD5NK50Z/-1 - STP5NK50Z - STP5NK50ZFP
Figure 9: Transconductance
Figure 10: Gate Charge vs Gate-source Voltage
Figure 12: Static Drain-Source On Resis tance
Figure 13: Capacitance Variations
Figure 11: Normalized Gate Threshold Voltage
vs Tem pera tur e
Figure 14: Normal ized On R esistance vs Temperature
5/17
STB5NK50Z/-1 - STD5NK50Z/-1 - STP5NK50Z - STP5NK50ZFP
Figure 15: S ource-Drain Forward Char acteristics
Figure 16: Maximum Avalanche Energy vs
Temperature
Figure 17: Normalized BV
vs Temperature
DSS
6/17
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