1
3
TAB
2
3
DPAK
TAB
1
D2PAK
2
D(2, TAB)
G(1)
S(3)
NG1D2TS3Z
STB13N60M2, STD13N60M2
Datasheet
N-channel 600 V, 0.35 Ω typ., 11 A MDmesh™ M2 Power MOSFETs in D²PAK
and DPAK packages
Features
Product status link
STB13N60M2
STD13N60M2
Order code
STB13N60M2
STD13N60M2 DPAK
VDS@T
JMAX.
650 V 0.38 Ω 11 A
R
max. I
DS(on)
D
Package
D²PAK
• Extremely low gate charge
• Excellent output capacitance (C
OSS
) profile
• 100% avalanche tested
• Zener-protected
Applications
• Switching applications
Description
These devices are N-channel Power MOSFETs developed using the MDmesh™ M2
technology. Thanks to their strip layout and improved vertical structure, these devices
exhibit low on-resistance and optimized switching characteristics, rendering them
suitable for the most demanding high-efficiency converters.
Product summary
Order code STB13N60M2
Marking 13N60M2
Package D²PAK
Packing Tape and reel
Order code STD13N60M2
Marking 13N60M2
Package DPAK
Packing Tape and reel
DS9632 - Rev 5 - February 2019
For further information contact your local STMicroelectronics sales office.
www.st.com
1 Electrical ratings
Symbol Parameter Value Unit
V
GS
I
D
I
D
(1)
IDM
P
TOT
dv/dt
dv/dt
T
stg
T
j
1. Pulse width limited by safe operating area.
2. ISD ≤ 11 A, di/dt ≤ 400 A/µs; V
3. VDS ≤ 480 V.
Gate-source voltage ± 25 V
Drain current (continuous) at TC = 25 °C
Drain current (continuous) at TC = 100 °C
Drain current (pulsed) 44 A
Total power dissipation at TC = 25 °C
(2)
Peak diode recovery voltage slope 15
(3)
MOSFET dv/dt ruggedness 50
Storage temperature range
Operating junction temperature range
DS peak
Table 1. Absolute maximum ratings
< V
(BR)DSS
, VDD = 400 V
STB13N60M2, STD13N60M2
Electrical ratings
11 A
7 A
110 W
V/ns
- 55 to 150 °C
Table 2. Thermal data
Symbol
R
thj-case
R
thj-pcb
1. When mounted on FR-4 board of 1 inch², 2 oz Cu.
Parameter
Thermal resistance junction-case 1.14
(1)
Thermal resistance junction-pcb 30 50
Table 3. Avalanche characteristics
Symbol
I
E
Parameter Value Unit
Avalanche current, repetetive or not repetetive (pulse width limited by T
AR
Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR; VDD = 50 V)
AS
Value
D²PAK DPAK
)
jmax.
Unit
°C/W
2.8 A
125 mJ
DS9632 - Rev 5
page 2/23
2 Electrical characteristics
TC = 25 °C unless otherwise specified
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
1. Defined by design, not subject to production test.
Drain-source breakdown
voltage
Zero-gate voltage drain
current
Gate-body leakage current
Gate threshold voltage
Static drain-source onresistance
STB13N60M2, STD13N60M2
Table 4. On/off-states
VGS = 0 V, ID = 1 mA
VGS = 0 V, VDS = 600 V
VGS = 0 V, VDS = 600 V, TC = 125 °C
VDS = 0 V, VGS = ±25 V
VDS = VGS, ID = 250 µA
VGS = 10 V, ID = 5.5 A
Electrical characteristics
600 V
(1)
2 3 4 V
0.35 0.38 Ω
1 µA
100 µA
±10 µA
C
1. C
Symbol
Table 5. Dynamic
Symbol
C
iss
C
oss
C
rss
oss eq.
R
G
Q
g
Q
gs
Q
gd
oss eq.
to 80% V
Parameter Test conditions Min. Typ. Max. Unit
Input capacitance
Output capacitance - 32 - pF
VDS= 100 V, f = 1 MHz, VGS = 0 V
Reverse transfer capacitance - 1.1 - pF
(1)
Equivalent output capacitance
Intrinsic gate resistance
Total gate charge
Gate-source charge - 2.5 - nC
Gate-drain charge - 9 - nC
VDS = 0 to 480 V, VGS = 0 V
f = 1 MHz, ID = 0 A
VDD = 480 V, ID = 11 A, VGS = 0 to 10 V
(see Figure 16. Test circuit for gate
charge behavior)
is defined as a constant equivalent capacitance giving the same charging time as C
DSS.
Table 6. Switching times
Parameter Test conditions Min. Typ. Max. Unit
t
d(on)
t
d(off)
t
t
Turn-on delay time
Rise time - 10 - ns
r
Turn-off-delay time - 41 - ns
Fall time - 9.5 - ns
f
VDD = 300 V, ID = 5.5 A, RG = 4.7 Ω,
VGS = 10 V (see Figure 15. Test circuit for
resistive load switching times and
Figure 20. Switching time waveform)
- 580 - pF
- 120 - pF
- 6.6 - Ω
- 17 - nC
when VDS increases from 0
oss
- 11 - ns
DS9632 - Rev 5
page 3/23
STB13N60M2, STD13N60M2
Electrical characteristics
Table 7. Source-drain diode
Symbol Parameter Test conditions Min. Typ. Max. Unit
I
SD
I
SDM
V
SD
t
Q
I
RRM
t
Q
I
RRM
1. Pulse width is limited by safe operating area.
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%.
Source-drain current - 11 A
(1)
Source-drain current (pulsed) - 44 A
(2)
Forward on voltage
Reverse recovery time
rr
Reverse recovery charge - 2.8 µC
rr
Reverse recovery current - 18.5 A
Reverse recovery time
rr
Reverse recovery charge - 3.8 µC
rr
Reverse recovery current - 19 A
VGS = 0 V, ISD = 11 A
ISD = 11 A, di/dt = 100 A/µs, VDD = 60 V
(see Figure 17. Test circuit for inductive
load switching and diode recovery times)
ISD = 11 A, di/dt = 100 A/µs, VDD = 60 V,
Tj = 150 °C (see Figure 17. Test circuit for
inductive load switching and diode
recovery times)
- 1.6 V
- 297 ns
- 394 ns
DS9632 - Rev 5
page 4/23
2.1 Electrical characteristics (curves)
ID
10
1
0.1
1
100
VDS(V)
10
(A)
Operation in this area is
Limited by max. RDS(on)
10 ms
1 ms
0.1
Tj=150 °C
Tc=25 °C
Single pulse
100 µs
10 µs
AM15710v1
ID
10
1
0.1
1
100
VDS(V)
10
(A)
Operation in this area is
Limited by max. RDS(on)
10 ms
1 ms
0.1
Tj=150 °C
Tc=25 °C
Single pulse
100 µs
10 µs
AM15711v1
GC20460
10
0
10
-1
10
-2
10-510-410-310-210
-1
K
tp (s)
ID
12
8
4
0
0
8
VDS(V)
(A)
4
12
16
4V
5V
6V
VGS=7, 8, 9, 10V
16
20
AM15712v1
ID
4
0
0
4
VGS(V)
8
(A)
2
6
8
12
VDS=18 V
16
20
AM15713v1
STB13N60M2, STD13N60M2
Electrical characteristics (curves)
Figure 1. Safe operating area for D2PAK
Figure 3. Safe operating area for DPAK
Figure 2. Thermal impedance for D2PAK
Figure 4. Thermal impedance for DPAK
Figure 5. Output characteristics
DS9632 - Rev 5
Figure 6. Transfer characteristics
page 5/23
V(BR)DSS
-50
TJ(°C)
(norm)
0
0.9
0.94
0.98
1.02
1.06
ID=1 mA
50
100
1.1
AM15714v1
R DS(on)
0.360
0.350
0.340
0.330
0
4
ID(A)
(Ω)
2
6
0.370
8
10
VGS=10 V
AM15715v1
VGS
6
4
2
0
0
Qg(nC)
(V)
8
8
4
10
VDD = 480 V
300
200
100
0
400
VDS
12
16
500
VDS
(V)
ID=11 A
AM15716v1
C
10
1
0.1
0.1
10
VDS(V)
(pF)
1
100
Ciss
Coss
Crss
100
1000
AM15717v1
VGS(th)
0.9
0.8
0.7
0.6
TJ(°C)
(norm)
-50
1.0
ID=250µA
0
50
100
1.1
AM15718v1
VGS = 10 V
ID = 5.5 A
RDS(on)
2.1
1.7
1.3
0.9
TJ(°C)
(norm)
0.5
-50
0
50
100
AM15719v1
STB13N60M2, STD13N60M2
Electrical characteristics (curves)
Figure 7. Normalized V
vs. temperature
(BR)DSS
Figure 9. Gate charge vs. gate-source voltage
Figure 8. Static drain-source on-resistance
Figure 10. Capacitance variations
DS9632 - Rev 5
Figure 11. Normalized gate threshold voltage vs.
temperature
Figure 12. Normalized on-resistance vs. temperature
page 6/23
VSD
0
4
ISD (A)
(V)
2
10
6
8
0.5
0.6
0.7
0.8
TJ =-50 °C
TJ=150 °C
TJ=25 °C
0.9
1
AM15720v1
Eoss
0
VDS(V)
(µJ)
200
100
500
0
1
2
3
4
300
400
AM15721v1
STB13N60M2, STD13N60M2
Electrical characteristics (curves)
Figure 13. Source-drain diode forward characteristics
Figure 14. Output capacitance stored energy
DS9632 - Rev 5
page 7/23
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