November 2017
DocID9522 Rev 8
1/19
This is information on a product in full production.
www.st.com
STB120NF10T4, STP120NF10,
STW120NF10
N-channel 100 V, 9.0 mΩ typ., 110 A STripFET™ II
Power MOSFETs in D²PAK, TO-220 and TO-247 packages
Datasheet - production data
Order code
VDS
R
DS(on)
max.
ID
STB120NF10T4
100 V
10.5 mΩ
110 A
STP120NF10
STW120NF10
Order code
Marking
Package
Packing
STB120NF10T4
B120NF10
D2PAK
Tape and reel
STP120NF10
P120NF10
TO-220
Tube
STW120NF10
120NF10
TO-247
1
2
3
TO-247
1
2
3
TAB
TO-220
TAB
D PAK
2
AM01475v1_noZen
D(2, TAB)
G(1)
S(3)
Features
Exceptional dv/dt capability
100% avalanche tested
Low gate charge
Applications
Figure 1: Internal schematic diagram
Switching applications
Description
These Power MOSFETs have been developed
using STMicroelectronics’ unique STripFET
process, which is specifically designed to
minimize input capacitance and gate charge.
This renders the devices suitable for use as
primary switch in advanced high-efficiency
isolated DC-DC converters for telecom and
computer applications, and applications with low
gate charge driving requirements.
Table 1: Device summary
Contents
STB120NF10T4, STP120NF10, STW120NF10
2/19
DocID9522 Rev 8
Contents
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1 Electrical characteristics (curves) ...................................................... 6
3 Test circuits ..................................................................................... 8
4 Package information ....................................................................... 9
4.1 D²PAK (TO-263) type A2 package information ................................. 9
4.2 D²PAK packing information ............................................................. 12
4.3 TO-220 package information ........................................................... 14
4.4 TO-247 package information ........................................................... 16
5 Revision history ............................................................................ 18
STB120NF10T4, STP120NF10, STW120NF10
Electrical ratings
DocID9522 Rev 8
3/19
Symbol
Parameter
Value
Unit
VDS
Drain-source voltage
100
V
VGS
Gate-source voltage
±20
V
ID
Drain current (continuous) at TC = 25 °C
110
A
Drain current (continuous) at TC = 100 °C
77
A
I
DM
(1)
Drain current (pulsed)
440
A
P
TOT
Total dissipation at TC = 25 °C
312
W
dv/dt
(2)
Peak diode recovery voltage slope
10
V/ns
E
AS
(3)
Single pulse avalanche energy
550
mJ
Tj
Operating junction temperature range
-55 to 175
°C
T
stg
Storage temperature range
Notes:
(1)
Pulse width is limited by safe operating area.
(2)
ISD ≤ 110 A, di/dt ≤ 300 A/μs, VDD = 80% V
(BR)DSS
(3)
Starting Tj =25 °C, ID = 60 A, VDD = 50 V
Symbol
Parameter
Value
Unit
TO-220
TO-247
D2PAK
R
thj-case
Thermal resistance junction-case
0.48
°C/W
R
thj-amb
Thermal resistance junction-ambient
62.5
°C/W
R
thj-pcb
Thermal resistance junction-pcb
(1)
35
°C/W
Notes:
(1)
When mounted on an 1-inch2 FR-4, 2 Oz copper board.
1 Electrical ratings
Table 2: Absolute maximum ratings
Table 3: Thermal data
Electrical characteristics
STB120NF10T4, STP120NF10, STW120NF10
4/19
DocID9522 Rev 8
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
V
(BR)DSS
Drain-source breakdown
voltage
VGS = 0 V, ID = 250 µA
100
V
I
DSS
Zero gate voltage drain
current
V
GS
= 0 V, VDS = 100 V
1
µA
VGS = 0 V, VDS= 100 V,
Tc = 125 °C
(1)
10
µA
I
GSS
Gate-source leakage current
V
DS
= 0 V, V
GS
= ±20 V
±100
nA
V
GS(th)
Gate threshold voltage
VDS = VGS, ID = 250 µA
2 4 V
R
DS(on)
Static drain-source
on-resistance
VGS = 10 V, ID = 60 A
9.0
10.5
mΩ
Notes:
(1)
Defined by design, not subject to production test.
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
C
iss
Input capacitance
VDS = 25 V, f = 1 MHz,
VGS= 0 V
-
5200
pF
C
oss
Output capacitance
785
pF
C
rss
Reverse transfer capacitance
325
pF
Qg
Total gate charge
V
DD
= 80 V, ID= 120 A,
V
GS
= 0 to 10 V
(see Figure 14: "Test
circuit for gate charge
behavior" )
-
172
233
(1)
nC
Qgs
Gate-source charge
32
nC
Qgd
Gate-drain charge
64 nC
Notes:
(1)
Defined by design, not subject to production test.
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
t
d(on)
Turn-on delay time
VDD = 50 V, ID = 60 A,
RG = 4.7 Ω, V
GS
= 10 V
(see Figure 13: "Test circuit
for resistive load switching
times" and Figure 18:
"Switching time waveform")
-
25 - ns
tr
Rise time
-
90 - ns
t
d(off)
Turn-off delay time
-
132 - ns
tf
Fall time
-
68 - ns
2 Electrical characteristics
(T
= 25 °C unless otherwise specified)
CASE
Table 4: On/off states
Table 5: Dynamic
Table 6: Switching times
STB120NF10T4, STP120NF10, STW120NF10
Electrical characteristics
DocID9522 Rev 8
5/19
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
ISD
Source drain current
-
110
A
I
SDM
(1)
Source-drain current
(pulsed)
- 440
A
V
SD
(2)
Forward on voltage
ISD = 120 A, VGS= 0 V
-
1.3 V trr
Reverse recovery time
ISD = 120 A, di/dt = 100 A/µs,
VDD = 40 V, Tj = 150 °C
(see Figure 15: "Test circuit for
inductive load switching and
diode recovery times")
-
152
ns
Qrr
Reverse recovery charge
-
760
nC
I
RRM
Reverse recovery current
-
10 A
Notes:
(1)
Pulse width is limited by safe operating area.
(2)
Pulsed: pulse duration = 300 µs, duty cycle 1.5%
Table 7: Source drain diode
Electrical characteristics
STB120NF10T4, STP120NF10, STW120NF10
6/19
DocID9522 Rev 8
Figure 2: Safe operating area
Figure 3: Thermal impedance
Figure 4: Output characteristics
Figure 5: Transfer characteristics
Figure 6: Normalized V
(BR)DSS
vs temperature
Figure 7: Static drain-source on-resistance
2.1 Electrical characteristics (curves)
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