ST MICROELECTRONICS STB11NK50Z Datasheet
Features
Typ e V
STB11NK50Z - STP11NK50ZFP
STP11NK50Z
N-channel 500 V, 0.48 Ω , 10 A TO-220, TO-220FP, D2PA K
TM
Power MOSFET
DSS
Zener-protected SuperMESH
R
DS(on)
max
I
Pw
D
STB11NK50Z 500 V < 0.52 Ω 10 A 125 W
STP11NK50ZFP 500 V < 0.52 Ω 10 A 30 W
STP11NK50Z 500 V < 0.52 Ω 10 A 125 W
■ Extremely high dv/dt capability
■ 100% avalanche tested
■ Gate charge minimized
■ Very low intrinsic capacitances
Application
■ Switching applications
Description
The SuperMESH™ series is obtained through an
extreme optimization of ST’s well established
strip-based PowerMESH™ layout. In addition to
pushing on-resistance significantly down, special
care is taken to ensure a very good dv/dt
capability for the most demanding applications.
3
2
1
TO-220
3
1
2
PAK
D
TO-220FP
Figure 1. Internal schematic diagram
3
2
1
Table 1. Device summary
Order codes Marking Package Packaging
STB11NK50ZT4 B11NK50Z D²PAK Tape and reel
STP11NK50ZFP P11NK50ZFP TO-220FP Tube
STP11NK50Z P11NK50Z TO-220 Tube
May 2008 Rev 6 1/16
www.st.com
16
Contents STB11NK50Z - STP11NK50ZFP - STP11NK50Z
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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STB11NK50Z - STP11NK50ZFP - STP11NK50Z Electrical ratings
1 Electrical ratings
Table 2. Absolute maximum ratings
Val ue
Symbol Parameter
I
V
V
DM
P
DS
GS
I
D
I
D
TOT
Drain-source voltage (VGS = 0) 500 V
Gate-source voltage ± 30 V
Drain current (continuous) at TC = 25 °C 10 10
Drain current (continuous) at TC=100 °C 6.3 6.3
(2)
Drain current (pulsed) 40 40
Total dissipation at TC = 25 °C 125 30 W
Derating factor 1 0.24 W/°C
V
ESD(G-S)
dv/dt
V
ISO
T
T
stg
1. Limited only by maximum temperature allowed
2. Pulse width limited by safe operating area
3. ISD ≤ 10 A, di/dt ≤ 200 A/µs, VDD ≤ V
Table 3. Thermal data
Gate source ESD (HBM-C= 100 pF,
R= 1.5 kΩ)
(3)
Peak diode recovery voltage slope 4.5 V/ns
Insulation withstand voltage (DC) -- 2500 V
Operating junction temperature
J
Storage temperature
(BR)DSS
, Tj ≤ T
JMAX
TO-220
D²PAK
TO-220FP
(1)
(1)
(1)
Unit
A
A
A
4000 V
-55 to 150 °C
.
Val ue
Symbol Parameter
R
thj-case
R
thj-a
T
Table 4. Avalanche characteristics
Thermal resistance junction-case max 1 4.2 °C/W
Thermal resistance junction-ambient max 62.5 °C/W
Maximum lead temperature for soldering
l
purpose
TO-220
D²PAK
TO-220FP
300 °C
Symbol Parameter Value Unit
I
AS
E
AS
Avalanche current, repetitive or notrepetitive (pulse width limited by Tj max)
Single pulse avalanche energy
(starting T
= 25 °C, ID=IAR, VDD = 50 V)
J
10 A
190 mJ
Unit
3/16
Electrical characteristics STB11NK50Z - STP11NK50ZFP - STP11NK50Z
2 Electrical characteristics
(T
= 25 °C unless otherwise specified)
CASE
Table 5. On/off states
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Drain-source breakdown
voltage
Zero gate voltage drain
current (VGS = 0)
Gate body leakage current
= 0)
(V
DS
Gate threshold voltage
Static drain-source on
resistance
= 1 mA, VGS= 0
I
D
V
= Max rating,
DS
V
= Max rating @125 °C
DS
= ±20 V
V
GS
= VGS, ID = 100 µA
V
DS
VGS= 10 V, ID= 4.5 A
500 V
1
50
±10 µA
33.754.5 V
0.48 0.52 Ω
Table 6. Dynamic
Symbol Parameter Test conditions Min. Typ. Max. Unit
(1)
g
fs
C
C
C
C
oss eq
Q
Q
Q
1. Pulsed: pulse duration=300µs, duty cycle 1.5%
2. C
increases from 0 to 80% V
Forward transconductance
Input capacitance
iss
Output capacitance
oss
Reverse transfer
rss
capacitance
(2)
Equivalent output
.
capacitance
g
Total gate charge
Gate-source charge
gs
Gate-drain charge
gd
is defined as a constant equivalent capacitance giving the same charging time as C
oss eq.
DSS
V
=15 V, ID = 4.5 A
DS
=25 V, f=1 MHz, VGS=0
V
DS
VGS=0, V
=400 V, ID = 11.4 A
V
DD
=10 V
V
GS
=0 to 400 V
DS
(see Figure 18)
7.7 S
1390
173
42
110 pF
49
68 nC
10
25
when VDS
oss
µA
µA
pF
pF
pF
nC
nC
4/16
STB11NK50Z - STP11NK50ZFP - STP11NK50Z Electrical characteristics
Table 7. Switching times
Symbol Parameter Test conditions Min. Typ. Max. Unit
= 250 V, ID=5.5 A,
V
t
d(on)
t
d(off)
t
r(Voff)
t
Turn-on delay time
t
Rise time
r
Turn-off delay time
t
Fall time
f
Off-voltage rise time
t
Fall time
f
Cross-over time
c
DD
= 4.7 Ω, VGS=10 V
R
G
(see Figure 19)
V
= 250 V, ID=5.5 A,
DD
= 4.7 Ω, VGS=10 V
R
G
(see Figure 19)
=400 V, ID=11.4 A,
V
DD
=4.7 Ω, VGS=10 V
R
G
(see Figure 19)
14.5
18
41
15
11.5
12
27
ns
ns
ns
ns
ns
ns
ns
Table 8. Source drain diode
Symbol Parameter Test conditions Min Typ. Max Unit
I
SD
I
SDM
V
SD
t
Q
I
RRM
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration=300µs, duty cycle 1.5%
Source-drain current 10 A
(1)
Source-drain current (pulsed) 40 A
(2)
Forward on voltage
rr
Reverse recovery time
Reverse recovery charge
rr
Reverse recovery current
=10 A, VGS=0
I
SD
=10 A,
I
SD
di/dt = 100 A/µs,
=45 V, Tj=150 °C
V
DD
308
2.4
16
1.6 V
Table 9. Gate-source Zener diode
Symbol Parameter Test conditions Min. Typ. Max. Unit
(1)
BV
GSO
1. The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the
usage of external components.
Gate-source breakdown voltage Igs=±1mA (open drain) 30 V
ns
µC
A
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