Features
• Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (V
• User-selectable Internal Organization
– 2K: 256 x 8 or 128 x 16
– 4K: 512 x 8 or 256 x 16
• Three-wire Serial Interface
• Sequential Read Operation
• 2 MHz Clock Rate (5V)
• Self-timed Write Cycle (10 ms Max)
• High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• Automotive Devices Available
• 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead Ultra Thin mini-MAP
(MLP 2x3), 8-lead TSSOP and 8-ball dBGA2 Packages
= 1.8V to 5.5V)
CC
Three-wire
Serial
EEPROM
2K (256 x 8 or 128 x 16)
Description
The AT93C56A/66A provides 2048/4096 bits of serial electrically erasable programmable read-only memory (EEPROM) organized as 128/256 words of 16 bits each
(when the ORG pin is connected to VCC) and 256/512 words of 8 bits each (when the
ORG pin is tied to ground). The device is optimized for use in many industrial and
commercial applications where low-power and low-voltage operations are essential.
The AT93C56A/66A is available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8lead EIAJ SOIC,
packages.
The AT93C56A/66A is enabled through the Chip Select pin (CS) and accessed via a
three-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift
Clock (SK). Upon receiving a read instruction at DI, the address is decoded and the
data is clocked out serially on the data output pin DO. The write cycle is completely
self-timed and no separate erase cycle is required before write. The write cycle is only
enabled when the part is in the Erase/Write Enable State. When CS is brought “high”
following the initiation of a write cycle, the DO pin outputs the Ready/Busy status of
the part.
The AT93C56A/66A is available in 2.7V to 5.5V and 1.8V to 5.5V versions.
Table 1. Pin Configurations
Pin Name Function
CS Chip Select
SK Serial Data Clock
DI Serial Data Input
DO Serial Data Output
GND Ground
VCC Power Supply
ORG Internal Organization
NC No Connect
8-lead Ultra Thin mini-MAP (MLP 2x3), 8-lead TSSOP, and 8-ball dBGA2
CS
SK
DI
DO
CS
SK
DI
DO
8-lead SOIC
1
2
3
4
8-lead PDIP
1
2
3
4
8
VCC
7
NC
6
ORG
5
GND
VCC
8
NC
7
ORG
6
GND
5
VCC
8
NC
7
ORG
6
GND
5
8-ball dBGA2
1
8
VCC
NC
ORG
GND
Bottom view
8-lead Ultra Thin mini-MAP (MLP 2x3)
VCC
NC
ORG
GND
2
7
3
6
4
5
8
7
6
5
Bottom view
CS
SK
DI
DO
CS
SK
DI
DO
1
CS
2
SK
3
DI
4
DO
8-lead TSSOP
1
2
3
4
4K (512 x 8 or 256 x 16)
AT93C56A
AT93C66A
3378K–SEEPR–12/06
1
Absolute Maximum Ratings*
Operating Temperature......................................−55°C to +125°C
Storage Temperature .........................................−65°C to +150°C
Voltage on Any Pin
with Respect to Ground........................................ −1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Figure 1. Block Diagram
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
Note: When the ORG pin is connected to VCC, the x 16 organization is selected. When it is connected to ground, the x 8 organization
is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of the internal 1
Meg ohm pullup, then the x 16 organization is selected.
2
AT93C56A/66A
3378K–SEEPR–12/06
AT93C56A/66A
Table 2. Pin Capacitance
(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted)
Symbol Test Conditions Max Units Conditions
C
OUT
C
IN
Output Capacitance (DO) 5 pF V
OUT
= 0V
Input Capacitance (CS, SK, DI) 5 pF VIN = 0V
Note: 1. This parameter is characterized and is not 100% tested.
Table 3. DC Characteristics
Applicable over recommended operating range from: T
V
= +1.8V to +5.5V (unless otherwise noted)
CC
Symbol Parameter Test Condition Min Typ Max Unit
V
CC1
V
CC2
V
CC3
I
CC
I
SB1
I
SB2
I
SB3
I
IL
I
OL
(1)
V
IL1
(1)
V
IH1
(1)
V
IL2
(1)
V
IH2
V
OL1
V
OH1
V
OL2
V
OH2
Note: 1. VIL min and VIH max are reference only and are not tested.
Supply Voltage 1.8 5.5 V
Supply Voltage 2.7 5.5 V
Supply Voltage 4.5 5.5 V
Supply Current VCC = 5.0V
Standby Current VCC = 1.8V CS = 0V 0.4 1.0 µA
Standby Current VCC = 2.7V CS = 0V 6.0 10.0 µA
Standby Current VCC = 5.0V CS = 0V 10.0 15.0 µA
Input Leakage VIN = 0V to VCC 0.1 3.0 µA
Output Leakage VIN = 0V to VCC 0.1 3.0 µA
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
2.7V ≤ V
1.8V ≤ V
2.7V ≤ V
1.8V ≤ V
≤ 5.5V
CC
≤ 2.7V
CC
≤ 5.5V
CC
≤ 2.7V
CC
= −40°C to +85°C, VCC = +1.8V to +5.5V,
AI
READ at 1.0 MHz 0.5 2.0 mA
WRITE at 1.0 MHz 0.5 2.0 mA
−0.6
2.0
−0.6
x 0.7
V
CC
I
= 2.1 mA 0.4 V
OL
= −0.4 mA 2.4 V
I
OH
I
= 0.15 mA 0.2 V
OL
= −100 µAV
I
OH
− 0.2 V
CC
0.8
V
+ 1
CC
V
x 0.3
CC
+ 1
V
CC
V
V
3378K–SEEPR–12/06
3
Table 4. AC Characteristics
Applicable over recommended operating range from T
= −40°C to + 85°C, VCC = As Specified,
AI
CL = 1 TTL Gate and 100 pF (unless otherwise noted)
Symbol Parameter Test Condition Min Typ Max Units
2
1
0.25
250
1000
250
1000
250
1000
150
400
f
SK
t
SKH
t
SKL
t
CS
t
CSS
t
DIS
t
CSH
t
DIH
t
PD1
t
PD0
t
SV
t
DF
t
WP
Endurance
SK Clock
Frequency
SK High Time
SK Low Time
Minimum CS
Low Time
4.5V ≤ V
2.7V ≤ V
1.8V ≤ V
2.7V ≤ V
1.8V ≤ V
2.7V ≤ V
1.8V ≤ V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ V
CS Setup Time Relative to SK
DI Setup Time Relative to SK
CS Hold Time Relative to SK 0 ns
DI Hold Time Relative to SK
Output Delay to “1” AC Test
Output Delay to “0” AC Test
CS to Status Valid AC Test
CS to DO in High
Impedance
AC Test
CS = V
Write Cycle Time
(1)
5.0V, 25°C 1M Write Cycles
CC
CC
CC
CC
CC
CC
CC
CC
IL
≤ 5.5V
≤ 5.5V
≤ 5.5V
≤ 5.5V
≤ 5.5V
≤ 5.5V
≤ 5.5V
≤ 5.5V
2.7V ≤ V
1.8V ≤ V
2.7V ≤ V
1.8V ≤ V
2.7V ≤ V
1.8V ≤ V
2.7V ≤ V
1.8V ≤ V
2.7V ≤ V
1.8V ≤ V
2.7V ≤ V
1.8V ≤ V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ V
1.8V ≤ V
Note: 1. This parameter is characterized and is not 100% tested.
0
0
0
250
1000
250
1000
250
1000
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V 0.1 3 10 ms
CC
50
200
100
400
100
400
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
AT93C56A/66A
3378K–SEEPR–12/06
Table 5. Instruction Set for the AT93C56A and AT93C66A
AT93C56A/66A
Op
Instruction SB
Code
READ 1 10 A8 – A
Address Data
0
A7 – A
0
EWEN 1 00 11XXXXXXX 11XXXXXX
ERASE 1 11 A
WRITE 1 01 A
8
8
– A
– A
0
0
A7 – A
A7 – A
0
0
D7 – D
D
0
ERAL 1 00 10XXXXXXX 10XXXXXX
WRAL 1 00 01XXXXXXX 01XXXXXX D
7
– D
D
0
EWDS 1 00 00XXXXXXX 00XXXXXX
Note: The X’s in the address field represent don’t care values and must be clocked.
Functional Description
The AT93C56A/66A is accessed via a simple and versatile three-wire serial communication interface. Device operation is controlled by seven instructions issued by the host
processor. A valid instruction starts with a rising edge of CS and consists of a Start
Bit (logic “1”) followed by the appropriate Op Code and the desired memory address
location.
15
15
– D
– D
Commentsx 8 x 16 x 8 x 16
Reads data stored in memory, at
specified address.
Write enable must precede all
programming modes.
Erases memory location An – A0.
Writes memory location An – A0.
0
Erases all memory locations. Valid
only at V
= 4.5V to 5.5V.
CC
Writes all memory locations. Valid
only at VCC = 5.0V ±10% and Disable
0
Register cleared.
Disables all programming
instructions.
3378K–SEEPR–12/06
READ (READ): The Read (READ) instruction contains the address code for the memory location to be read. After the instruction and address are decoded, data from the
selected memory location is available at the serial output pin DO. Output data changes
are synchronized with the rising edges of serial clock SK. It should be noted that a
dummy bit (logic “0”) precedes the 8- or 16-bit data output string. The AT93C56A/66A
supports sequential read operations. The device will automatically increment the internal address pointer and clock out the next memory location as long as Chip Select (CS)
is held high. In this case, the dummy bit (logic “0”) will not be clocked out between memory locations, thus allowing for a continuous stream of data to be read.
ERASE/WRITE (EWEN): To assure data integrity, the part automatically goes into the
Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable
(EWEN) instruction must be executed first before any programming instructions can be
carried out. Please note that once in the EWEN state, programming remains enabled
until an EWDS instruction is executed or V
power is removed from the part.
CC
ERASE (ERASE): The Erase instruction programs all bits in the specified memory location to the logical “1” state. The self-timed erase cycle starts once the ERASE instruction
and address are decoded. The DO pin outputs the Ready/Busy status of the part if CS is
brought high after being kept low for a minimum of 250 ns (t
). A logic “1” at pin DO
CS
indicates that the selected memory location has been erased, and the part is ready for
another instruction.
5
WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be
written into the specified memory location. The self-timed programming cycle t
WP
starts
after the last bit of data is received at serial data input pin DI. The DO pin outputs the
Ready/Busy status of the part if CS is brought high after being kept low for a minimum of
250 ns (t
). A logic “0” at DO indicates that programming is still in progress. A logic “1”
CS
indicates that the memory location at the specified address has been written with the
data pattern contained in the instruction and the part is ready for further instructions. A
READY/BUSY status cannot be obtained if the CS is brought high after the end of
the self-timed programming cycle t
WP
.
ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the mem-
ory array to the logic “1” state and is primarily used for testing purposes. The DO pin
outputs the Ready/Busy status of the part if CS is brought high after being kept low for a
minimum of 250 ns (t
). The ERAL instruction is valid only at VCC = 5.0V ± 10%.
CS
WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations
with the data patterns specified in the instruction. The DO pin outputs the Ready/Busy
status of the part if CS is brought high after being kept low for a minimum of 250 ns (t
The WRAL instruction is valid only at V
= 5.0V ± 10%.
CC
CS
ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the
Erase/Write Disable (EWDS) instruction disables all programming modes and should be
executed after all programming operations. The operation of the READ instruction is
independent of both the EWEN and EWDS instructions and can be executed at any
time.
).
Timing Diagrams
Figure 2. Synchronous Data Timing
Note: 1. This is the minimum SK period.
6
AT93C56A/66A
3378K–SEEPR–12/06
Figure 3. READ Timing
C
S
D
D
C
S
C
S
S
K
I
AT93C56A/66A
Table 6. Organization Key for Timing Diagrams
AT93C56A (2K) AT93C66A (4K)
I/O
A
N
D
N
Notes: 1. A8 is a DON’T CARE value, but the extra clock is required.
2. A7 is a DON’T CARE value, but the extra clock is required.
x 8 x 16 x 8 x 16
(1)
A
8
D
7
(2)
A
7
D
15
A
D
8
7
t
CS
A
7
D
15
O
Figure 4. EWEN Timing
S
K
DI
Figure 5. EWDS Timing
S
K
High Impedance
001
11
t
CS
...
t
CS
DI 1 0
000
...
7
3378K–SEEPR–12/06
Figure 6. WRITE Timing
S
C
D
C
D
C
D
E
S
K
t
CS
DI
HIGH IMPEDANCE
O
Figure 7. WRAL Timing
S
SK
DI
HIGH IMPEDANCE
O
... ...
11
0A0D0
(1)
A
N
1 0 0 1 ... D
D
N
BUSY
t
WP
t
CS
... D00
N
READY
BUSY
READY
t
WP
Note: 1. Valid only at VCC = 4.5V to 5.5V.
Figure 8. ERASE Timing
t
CS
READY
STANDBY
t
DF
HIGH IMPEDANC
3378K–SEEPR–12/06
S
CHECK
STATUS
SK
DI A
HIGH IMPEDANCE
8
O
AT93C56A/66A
1 1 ...1
N
A
N-1AN-2
A0
t
SV
BUSY
t
WP
AT93C56A/66A
C
D
E
Figure 9. ERAL Timing
(1)
S
SK
DI 1 1000
HIGH IMPEDANCE
O
Note: 1. Valid only at VCC = 4.5V to 5.5V.
t
CS
READY
STANDBY
t
DF
HIGH IMPEDANC
CHECK
STATUS
t
SV
BUSY
t
WP
9
3378K–SEEPR–12/06
AT93C56A Ordering Information
(1)
Ordering Code Package Operation Range
AT93C56A-10PU-2.7
AT93C56A-10PU-1.8
AT93C56A-10SU-2.7
AT93C56A-10SU-1.8
(2)
(2)
(2)
(2)
AT93C56AW-10SU-2.7
AT93C56AW-10SU-1.8
AT93C56A-10TU-2.7
AT93C56A-10TU-1.8
(2)
(2)
AT93C56AU3-10UU-1.8
AT93C56AY1-10YU-1.8
AT93C56AY6-10YH-1.8
AT93C56A-W1.8-11
(4)
(2)
(2)
(2)
(2)
(Not recommended for new design)
(3)
8P3
8P3
8S1
8S1
8S2
8S2
8A2
8A2
8U3-1
8Y1
8Y6
Die Sales
Lead-free/Halogen-free/
Industrial Temperature
(−40°C to 85°C)
Industrial Temperature
(−40°C to 85°C)
Notes: 1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.
2. “U” designates Green package + RoHS compliant.
3. “H” designates Green package + RoHS compliant, with NiPdAu Lead Finish.
4. Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please
contact Serial EEPROM Marketing.
Package Type
8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8S2 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC)
8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8U3-1 8-ball, die Ball Grid Array Package (dBGA2)
8Y1 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
8Y6 8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead package (DFN), (MLP 2x3 mm)
Options
−2.7 Low-voltage (2.7V to 5.5V)
−1.8 Low-voltage (1.8V to 5.5V)
10
AT93C56A/66A
3378K–SEEPR–12/06
AT93C56A/66A
AT93C66A Ordering Information
(1)
Ordering Code Package Operation Range
AT93C66A-10PU-2.7
AT93C66A-10PU-1.8
AT93C66A-10SU-2.7
AT93C66A-10SU-1.8
(2)
(2)
(2)
(2)
AT93C66AW-10SU-2.7
AT93C66AW-10SU-1.8
AT93C66A-10TU-2.7
AT93C66A-10TU-1.8
(2)
(2)
AT93C66AU3-10UU-1.8
AT93C66AY1-10YU-1.8
AT93C66AY6-10YH-1.8
AT93C66A-W1.8-11
(4)
(2)
(2)
(2)
(2)
(Not recommended for new design)
(3)
8P3
8P3
8S1
8S1
8S2
8S2
8A2
8A2
8U3-1
8Y1
8Y6
Die Sale
Lead-free/Halogen-free/
Industrial Temperature
(−40°C to 85°C)
Industrial Temperature
(−40°C to 85°C)
Notes: 1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.
2. “U” designates Green package + RoHS compliant.
3. “H” designates Green package + RoHS compliant, with NiPdAu Lead Finish.
4. Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please
contact Serial EEPROM Marketing.
Package Type
8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8S2 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC)
8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8U3-1 8-ball, die Ball Grid Array Package (dBGA2)
8Y1 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
8Y6 8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead package (DFN), (MLP 2x3 mm)
Options
−2.7 Low-voltage (2.7V to 5.5V)
−1.8 Low-voltage (1.8V to 5.5V)
3378K–SEEPR–12/06
11
Packaging Information
8P3 – PDIP
D1
b3
4 PLCS
Top View
D
e
Side View
1
E
E1
N
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
b
b2
A2 A
SYMBOL
A 0.210 2
A2 0.115 0.130 0.195
b 0.014 0.018 0.022 5
b2 0.045 0.060 0.070 6
b3 0.030 0.039 0.045 6
c 0.008 0.010 0.014
D 0.355 0.365 0.400 3
L
D1 0.005 3
E 0.300 0.310 0.325 4
E1 0.240 0.250 0.280 3
e 0.100 BSC
eA 0.300 BSC 4
L 0.115 0.130 0.150 2
MIN
NOM
MAX
NOTE
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
12
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
TITLE
2325 Orchard Parkway
R
San Jose, CA 95131
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
AT93C56A/66A
DRAWING NO.
8P3
3378K–SEEPR–12/06
01/09/02
REV.
B
8S1 – JEDEC SOIC
AT93C56A/66A
C
1
E
N
∅
E1
L
Top View
End View
e
D
Side View
B
A
SYMBOL
A1
A 1.35 – 1.75
A1 0.10 – 0.25
b 0.31 – 0.51
C 0.17 – 0.25
D 4.80 – 5.00
E1 3.81 – 3.99
E 5.79 – 6.20
e 1.27 BSC
L 0.40 – 1.27
∅ 0˚ – 8˚
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
NOM
MAX
NOTE
Note:
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
R
3378K–SEEPR–12/06
TITLE
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
DRAWING NO.
8S1 B
10/7/03
REV.
13
8S2 – EIAJ SOIC
C
1
Top View
E
N
∅
E1
L
End View
e
D
Side View
b
A
SYMBOL
A1
A 1.70 2.16
A1 0.05 0.25
b 0.35 0.48 5
C 0.15 0.35 5
D 5.13 5.35
E1 5.18 5.40 2, 3
E 7.70 8.26
L 0.51 0.85
∅
e 1.27 BSC 4
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
0˚ 8˚
NOM
MAX
NOTE
Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
2. Mismatch of the upper and lower dies and resin burrs are not included.
3. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.
4. Determines the true geometric position.
5. Values b and C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/−0.005 mm.
TITLE
8S2, 8-lead, 0.209" Body, Plastic Small
Outline Package (EIAJ)
14
2325 Orchard Parkway
R
San Jose, CA 95131
AT93C56A/66A
DRAWING NO.
8S2
3378K–SEEPR–12/06
10/7/03
REV.
C
8Y1 - MAP
AT93C56A/66A
PIN 1 INDEX AREA
A
1
PIN 1 INDEX AREA
2
34
E1
D
D1
L
E
Top View
Side View
A
End View
8
A1
SYMBOL
b
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
A – – 0.90
A1 0.00 – 0.05
D 4.70 4.90 5.10
E 2.80 3.00 3.20
D1 0.85 1.00 1.15
E1 0.85 1.00 1.15
b 0.25 0.30 0.35
e 0.65 TYP
L 0.50 0.60 0.70
NOM
6
7
Bottom View
MAX
5
e
NOTE
2325 Orchard Parkway
R
San Jose, CA 95131
3378K–SEEPR–12/06
TITLE
8Y1, 8-lead (4.90 x 3.00 mm Body) MSOP Array Package
(MAP) Y1
DRAWING NO.
8Y1
2/28/03
REV.
C
15
8Y6 - Mini-MAP (MLP 2x3)
A
Pin 1
Index
Area
E
D
A2
A3
E2
A1
SYMBOL
D 2.00 BSC
E 3.00 BSC
D2 1.40 1.50 1.60
E2 - - 1.40
A - - 0.60
A1 0.0 0.02 0.05
A2 - - 0.55
A3 0.20 REF
L 0.20 0.30 0.40
e 0.50 BSC
b 0.20 0.25 0.30 2
D2
e (6X)
1.50 REF.
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
NOM
MAX
b
(8X)
Pin 1 ID
L (8X)
NOTE
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-229, for proper dimensions,
tolerances, datums, etc.
2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the
terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area.
TITLE
16
2325 Orchard Parkway
R
San Jose, CA 95131
AT93C56A/66A
8Y6, 8-lead 2.0 x 3.0 mm Body, 0.50 mm Pitch, Utlra Thin Mini-Map,
Dual No Lead Package (DFN) ,(MLP 2x3)
DRAWING NO.
8Y6
3378K–SEEPR–12/06
8/26/05
REV.
C
8A2 – TSSOP
Pin 1 indicator
this corner
AT93C56A/66A
123
N
Top View
b
e
D
Side View
A2
E1
E
L1
L
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A
D 2.90 3.00 3.10 2, 5
E 6.40 BSC
E1 4.30 4.40 4.50 3, 5
A – – 1.20
A2 0.80 1.00 1.05
b 0.19 – 0.30 4
e 0.65 BSC
L 0.45 0.60 0.75
L1 1.00 REF
MIN
NOM
MAX
NOTE
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
3378K–SEEPR–12/06
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
2325 Orchard Parkway
R
San Jose, CA 95131
TITLE
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
DRAWING NO.
8A2
5/30/02
REV.
B
17
8U3-1 – dBGA2
E
D
PIN 1 BALL PAD CORNER
Top View
PIN 1 BALL PAD CORNER
2
31
4
(d1)
d
8
67
5
e
(e1)
Bottom View
8 Solder Balls
1. This drawing is for general information only.
2. Dimension ‘b’ is measured at maximum solder ball diameter
A
2
A
Side View
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A 0.713 0.79 0.85
A1 0.09 0.14 0.19
A2 0.40 0.45 0.50
b 0.20 0.25 0.30 2
D 1.50 BSC
E 2.00 BSC
e 0.50 BSC
e1 0.25 REF
d 1.00 BSC
d1 0.25 REF
MIN
NOM
1.
b
A
1
NOTE
MAX
18
1150E Cheyenne Mt. Blvd
Colorado Springs, CO 80906
R
AT93C56A/66A
TITLE
8U3-1, 8-ball, 1.50 x 2.00 mm Body, 0.50 mm pitch,
Small Die Ball Grid Array Package (dBGA2)
DRAWING NO.
PO8U3-1 b
3378K–SEEPR–12/06
5/3/05
REV.
Revision History
AT93C56A/66A
Revision No. Date Comments
3378K 12/06 Removed DC/Don’t Connect and replaced with NC/No Conenct
Adjusted size of Block diagram on pg. 2
Made all diagrams on pages 6-9 consistently the same size
Corrected 8U3-1
3378K–SEEPR–12/06
19
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3378K–SEEPR–12/06
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