STMicroelectronics ST7LITE0, ST7SUPERLITE Technical data
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,
■ Memories
– 1K or 1.5K bytes single voltage Flash Pro-
gram memory with read-out protection, In-Circuit and In-Application Programming (ICP and
IAP). 10K write/erase cycles guaranteed, data
retention: 20 years at 55°C.
– 128 bytes RAM.
– 128 bytes data EEPROM with read-out pro-
tection. 300K write/erase cycles guaranteed,
data retention: 20 years at 55°C.
■ Clock, Reset and Supply Management
– 3-level low voltage supervisor (LVD) and aux-
iliary voltage detector (AVD) for safe power-
on/off procedures
– Clock sources: internal 1MHz RC 1% oscilla-
tor or external clock
– PLL x4 or x8 for 4 or 8 MHz internal clock
– Four Power Saving Modes: Halt, Active-Halt,
Wait and Slow
■ Interrupt Management
– 10 interrupt vectors plus TRAP and RESET
– 4 external interrupt lines (on 4 vectors)
■ I/O Ports
– 13 multifunctional bidirectional I/O lines
– 9 alternate function lines
– 6 high sink outputs
■ 2 Timers
– One 8-bit Lite Timer (LT) with prescaler in-
cluding: watchdog, 1 realtime base and 1 in-
put capture.
– One 12-bit Auto-reload Timer (AT) with output
Device Summary
ST7LITE0, ST7SUPERLITE
DATA EEPROM, ADC, TIMERS, SPI
DIP16
SO16
150”
compare function and PWM
■ 1 Communication Interface
– SPI synchronous serial interface
■ A/D Converter
– 8-bit resolution for 0 to V
– Fixed gain Op-amp for 11-bit resolution in 0 to
250 mV range (@ 5V V
– 5 input channels
■ Instruction Set
– 8-bit data manipulation
– 63 basic instructions with illegal opcode de-
tection
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction
■ Development Tools
– Full hardware/software development package
DD
DD
)
Rev. 3.0
October 2004 1/124
Table of Contents
ST7LITE0, ST7SUPERLITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.5 MEMORY PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.6 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3 MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.5 ACCESS ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.6 DATA EEPROM READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.1 INTERNAL RC OSCILLATOR ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.2 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.3 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.4 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.4 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
10 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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Table of Contents
10.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.3 UNUSED I/O PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10.6 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
11.1 LITE TIMER (LT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
11.2 12-BIT AUTORELOAD TIMER (AT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
11.3 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
11.4 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
12.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
13.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
13.10 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 102
13.11 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
14.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
14.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 111
15.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 113
15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
16 IMPORTANT NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
16.1 EXECUTION OF BTJX INSTRUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
16.2 IN-CIRCUIT PROGRAMMING OF DEVICES PREVIOUSLY PROGRAMMED WITH HARDWARE WATCHDOG OPTION 119
16.3 IN-CIRCUIT DEBUGGING WITH HARDWARE WATCHDOG . . . . . . . . . . . . . . . . . . . 119
17 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
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Table of Contents
ERRATA SHEET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
1 SILICON IDENTIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
2 REFERENCE SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
3 SILICON limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
3.1 NEGATIVE INJECTION IMPACT ON ADC ACCURACY . . . . . . . . . . . . . . . . . . . . . . . 121
3.2 ADC CONVERSION SPURIOUS RESULTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
3.3 FUNCTIONAL ESD SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
3.4 CLEARING ACTIVE INTERRUPTS OUTSIDE INTERRUPT ROUTINE . . . . . . . . . . . . 122
4 DEVICE MARKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
5 ERRATA SHEET REVISION History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
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1 INTRODUCTION
ST7LITE0, ST7SUPERLITE
The ST7LITE0 and ST7SUPERLITE are members
of the ST7 microcontroller family. All ST7 devices
are based on a common industry-standard 8-bit
core, featuring an enhanced instruction set.
The ST7LITE0 and ST7SUPERLITE feature
FLASH memory with byte-by-byte In-Circuit Programming (ICP) and In-Application Programming
(IAP) capability.
Under software control, the ST7LITE0 and
ST7SUPERLITE devices can be placed in WAIT,
SLOW, or HALT mode, reducing power consumption when the application is in idle or standby state.
Figure 1. General Block Diagram
Internal
CLOCK
V
V
RESET
DD
SS
1 MHz. RC OSC
+
PLL x 4 or x 8
LVD/AVD
POWER
SUPPLY
CONTROL
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing
modes.
For easy reference, all parametric data are located
in section 13 on page 80.
LITE TIMER
w/ WATCHDOG
PORT A
ADDRESS AND DATA BUS
12-BIT AUTO-
RELOAD TIMER
PA7:0
(8 bits)
8-BIT CORE
ALU
FLASH
MEMORY
(1 or 1.5K Bytes)
RAM
(128 Bytes)
DATA EEPROM
(128 Bytes)
SPI
PORT B
8-BIT ADC
PB4:0
(5 bits)
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ST7LITE0, ST7SUPERLITE
2 PIN DESCRIPTION
Figure 2. 16-Pin Package Pinout (150mil)
k
V
SS
V
DD
RESET
SS/AIN0/PB0
SCK/AIN1/PB1
MISO/AIN2/PB2
MOSI/AIN3/PB3
CLKIN/AIN4/PB4
1
2
3
ei3
4
5
6
ei2
7
8
ei0
ei1
PA0 (HS)/LTIC
16
PA1 (HS)
15
PA2 (HS)/ATPWM0
14
PA3 (HS)
13
PA4 (HS)
12
PA5 (HS)/ICCDATA
11
PA6/MCO/ICCCLK
10
PA7
9
(HS) 20mA high sink capability
eixassociated external interrupt vector
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1
PIN DESCRIPTION (Cont’d)
Legend / Abbreviations for Table 1:
Type: I = input, O = output, S = supply
In/Output level: C= CMOS 0.15V
= CMOS 0.3VDD/0.7VDD with input trigger
C
T
/0.85VDD with input trigger
DD
Output level: HS = 20mA high sink (on N-buffer only)
Port and control configuration:
– Input: float = floating, wpu = weak pull-up, int = interrupt
– Output: OD = open drain, PP = push-pull
Table 1. Device Pin Description
ST7LITE0, ST7SUPERLITE
1)
, ana = analog
Pin
n°
1V
2V
3 RESET
4 PB0/AIN0/SS
5 PB1/AIN1/SCK I/O C
6 PB2/AIN2/MISO I/O C
7 PB3/AIN3/MOSI I/O C
8 PB4/AIN4/CLKIN I/O C
9 PA7 I/O C
10 PA6 /MCO/ICCCLK I/O C
11
Pin Name
SS
DD
I/O C
PA5/
ICCDATA
Type
S Ground
S Main power supply
I/O C
I/O C
Level Port / Control
Input Output
Input
Output
float
T
X ei3 X X X Port B0
T
X XXXXPort B1
T
X XXXXPort B2
T
X ei2 X X X Port B3
T
X XXXXPort B4
T
X ei1 X X Port A7
T
X X XXPort A6
T
HS X XXXPort A5 In Circuit Communication Data
T
int
wpu
X X Top priority non maskable interrupt (active low)
ana
OD
Main
Function
(after reset)
PP
Alternate Function
ADC Analog Input 0 or SPI Slave
Select (active low)
Caution: No negative current injection allowed on this pin. For
details, refer to section 13.2.2 on
page 81
ADC Analog Input 1 or SPI Clock
Caution: No negative current injection allowed on this pin. For
details, refer to section 13.2.2 on
page 81
ADC Analog Input 2 or SPI Master In/ Slave Out Data
ADC Analog Input 3 or SPI Master Out / Slave In Data
ADC Analog Input 4 or External
clock input
Main Clock Output/In Circuit
Communication Clock.
Caution: During normal operation this pin must be pulled- up,
internally or externally (external
pull-up of 10k mandatory in noisy
environment). This is to avoid entering ICC mode unexpectedly
during a reset. In the application,
even if the pin is configured as
output, any reset will put it back in
input pull-up
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ST7LITE0, ST7SUPERLITE
8/124
3 REGISTER & MEMORY MAP
ST7LITE0, ST7SUPERLITE
As shown in Figure 3 and Figure 4, the MCU is capable of addressing 64K bytes of memories and I/
O registers.
The available memory locations consist of up to
128 bytes of register locations, 128 bytes of RAM,
128 bytes of data EEPROM and up to 1.5 Kbytes
of user program memory. The RAM space includes up to 64 bytes for the stack from 0C0h to
0FFh.
Figure 3. Memory Map (ST7LITE0)
0000h
007Fh
0080h
00FFh
0100h
0FFFh
1000h
107Fh
1080h
HW Registers
(see Table 2)
RAM
(128 Bytes)
Reserved
Data EEPROM
(128 Bytes)
0080h
00BFh
00C0h
00FFh
The highest address bytes contain the user reset
and interrupt vectors.
The size of Flash Sector 0 is configurable by Option byte.
IMPORTANT: Memory locations marked as “Reserved” must never be accessed. Accessing a reserved area can have unpredictable effects on the
device.
Short Addressing
RAM (zero page)
64 Bytes Stack
1000h
1001h
see section 7.1 on page 24
RCCR0
RCCR1
F9FFh
FA00h
FFDFh
FFE0h
FFFFh
Reserved
Flash Memory
(1.5K)
Interrupt & Reset Vectors
(see Table 6)
PROGRAM MEMORY
FA00h
FBFFh
FC00h
FFFFh
1.5K FLASH
0.5 Kbytes
SECTOR 1
1 Kbytes
SECTOR 0
FFDEh
RCCR0
FFDFh
RCCR1
see section 7.1 on page 24
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ST7LITE0, ST7SUPERLITE
REGISTER AND MEMORY MAP (Cont’d)
Figure 4. Memory Map (ST7SUPERLITE)
0000h
007Fh
0080h
00FFh
0100h
FBFFh
FC00h
FFDFh
FFE0h
FFFFh
HW Registers
(see Table 2)
RAM
(128 Bytes)
Reserved
Flash Memory
(1K)
Interrupt & Reset Vectors
(see Table 6)
FC00h
FDFFh
FE00h
FFFFh
0080h
00BFh
00C0h
00FFh
Short Addressing
RAM (zero page)
64 Bytes Stack
1K FLASH
PROGRAM MEMORY
0.5 Kbytes
SECTOR 1
0.5 Kbytes
SECTOR 0
FFDEh
FFDFh
see section 7.1 on page 24
RCCR0
RCCR1
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REGISTER AND MEMORY MAP (Cont’d)
Legend: x=undefined, R/W=read/write
Table 2. Hardware Register Map
ST7LITE0, ST7SUPERLITE
Address Block
0000h
0001h
0002h
0003h
0004h
0005h
0006h to
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h to
0016h
0017h
0018h
Port A
Port B
LITE
TIMER
AUTO-RELOAD
TIMER
AUTO-RELOAD
TIMER
Register
Label
PADR
PADDR
PAOR
PBDR
PBDDR
PBOR
LTCSR
LTICR
ATCSR
CNTRH
CNTRL
ATRH
ATRL
PWMCR
PWM0CSR
DCR0H
DCR0L
Register Name
Port A Data Register
Port A Data Direction Register
Port A Option Register
Port B Data Register
Port B Data Direction Register
Port B Option Register
Reserved area (5 bytes)
Lite Timer Control/Status Register
Lite Timer Input Capture Register
Timer Control/Status Register
Counter Register High
Counter Register Low
Auto-Reload Register High
Auto-Reload Register Low
PWM Output Control Register
PWM 0 Control/Status Register
Reserved area (3 bytes)
PWM 0 Duty Cycle Register High
PWM 0 Duty Cycle Register Low
Reset
Status
1)
00h
00h
40h
1)
E0h
00h
00h
xxh
xxh
00h
00h
00h
00h
00h
00h
00h
00h
00h
Remarks
R/W
R/W
R/W
R/W
R/W
2)
R/W
R/W
Read Only
R/W
Read Only
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
0019h to
002Eh
0002Fh FLASH FCSR Flash Control/Status Register 00h R/W
00030h EEPROM EECSR Data EEPROM Control/Status Register 00h R/W
0031h
0032h
0033h
0034h
0035h
0036h
0037h ITC EICR External Interrupt Control Register 00h R/W
0038h
0039h
SPI
ADC
CLOCKS
SPIDR
SPICR
SPICSR
ADCCSR
ADCDR
ADCAMP
MCCSR
RCCR
SPI Data I/O Register
SPI Control Register
SPI Control/Status Register
A/D Control Status Register
A/D Data Register
A/D Amplifier Control Register
Main Clock Control/Status Register
RC oscillator Control Register
Reserved area (22 bytes)
xxh
0xh
00h
00h
00h
00h
00h
FFh
R/W
R/W
R/W
R/W
Read Only
R/W
R/W
R/W
11/124
1
ST7LITE0, ST7SUPERLITE
12/124
4 FLASH PROGRAM MEMORY
ST7LITE0, ST7SUPERLITE
4.1 Introduction
The ST7 single voltage extended Flash (XFlash) is
a non-volatile memory that can be electrically
erased and programmed either on a byte-by-byte
basis or up to 32 bytes in parallel.
The XFlash devices can be programmed off-board
(plugged in a programming tool) or on-board using
In-Circuit Programming or In-Application Programming.
The array matrix organisation allows each sector
to be erased and reprogrammed without affecting
other sectors.
4.2 Main Features
■ ICP (In-Circuit Programming)
■ IAP (In-Application Programming)
■ ICT (In-Circuit Testing) for downloading and
executing user application test patterns in RAM
■ Sector 0 size configurable by option byte
■ Read-out and write protection
4.3 PROGRAMMING MODES
The ST7 can be programmed in three different
ways:
– Insertion in a programming tool. In this mode,
FLASH sectors 0 and 1, option byte row and
data EEPROM can be programmed or
erased.
– In-Circuit Programming. In this mode, FLASH
sectors 0 and 1, option byte row and data
EEPROM can be programmed or erased without removing the device from the application
board.
– In-Application Programming. In this mode,
sector 1 and data EEPROM can be programmed or erased without removing the device from the application board and while the
application is running.
4.3.1 In-Circuit Programming (ICP)
ICP uses a protocol called ICC (In-Circuit Communication) which allows an ST7 plugged on a printed circuit board (PCB) to communicate with an external programming device connected via cable.
ICP is performed in three steps:
Switch the ST7 to ICC mode (In-Circuit Communications). This is done by driving a specific signal
sequence on the ICCCLK/DATA pins while the
RESET pin is pulled low. When the ST7 enters
ICC mode, it fetches a specific RESET vector
which points to the ST7 System Memory containing the ICC protocol routine. This routine enables
the ST7 to receive bytes from the ICC interface.
– Download ICP Driver code in RAM from the
ICCDATA pin
– Execute ICP Driver code in RAM to program
the FLASH memory
Depending on the ICP Driver code downloaded in
RAM, FLASH memory programming can be fully
customized (number of bytes to program, program
locations, or selection of the serial communication
interface for downloading).
4.3.2 In Application Programming (IAP)
This mode uses an IAP Driver program previously
programmed in Sector 0 by the user (in ICP
mode).
This mode is fully controlled by user software. This
allows it to be adapted to the user application, (user-defined strategy for entering programming
mode, choice of communications protocol used to
fetch the data to be stored etc.)
IAP mode can be used to program any memory areas except Sector 0, which is write/erase protected to allow recovery in case errors occur during
the programming operation.
13/124
1
ST7LITE0, ST7SUPERLITE
FLASH PROGRAM MEMORY (Cont’d)
4.4 ICC interface
ICP needs a minimum of 4 and up to 6 pins to be
connected to the programming tool. These pins
are:
– RESET
–V
: device reset
: device power supply ground
SS
– ICCCLK: ICC output serial clock pin
– ICCDATA: ICC input serial data pin
– CLKIN: main clock input for external source
: application board power supply (option-
–V
DD
al, see Note 3)
Notes:
1. If the ICCCLK or ICCDATA pins are only used
as outputs in the application, no signal isolation is
necessary. As soon as the Programming Tool is
plugged to the board, even if an ICC session is not
in progress, the ICCCLK and ICCDATA pins are
not available for the application. If they are used as
inputs by the application, isolation such as a serial
resistor has to be implemented in case another device forces the signal. Refer to the Programming
Tool documentation for recommended resistor values.
2. During the ICP session, the programming tool
must control the RESET
pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at
Figure 5. Typical ICC Interface
high level (push pull output or pull-up resistor<1K).
A schottky diode can be used to isolate the application RESET circuit in this case. When using a
classical RC network with R>1K or a reset management IC with open drain output and pull-up resistor>1K, no additional components are needed.
In all cases the user must ensure that no external
reset is generated by the application during the
ICC session.
3. The use of Pin 7 of the ICC connector depends
on the Programming Tool architecture. This pin
must be connected when using most ST Programming Tools (it is used to monitor the application
power supply). Please refer to the Programming
Tool manual.
4. Pin 9 has to be connected to the CLKIN pin of
the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte.
Caution: During normal operation, ICCCLK pin
must be pulled- up, internally or externally (external pull-up of 10k mandatory in noisy environment). This is to avoid entering ICC mode unexpectedly during a reset. In the application, even if
the pin is configured as output, any reset will put it
back in input pull-up.
APPLICATION
POWER SUPPLY
14/124
(See Note 3)
VDD
OPTIONAL
(See Note 4)
CLKIN
ST7
PROGRAMMING TOOL
ICC CONNECTOR
ICC Cable
ICC CONNECTOR
HE10 CONNECTOR TYPE
9753
1
246810
RESET
ICCCLK
ICCDATA
APPLICATION BOARD
APPLICATION
RESET SOURCE
See Note 2
See Note 1 and Caution
See Note 1
APPLICATION
I/O
1
FLASH PROGRAM MEMORY (Cont’d)
ST7LITE0, ST7SUPERLITE
4.5 Memory Protection
There are two different types of memory protection: Read Out Protection and Write/Erase Protection which can be applied individually.
4.5.1 Read out Protection
Readout protection, when selected provides a protection against program memory content extraction and against write access to Flash memory.
Even if no protection can be considered as totally
unbreakable, the feature provides a very high level
of protection for a general purpose microcontroller.
Both program and data E
2
memory are protected.
In flash devices, this protection is removed by reprogramming the option. In this case, both program and data E
2
memory are automatically
erased, and the device can be reprogrammed.
Read-out protection selection depends on the de-
vice type:
– In Flash devices it is enabled and removed
through the FMP_R bit in the option byte.
– In ROM devices it is enabled by mask option
specified in the Option List.
4.5.2 Flash Write/Erase Protection
Write/erase protection, when set, makes it impossible to both overwrite and erase program memory. It does not apply to E
2
data. Its purpose is to
provide advanced security to applications and prevent any change being made to the memory content.
Warning: Once set, Write/erase protection can
never be removed. A write-protected flash device
is no longer reprogrammable.
Write/erase protection is enabled through the
FMP_W bit in the option byte.
4.6 Related Documentation
For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual
.
4.7 Register Description
FLASH CONTROL/STATUS REGISTER (FCSR)
Read/Write
Reset Value: 000 0000 (00h)
1st RASS Key: 0101 0110 (56h)
2nd RASS Key: 1010 1110 (AEh)
70
00000OPTLATPGM
Note: This register is reserved for programming
using ICP, IAP or other programming methods. It
controls the XFlash programming and erasing operations.
When an EPB or another programming tool is
used (in socket or ICP mode), the RASS keys are
sent automatically.
Table 3. FLASH Register Map and Reset Values
Address
(Hex.)
002Fh
Register
Label
FCSR
Reset Value
76543210
00000
OPT
0
LAT
0
PGM
0
15/124
1
ST7LITE0, ST7SUPERLITE
5 DATA EEPROM
5.1 INTRODUCTION
The Electrically Erasable Programmable Read
Only Memory can be used as a non volatile backup for storing data. Using the EEPROM requires a
basic access protocol described in this chapter.
Figure 6. EEPROM Block Diagram
EECSR
ADDRESS
DECODER
4
0 E2LAT00 0 0 0 E2PGM
ROW
DECODER
5.2 MAIN FEATURES
■ Up to 32 Bytes programmed in the same cycle
■ EEPROM mono-voltage (charge pump)
■ Chained erase and programming cycles
■ Internal control of the global programming cycle
duration
■ WAIT mode management
■ Readout protection
HIGH VOLTAGE
PUMP
EEPROM
MEMORY MATRIX
(1 ROW = 32 x 8 BITS)
ADDRESS BUS
128128
4
4
DATA
MULTIPLEXER
DATA BUS
32 x 8 BITS
DATA LATCHES
16/124
1
DATA EEPROM (Cont’d)
ST7LITE0, ST7SUPERLITE
5.3 MEMORY ACCESS
The Data EEPROM memory read/write access
modes are controlled by the E2LAT bit of the EEPROM Control/Status register (EECSR). The flowchart in Figure 7 describes these different memory
access modes.
Read Operation (E2LAT=0)
The EEPROM can be read as a normal ROM location when the E2LAT bit of the EECSR register is
cleared. In a read cycle, the byte to be accessed is
put on the data bus in less than 1 CPU clock cycle.
This means that reading data from EEPROM
takes the same time as reading data from
EPROM, but this memory cannot be used to execute machine code.
Write Operation (E2LAT=1)
To access the write mode, the E2LAT bit has to be
set by software (the E2PGM bit remains cleared).
When a write access to the EEPROM area occurs,
Figure 7. Data EEPROM Programming Flowchart
READ MODE
E2LAT=0
E2PGM=0
the value is latched inside the 32 data latches according to its address.
When PGM bit is set by the software, all the previous bytes written in the data latches (up to 32) are
programmed in the EEPROM cells. The effective
high address (row) is determined by the last EEPROM write sequence. To avoid wrong programming, the user must take care that all the bytes
written between two programming sequences
have the same high address: only the five Least
Significant Bits of the address can change.
At the end of the programming cycle, the PGM and
LAT bits are cleared simultaneously.
Note: Care should be taken during the programming cycle. Writing to the same memory location
will over-program the memory (logical AND between the two write access data result) because
the data latches are only cleared at the end of the
programming cycle and by the falling edge of the
E2LAT bit.
It is not possible to read the latched data.
This note is ilustrated by the Figure 9.
WRITE MODE
E2LAT=1
E2PGM=0
READ BYTES
IN EEPROM AREA
CLEARED BY HARDWARE
WRITE UP TO 32 BYTES
(with the same 11 MSB of the address)
IN EEPROM AREA
START PROGRAMMING CYCLE
E2PGM=1 (set by software)
E2LAT=1
01
E2LAT
17/124
1
ST7LITE0, ST7SUPERLITE
DATA EEPROM (Cont’d)
2
Figure 8. Data E
DEFINITION
PROM Write Operation
⇓ Row / Byte ⇒ 0 1 2 3 ... 30 31 Physical Address
ROW
...
N
0
1
00h...1Fh
20h...3Fh
Nx20h...Nx20h+1Fh
E2LAT bit
E2PGM bit
Read operation impossible
Byte 1 Byte 2 Byte 32
PHASE 1
Writing data latches Waiting E2PGM and E2LAT to fall
Set by USER application
Programming cycle
PHASE 2
Read operation possible
Cleared by hardware
Note: If a programming cycle is interrupted (by software or a reset action), the integrity of the data in mem-
ory is not guaranteed.
18/124
1
DATA EEPROM (Cont’d)
ST7LITE0, ST7SUPERLITE
5.4 POWER SAVING MODES
Wait mode
The DATA EEPROM can enter WAIT mode on execution of the WFI instruction of the microcontroller or when the microcontroller enters Active-HALT
mode.The DATA EEPROM will immediately enter
this mode if there is no programming in progress,
otherwise the DATA EEPROM will finish the cycle
and then enter WAIT mode.
Active-Halt mode
Refer to Wait mode.
Halt mode
The DATA EEPROM immediately enters HALT
mode if the microcontroller executes the HALT instruction. Therefore the EEPROM will stop the
function in progress, and data may be corrupted.
5.5 ACCESS ERROR HANDLING
If a read access occurs while E2LAT=1, then the
data bus will not be driven.
If a write access occurs while E2LAT=0, then the
data on the bus will not be latched.
If a programming cycle is interrupted (by software/
RESET action), the memory data will not be guaranteed.
5.6 Data EEPROM Read-out Protection
The read-out protection is enabled through an option bit (see section 15.1 on page 111).
When this option is selected, the programs and
data stored in the EEPROM memory are protected
against read-out (including a re-write protection).
In Flash devices, when this protection is removed
by reprogramming the Option Byte, the entire Program memory and EEPROM is first automatically
erased.
Note: Both Program Memory and data EEPROM
are protected using the same option bit.
Figure 9. Data EEPROM Programming Cycle
READ OPERATION NOT POSSIBLE
INTERNAL
PROGRAMMING
VOLTAGE
ERASE CYCLE WRITE CYCLE
WRITE OF
DATA LATCHES
t
PROG
READ OPERATION POSSIBLE
LAT
PGM
19/124
1
ST7LITE0, ST7SUPERLITE
DATA EEPROM (Cont’d)
5.7 REGISTER DESCRIPTION
EEPROM CONTROL/STATUS REGISTER (EECSR)
Read/Write
Reset Value: 0000 0000 (00h)
70
000000E2LATE2PGM
Bits 7:2 = Reserved, forced by hardware to 0.
Bit 1 = E2LAT Latch Access Transfer
This bit is set by software. It is cleared by hardware at the end of the programming cycle. It can
only be cleared by software if the E2PGM bit is
cleared.
0: Read mode
1: Write mode
Bit 0 = E2PGM Programming control and status
This bit is set by software to begin the programming
cycle. At the end of the programming cycle, this bit
is cleared by hardware.
0: Programming finished or not yet started
1: Programming cycle is in progress
Note: if the E2PGM bit is cleared during the programming cycle, the memory data is not guaranteed
Table 4. DATA EEPROM Register Map and Reset Values
Address
(Hex.)
0030h
Register
Label
EECSR
Reset Value
76543210
000000
E2LAT0E2PGM
0
20/124
1
6 CENTRAL PROCESSING UNIT
ST7LITE0, ST7SUPERLITE
6.1 INTRODUCTION
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
6.2 MAIN FEATURES
■ 63 basic instructions
■ Fast 8-bit by 8-bit multiply
■ 17 main addressing modes
■ Two 8-bit index registers
■ 16-bit stack pointer
■ Low power modes
■ Maskable hardware interrupts
■ Non-maskable software interrupt
6.3 CPU REGISTERS
The 6 CPU registers shown in Figure 10 are not
present in the memory mapping and are accessed
by specific instructions.
Figure 10. CPU Registers
70
Accumulator (A)
The Accumulator is an 8-bit general purpose register used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
Index Registers (X and Y)
In indexed addressing modes, these 8-bit registers
are used to create either effective addresses or
temporary storage areas for data manipulation.
(The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)
The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from
the stack).
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
ACCUMULATOR
70
70
7
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
70
1C11HINZ
0
X INDEX REGISTER
Y INDEX REGISTER
PROGRAM COUNTER
CONDITION CODE REGISTER
STACK POINTER
21/124
ST7LITE0, ST7SUPERLITE
CPU REGISTERS (Cont’d)
CONDITION CODE REGISTER (CC)
Read/Write
Reset Value: 111x1xxx
70
111HINZC
The 8-bit Condition Code register contains the interrupt mask and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP instructions.
These bits can be individually tested and/or controlled by specific instructions.
Bit 4 = H Half carry.
This bit is set by hardware when a carry occurs be-
tween bits 3 and 4 of the ALU during an ADD or
ADC instruction. It is reset by hardware during the
same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.
Bit 3 = I Interrupt mask.
This bit is set by hardware when entering in inter-
rupt or by software to disable all interrupts except
the TRAP software interrupt. This bit is cleared by
software.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions.
Note: Interrupts requested while I is set are
latched and can be processed when I is cleared.
By default an interrupt routine is not interruptable
because the I bit is set by hardware at the start of
the routine and reset by the IRET instruction at the
end of the routine. If the I bit is cleared by software
in the interrupt routine, pending interrupts are
serviced regardless of the priority level of the current interrupt routine.
Bit 2 = N Negative.
This bit is set and cleared by hardware. It is repre-
sentative of the result sign of the last arithmetic,
logical or data manipulation. It is a copy of the 7
bit of the result.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(i.e. the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instructions.
Bit 1 = Z Zero.
This bit is set and cleared by hardware. This bit in-
dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test
instructions.
Bit 0 = C Carry/borrow.
This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
th
22/124
1
ST7LITE0, ST7SUPERLITE
CPU REGISTERS (Cont’d)
Stack Pointer (SP)
Read/Write
Reset Value: 00 FFh
15 8
00000000
70
1 1 SP5 SP4 SP3 SP2 SP1 SP0
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 11).
Since the stack is 64 bytes deep, the 10 most significant bits are forced by hardware. Following an
MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP5 to SP0 bits are set) which is the stack
higher address.
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD instruction.
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously
stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 11.
– When an interrupt is received, the SP is decre-
mented and the context is pushed on the stack.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an interrupt five locations in the stack area.
Figure 11. Stack Manipulation Example
PCH
23/124
ST7LITE0, ST7SUPERLITE
7 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for
securing the application in critical situations (for
example in case of a power brown-out), and reducing the number of external components.
Main features
■ Clock Management
– 1 MHz internal RC oscillator (enabled by op-
tion byte)
– External Clock Input (enabled by option byte)
– PLL for multiplying the frequency by 4 or 8
(enabled by option byte)
■ Reset Sequence Manager (RSM)
■ System Integrity Management (SI)
– Main supply Low voltage detection (LVD) with
reset generation (enabled by option byte)
– Auxiliary Voltage detector (AVD) with interrupt
capability for monitoring the main supply (en-
abled by option byte)
7.1 INTERNAL RC OSCILLATOR ADJUSTMENT
The ST7 contains an internal RC oscillator with an
accuracy of 1% for a given device, temperature
and voltage. It must be calibrated to obtain the frequency required in the application. This is done by
software writing a calibration value in the RCCR
(RC Control Register).
Whenever the microcontroller is reset, the RCCR
returns to its default value (FFh), i.e. each time the
device is reset, the calibration value must be loaded in the RCCR. Predefined calibration values are
stored in EEPROM for 3.0 and 5V V
ages at 25°C, as shown in the following table.
supply volt-
DD
Notes:
– See “ELECTRICAL CHARACTERISTICS” on
page 80. for more information on the frequency
and accuracy of the RC oscillator.
– To improve clock stability, it is recommended to
place a decoupling capacitor between the V
and V
pins as close as possible to the ST7 de-
SS
DD
vice.
ST7FLITE05/
ST7FLITES5
Address
FFDEh
FFDFh
RCCR Conditions
=5V
V
DD
=25°C
RCCR0
RCCR1
T
A
=1MHz
f
RC
=3.0V
V
DD
=25°C
T
A
=700KHz
f
RC
ST7FLITE09
Address
1000h and
FFDEh
1001h andFFDFh
– These two bytes are systematically programmed
by ST, including on FASTROM devices. Consequently, customers intending to use FASTROM
service must not use these two bytes.
– RCCR0 and RCCR1 calibration values will be
erased if the read-out protection bit is reset after
it has been set. See “Read out Protection” on
page 15.
Caution: If the voltage or temperature conditions
change in the application, the frequency may need
to be recalibrated.
Refer to application note AN1324 for information
on how to calibrate the RC frequency using an external reference signal.
7.2 PHASE LOCKED LOOP
The PLL can be used to multiply a 1MHz frequency from the RC oscillator or the external clock by 4
or 8 to obtain f
of 4 or 8 MHz. The PLL is ena-
OSC
bled and the multiplication factor of 4 or 8 is selected by 2 option bits.
– The x4 PLL is intended for operation with V
DD
in
the 2.4V to 3.3V range
– The x8 PLL is intended for operation with V
DD
in
the 3.3V to 5.5V range
Refer to Section 15.1 for the option byte description.
If the PLL is disabled and the RC oscillator is enabled, then f
OSC =
1MHz.
If both the RC oscillator and the PLL are disabled,
is driven by the external clock.
f
OSC
24/124
1
ST7LITE0, ST7SUPERLITE
Figure 12. PLL Output Frequency Timing
Diagram
When the PLL is started, after reset or wakeup
from Halt mode or AWUFH mode, it outputs the
clock after a delay of t
STARTUP
.
When the PLL output signal reaches the operating
frequency, the LOCKED bit in the SICSCR register
is set. Full PLL accuracy (ACC
a stabilization time of t
STAB
) is reached after
PLL
(see Figure 12 and
13.3.4 Internal RC Oscillator and PLL)
Refer to section 8.4.4 on page 36 for a description
of the LOCKED bit in the SICSR register.
Bit 1 = MCO Main Clock Out enable
This bit is read/write by software and cleared by
hardware after a reset. This bit allows to enable
the MCO output clock.
0: MCO clock disabled, I/O port free for general
purpose I/O.
1: MCO clock enabled.
Bit 0 = SMS Slow Mode select
This bit is read/write by software and cleared by
hardware after a reset. This bit selects the input
OSC
or f
clock f
0: Normal mode (f
1: Slow mode (f
/32.
OSC
CPU = fOSC
CPU = fOSC
/32)
RC CONTROL REGISTER (RCCR)
Read / Write
Reset Value: 1111 1111 (FFh) 0:C
7.3 REGISTER DESCRIPTION
MAIN CLOCK CONTROL/STATUS REGISTER
(MCCSR)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 7:2 = Reserved, must be kept cleared.
25/124
ST7LITE0, ST7SUPERLITE
Figure 13. Clock Management Block Diagram
CLKIN
f
OSC
7
CR4CR7 CR0CR1CR2CR3CR6 CR5
Tunable
Oscillator1% RC
/2 DIVIDER
/32 DIVIDER
Option byte
8-BIT
LITE TIMER COUNTER
f
/32
f
OSC
OSC
MCO
1
0
SMS
RCCR
PLL 1MHz -> 8MHz
PLL 1MHz -> 4MHz
MCCSR
0
1MHz
8MHz
4MHz
0 to 8 MHz
Option byte
f
LTIMER
(1ms timebase @ 8 MHz f
f
CPU
TO CPU AND
PERIPHERALS
(except LITE
TIMER)
OSC
f
CPU
f
OSC
)
MCO
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7.4 RESET SEQUENCE MANAGER (RSM)
ST7LITE0, ST7SUPERLITE
7.4.1 Introduction
The reset sequence manager includes three RESET sources as shown in Figure 15:
■ External RESET source pulse
■ Internal LVD RESET (Low Voltage Detection)
■ Internal WATCHDOG RESET
These sources act on the RESET
pin and it is al-
ways kept low during the delay phase.
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of 3 phases
as shown in Figure 14:
■ Active Phase depending on the RESET source
■ 256 CPU clock cycle delay
■ RESET vector fetch
The 256 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state.
Figure 15. Reset Block Diagram
V
DD
The RESET vector fetch phase duration is 2 clock
cycles.
If the PLL is enabled by option byte, it outputs the
clock after an additional delay of t
STARTUP
(see
Figure 12).
Figure 14. RESET Sequence Phases
RESET
Active Phase
INTERNAL RESET
256 CLOCK CYCLES
FETCH
VECTOR
RESET
R
ON
FILTER
PULSE
GENERATOR
INTERNAL
RESET
WATCHDOG RESET
LVD RESET
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1
ST7LITE0, ST7SUPERLITE
RESET SEQUENCE MANAGER (Cont’d)
7.4.2 Asynchronous External RESET
The RESET
output with integrated R
pin is both an input and an open-drain
weak pull-up resistor.
ON
pin
This pull-up has no fixed value but varies in accordance with the input voltage. It
can be pulled
low by external circuitry to reset the device. See
Electrical Characteristic section for more details.
A RESET signal originating from an external
source must have a duration of at least t
h(RSTL)in
in
order to be recognized (see Figure 16). This detection is asynchronous and therefore the MCU
can enter reset state even in HALT mode.
The RESET
pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteristics section.
7.4.3 External Power-On RESET
If the LVD is disabled by option byte, to start up the
microcontroller correctly, the user must ensure by
means of an external reset circuit that the reset
signal is held low until V
level specified for the selected f
is over the minimum
DD
frequency.
OSC
Figure 16. RESET Sequences
V
DD
A proper reset signal for a slow rising V
supply
DD
can generally be provided by an external RC network connected to the RESET
pin.
7.4.4 Internal Low Voltage Detector (LVD) RESET
Two different RESET sequences caused by the internal LVD circuitry can be distinguished:
■ Power-On RESET
■ Voltage Drop RESET
The device RESET
pulled low when V
V
DD<VIT-
(falling edge) as shown in Figure 16.
The LVD filters spikes on V
pin acts as an output that is
DD<VIT+
(rising edge) or
larger than t
DD
g(VDD)
to
avoid parasitic resets.
7.4.5 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 16.
Starting from the Watchdog counter underflow, the
device RESET
low during at least t
pin acts as an output that is pulled
w(RSTL)out
.
V
IT+(LVD)
V
IT-(LVD)
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
RUN
LVD
RESET
ACTIVE PHASE
RUN
t
h(RSTL)in
EXTERNAL
RESET
ACTIVE
PHASE
WATCHDOG UNDERFLOW
RUN RUN
INTERNALRESET (256 T
VECTOR FETCH
WATCHDOG
RESET
ACTIVE
PHASE
t
w(RSTL)out
CPU
)
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8 INTERRUPTS
ST7LITE0, ST7SUPERLITE
The ST7 core may be interrupted by one of two different methods: maskable hardware interrupts as
listed in the Interrupt Mapping Table and a nonmaskable software interrupt (TRAP). The Interrupt
processing flowchart is shown in Figure 17.
The maskable interrupts must be enabled by
clearing the I bit in order to be serviced. However,
disabled interrupts may be latched and processed
when they are enabled (see external interrupts
subsection).
Note: After reset, all interrupts are disabled.
When an interrupt has to be serviced:
– Normal processing is suspended at the end of
the current instruction execution.
– The PC, X, A and CC registers are saved onto
the stack.
– The I bit of the CC register is set to prevent addi-
tional interrupts.
– The PC is then loaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
the Interrupt Mapping Table for vector addresses).
The interrupt service routine should finish with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
Note: As a consequence of the IRET instruction,
the I bit will be cleared and the main program will
resume.
Priority Management
By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware entering in interrupt routine.
In the case when several interrupts are simultaneously pending, an hardware priority defines which
one will be serviced first (see the Interrupt Mapping Table).
Interrupts and Low Power Mode
All interrupts allow the processor to leave the
WAIT low power mode. Only external and specifically mentioned interrupts allow the processor to
leave the HALT low power mode (refer to the “Exit
from HALT“ column in the Interrupt Mapping Table).
8.1 NON MASKABLE SOFTWARE INTERRUPT
This interrupt is entered when the TRAP instruction is executed regardless of the state of the I bit.
It will be serviced according to the flowchart on
Figure 17.
8.2 EXTERNAL INTERRUPTS
External interrupt vectors can be loaded into the
PC register if the corresponding external interrupt
occurred and if the I bit is cleared. These interrupts
allow the processor to leave the Halt low power
mode.
The external interrupt polarity is selected through
the miscellaneous register or interrupt register (if
available).
An external interrupt triggered on edge will be
latched and the interrupt request automatically
cleared upon entering the interrupt service routine.
Caution: The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies to the ei source.
8.3 PERIPHERAL INTERRUPTS
Different peripheral interrupt flags in the status
register are able to cause an interrupt when they
are active if both:
– The I bit of the CC register is cleared.
– The corresponding enable bit is set in the control
register.
If any of these two conditions is false, the interrupt
is latched and thus remains pending.
Clearing an interrupt request is done by:
– Writing “0” to the corresponding bit in the status
register or
– Access to the status register while the flag is set
followed by a read or write of an associated register.
Note: the clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being enabled) will therefore be lost if the clear sequence is
executed.
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1
ST7LITE0, ST7SUPERLITE
INTERRUPTS (Cont’d)
Figure 17. Interrupt Processing Flowchart
FROM RESET
N
N
INTERRUPT
PENDING?
Y
STACK PC, X, A, CC
SET I BIT
LOAD PC FROM INTERRUPT VECTOR
EXECUTE INSTRUCTION
RESTORE PC, X, A, CC FROM STACK
I BIT SET?
Y
FETCH NEXT INSTRUCTION
N
THIS CLEARS I BIT BY DEFAULT
IRET?
Y
Table 6. Interrupt Mapping
Exit
from
HALT
Address
Vector
yes FFFEh-FFFFh
FFF8h-FFF9h
yes
N°
Source
Block
Description
RESET Reset
TRAP Software Interrupt no FFFCh-FFFDh
Register
Label
Priority
Order
Highest
Priority
0 Not used FFFAh-FFFBh
1 ei0 External Interrupt 0
N/A
2 ei1 External Interrupt 1 FFF6h-FFF7h
3 ei2 External Interrupt 2 FFF4h-FFF5h
4 ei3 External Interrupt 3 FFF2h-FFF3h
5 Not used FFF0h-FFF1h
6 Not used FFEEh-FFEFh
7 SI AVD interrupt SICSR no FFECh-FFEDh
8
AT TIMER
9 AT TIMER Overflow Interrupt ATCSR yes FFE8h-FFE9h
10
LITE TIMER
11 LITE TIMER RTC Interrupt LTCSR yes FFE4h-FFE5h
12 SPI SPI Peripheral Interrupts SPICSR yes FFE2h-FFE3h
13 Not used FFE0h-FFE1h
AT TIMER Output Compare Interrupt PWM0CSR no FFEAh-FFEBh
LITE TIMER Input Capture Interrupt LTCSR no FFE6h-FFE7h
Lowest
Priority
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