STMicroelectronics ST72104G, ST72215G, ST72216G, ST72254G Technical data

8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,

ADC, 16-BIT TIMERS, SPI, I

■ Memories

– 4K or 8K bytes Program mem ory (ROM and

single voltage FLA SH) with read-out protec­tion and in-situ programming (remote ISP)

– 256 bytes RAM

■ Clock, Res et and Supply M ana g e m ent

– Enhanced reset system
– Enhanced low voltage supply supervisor with

3 programmable levels

– Clock sources: crystal/ceramic resonat or os-

cillators or RC oscillators, external clock,

backup Clock Security System
– Clock-out capability
– 3 Power Saving Modes: Halt, Wait and Slow

■ Interrupt Management

– 7 interru pt vectors plus TRAP and RESET
– 22 external interrupt lines (on 2 vectors)

■ 22 I/O Port s

– 22 multifunctional bidirectional I/O lines
– 14 alternate function lines
– 8 high sink outputs

■ 3 Timers

– Configurable watchdog timer
– Two 16-bit timers with: 2 input captures, 2 out-

put compares, external clock input on one tim-

er, PWM and Pulse generator modes

(one only on ST72104Gx and ST72216G1)

■ 2 Communications Interfaces

– SPI synchronous serial interface
– I2C multimaster interface

(only on ST72254Gx)

■ 1 Analog peripheral

– 8-bit ADC with 6 input channels

(except on ST72104Gx)

ST72104G, ST72215G,

ST72216G, ST72254G

2

C INTERFACES

PRELIMINARY DATA

SDIP32

SO28

■ Instruction Set

– 8-bit data manipulation
– 63 basic instructions
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction
– True bit manipulation

■ Development Tools

– Full hardware/software development package

Device Summary

Features ST72104G1 ST72104G2 ST72216G1 ST72215G2 ST72254G1 ST72254G2

Program memory - bytes 4K 8K 4K 8K 4K 8K
RAM (stack) - bytes 256 (128)

Periphe rals

Operating Supply 3.2V to 5.5V
CPU Frequency Up to 8 MHz (with oscillator up to 16 MHz)
Operati ng T emperature 0°C to 70°C / -10°C to +85°C (-40°C to +85°C / -40°C t o105°C / -40°C to 125°C optional)
Package s SO28 / SDIP32

Watchdog t i mer,

One 16-bit timer,

SPI

Watchdog timer,

One 16-bit timer,

SPI, ADC

Watchdog t imer,

Two 16-bit timers,

SPI, ADC

Watchdog t i m er,

Two 16-bit timers,

SPI, I²C, ADC

Rev. 2.6

November 2000 1/140

This is preliminary information on a new product in development or undergoing evaluation. Details are subject to change without notice.

1

Table of Contents

1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 PIN DESCRIPT ION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 REGISTER & ME MORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.3 STRUCTURAL ORGANISATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.4 IN-SITU PROGRAMMING (ISP) MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.5 MEMORY READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6 CENTRAL PROCESSING UNIT (Cont’d ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7.1 LOW VOLTAGE DET ECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.2 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.2.2 Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.2.3 Internal Low Voltage Detection RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.2.4 Internal Watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.3 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.4 CLOCK SECURITY SYSTEM (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.4.1 Clock Filter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.4.2 Safe Os c illator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.4.3 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.4.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.5 CLOCK RESET AND SUPPLY REGISTER DESCRIPTION (CRSR) . . . . . . . . . . . . . . . 23

7.6 MAIN CLOCK CONTROLLER (MCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

9 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

9.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

9.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8

9.4 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

10 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

10.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

10.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

10.2.1 Input Mod es . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

10.2.2 O ut put Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

140

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Table of Contents

10.2.3Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

10.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

10.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

10.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

10.6 REGISTER DESCRIPT ION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

11 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

11.1 I/O PORT INTERRUPT SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

11.2 I/O PORT ALTERNATE FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

11.3 MISCELLANEOUS REGISTER DESCRIPT ION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

12 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

12.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

12.1.1 Int roduc tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

12.1.2Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

12.1.3 F unct ional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

12.1.4Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

12.1.5L ow Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

12.1.6Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

12.1.7Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

12.2 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

12.2.1 Int roduc tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

12.2.2Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

12.2.3 F unct ional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

12.2.4L ow Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

12.2.5Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

12.2.6Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

12.2.7Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

12.3 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

12.3.1 Int roduc tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

12.3.2Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

12.3.3 G eneral description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

12.3.4 F unct ional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

12.3.5L ow Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

12.3.6Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

12.3.7Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

12.4 I2C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

12.4.1 Int roduc tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

12.4.2Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

12.4.3General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

12.4.4 F unct ional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

12.4.5L ow Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

12.4.6Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

12.4.7Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

12.5 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

12.5.1 Int roduc tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

12.5.2Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

12.5.3 F unct ional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

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12.5.4L ow Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

12.5.5Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

12.5.6Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

13 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

13.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

13.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

13.1.2Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

13.1.3Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

13.1.4 Index ed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

13.1.5Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

13.1.6I ndi rect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

13.1.7Relative Mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

13.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

14 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

14.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

14.1.1 M inimu m and M axim um values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

14.1.2Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

14.1.3Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

14.1.4 L oading capaci tor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

14.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

14.2 ABSOLUTE MAXIM UM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

14.2.1Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

14.2.2Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

14.2.3Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

14.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

14.3.1 G eneral Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

14.3.2Operating Conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . 100

14.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

14.4.1RUN and SLOW Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

14.4.2 W AIT and SLOW WAIT M odes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

14.4.3HALT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

14.4.4 Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

14.4.5On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

14.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

14.5.1 G eneral Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

14.5.2External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

14.5.3Cry st al and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

14.5.4RC Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

14.5.5Clock Security System (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

14.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

14.6.1RA M and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

14.6.2FLASH Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

14.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

14.7.1 F unct ional EMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

14.7.2Absolute Electrical Sen sitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

14.7.3ESD Pin Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

14.8 I/O PORT PIN CHARACT ERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

140

4/140

Table of Contents

14.8.1General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

14.8.2Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

14.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

14.9.1A sy nchronous RE SET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

14.9.2ISPSEL Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

14.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

14.10.1Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

14.10.216-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

14.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 125

14.11.1SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

14.11.2I2C - Inter IC Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

14.12 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

15 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

15.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

15.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

15.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

16 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 133

16.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

16.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 134

16.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

16.3.1PACKAGE/SOCKET FOOTPRINT PROPOSAL . . . . . . . . . . . . . . . . . . . . . . . . . . 137

16.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

16.5 TO GET MORE INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

17 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

5/140

ST72104G, ST72215G, ST72216G, ST 72254G

1 INTRODUCTION

The ST72104G, ST72215G, ST72216G and
ST72254G devices are members of the S T7 mi­crocontroller family. They can be grouped as fol­lows:

– ST72254G devices are designed for mid-range

applications with ADC and I²C interface capabili­ties.

– ST72215/6G dev ices ta rget the same range of

applications but without I²C interface.

– ST72104G devices are for applications that do

not need ADC and I²C peripherals.

All devices are based on a common industry­standard 8-bit core, featuring an enhanced instruc­tion set.

The ST72C104G, ST72C215 G, ST72C216G and
ST72C254G versions feature single-voltage
FLASH memory with byte-by-byte In-Situ Pro­gramming (ISP) capability.

Figure 1. General Block D iagram

Internal

OSC1
OSC2

V
V

RESET

DD

SS

MULTI OSC

+

CLOCK F ILTE R

LVD

POWER

SUPPLY

CONTROL

8-BIT CO RE

ALU

PROGRAM

MEMORY

(4 or 8K Bytes)

CLOCK

Under software control, all devices can be p laced
in WAIT, SLOW, or HALT mode , reducing power
consumption when the application is in idle or
stand-by state.

The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micro­controllers feature true bit manipulation, 8x8 un­signed multiplication and indirect addressing
modes.

For easy reference, all parametric data are located
in Section 14 on page 96.

I2C

PA7:0

PORT A

SPI

ADDRESS AND DATA BUS

PORT B

16-BIT TIMER A

PORT C

8-BIT ADC

16-BIT TIMER B

(8 bits)

PB7:0

(8 bits)

PC5:0

(6 bits)

6/140

4

RAM

(256 Bytes)

WATCHDOG

2 PIN DESCRI PTION

Figure 2. 28-Pin SO Package Pinout

ST72104G, ST72215G, ST72216G, ST72254G

RESET

OSC1
OSC2

SS

/PB7

ISPCLK/SCK/PB6

ISPDATA/MISO/PB5

MOSI/PB4

OCMP2_A/PB3

ICAP2_A/PB2

OCMP1_A/PB1

ICAP1_A/PB0

AIN5/EXTCLK_A/PC5

AIN4/OCMP2_B/PC4

AIN3/ICAP2_B/PC3

Figure 3. 32-Pin SDIP Package Pinout

RESET

OSC1
OSC2

SS

/PB7

ISPCLK/SCK/PB6

ISPDATA/MISO/PB5

MOSI/PB4

NC
NC

OCMP2_A/PB3

ICAP2_A/PB2

OCMP1_A/PB1

ICAP1_A/PB0

AIN5/EXTCLK_A/PC5

AIN4/OCMP2_B/PC4

AIN3/ICAP2_B/PC3

1
2
3
4
5
6
7
8
9
10
11
12
13

14

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

ei1 ei0

ei0 or ei1

ei1

ei0

ei0

ei1

ei0 or ei1

V

28

DD

V

27

SS

ISPSEL

26

PA0

25
24
23
22
21
20
19
18
17
16
15

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

(HS)

PA1

(HS)

PA2

(HS)

PA3

(HS)

PA4

(HS)/SCLI

PA5

(HS)

PA6

(HS)/SDAI

PA7

(HS)
PC0/ICAP1_B/AIN0
PC1/OCMP1_B/AIN1
PC2/MCO/AIN2

(HS) 20mA high sink capability
eiX associated external interrupt vector

V

DD

V

SS

ISPSEL
PA0 (HS)
PA1 (HS)
PA2 (HS)
PA3 (HS)

NC
NC

PA4 (HS)/SCLI
PA5 (HS)
PA6 (HS)/SDAI

PA7 (HS)
PC0/ICAP1_B/AIN0
PC1/OCMP1_B/AIN1

PC2/MCO/AIN2

(HS) 20mA high sink capability
eiX associated external interrupt vector

7/140

5

ST72104G, ST72215G, ST72216G, ST 72254G

PIN DESCRIPTION (Cont’d)

For external pin connection guidelines, refer to Section 14 "ELECTRICAL CHARACTERISTICS" on page

96.

Legend / Abbreviations for Table 1:

Type: I = input, O = output, S = supply
Input level: A = Dedicated analog input
In/Output level: C = CMOS 0.3V

= CMOS 0.3VDD/0.7VDD with input trigger

C

T

Output level: HS = 20mA high sink (on N-buffer only)
Port and control configuration:

– Input: float = floating, wpu = weak pull-up, int = interrupt
– Output : OD = open drain

Refe r to Section 10 "I/O PORTS" on page 30 f or more details on the software configuration of the I/O
ports.

The RESET configur at i on of each pin i s sh ow n in b o ld. This config u ra ti o n is valid as long as the device i s
in reset state.

Table 1. Device Pin Description

/0.7VDD,

DD

2)

, PP = push-pull

1)

, ana = analog

Pin n°

Pin Name

SO28

SDIP32

1 1 RESET I/O C
2 2 OSC1

3 3 OSC2
4 4 PB7/SS

5 5 PB6/SCK/ISPCLK I/O C
6 6 PB5/MISO/ISPDATA I/O C
7 7 PB4/MOSI I/O C

8 NC

9 NC
10 8 PB3/OCMP2_A I/O C
11 9 PB2/ICAP2_A I/O C
12 10 PB1 /OCMP1_A I/O C
13 11 PB0 /ICAP1_A I/O C

14 12 PC5/EXTCLK_A/AIN5 I/O C

15 13 PC4/OCMP2_B/AIN4 I/O C

16 14 PC3/ ICAP2_B/AIN3 I/O C

3)

3)

I/O C

Level Port / Control

Type

T

I

O

Input Output

Input

Output

float

X ei1 X X Port B7 SPI Slave Select (active low)

T

X ei1 X X Port B6 SPI Serial Clock or ISP Clock

T

X ei1 X X Port B5

T

X ei1 X X Port B4 SPI Master Out / Slave In Data

T

X ei1 X X Port B3 Timer A Output Compare 2

T

X ei1 X X Port B2 Timer A Input Capture 2

T

X ei1 X X Port B1 Timer A Output Compare 1

T

X ei1 X X Port B0 Timer A Input Capture 1

T

X ei0/ei1 X X Port C5

T

X ei0/ei1 X X Port C4

T

X ei0/ei1 X X X Port C3

T

int

wpu

X X Top priority non maskable interrupt (active low)

ana

OD

Not Connected

Main

Function

(after reset)

PP

External clock input or Resonator oscillator in­verter input or resistor input for RC oscillator

Resonator oscillator inverter output or capaci­tor input for RC oscillator

Alternate Function

SPI Master In/ Slave Out Data
or ISP Data

Timer A Input Clock or ADC
Analog Input 5

Timer B Output Compare 2 or
ADC Analog Input 4

Timer B Input Capture 2 or
ADC Analog Input 3

8/140

6

ST72104G, ST72215G, ST72216G, ST72254G

Pin n°

Level Port / Control

Pin Name

Type

SO28

SDIP32

17 15 PC2/MCO/AIN2 I/O C

18 16 PC1/OCMP1_B/AIN1 I/O C

19 17 PC0/ICAP1_B/AIN0 I/O C
20 18 PA7 I/O C

21 19 PA6 /SDAI I/O C
22 20 PA5 I/O C
23 21 PA4 /SCLI I/O C

Input

Output

T

T

T

HS X ei0 X X Port A7

T

HS X ei0 T Port A6 I2C Data

T

HS X ei0 X X Port A5

T

HS X ei0 T Port A4 I2C Clock

T

24 NC
25 NC
26 22 PA3 I/O C
27 23 PA2 I/O C
28 24 PA1 I/O C
29 25 PA0 I/O C

HS X ei0 X X Port A3

T

HS X ei0 X X Port A2

T

HS X ei0 X X Port A1

T

HS X ei0 X X Port A0

T

30 26 ISPSEL I C X
31 27 V

32 28 V

SS
DD

S Ground
S Main power supply

Input Output

Function

(after reset)

Main

int

wpu

float

ana

OD

PP

X ei0/ei1 X X X Port C2

X ei0/ei1 X X X Port C1

X ei0/ei1 X X X Port C0

Not Connected

In situ programming selection (Should be tied
low in standard user mode).

Alternate Function

Main clock output (f

CPU

) or

ADC Analog Input 2
Timer B Output Compare 1 or

ADC Analog Input 1
Timer B Input Capture 1 or

ADC Analog Input 0

Notes:

1. In the interrupt input column, “eiX” defines the associated exte rnal interrupt vecto r. If the weak pul l-up

column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input,
else the configuration is floating interrupt input.

2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to V
are not implemented). See Section 10 "I/O PORTS" on page 30 and Section 14.8 "I/O PORT PIN CHAR-

DD

ACTERISTICS" on page 118 for more details.

3. OSC1 and OSC2 pins connect a crystal or ceramic resonator, an external RC, or an external source to
the on-chip oscillator see Section 2 "PIN DESCRIPTION" on page 7 and Section 14.5 "CLOCK AND TIM-

ING CHARACTERISTICS" on page 105 for more details.

9/140

ST72104G, ST72215G, ST72216G, ST 72254G

3 REGISTER & MEMORY MAP

As shown in the Figure 4, the MCU is capable of
addressing 64K bytes of memories and I/O regis­ters.

The available memory locations consist of 128
bytes of register location, 256 bytes of RAM and
up to 8Kbytes of user program memory. The RAM
space includes up to 128 bytes for the sta ck from
0100h to 017Fh.

The highest address b ytes contain the user reset
and interrupt vectors.

Figure 4. Me m ory Map

0000h

007Fh
0080h

017Fh
0180h

DFFFh
E000h

FFDFh
FFE0h

FFFFh

HW Registers

(see Table 2)

256 Bytes RAM

Reserved

Program Memory

(4K, 8 KBytes)

Interrupt & Reset Vectors

(see Table 5 on page 26)

IMPORTANT: Memory locations marked as “Re-
served” must neve r be ac cess ed. A cce ssing a re­served area can have unpredictable effects on the
device.

0080h

00FFh
0100h

017Fh

E000h

F000h
FFFFh

Short Addressing RAM

Zero page

(128 Bytes)

Stack or

16-bit Addressing RAM

(128 Bytes)

8 KBytes

4 KBytes

10/140

Table 2. Hardware Register Map

ST72104G, ST72215G, ST72216G, ST72254G

Address Block

0000h
0001h

Port C

0002h

Register

Label

PCDR
PCDDR
PCOR

Register Name

Port C Data Register
Port C Data Direction Register
Port C Option Register

Reset

Status

1)

00h

00h
00h

0003h Reserved (1 Byte)

1)

0004h
0005h
0006h

Port B

PBDR
PBDDR
PBOR

Port B Data Register
Port B Data Direction Register
Port B Option Register

00h

00h
00h

0007h Reserved (1 Byte)
0008h

0009h

000Ah

Port A

PADR
PADDR
PAOR

Port A Data Register
Port A Data Direction Register
Port A Option Register

00h

00h
00h

1)

000Bh

to

Reserved (21 Bytes)

001Fh
0020h MISCR1 Miscellaneous Register 1 00h R/W
0021h

0022h
0023h

SPI

SPIDR
SPICR
SPISR

SPI Data I/O Register
SPI Control Register
SPI Status Register

xxh
0xh
00h

0024h WATCHDOG WDGCR Watchdog Control Register 7Fh R/W

Remarks

2)

R/W

2)

R/W

2)

R/W

R/W
R/W
R/W.

R/W
R/W

R/W

R/W
R/W
Read Only

0025h CRSR Clock, Reset, Supply Control / Status Register 000x 000x R/W
0026h

0027h

0028h

0029h
002Ah
002Bh
002Ch
002Dh
002Eh

I2CCR
I2CSR1

2

I

C

I2CSR2
I2CCCR
I2COAR1
I2COAR2
I2CDR

Control Register
Status Register 1
Status Register 2
Clock Control Register
Own Address Register 1
Own Address Register 2
Data Register

Reserved (2 bytes)

00h
00h
00h
00h
00h
00h
00h

R/W
Read Only
Read Only
R/W
R/W
R/W
R/W

002Fh

to

Reserved (4 Bytes)

0030h

11/140

ST72104G, ST72215G, ST72216G, ST 72254G

Address Block

0031h

0032h

0033h

0034h

0035h

0036h

0037h

0038h

0039h
003Ah
003Bh
003Ch
003Dh
003Eh

003Fh

0040h MISCR2 Miscellaneous Register 2 00h R/W

0041h

0042h

0043h

0044h

0045h

0046h

0047h

0048h

0049h
004Ah
004Bh
004Ch
004Dh
004Eh

004Fh

TIMER A

TIMER B

Register

Label

TACR2
TACR1
TASR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
TACHR
TACLR
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR

TBCR2
TBCR1
TBSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
TBCLR
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR

Register Name

Timer A Control Register 2
Timer A Control Register 1
Timer A Status Register
Timer A Input Capture 1 High Register
Timer A Input Capture 1 Low Register
Timer A Output Compare 1 High Register
Timer A Output Compare 1 Low Register
Timer A Counter High Register
Timer A Counter Low Register
Timer A Alternate Counter High Register
Timer A Alternate Counter Low Register
Timer A Input Capture 2 High Register
Timer A Input Capture 2 Low Register
Timer A Output Compare 2 High Register
Timer A Output Compare 2 Low Register

Timer B Control Register 2
Timer B Control Register 1
Timer B Status Register
Timer B Input Capture 1 High Register
Timer B Input Capture 1 Low Register
Timer B Output Compare 1 High Register
Timer B Output Compare 1 Low Register
Timer B Counter High Register
Timer B Counter Low Register
Timer B Alternate Counter High Register
Timer B Alternate Counter Low Register
Timer B Input Capture 2 High Register
Timer B Input Capture 2 Low Register
Timer B Output Compare 2 High Register
Timer B Output Compare 2 Low Register

Reset

Status

00h
00h
xxh
xxh
xxh
80h
00h

FFh
FCh
FFh
FCh

xxh

xxh

80h

00h

00h

00h

xxh

xxh

xxh

80h

00h
FFh
FCh
FFh
FCh

xxh

xxh

80h

00h

Remarks

R/W
R/W
Read Only
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W

R/W
R/W
Read Only
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W

0050h

to

006Fh
0070h

0071h
0072h

to

007Fh

ADC

ADCDR
ADCCSR

Data Register
Control/Status Register

Reserved (32 Bytes)

Reserved (14 Bytes)

00h

00h

Read Only
R/W

Legend: x=undefined, R/W=read/write
Notes:

1. The contents of the I/O p ort DR registers are readable only i n out put conf iguration. I n i nput conf igura­tion, the values of the I/O pins are returned instead of the DR register contents.

2. The bits associated with unavailable pins must always keep their reset value.

12/140

4 FLASH PROGRAM MEMORY

ST72104G, ST72215G, ST72216G, ST72254G

4.1 INTRODUCTION

FLASH devices have a single voltage non-volatil e
FLASH memory that may be programmed in-situ
(or plugged in a programming t ool) on a byte-by­byte basis.

4.2 MAIN FEATURES

■ Remote In-Situ Programming (ISP) mode

■ Up to 16 bytes programmed in the same cycle

■ MTP memory (Multiple Time Programmable)

■ Read-out memory protection against piracy

4.3 STRUCTURAL ORGANISATION

The FLASH program memory is organised in a
single 8-bit wide memory block which can be used
for storing both code and data constants.

The FLASH program memory is mapped in the up­per part of the ST7 addressing space and includes
the reset and interrupt user vector area .

4.4 IN-SITU PROGRAMMING (ISP) MODE

The FLASH program memory can be programmed
using Remote ISP mode. This ISP mode allows
the contents of the ST7 program memory to be up­dated using a standard ST7 programming tools af­ter the device is mounted on the application board.
This feature can be implem ented with a m inimum
number of added componen ts and bo ard area im­pact.

An example Remote ISP hardware interface to t he
standard ST7 programmi ng tool is described be­low. For more details on ISP programming, refer to
the ST7 Programming Specification.

Remote ISP Overview

The Remote ISP mode is initiated by a specific se­quence on the dedicated ISPSEL pin.

The Remote ISP is performed in three steps:

– Selection of the RAM execution mode
– Download of Remote ISP code in RAM
– Execution of Remote ISP code in RAM to pro-

gram the user program into the FLASH

Remote ISP hardware configuration

In Remote ISP mode, the ST7 has to be supplied
with power (V

and VSS) and a clock signal (os-

DD

cillator and application crystal circuit for example).

This mode needs five signals (plus the V

DD

signal
if necessary) to be connected to the program m ing
tool. This signals are:

– RESET
–V

: device reset

: device ground power supply

SS

– ISPCLK: ISP output serial clock pin
– ISPDATA: ISP input serial data pin
– ISPSEL: Remote ISP mode selection. This pin

must be connected to V
board through a pull-down resistor.

on the application

SS

If any of these pins are used for other purposes on
the application, a serial resist or has to be imple­mented to avoid a conflict if the other device forces
the signal level.

Figure 5 shows a typical hardware interface to a

standard ST7 programming t ool. For more det ails
on the pin locations, refer t o t he d ev ice pin out de­scription.

Figure 5. Typi ca l Remote ISP Inter fa ce

HE10 CONNECTOR TYPE

TO PROGRAMMING TOOL

ISPSEL

DD

V

V

RESET

ISPCLK

ISPDATA

SS

10K

Ω

APPLICATION

47K

1

Ω

C

XTAL

L0

OSC2

ST7

C

L1

OSC1

4.5 MEMORY READ-OUT PROTECTION

The read-out protection is enabled throug h an op­tion bit.

For FLASH devices, when this option is selected,
the program and data stored in the FLASH memo­ry are protected against read-out piracy (including
a re-write protection). When this protection opt ion
is removed the entire FLASH program memory is
first automatically erased. However, the E

2

PROM
data memory (when available) can be protected
only with ROM devices.

13/140

ST72104G, ST72215G, ST72216G, ST 72254G

5 CENTRAL PROCE SSI NG UNIT

5.1 INTRODUCTION

This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.

5.2 MAIN FEATURES

■ 63 basic instructions

■ Fast 8-bit by 8-bit multiply

■ 17 main addressing modes

■ Two 8-bit index registers

■ 16-bit stack pointer

■ Low po wer modes

■ Maskable hardware interrupts

■ Non-maskable software interrupt

5.3 CPU REGISTERS

The 6 CPU registers shown in Figure 1 are not
present in the memory mapping and are accessed
by specific instructions.

Figure 6. CPU Registers

70

RESET VALUE = XXh

70

RESET VALUE = XXh

70

RESET VALUE = XXh

Accumulator (A)

The Accumulator is an 8-bit general purpose reg­ister used to hold operan ds and the results of the
arithmetic and logic calculations and to manipulate
data.

Index Registers (X and Y)

In indexed addressing modes, these 8-bit registers
are used to create either effective addresses or
temporary storage areas for data manipulation.
(The Cross-Assembler generates a precede in­struction (PRE) to indicate that the following in­struction refers to the Y register.)

The Y register is not affected by the interrupt auto­matic procedures (not pushed to and popped from
the stack).

Program Cou nt er (P C )

The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).

ACCUMULA T OR

X INDEX REGISTER

Y INDEX REGISTER

15 8

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

15

RESET VALUE = STACK HIGHER ADDRESS

14/140

PCH

RESET VALUE =

7

70
1C11HI NZ
1X11X1XX

70

8

PCL

0

PROGRAM COUNTER

CONDITION CODE REGISTER

STACK POINTER

X = Undefined Value

ST72104G, ST72215G, ST72216G, ST72254G

CPU REGISTERS (Cont’d)
CONDITION CODE REGISTER (CC)

Read/Write
Reset Value: 111x1xxx

70

111HINZC

The 8-bit Condition Code register c ontains the in­terrupt mask and four flags represent ative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP in­structions.

These bits can be individually tested and/or con­trolled by specific instructions.

Bit 4 = H

Half carry

.

This bit is set by hardware when a carry occurs be­tween bits 3 and 4 of t he ALU during an ADD or
ADC instruction. It is reset by hardware during the
same instructions.
0: No half carry has occurred.
1: A half carry has occurred.

This bit is tested using the JRH or JRNH instruc­tion. The H bit is useful in BCD arithmetic subrou­tines .

Bit 3 = I

Interrupt mask

.

This bit is set by hardware when entering in inter­rupt or by software to disable all interrup ts except
the TRAP software interrupt. This bit is cleared by
software.
0: Interrupts are enabled.
1: Interrupts are disabled.

This bit is controlled by the RIM, SIM and IRET in­structions and is tested by the JRM and JRNM in­structions.

Note: Interrupts requested while I is set are
latched and can be processed whe n I is cleared.
By default an interrupt routine is not in terruptable

because the I bi t is set by hardware at the start of
the routine and reset by the IRET instruction at the
end of the routine. If the I bit is cleared by software
in the interrupt routine, pending interrupts are
serviced regardless of the priority level of the cur­rent interrupt routine.

Bit 2 = N

Negative

.

This bit is set and cleared by hardware. It is repre­sentative of the result sign of the last arithmeti c,
logical or data manipulation. It is a copy of the 7
bit of the result.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative

(i.e. the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instruc­tions.

Zero

Bit 1 = Z

.

This bit is set and cleared by hardware. This bit in­dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from

zero.

1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test

instructions.

Bit 0 = C

Carry/borrow.

This bit is set and cleared b y hardware and soft­ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.

th

15/140

ST72104G, ST72215G, ST72216G, ST 72254G

6 CENTRAL PROCE SSI NG UNIT (Cont’d)

Stack Pointer (SP)

Read/Write
Reset Value: 01 7Fh

15 8

The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD in­struction.

Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, wi th­out indicating the s tack overflow. The previously

00000001

stored information is then o verwritten and there­fore lost. The stack also wraps in case of an under-

70

flow.
The stack is used to save the retu rn address dur-

0 SP6 SP5 SP4 SP3 SP2 SP1 SP0

ing a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate

The Stack Pointer is a 16-bit register which is al­ways pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 7).

Since the stack is 128 bytes deep, the 9 most sig­nificant bits are forced by hardw are. Following a n
MCU Reset, or after a Reset Stack Pointe r instruc­tion (RSP), the Stack Pointer contains its reset val­ue (the SP6 to SP0 bits are set) which is the stack
higher address.

the stack by means of the PUSH and POP instruc­tions. In the case of an interrupt, the PCL is stored
at the first location point ed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 7.

– When an interrupt is received, the SP is decre-

mented and the context is pushed on the stack.

– On return from interrupt, the SP is incremented

and the context is popped from the stack.

A subroutine call occupies two locations and an in­terrupt five locat ions i n the sta ck ar ea.

Figure 7. Stack Manipulation Example

@ 0100h

SP

@ 017Fh

CALL

Subroutine

SP

PCH
PCL

Stack Higher Address = 017Fh
Stack Lower Address =

Interrupt

Event

CC

A

X
PCH
PCL
PCH

PCL

0100h

SP

PUSH Y POP Y IRET

SP

Y

CC

A

X
PCH
PCL
PCH

PCL

CC

A

X
PCH
PCL
PCH
PCL

SP

PCH

PCL

RET

or RSP

SP

16/140

ST72104G, ST72215G, ST72216G, ST72254G

7 SUPPLY, RESET AND CLOCK M ANAGEMENT

The ST72104G, ST72215G, ST72216G and
ST72254G microcontrollers include a range of util­ity features for securing the application in critical
situations (for example in case of a powe r brown­out), and reducing the num ber o f e xternal com po­nents. An overview is shown in Figure 8.

See Section 14 "ELECTRICAL CHARACTERIS-

TICS" on page 96 for more details.

Main Features

■ Supply Manager w ith main supply low vol tage

detection (LVD)

■ Reset Sequence Manager (RSM)

■ Multi-Oscillator (MO)

– 4 Crystal/ C e ra m ic res on ator oscillato r s
– 1 External RC oscillator
– 1 Internal R C os c illa t or

■ Clock Security System (CSS)

– Clock Filt er
– Backup Safe Oscillator

Figure 8. Clock, Reset and Supply Block Diagram

MCO

OSC2

OSC1

RESET

VDD

VSS

MULTI-

OSCILLATOR

(MO)

RESET SEQUENCE

MANAGER

(RSM)

LOW VOLTAGE

DETECTOR

(LVD)

CLOCK SECURITY SYSTEM

CLOCK
FILTER

(CSS)

CRSR

SAFE

OSC

WATCHDOG

PERIPHERAL

FROM

f

OSC

MAIN CLOCK

CONTROLLER

(MCC)

LVD

f

CPU

CSS WDG

IE D00 0 0 RF RF

CSS INTERRUPT

17/140

ST72104G, ST72215G, ST72216G, ST 72254G

7.1 LOW VOLTAGE DETECTOR (LVD)

To allow the integration of power management
features in the application, the Low Voltage Detec­tor function (LVD) generates a static reset when
the V

supply voltage is below a V

DD

reference

IT-

value. This means that it secures the power-up as
well as the power-down keeping the ST7 in reset.

The V
than the V

reference value for a voltage drop is lower

IT-

reference value for power-on in order

IT+

to avoid a parasitic reset when the MCU starts run­ning and sinks current on the supply (hysteresis).

The LVD Reset circuitry generates a reset when
V

is below:

DD

when VDD is rising

–V

IT+

when VDD is falling

–V

IT-

The LVD func t ion is illustrated in the Figure 9.
Provided the minimum V

the oscillator frequency) is above V

value (guaranteed for

DD

, the MCU

IT-

can only be in two modes:

– under full software control
– in static safe reset

Figure 9. Low Voltage Detector vs Reset

V

DD

In these conditions, secure operation is always en­sured for the application without the need for ex­ternal reset hardware.

During a Low Voltage Detector Reset, the RESET
pin is held low, thus p ermitting the MCU to reset
other devices.

Notes:

1. The LVD allows the device to be used without
any external RESET circuitry.

2. Three different reference levels are selectable
through the option byte according to th e applica­tion requirement.

LVD application note

Application software can detect a reset caus ed by
the LVD by reading the LVDRF bit in the CRSR
register.

This bit is set by hardware when a LVD reset is
generated and cleared by software (writing zero).

V

IT+

V

IT-

RESET

V

hyst

18/140

7.2 RESET SEQUENCE MANAGER (RSM)

ST72104G, ST72215G, ST72216G, ST72254G

7.2.1 Introd uction

The reset sequence manager in cludes three RE­SET sources as shown in Figure 11:

■ External RESET source pulse

■ Internal LVD RESET (Low Voltage Detection)

■ Internal WATCHDOG RESET

These sources act on the RESET

pin and it is al-

ways kept low during the delay phase.
The RESET service routine vector is fixed at ad-

dresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET s eque nc e cons i sts o f 3 p has es

as shown in Figure 10:

■ Delay depending on the RESET source

■ 4096 CPU clock cycle delay

■ RESET vector fetch

Figure 11. Reset Block Diagram

V

RESET

DD

R

ON

f

CPU

The 4096 CPU clock cycle delay allows the oscil­lator to stabilise and ensures that recovery has
taken place from the Reset state.

The RESET vector fetch phase duration is 2 clock
cycles.

Figure 10. RESET Sequence Phases

RESET

DELAY

INTERNAL RESET

4096 CLOCK CYCLES

COUNTER

FETCH

VECTOR

INTERNAL
RESET

WATC HDOG RESET

LVD RESET

19/140

ST72104G, ST72215G, ST72216G, ST 72254G

RESET SEQUENCE MANAGER (Cont’d)

7.2.2 Asynchronous External RESET

The RESET
output with integrated R

pin is both an input and an open-drain

weak pull-up resistor.

ON

pin

This pull-up has no fixe d value but varies in ac­cordance with the input voltage. It

can be pulled
low by external circuitry to reset the device. See
electrical characteristics section for more details.

A RESET signal originating from an external
source must have a duration of at least t

h(RSTL)in

in
order to be recognized. This detection is asynchro­nous and therefore the MCU can enter reset state
even in HALT mode.

The RESET

pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electr ical characteris­tics section.

Two RESET sequences can be associated with
this RESET source: short or long external reset
pulse (see Figure 12).

Starting from the external RESET pulse recogni­tion, the device RESET
is pulled low during at least t

pin acts as an output that

w(RSTL)out

.

Figure 12. RESET Sequences

7.2.3 Inte r na l Lo w Volta ge Detection RESET

Two differen t RESET sequences caused by the in­ternal LVD circuitry can be distinguished:

■ Power-On RESET

■ Voltage Drop RESET

The device RESET
pulled low when V
V

DD<VIT-

(falling edge) as shown in Figure 12.

The LVD filters spikes on V

pin acts as an output that is

DD<VIT+

(rising edge) or

larger than t

DD

g(VDD)

to

avoid parasitic resets.

7.2.4 Internal Watchdog RESET

The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 12.

Starting from the Watchdog counter underflow, the
device RESET
low during at least t

pin acts as an output that is pulled

w(RSTL)out

.

V
V

EXTERNAL
RESET
SOURCE

RESET PIN

WATCHDOG
RESET

IT+
IT-

V

DD

RUN

LVD

RESET

DELAY

RUN

t

w(RSTL)out

t

h(RSTL)in

SHORT EXT.

RESET

DELAY

LONG EXT.

RESET

RUN RUN

DELAY

t

h(RSTL)in

WATCHDOG UNDERFLOW

WATCHDOG

RESET

RUN

DELAY

t

w(RSTL)out

INTERNAL RESET (4096 T
FETCH V ECTOR

CPU

)

20/140

7.3 MULTI-OSCILLATOR (MO)

ST72104G, ST72215G, ST72216G, ST72254G

The main clock of the ST7 can be generated by
four different source types coming from the multi­oscillator block:

■ an external source

■ 4 crystal or ceramic resonator oscillators

■ an extern al R C os c illa t or

■ an internal high frequency RC oscillator

Each oscillator is optimized for a given frequenc y
range in terms of consumption and is selectable
through the option byte. The associated hardware
configuration are shown in Table 3. Refer to the
electrical characteristics section for more details.

External Clock Source

In this external clock mode, a clock signal (square,
sinus or triangle) with ~50% duty cycle has to drive
the OSC1 pin while the OSC2 pin is tied to ground.

Crystal/Ceramic Oscillators

This family of oscillators has the advantage of pro­ducing a very accurate rate on the main clock of
the ST7. The select ion within a list of 4 oscillators
with different frequency ranges has to be done by
option byte in order to reduce consumption. In this
mode of the multi-oscillator, the resonator a nd the
load capacitors have to be placed as close as pos­sible to the oscillator pins in order to minimize out­put distortion and start-up stabilization time. Th e
loading capacitance values mu st be adjusted ac­cording to the selected oscillator.

These oscillators are not stopped during the
RESET phase to avoid losing time in the oscillator
start-up phase.

Table 3. ST7 Clock Sources

Hardware Configuration

ST7

ST7

LOAD

CAPACITORS

ST7

External ClockCrystal/Ceramic ResonatorsExternal RC OscillatorInternal RC Oscillator

OSC1 OSC2

EXTERNAL

SOURCE

OSC1 OSC2

C

L1

OSC1 OSC2

R

EX

C

L2

C

EX

External RC Oscillator

This oscillator allows a low cost solution for the
main clock of the ST7 using only an external resis­tor and an external capacitor. The frequency of the
external RC oscillator (in the range of some MHz.)
is fixed by the resistor and the capacitor values.
Consequently in this MO mode, the accuracy of
the clock is directly linked to the accuracy of the
discrete components.

Internal RC Oscillator

The internal RC oscillator mode is based on the
same principle as the external RC oscillator includ­ing the resistance and the c apacitance of the de­vice. This mode is the most cost effective one with
the drawback of a lower frequency ac curacy. Its
frequency is in the range of several MHz.

In this mode, the two oscillator pi ns have to be tied
to ground.

ST7

OSC1 OSC2

21/140

ST72104G, ST72215G, ST72216G, ST 72254G

7.4 CLOCK SECURITY SYSTEM (CSS)

The Clock Security System (CSS) protects the
ST7 against main clock problems. To allow the in­tegration of the security features in the applica­tions, it is based on a clock filter control and an In­ternal safe oscillator. The CSS can be e nabled or
disabled by option byte.

7.4.1 Clock Filter Control

The clock filter is based on a clock frequ ency limi­tation function.

This filter function is able to detect and filter high
frequency spikes on the ST7 main clock.

If the oscillator is not working p roperly (e.g. work­ing at a harmonic fr equency of the resonator), the
current active oscillator clock can be totally fil­tered, and then no clock signal is available for the
ST7 from this oscillator anymore. If the original
clock source recovers, the f iltering is s topped au­tomatically and the oscillator supplies the ST7
clock.

7.4.2 Safe Oscillator Control

The safe oscillator of the CSS blo ck is a low fre­quency back-up clock source (see Figur e 13).

If the clock signal disappears (due to a broken or
disconnected resonator...) during a saf e oscillator
period, the safe oscillator delivers a low frequency
clock signal which allows the ST7 to perform some
rescue operations.

Automatically, the ST7 clock source switches back
from the s afe oscilla tor if the orig ina l cloc k sou rce
reco ve rs .

Limitat io n det ect i on

The auto matic safe oscillat or selection is notified
by hardware setting the CSSD bit of the CRSR
register. An interrupt can be generat ed if the CS­SIE bit has been previously set.
These two bits are described in the CRSR register
description.

7.4.3 Low Power Modes

Mode Description

WAIT

HALT

No effect on CSS. CSS interrupt cause the
device to exit from Wait mode.

The CRSR register is frozen. The CSS (in­cluding the safe oscillator) is disabled until
HALT mode is exited. The previous CSS
configuration resumes when the MCU is

woken up by an interrupt with “exit from
HALT mode” capability or from the counter
reset value when the MCU is woken up by a
RESET.

7.4.4 Interrupts

The CSS interrupt event generates an interrupt if
the corresponding Enable Control Bit (CSSIE) is
set and the interrupt mask in the CC register is re­set (RIM instruction).

Interrupt Event

CSS event detection
(safe oscillator acti­vated as main clock)

Flag

Enable

Control

Bit

Event

CSSD CSSIE Yes No

Exit
from
Wait

Exit

from

Halt

1)

Note 1: This interrupt allows to exit from active-halt
mode if this mode is available in the MCU.

Figure 13. C l ock Fi l te r Fun ct ion and S af e Os cillator Functi on

f

/2

OSC

f

FUNCTION

CPU

CLOCK FILTER

f

/2

OSC

f

SFOSC

FUNCTION

f

CPU

SAFE OSCILLATOR

22/140

ST72104G, ST72215G, ST72216G, ST72254G

7.5 CLOCK RESET AND SUPPLY REGISTER DESCRIPTION (CRSR)

Read/Write
Reset Value: 000x 000x (XXh)

70

000

LVD

RF

CSSIECSSDWDG

0

RF

Bit 1 = CSSD
This bit indicates that the safe oscillator of the
clock security system block h as been select ed by
hardware due to a dist urbance on the main clock
signal (f
reading the CRSR register when the original oscil­lato r recovers.

Clock security system detecti o n

). It is set by hardware and c lea red by

OSC

0: Safe oscillator is not active

Bit 7:5 = Reserved, always read as 0.

1: Safe oscillator has been activated
When the CSS is disabled by option byte, the
CSSD bit value is forced to 0.

Bit 4 = LV DRF
This bit indicates that the last RESET was gener­ated by the LVD block. It is set by hardware (LVD
reset) and cleared by software (writing zero). See
WDGRF flag description for more details. When
the LVD is disabled by option by te, the LV DRF bit
value is undefined.

LVD reset flag

Bit 0 = WDGRF

Watchdog reset flag

This bit indicates that the last RESET was gener­ated by the watchdog peripheral. It is set by hard­ware (Watchdog RESET) and cleared by software
(writing zero) or an LVD RESET (to ensure a sta­ble cleared state of the WDGRF flag when the
CPU starts).

Bit 3 = R eserved , always read as 0.

Bit 2 = CSSIE

Clock security syst. interrupt enable

This bit enables the interrupt when a disturbance
is detected by the clock security syste m (CSSD bit
set). It is set and cleared by software.

Combined with the LVDRF flag information, the
flag description is given by the following table.

RESET Sources LVDRF WDGRF

External RESET
Watchdog 0 1
LVD 1 X

pin 0 0

0: Clock security system interrupt disabled
1: Clock security system interrupt enabled
Refer to Table 5, “Interrupt Mapping,” o n page 26

for more details on the CSS interrupt vector. When
the CSS is disabled by option byte, the CSSIE bit
has no effect.

Application notes

The LVDRF flag is not cleared when another RE­SET type occurs (external or watchdog), the
LVDRF flag remains set to keep t race of the origi­nal failure.
In this case, a watchdog reset can be detected by
software while an external reset can not.

Table 4. Clock, Reset and Supply Register Map and Reset Values

Address

(Hex.)

0025h

Register

Label

CRSR

Reset Value 0 0 0

76543210

LVDRF

x0

CSSIE0CSSD0WDGRF

x

23/140

ST72104G, ST72215G, ST72216G, ST 72254G

7.6 MAIN CLOCK CONTROLLER (MCC)

The Main Clock Controller (MCC) supplies the
clock for the ST7 CPU and its internal peripherals.
It allows SLOW power saving mode to be man­aged by the application.

All functions are managed by the Miscellaneous
register 1 (MISCR1).

The MCC block consists of:

■ A programmable CPU clock prescaler

■ A clock-out signal to supply external devices

The prescaler allows the selection of the main
clock frequency and i s controlled by three bits of
the MISCR1: CP1, CP0 and SMS.

The clock-out capability consists of a dedicated
I/O port pin configurable as an f
drive external devices. It is controlled by the M CO
bit in the MISCR1 register.

See Section 11 "MISCELLANEOUS REGIS-

TERS" on page 36 for more details.

Figure 14. Main Clock Controller (MCC) Block Diagram

PORT

ALTERNATE

f

OSC

/2

MISCR1

FUNCTION

MCO ----

CP1 CP 0

SMS

cloc k out p ut t o

CPU

CLOCK TO CAN

PERIPHERAL

MCO

f

OSC

DIV 2

DIV 2, 4, 8, 16

f

CPU

CPU CLOCK

TO CPU AND

PERIPHERALS

24/140

8 INTE RRUPTS

ST72104G, ST72215G, ST72216G, ST72254G

The ST7 core may be interrupted by one of two dif­ferent methods: maskable hardware interrupts as
listed in the Interrupt Mapping Table and a non­maskable software interrupt (TRAP). The Interrupt
processing flowchart is shown in F igure 1.
The maskable interrupts must be enabled clearing
the I bit in order to be serviced. However, disabled
interrupts may be latched and processed when
they are enabled (see external interrupts subsec ­tion) .

When an interrupt has to be serviced:

– No rmal processing is susp ended at the end of

the current instruction execution.

– The PC, X, A and CC registers are saved onto

the stack.

– The I bit of the CC register is set to prevent addi-

tional interrupts.

– The PC is then loaded with the interrupt vector of

the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
the Interrupt Mapping Table for vector address­es).

The interrupt service routine should finish with the
IRET instruction which c auses the contents o f the
saved registers to be recovered from the stack.

Note: As a consequence of the IRET instruction,
the I bit will be cleared a nd the main pro gram will
resume.

Priority Management

By default, a servicing interrupt cannot be inter­rupted because the I bit is set by hardware enter­ing in interrupt routine.

In the case when several inte rrupt s are simultane­ously pending, an hardware priority defines which
one will be serviced first (see the Interrupt Map­ping Table).

Interrupts and Low Power Mode

All interrupts allow the processor to leave the
WAIT low power mode. Only external and specifi­cally mentioned interrupts allow the processor to
leave the HALT low power mode (refer to the “Exit
from HALT“ column in the I nterrupt Mapping Ta­ble).

8.1 NON MASKABLE SOFTWARE INTERRUPT

This interrupt is entered when the TRAP instruc­tion is executed regardless of the state of the I bit.

It will be serviced according to the flowchart on

Figure 1.

8.2 EXTERNAL INTERRUPTS

External interrupt vectors can be loaded into the
PC register if the corresponding ext ernal interrupt
occurred and if the I bit is cleared. These interrupts
allow the processor to leave the Halt low power
mode.

The external interrupt polarity is selected through
the miscellaneous register or interrupt register (if
available).

An external interrupt triggered on edge will be
latched and the interrupt request automatically
cleared upon entering the interrupt service routine.

If several input pins, connected to the same inter­rupt vector, are configured as interrupts, their sig­nals are logically ANDed before entering the edge/
level detection block.

Caution: The type of sensitivity defined in the Mis­cellaneous or Interrupt register (if available) ap­plies to the ei source. In case of an ANDed source
(as described on the I/O ports section), a low level
on an I/O pin configured as input with interrupt,
masks the interrupt request even in case of rising­edge sensitivity.

8.3 PERIPHERAL INTERRUPTS

Different peripheral interrupt flags in the status
register are able to cause an interrupt when they
are active if both:

– The I bit of the CC register is cleared.
– The corresponding enable bit is set in the control

register.

If any of these two conditions is false, the interrupt
is latched and thus remains pending.

Clearing an interrupt request is done by:
– Writing “0” to the corresponding bit in the status

register or

– Access to the status register while the f lag i s set

followed by a read or write of an associated reg­ister.

Note: the clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being en­abled) will therefore be lost if the clear sequence is
executed.

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ST72104G, ST72215G, ST72216G, ST 72254G

INTERRUPTS (Cont’d)
Figure 15. Inte rru pt P rocessing Flow chart

FROM RESET

N

N

INTER RUPT

PENDING?

Y

STACK PC, X, A, CC

SET I BIT

LOAD PC FROM INTERRUPT VECTOR

EXECUTE INSTRUCTION

RESTORE PC, X, A, CC FROM STACK

I BIT SET?

Y

FETCH NEXT INSTRUCTION

N

THIS CLEARS I BIT BY DEFAULT

IRET?

Y

Table 5. Int errupt Mappin g

N°

Source

Block

Description

RESET Reset

TRAP Soft ware Interr upt no FFFCh-FFFDh
0 ei0 External Interrupt Port A7..0 (C5..0
1 ei1 External Interrupt Port B7..0 (C5..0

1

)

1

) FFF8h-FFF9h

Register

Label

N/A

Priority

Order

Highest

Priority

2 CSS Clock Security System Interrupt CRSR
3 SPI SPI Peripheral Interrupts SPISR FFF4h-FFF5h
4 TIMER A TIMER A Peripheral Interrupts TASR FFF2h-FFF3h
5 Not used FFF0h-FFF1h
6 TIMER B TIMER B Peripheral Interrupts TBSR no FFEEh-FFEFh
7 Not used FFECh-FFEDh
8 Not used FFEA h-FFE Bh
9 Not used FFE8h-FFE9h

10 Not used FFE6h-FFE7h
11 I²C I²C Peripheral Interrupt I2CSRx no FFE4h-FFE5h

12 Not Used FFE2h-FFE3h
13 Not Used FFE0h-FFE1h

Lowest

Priority

Exit
from

HALT

Address

Vector

yes FFFEh-FFFFh

yes

FFFAh-FFFBh

FFF6h-FFF7h

no

Note

1. Configurable by option byte.

26/140

9 POWER SAVIN G MO DES

ST72104G, ST72215G, ST72216G, ST72254G

9.1 INTRODUCTION

To give a large measure of flexibility to the applica­tion in terms of power consumption, three main
power saving modes are implemented in the ST7
(see Figure 16).

After a RESET the normal operating mode is se­lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided by 2 (f

CPU

).

From Run mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.

Figure 16. P ower Saving Mo de Transitions

High

RUN

SLOW

WAIT

9.2 SLOW MODE

This mode has two targets:

– To reduce power consumption by decreasing the

internal clock in the device,

– To adapt the internal clock frequency (f

CPU

) to

the available supply voltage.

SLOW mode is controlled by three bits in the
MISCR1 register: the SMS bit which enables or
disables Slow mode and two CPx bits which select
the internal slow frequency (f

CPU

).

In this mode, the oscillator frequency can be divid­ed by 4, 8, 16 or 32 instead of 2 in norm al ope ra t­ing mode. The CPU and peripherals are clocked at
this lower frequency.

Note: SLOW-WAIT mode is activated when enter­ing WAIT mode while the device is already in
SLOW mode.

Figure 17. SLOW Mode Clock Transitions

f

f

CPU

f

OSC

CP1:0

/2

/4 f

OSC

00 01

/8 f

OSC

OSC

/2

SLOW WAIT

HALT

Low

POWER CONSUMPTION

SMS

MISCR1

NORMALRUN MODE

NEW SLOW

FREQUENCY

REQUEST

REQUEST

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ST72104G, ST72215G, ST72216G, ST 72254G

POWER SAVING MODES (Cont’d)

9.3 WAIT MODE

WAIT mode places the MCU in a low power con­sumption mode by stopping the CPU.
This pow er s av in g mode is s elected by ca llin g the
“WFI” ST7 software instruction.
All peripherals remain active. During WAIT mode,
the I bit of the CC register is forced to 0, to enable
all interrupts. All other registers and mem ory re­main unchanged. The MCU remains in WAIT
mode until an interrupt or Reset occu rs, where up­on the Program Counter branc hes to the starting
address of the interrupt or Reset service routine.
The MCU will r e main in W AIT mod e unt il a Rese t
or an Interrupt occurs, causing it to wake up.

Refer to Figure 18.

Figure 18. WAIT Mode Flow-chart

OSCILLATOR

WFI INSTRUCTION

N

INTERRUPT

Y

PERIPHERALS
CPU
I BIT

N

RESET

Y

OSCILLATOR
PERIPHERALS
CPU
I BIT

4096 CPU CL OCK CYCLE

DELAY

OSCILLATOR
PERIPHERALS
CPU
I BIT

ON
ON

OFF

0

ON

OFF

ON

1

ON
ON
ON

X

1)

FETCH RESE T VECTOR

OR SERVICE INTERRUPT

Note:

1. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.

28/140

POWER SAVING MODES (Cont’d)

ST72104G, ST72215G, ST72216G, ST72254G

9.4 HALT MODE

The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
ST7 HALT instruction (see Figure 20).

The MCU can exit HALT m ode on reception of ei­ther a specific interrupt (see Table 5, “Interrupt

Mapping,” on page 26) or a RESET. When exiting

HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the
4096 CPU cycle delay is used to stabilize the os­cillator. After the start up delay, the CPU resumes
operation by servicing the i nterrupt or by fetching
the reset vector which woke it up (see Figure 19).

When entering HALT mode, the I bit in the CC reg­ister is forced to 0 to e nable interrupt s. Therefore,
if an interrupt is pending, the MCU wakes immedi­ately.

In the HALT mode the m ain oscillator is t urned o ff
causing all internal processing to be stopped, in­cluding the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscilla­tor).

The compatibility of Watchdog operation with
HALT mode is configured by t he “WD GHA LT” op­tion bit of the option byte. The HALT instruction
when executed while the Watchdog system is en­abled, can generate a Watchdog RESET (see

Section 16.1 "OPTION BYTES" on page 133 for

more details).

Figure 19. HALT Mode Timing Overview

HALTRUN RUN

4096 CPU CYCLE

DELAY

Figure 20. HALT Mode Fl ow-chart

HALT INSTRUCTION

WDGHALT

1

WATCHDOG

RESET

N

INTERRUPT

Y

1)

ENABLE

0

OSCILLATOR
PERIPHERALS
CPU
I BIT

N

3)

OSCILLATOR
PERIPHERALS
CPU
I BIT

4096 CPU CL OCK CYCLE

OSCILLATOR
PERIPHERALS
CPU
I BIT

FETCH RESE T VECTOR

OR SERVIC E INTERRUPT

WATCHDO G

RESET

Y

DELAY

DISABLE

OFF

2)

OFF
OFF

0

ON

OFF

ON

1

ON
ON
ON

4)

X

HALT

INSTRUCTION

INTERRUPT

RESET

OR

FETCH

VECTOR

Notes:

1. WDGHALT is an option bit. See option byte sec­tion for more details.

2. Peripheral clocked with an external clock source
can still be active.

3. Only some spec ific interrupt s can exit the MCU
from HALT mode (su ch as ex ternal i nterrupt). Re­fer to Table 5, “Interrupt Mapping,” on page 26 for
more details.

4. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.

29/140

ST72104G, ST72215G, ST72216G, ST 72254G

10 I/O P ORTS

10.1 INTRODUCTION

The I/O ports offer different functional modes:

– transfer of data through digital inputs and outputs
and for specific pins:

– external interrupt generat ion
– alterna te signal input/output for the on-chip pe-

ripherals.

An I/O port contains up to 8 pins. Each pin can be
programmed independently as digital input (with or
without interrupt generation) or digital output.

10.2 FUNCTIONAL DESCRIPTION

Each port has 2 main registers:
– Data Register (DR)
– Data Direction Register (DDR)
and one optional register:
– Option Register (OR)
Each I/O pin may be programmed using the corre-

sponding register bits in the DDR and OR regis­ters: bit X corresponding to pin X of the port. The
same correspondence is used for the DR register.

The following description takes into account the
OR register, (for specific ports which do not pro­vide this register refer to the I/O Port Implem enta­tion section). The generic I/O block diagram is
shown in Figure 21

10.2.1 Input Modes

The input configuration is sele cted by clearing the
corresponding DDR register bit.

In this case, reading the DR register returns the
digital value applied to the external I/O pin.

Different input modes can be selected by software
through the OR register.

Notes:

1. Writing the DR register modifies the latc h valu e
but does not affect the pin status.

2. When switching from input to output mode, the
DR register has to be written first to drive the cor­rect level on the pin as soon as the port is config­ured as an output.

External interrupt function

When an I/O is configured as Input with Interrupt,
an event on this I/O can generate an external inter­rupt request to the CPU.

Each pin can independent ly generate an int errupt
request. The interrupt sensitivity is independently

programmable using the sensitivity bits in the Mis­cellaneous register.

Each external interrupt vector is linked t o a dedi­cated group of I/O port pins (see pinout description
and interrupt section). If several input pins are se­lected simultaneously as interrupt source, these
are logically ANDed. For t his reason if one of the
interrupt pins is tied low, it masks the other ones.

In case of a floating input with interrupt configura­tion, special care must be taken when changing
the configuration (see Fi gure 22).

The external interrupts are hardware interrupts,
which means that the request latch (not accessible
directly by the application) is automatically cleared
when the corresponding interrupt vector is
fetched. To clear an unwanted pending interrupt
by software, the sensitivity bits in the Miscellane­ous register must be modified.

10.2.2 Output Modes

The output configuration is selecte d by setting the
corresponding DDR register bit. In this case, writ­ing the DR register applies this digital value to the
I/O pin through the latch. Then reading the DR reg­ister returns the previously stored value.

Two different output modes can be selected by
software through the OR register: Output push-pull
and open-drain.

DR register value and output pin status:

DR Push-pull Open-drain

0V
1V

SS
DD

Vss

Floating

10.2.3 Alternate Functions

When an on-chip peripheral is configured to use a
pin, the alternate function is au tomatically select­ed. This alternate function takes priority over the
standard I/O programming.

When the signal is coming from an on-chip periph­eral, the I/O pin is autom atically conf igured in ou t­put mode (push-pull or open drain according to the
peripheral).

When the signal is goi ng to an on-chip peripheral,
the I/O pin must be configured in input mode. In
this case, the pin state is also digitally readable by
addressing the DR register.

Note: Input pull-up configuration can cause unex­pected value at the input of the alternate peripheral
input. When an on-chip peripheral use a pin as in­put and output, this pin h as to be configured in in­put floating mode.

30/140