STMicroelectronics ST72104G, ST72215G, ST72216G, ST72254G Technical data

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8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,

ADC, 16-BIT TIMERS, SPI, I

■ Memories

– 4K or 8K bytes Program mem ory (ROM and

single voltage FLA SH) with read-out protection and in-situ programming (remote ISP)

– 256 bytes RAM

■ Clock, Res et and Supply M ana g e m ent

– Enhanced reset system – Enhanced low voltage supply supervisor with

3 programmable levels

– Clock sources: crystal/ceramic resonat or os-

cillators or RC oscillators, external clock,

backup Clock Security System – Clock-out capability – 3 Power Saving Modes: Halt, Wait and Slow

■ Interrupt Management

– 7 interru pt vectors plus TRAP and RESET – 22 external interrupt lines (on 2 vectors)

■ 22 I/O Port s

– 22 multifunctional bidirectional I/O lines – 14 alternate function lines – 8 high sink outputs

■ 3 Timers

– Configurable watchdog timer – Two 16-bit timers with: 2 input captures, 2 out-

put compares, external clock input on one tim-

er, PWM and Pulse generator modes

(one only on ST72104Gx and ST72216G1)

■ 2 Communications Interfaces

– SPI synchronous serial interface – I2C multimaster interface

(only on ST72254Gx)

■ 1 Analog peripheral

– 8-bit ADC with 6 input channels

(except on ST72104Gx)

ST72104G, ST72215G,

ST72216G, ST72254G

C INTERFACES

PRELIMINARY DATA

SDIP32

SO28

■ Instruction Set

– 8-bit data manipulation – 63 basic instructions – 17 main addressing modes – 8 x 8 unsigned multiply instruction – True bit manipulation

■ Development Tools

– Full hardware/software development package

Device Summary

Features ST72104G1 ST72104G2 ST72216G1 ST72215G2 ST72254G1 ST72254G2

Program memory - bytes 4K 8K 4K 8K 4K 8K RAM (stack) - bytes 256 (128)

Periphe rals

Operating Supply 3.2V to 5.5V CPU Frequency Up to 8 MHz (with oscillator up to 16 MHz) Operati ng T emperature 0°C to 70°C / -10°C to +85°C (-40°C to +85°C / -40°C t o105°C / -40°C to 125°C optional) Package s SO28 / SDIP32

Watchdog t i mer,

One 16-bit timer,

SPI

Watchdog timer,

One 16-bit timer,

SPI, ADC

Watchdog t imer,

Two 16-bit timers,

SPI, ADC

Watchdog t i m er,

Two 16-bit timers,

SPI, I²C, ADC

Rev. 2.6

November 2000 1/140

This is preliminary information on a new product in development or undergoing evaluation. Details are subject to change without notice.

Table of Contents

1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 PIN DESCRIPT ION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 REGISTER & ME MORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.3 STRUCTURAL ORGANISATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.4 IN-SITU PROGRAMMING (ISP) MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.5 MEMORY READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6 CENTRAL PROCESSING UNIT (Cont’d ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7.1 LOW VOLTAGE DET ECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.2 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.2.2 Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.2.3 Internal Low Voltage Detection RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.2.4 Internal Watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.3 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.4 CLOCK SECURITY SYSTEM (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.4.1 Clock Filter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.4.2 Safe Os c illator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.4.3 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.4.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.5 CLOCK RESET AND SUPPLY REGISTER DESCRIPTION (CRSR) . . . . . . . . . . . . . . . 23

7.6 MAIN CLOCK CONTROLLER (MCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

9 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

9.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

9.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8

9.4 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

10 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

10.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

10.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

10.2.1 Input Mod es . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

10.2.2 O ut put Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

140

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Table of Contents

10.2.3Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

10.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

10.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

10.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

10.6 REGISTER DESCRIPT ION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

11 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

11.1 I/O PORT INTERRUPT SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

11.2 I/O PORT ALTERNATE FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

11.3 MISCELLANEOUS REGISTER DESCRIPT ION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

12 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

12.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

12.1.1 Int roduc tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

12.1.2Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

12.1.3 F unct ional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

12.1.4Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

12.1.5L ow Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

12.1.6Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

12.1.7Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

12.2 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

12.2.1 Int roduc tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

12.2.2Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

12.2.3 F unct ional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

12.2.4L ow Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

12.2.5Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

12.2.6Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

12.2.7Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

12.3 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

12.3.1 Int roduc tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

12.3.2Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

12.3.3 G eneral description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

12.3.4 F unct ional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

12.3.5L ow Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

12.3.6Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

12.3.7Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

12.4 I2C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

12.4.1 Int roduc tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

12.4.2Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

12.4.3General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

12.4.4 F unct ional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

12.4.5L ow Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

12.4.6Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

12.4.7Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

12.5 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

12.5.1 Int roduc tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

12.5.2Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

12.5.3 F unct ional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

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12.5.4L ow Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

12.5.5Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

12.5.6Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

13 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

13.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

13.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

13.1.2Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

13.1.3Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

13.1.4 Index ed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

13.1.5Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

13.1.6I ndi rect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

13.1.7Relative Mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

13.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

14 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

14.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

14.1.1 M inimu m and M axim um values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

14.1.2Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

14.1.3Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

14.1.4 L oading capaci tor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

14.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

14.2 ABSOLUTE MAXIM UM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

14.2.1Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

14.2.2Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

14.2.3Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

14.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

14.3.1 G eneral Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

14.3.2Operating Conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . 100

14.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

14.4.1RUN and SLOW Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

14.4.2 W AIT and SLOW WAIT M odes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

14.4.3HALT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

14.4.4 Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

14.4.5On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

14.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

14.5.1 G eneral Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

14.5.2External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

14.5.3Cry st al and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

14.5.4RC Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

14.5.5Clock Security System (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

14.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

14.6.1RA M and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

14.6.2FLASH Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

14.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

14.7.1 F unct ional EMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

14.7.2Absolute Electrical Sen sitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

14.7.3ESD Pin Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

14.8 I/O PORT PIN CHARACT ERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

140

4/140

Table of Contents

14.8.1General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

14.8.2Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

14.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

14.9.1A sy nchronous RE SET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

14.9.2ISPSEL Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

14.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

14.10.1Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

14.10.216-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

14.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 125

14.11.1SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

14.11.2I2C - Inter IC Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

14.12 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

15 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

15.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

15.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

15.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

16 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 133

16.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

16.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 134

16.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

16.3.1PACKAGE/SOCKET FOOTPRINT PROPOSAL . . . . . . . . . . . . . . . . . . . . . . . . . . 137

16.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

16.5 TO GET MORE INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

17 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

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ST72104G, ST72215G, ST72216G, ST 72254G

1 INTRODUCTION

The ST72104G, ST72215G, ST72216G and ST72254G devices are members of the S T7 microcontroller family. They can be grouped as follows:

– ST72254G devices are designed for mid-range

applications with ADC and I²C interface capabilities.

– ST72215/6G dev ices ta rget the same range of

applications but without I²C interface.

– ST72104G devices are for applications that do

not need ADC and I²C peripherals.

All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruction set.

The ST72C104G, ST72C215 G, ST72C216G and ST72C254G versions feature single-voltage FLASH memory with byte-by-byte In-Situ Programming (ISP) capability.

Figure 1. General Block D iagram

Internal

OSC1 OSC2

V V

RESET

MULTI OSC

CLOCK F ILTE R

LVD

POWER

SUPPLY

CONTROL

8-BIT CO RE

ALU

PROGRAM

MEMORY

(4 or 8K Bytes)

CLOCK

Under software control, all devices can be p laced in WAIT, SLOW, or HALT mode , reducing power consumption when the application is in idle or stand-by state.

The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.

For easy reference, all parametric data are located in Section 14 on page 96.

I2C

PA7:0

PORT A

SPI

ADDRESS AND DATA BUS

PORT B

16-BIT TIMER A

PORT C

8-BIT ADC

16-BIT TIMER B

(8 bits)

PB7:0

(8 bits)

PC5:0

(6 bits)

6/140

RAM

(256 Bytes)

WATCHDOG

2 PIN DESCRI PTION

Figure 2. 28-Pin SO Package Pinout

ST72104G, ST72215G, ST72216G, ST72254G

RESET

OSC1 OSC2

/PB7

ISPCLK/SCK/PB6

ISPDATA/MISO/PB5

MOSI/PB4

OCMP2_A/PB3

ICAP2_A/PB2

OCMP1_A/PB1

ICAP1_A/PB0

AIN5/EXTCLK_A/PC5

AIN4/OCMP2_B/PC4

AIN3/ICAP2_B/PC3

Figure 3. 32-Pin SDIP Package Pinout

RESET

OSC1 OSC2

/PB7

ISPCLK/SCK/PB6

ISPDATA/MISO/PB5

MOSI/PB4

NC NC

OCMP2_A/PB3

ICAP2_A/PB2

OCMP1_A/PB1

ICAP1_A/PB0

AIN5/EXTCLK_A/PC5

AIN4/OCMP2_B/PC4

AIN3/ICAP2_B/PC3

1 2 3 4 5 6 7 8 9 10 11 12 13

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

ei1 ei0

ei0 or ei1

ei1

ei0

ei1

ei0 or ei1

ISPSEL

PA0

25 24 23 22 21 20 19 18 17 16 15

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

(HS)

PA1

(HS)

PA2

(HS)

PA3

(HS)

PA4

(HS)/SCLI

PA5

(HS)

PA6

(HS)/SDAI

PA7

(HS) PC0/ICAP1_B/AIN0 PC1/OCMP1_B/AIN1 PC2/MCO/AIN2

(HS) 20mA high sink capability eiX associated external interrupt vector

ISPSEL PA0 (HS) PA1 (HS) PA2 (HS) PA3 (HS)

NC NC

PA4 (HS)/SCLI PA5 (HS) PA6 (HS)/SDAI

PA7 (HS) PC0/ICAP1_B/AIN0 PC1/OCMP1_B/AIN1

PC2/MCO/AIN2

(HS) 20mA high sink capability eiX associated external interrupt vector

7/140

ST72104G, ST72215G, ST72216G, ST 72254G

PIN DESCRIPTION (Cont’d)

For external pin connection guidelines, refer to Section 14 "ELECTRICAL CHARACTERISTICS" on page

96.

Legend / Abbreviations for Table 1:

Type: I = input, O = output, S = supply Input level: A = Dedicated analog input In/Output level: C = CMOS 0.3V

= CMOS 0.3VDD/0.7VDD with input trigger

Output level: HS = 20mA high sink (on N-buffer only) Port and control configuration:

– Input: float = floating, wpu = weak pull-up, int = interrupt – Output : OD = open drain

Refe r to Section 10 "I/O PORTS" on page 30 f or more details on the software configuration of the I/O ports.

The RESET configur at i on of each pin i s sh ow n in b o ld. This config u ra ti o n is valid as long as the device i s in reset state.

Table 1. Device Pin Description

/0.7VDD,

, PP = push-pull

, ana = analog

Pin n°

Pin Name

SO28

SDIP32

1 1 RESET I/O C 2 2 OSC1

3 3 OSC2 4 4 PB7/SS

5 5 PB6/SCK/ISPCLK I/O C 6 6 PB5/MISO/ISPDATA I/O C 7 7 PB4/MOSI I/O C

8 NC

9 NC 10 8 PB3/OCMP2_A I/O C 11 9 PB2/ICAP2_A I/O C 12 10 PB1 /OCMP1_A I/O C 13 11 PB0 /ICAP1_A I/O C

14 12 PC5/EXTCLK_A/AIN5 I/O C

15 13 PC4/OCMP2_B/AIN4 I/O C

16 14 PC3/ ICAP2_B/AIN3 I/O C

I/O C

Level Port / Control

Type

Input Output

Input

Output

float

X ei1 X X Port B7 SPI Slave Select (active low)

X ei1 X X Port B6 SPI Serial Clock or ISP Clock

X ei1 X X Port B5

X ei1 X X Port B4 SPI Master Out / Slave In Data

X ei1 X X Port B3 Timer A Output Compare 2

X ei1 X X Port B2 Timer A Input Capture 2

X ei1 X X Port B1 Timer A Output Compare 1

X ei1 X X Port B0 Timer A Input Capture 1

X ei0/ei1 X X Port C5

X ei0/ei1 X X Port C4

X ei0/ei1 X X X Port C3

int

wpu

X X Top priority non maskable interrupt (active low)

ana

Not Connected

Main

Function

(after reset)

External clock input or Resonator oscillator inverter input or resistor input for RC oscillator

Resonator oscillator inverter output or capacitor input for RC oscillator

Alternate Function

SPI Master In/ Slave Out Data or ISP Data

Timer A Input Clock or ADC Analog Input 5

Timer B Output Compare 2 or ADC Analog Input 4

Timer B Input Capture 2 or ADC Analog Input 3

8/140

ST72104G, ST72215G, ST72216G, ST72254G

Pin n°

Level Port / Control

Pin Name

Type

SO28

SDIP32

17 15 PC2/MCO/AIN2 I/O C

18 16 PC1/OCMP1_B/AIN1 I/O C

19 17 PC0/ICAP1_B/AIN0 I/O C 20 18 PA7 I/O C

21 19 PA6 /SDAI I/O C 22 20 PA5 I/O C 23 21 PA4 /SCLI I/O C

Input

Output

HS X ei0 X X Port A7

HS X ei0 T Port A6 I2C Data

HS X ei0 X X Port A5

HS X ei0 T Port A4 I2C Clock

24 NC 25 NC 26 22 PA3 I/O C 27 23 PA2 I/O C 28 24 PA1 I/O C 29 25 PA0 I/O C

HS X ei0 X X Port A3

HS X ei0 X X Port A2

HS X ei0 X X Port A1

HS X ei0 X X Port A0

30 26 ISPSEL I C X 31 27 V

32 28 V

SS DD

S Ground S Main power supply

Input Output

Function

(after reset)

Main

int

wpu

float

ana

X ei0/ei1 X X X Port C2

X ei0/ei1 X X X Port C1

X ei0/ei1 X X X Port C0

Not Connected

In situ programming selection (Should be tied low in standard user mode).

Alternate Function

Main clock output (f

CPU

) or

ADC Analog Input 2 Timer B Output Compare 1 or

ADC Analog Input 1 Timer B Input Capture 1 or

ADC Analog Input 0

Notes:

1. In the interrupt input column, “eiX” defines the associated exte rnal interrupt vecto r. If the weak pul l-up

column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input.

2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to V are not implemented). See Section 10 "I/O PORTS" on page 30 and Section 14.8 "I/O PORT PIN CHAR-

ACTERISTICS" on page 118 for more details.

3. OSC1 and OSC2 pins connect a crystal or ceramic resonator, an external RC, or an external source to the on-chip oscillator see Section 2 "PIN DESCRIPTION" on page 7 and Section 14.5 "CLOCK AND TIM-

ING CHARACTERISTICS" on page 105 for more details.

9/140

ST72104G, ST72215G, ST72216G, ST 72254G

3 REGISTER & MEMORY MAP

As shown in the Figure 4, the MCU is capable of addressing 64K bytes of memories and I/O registers.

The available memory locations consist of 128 bytes of register location, 256 bytes of RAM and up to 8Kbytes of user program memory. The RAM space includes up to 128 bytes for the sta ck from 0100h to 017Fh.

The highest address b ytes contain the user reset and interrupt vectors.

Figure 4. Me m ory Map

0000h

007Fh 0080h

017Fh 0180h

DFFFh E000h

FFDFh FFE0h

FFFFh

HW Registers

(see Table 2)

256 Bytes RAM

Reserved

Program Memory

(4K, 8 KBytes)

Interrupt & Reset Vectors

(see Table 5 on page 26)

IMPORTANT: Memory locations marked as “Re- served” must neve r be ac cess ed. A cce ssing a reserved area can have unpredictable effects on the device.

0080h

00FFh 0100h

017Fh

E000h

F000h FFFFh

Short Addressing RAM

Zero page

(128 Bytes)

Stack or

16-bit Addressing RAM

(128 Bytes)

8 KBytes

4 KBytes

10/140

Table 2. Hardware Register Map

ST72104G, ST72215G, ST72216G, ST72254G

Address Block

0000h 0001h

Port C

0002h

Label

PCDR PCDDR PCOR

Port C Data Register Port C Data Direction Register Port C Option Register

Reset

Status

00h

00h 00h

0003h Reserved (1 Byte)

0004h 0005h 0006h

Port B

PBDR PBDDR PBOR

Port B Data Register Port B Data Direction Register Port B Option Register

00h

00h 00h

0007h Reserved (1 Byte) 0008h

0009h

000Ah

Port A

PADR PADDR PAOR

Port A Data Register Port A Data Direction Register Port A Option Register

00h

00h 00h

000Bh

Reserved (21 Bytes)

001Fh 0020h MISCR1 Miscellaneous Register 1 00h R/W 0021h

0022h 0023h

SPI

SPIDR SPICR SPISR

SPI Data I/O Register SPI Control Register SPI Status Register

xxh 0xh 00h

0024h WATCHDOG WDGCR Watchdog Control Register 7Fh R/W

Remarks

R/W

R/W R/W R/W.

R/W R/W

R/W

R/W R/W Read Only

0025h CRSR Clock, Reset, Supply Control / Status Register 000x 000x R/W 0026h

0027h

0028h

0029h 002Ah 002Bh 002Ch 002Dh 002Eh

I2CCR I2CSR1

I2CSR2 I2CCCR I2COAR1 I2COAR2 I2CDR

Control Register Status Register 1 Status Register 2 Clock Control Register Own Address Register 1 Own Address Register 2 Data Register

Reserved (2 bytes)

00h 00h 00h 00h 00h 00h 00h

R/W Read Only Read Only R/W R/W R/W R/W

002Fh

Reserved (4 Bytes)

0030h

11/140

ST72104G, ST72215G, ST72216G, ST 72254G

Address Block

0031h

0032h

0033h

0034h

0035h

0036h

0037h

0038h

0039h 003Ah 003Bh 003Ch 003Dh 003Eh

003Fh

0040h MISCR2 Miscellaneous Register 2 00h R/W

0041h

0042h

0043h

0044h

0045h

0046h

0047h

0048h

0049h 004Ah 004Bh 004Ch 004Dh 004Eh

004Fh

TIMER A

TIMER B

Label

TACR2 TACR1 TASR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR

TBCR2 TBCR1 TBSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR

Timer A Control Register 2 Timer A Control Register 1 Timer A Status Register Timer A Input Capture 1 High Register Timer A Input Capture 1 Low Register Timer A Output Compare 1 High Register Timer A Output Compare 1 Low Register Timer A Counter High Register Timer A Counter Low Register Timer A Alternate Counter High Register Timer A Alternate Counter Low Register Timer A Input Capture 2 High Register Timer A Input Capture 2 Low Register Timer A Output Compare 2 High Register Timer A Output Compare 2 Low Register

Timer B Control Register 2 Timer B Control Register 1 Timer B Status Register Timer B Input Capture 1 High Register Timer B Input Capture 1 Low Register Timer B Output Compare 1 High Register Timer B Output Compare 1 Low Register Timer B Counter High Register Timer B Counter Low Register Timer B Alternate Counter High Register Timer B Alternate Counter Low Register Timer B Input Capture 2 High Register Timer B Input Capture 2 Low Register Timer B Output Compare 2 High Register Timer B Output Compare 2 Low Register

Reset

Status

00h 00h xxh xxh xxh 80h 00h

FFh FCh FFh FCh

xxh

80h

00h

xxh

80h

00h FFh FCh FFh FCh

xxh

80h

00h

Remarks

R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W

0050h

006Fh 0070h

0071h 0072h

007Fh

ADC

ADCDR ADCCSR

Data Register Control/Status Register

Reserved (32 Bytes)

Reserved (14 Bytes)

00h

Read Only R/W

Legend: x=undefined, R/W=read/write Notes:

1. The contents of the I/O p ort DR registers are readable only i n out put conf iguration. I n i nput conf iguration, the values of the I/O pins are returned instead of the DR register contents.

2. The bits associated with unavailable pins must always keep their reset value.

12/140

4 FLASH PROGRAM MEMORY

ST72104G, ST72215G, ST72216G, ST72254G

4.1 INTRODUCTION

FLASH devices have a single voltage non-volatil e FLASH memory that may be programmed in-situ (or plugged in a programming t ool) on a byte-bybyte basis.

4.2 MAIN FEATURES

■ Remote In-Situ Programming (ISP) mode

■ Up to 16 bytes programmed in the same cycle

■ MTP memory (Multiple Time Programmable)

■ Read-out memory protection against piracy

4.3 STRUCTURAL ORGANISATION

The FLASH program memory is organised in a single 8-bit wide memory block which can be used for storing both code and data constants.

The FLASH program memory is mapped in the upper part of the ST7 addressing space and includes the reset and interrupt user vector area .

4.4 IN-SITU PROGRAMMING (ISP) MODE

The FLASH program memory can be programmed using Remote ISP mode. This ISP mode allows the contents of the ST7 program memory to be updated using a standard ST7 programming tools after the device is mounted on the application board. This feature can be implem ented with a m inimum number of added componen ts and bo ard area impact.

An example Remote ISP hardware interface to t he standard ST7 programmi ng tool is described below. For more details on ISP programming, refer to the ST7 Programming Specification.

Remote ISP Overview

The Remote ISP mode is initiated by a specific sequence on the dedicated ISPSEL pin.

The Remote ISP is performed in three steps:

– Selection of the RAM execution mode – Download of Remote ISP code in RAM – Execution of Remote ISP code in RAM to pro-

gram the user program into the FLASH

Remote ISP hardware configuration

In Remote ISP mode, the ST7 has to be supplied with power (V

and VSS) and a clock signal (os-

cillator and application crystal circuit for example).

This mode needs five signals (plus the V

signal if necessary) to be connected to the program m ing tool. This signals are:

– RESET –V

: device reset

: device ground power supply

– ISPCLK: ISP output serial clock pin – ISPDATA: ISP input serial data pin – ISPSEL: Remote ISP mode selection. This pin

must be connected to V board through a pull-down resistor.

on the application

If any of these pins are used for other purposes on the application, a serial resist or has to be implemented to avoid a conflict if the other device forces the signal level.

Figure 5 shows a typical hardware interface to a

standard ST7 programming t ool. For more det ails on the pin locations, refer t o t he d ev ice pin out description.

Figure 5. Typi ca l Remote ISP Inter fa ce

HE10 CONNECTOR TYPE

TO PROGRAMMING TOOL

ISPSEL

RESET

ISPCLK

ISPDATA

10K

Ω

APPLICATION

47K

Ω

XTAL

OSC2

ST7

OSC1

4.5 MEMORY READ-OUT PROTECTION

The read-out protection is enabled throug h an option bit.

For FLASH devices, when this option is selected, the program and data stored in the FLASH memory are protected against read-out piracy (including a re-write protection). When this protection opt ion is removed the entire FLASH program memory is first automatically erased. However, the E

PROM data memory (when available) can be protected only with ROM devices.

13/140

ST72104G, ST72215G, ST72216G, ST 72254G

5 CENTRAL PROCE SSI NG UNIT

5.1 INTRODUCTION

This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation.

5.2 MAIN FEATURES

■ 63 basic instructions

■ Fast 8-bit by 8-bit multiply

■ 17 main addressing modes

■ Two 8-bit index registers

■ 16-bit stack pointer

■ Low po wer modes

■ Maskable hardware interrupts

■ Non-maskable software interrupt

5.3 CPU REGISTERS

The 6 CPU registers shown in Figure 1 are not present in the memory mapping and are accessed by specific instructions.

Figure 6. CPU Registers

RESET VALUE = XXh

Accumulator (A)

The Accumulator is an 8-bit general purpose register used to hold operan ds and the results of the arithmetic and logic calculations and to manipulate data.

Index Registers (X and Y)

In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)

The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack).

Program Cou nt er (P C )

The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).

ACCUMULA T OR

X INDEX REGISTER

Y INDEX REGISTER

15 8

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

RESET VALUE = STACK HIGHER ADDRESS

14/140

PCH

RESET VALUE =

70 1C11HI NZ 1X11X1XX

PCL

PROGRAM COUNTER

CONDITION CODE REGISTER

STACK POINTER

X = Undefined Value

ST72104G, ST72215G, ST72216G, ST72254G

CPU REGISTERS (Cont’d) CONDITION CODE REGISTER (CC)

Read/Write Reset Value: 111x1xxx

111HINZC

The 8-bit Condition Code register c ontains the interrupt mask and four flags represent ative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions.

These bits can be individually tested and/or controlled by specific instructions.

Bit 4 = H

Half carry

This bit is set by hardware when a carry occurs between bits 3 and 4 of t he ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred.

This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines .

Bit 3 = I

Interrupt mask

This bit is set by hardware when entering in interrupt or by software to disable all interrup ts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled.

This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions.

Note: Interrupts requested while I is set are latched and can be processed whe n I is cleared. By default an interrupt routine is not in terruptable

because the I bi t is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine.

Bit 2 = N

Negative

This bit is set and cleared by hardware. It is representative of the result sign of the last arithmeti c, logical or data manipulation. It is a copy of the 7 bit of the result. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative

(i.e. the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instructions.

Zero

Bit 1 = Z

This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from

zero.

1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test

instructions.

Bit 0 = C

Carry/borrow.

This bit is set and cleared b y hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.

15/140

ST72104G, ST72215G, ST72216G, ST 72254G

6 CENTRAL PROCE SSI NG UNIT (Cont’d)

Stack Pointer (SP)

Read/Write Reset Value: 01 7Fh

15 8

The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction.

Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, wi thout indicating the s tack overflow. The previously

00000001

stored information is then o verwritten and therefore lost. The stack also wraps in case of an under-

flow. The stack is used to save the retu rn address dur-

0 SP6 SP5 SP4 SP3 SP2 SP1 SP0

ing a subroutine call and the CPU context during an interrupt. The user may also directly manipulate

The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 7).

Since the stack is 128 bytes deep, the 9 most significant bits are forced by hardw are. Following a n MCU Reset, or after a Reset Stack Pointe r instruction (RSP), the Stack Pointer contains its reset value (the SP6 to SP0 bits are set) which is the stack higher address.

the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location point ed to by the SP. Then the other registers are stored in the next locations as shown in Figure 7.

– When an interrupt is received, the SP is decre-

mented and the context is pushed on the stack.

– On return from interrupt, the SP is incremented

and the context is popped from the stack.

A subroutine call occupies two locations and an interrupt five locat ions i n the sta ck ar ea.

Figure 7. Stack Manipulation Example

@ 0100h

@ 017Fh

CALL

Subroutine

PCH PCL

Stack Higher Address = 017Fh Stack Lower Address =

Interrupt

Event

X PCH PCL PCH

PCL

0100h

PUSH Y POP Y IRET

X PCH PCL PCH

PCL

X PCH PCL PCH PCL

PCH

PCL

RET

or RSP

16/140

ST72104G, ST72215G, ST72216G, ST72254G

7 SUPPLY, RESET AND CLOCK M ANAGEMENT

The ST72104G, ST72215G, ST72216G and ST72254G microcontrollers include a range of utility features for securing the application in critical situations (for example in case of a powe r brownout), and reducing the num ber o f e xternal com ponents. An overview is shown in Figure 8.

See Section 14 "ELECTRICAL CHARACTERIS-

TICS" on page 96 for more details.

Main Features

■ Supply Manager w ith main supply low vol tage

detection (LVD)

■ Reset Sequence Manager (RSM)

■ Multi-Oscillator (MO)

– 4 Crystal/ C e ra m ic res on ator oscillato r s – 1 External RC oscillator – 1 Internal R C os c illa t or

■ Clock Security System (CSS)

– Clock Filt er – Backup Safe Oscillator

Figure 8. Clock, Reset and Supply Block Diagram

MCO

OSC2

OSC1

RESET

VDD

VSS

MULTI-

OSCILLATOR

(MO)

RESET SEQUENCE

MANAGER

(RSM)

LOW VOLTAGE

DETECTOR

(LVD)

CLOCK SECURITY SYSTEM

CLOCK FILTER

(CSS)

CRSR

SAFE

OSC

WATCHDOG

PERIPHERAL

FROM

OSC

MAIN CLOCK

CONTROLLER

(MCC)

LVD

CPU

CSS WDG

IE D00 0 0 RF RF

CSS INTERRUPT

17/140

ST72104G, ST72215G, ST72216G, ST 72254G

7.1 LOW VOLTAGE DETECTOR (LVD)

To allow the integration of power management features in the application, the Low Voltage Detector function (LVD) generates a static reset when the V

supply voltage is below a V

reference

IT-

value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset.

The V than the V

reference value for a voltage drop is lower

IT-

reference value for power-on in order

IT+

to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis).

The LVD Reset circuitry generates a reset when V

is below:

when VDD is rising

–V

IT+

when VDD is falling

–V

IT-

The LVD func t ion is illustrated in the Figure 9. Provided the minimum V

the oscillator frequency) is above V

value (guaranteed for

, the MCU

IT-

can only be in two modes:

– under full software control – in static safe reset

Figure 9. Low Voltage Detector vs Reset

In these conditions, secure operation is always ensured for the application without the need for external reset hardware.

During a Low Voltage Detector Reset, the RESET pin is held low, thus p ermitting the MCU to reset other devices.

Notes:

1. The LVD allows the device to be used without any external RESET circuitry.

2. Three different reference levels are selectable through the option byte according to th e application requirement.

LVD application note

Application software can detect a reset caus ed by the LVD by reading the LVDRF bit in the CRSR register.

This bit is set by hardware when a LVD reset is generated and cleared by software (writing zero).

IT+

IT-

RESET

hyst

18/140

7.2 RESET SEQUENCE MANAGER (RSM)

ST72104G, ST72215G, ST72216G, ST72254G

7.2.1 Introd uction

The reset sequence manager in cludes three RESET sources as shown in Figure 11:

■ External RESET source pulse

■ Internal LVD RESET (Low Voltage Detection)

■ Internal WATCHDOG RESET

These sources act on the RESET

pin and it is al-

ways kept low during the delay phase. The RESET service routine vector is fixed at ad-

dresses FFFEh-FFFFh in the ST7 memory map. The basic RESET s eque nc e cons i sts o f 3 p has es

as shown in Figure 10:

■ Delay depending on the RESET source

■ 4096 CPU clock cycle delay

■ RESET vector fetch

Figure 11. Reset Block Diagram

RESET

CPU

The 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state.

The RESET vector fetch phase duration is 2 clock cycles.

Figure 10. RESET Sequence Phases

RESET

DELAY

INTERNAL RESET

4096 CLOCK CYCLES

COUNTER

FETCH

VECTOR

INTERNAL RESET

WATC HDOG RESET

LVD RESET

19/140

ST72104G, ST72215G, ST72216G, ST 72254G

RESET SEQUENCE MANAGER (Cont’d)

7.2.2 Asynchronous External RESET

The RESET output with integrated R

pin is both an input and an open-drain

weak pull-up resistor.

This pull-up has no fixe d value but varies in accordance with the input voltage. It

can be pulled low by external circuitry to reset the device. See electrical characteristics section for more details.

A RESET signal originating from an external source must have a duration of at least t

h(RSTL)in

in order to be recognized. This detection is asynchronous and therefore the MCU can enter reset state even in HALT mode.

The RESET

pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electr ical characteristics section.

Two RESET sequences can be associated with this RESET source: short or long external reset pulse (see Figure 12).

Starting from the external RESET pulse recognition, the device RESET is pulled low during at least t

pin acts as an output that

w(RSTL)out

Figure 12. RESET Sequences

7.2.3 Inte r na l Lo w Volta ge Detection RESET

Two differen t RESET sequences caused by the internal LVD circuitry can be distinguished:

■ Power-On RESET

■ Voltage Drop RESET

The device RESET pulled low when V V

DD<VIT-

(falling edge) as shown in Figure 12.

The LVD filters spikes on V

pin acts as an output that is

DD<VIT+

(rising edge) or

larger than t

g(VDD)

avoid parasitic resets.

7.2.4 Internal Watchdog RESET

The RESET sequence generated by a internal Watchdog counter overflow is shown in Figure 12.

Starting from the Watchdog counter underflow, the device RESET low during at least t

pin acts as an output that is pulled

w(RSTL)out

V V

EXTERNAL RESET SOURCE

RESET PIN

WATCHDOG RESET

IT+ IT-

RUN

LVD

RESET

DELAY

RUN

w(RSTL)out

h(RSTL)in

SHORT EXT.

RESET

DELAY

LONG EXT.

RESET

RUN RUN

DELAY

h(RSTL)in

WATCHDOG UNDERFLOW

WATCHDOG

RESET

RUN

DELAY

w(RSTL)out

INTERNAL RESET (4096 T FETCH V ECTOR

CPU

)

20/140

7.3 MULTI-OSCILLATOR (MO)

ST72104G, ST72215G, ST72216G, ST72254G

The main clock of the ST7 can be generated by four different source types coming from the multioscillator block:

■ an external source

■ 4 crystal or ceramic resonator oscillators

■ an extern al R C os c illa t or

■ an internal high frequency RC oscillator

Each oscillator is optimized for a given frequenc y range in terms of consumption and is selectable through the option byte. The associated hardware configuration are shown in Table 3. Refer to the electrical characteristics section for more details.

External Clock Source

In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground.

Crystal/Ceramic Oscillators

This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. The select ion within a list of 4 oscillators with different frequency ranges has to be done by option byte in order to reduce consumption. In this mode of the multi-oscillator, the resonator a nd the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Th e loading capacitance values mu st be adjusted according to the selected oscillator.

These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase.

Table 3. ST7 Clock Sources

Hardware Configuration

ST7

LOAD

CAPACITORS

ST7

External ClockCrystal/Ceramic ResonatorsExternal RC OscillatorInternal RC Oscillator

OSC1 OSC2

EXTERNAL

SOURCE

OSC1 OSC2

External RC Oscillator

This oscillator allows a low cost solution for the main clock of the ST7 using only an external resistor and an external capacitor. The frequency of the external RC oscillator (in the range of some MHz.) is fixed by the resistor and the capacitor values. Consequently in this MO mode, the accuracy of the clock is directly linked to the accuracy of the discrete components.

Internal RC Oscillator

The internal RC oscillator mode is based on the same principle as the external RC oscillator including the resistance and the c apacitance of the device. This mode is the most cost effective one with the drawback of a lower frequency ac curacy. Its frequency is in the range of several MHz.

In this mode, the two oscillator pi ns have to be tied to ground.

ST7

OSC1 OSC2

21/140

ST72104G, ST72215G, ST72216G, ST 72254G

7.4 CLOCK SECURITY SYSTEM (CSS)

The Clock Security System (CSS) protects the ST7 against main clock problems. To allow the integration of the security features in the applications, it is based on a clock filter control and an Internal safe oscillator. The CSS can be e nabled or disabled by option byte.

7.4.1 Clock Filter Control

The clock filter is based on a clock frequ ency limitation function.

This filter function is able to detect and filter high frequency spikes on the ST7 main clock.

If the oscillator is not working p roperly (e.g. working at a harmonic fr equency of the resonator), the current active oscillator clock can be totally filtered, and then no clock signal is available for the ST7 from this oscillator anymore. If the original clock source recovers, the f iltering is s topped automatically and the oscillator supplies the ST7 clock.

7.4.2 Safe Oscillator Control

The safe oscillator of the CSS blo ck is a low frequency back-up clock source (see Figur e 13).

If the clock signal disappears (due to a broken or disconnected resonator...) during a saf e oscillator period, the safe oscillator delivers a low frequency clock signal which allows the ST7 to perform some rescue operations.

Automatically, the ST7 clock source switches back from the s afe oscilla tor if the orig ina l cloc k sou rce reco ve rs .

Limitat io n det ect i on

The auto matic safe oscillat or selection is notified by hardware setting the CSSD bit of the CRSR register. An interrupt can be generat ed if the CSSIE bit has been previously set. These two bits are described in the CRSR register description.

7.4.3 Low Power Modes

Mode Description

WAIT

HALT

No effect on CSS. CSS interrupt cause the device to exit from Wait mode.

The CRSR register is frozen. The CSS (including the safe oscillator) is disabled until HALT mode is exited. The previous CSS configuration resumes when the MCU is

woken up by an interrupt with “exit from HALT mode” capability or from the counter reset value when the MCU is woken up by a RESET.

7.4.4 Interrupts

The CSS interrupt event generates an interrupt if the corresponding Enable Control Bit (CSSIE) is set and the interrupt mask in the CC register is reset (RIM instruction).

Interrupt Event

CSS event detection (safe oscillator activated as main clock)

Flag

Enable

Control

Bit

Event

CSSD CSSIE Yes No

Exit from Wait

Exit

from

Halt

Note 1: This interrupt allows to exit from active-halt mode if this mode is available in the MCU.

Figure 13. C l ock Fi l te r Fun ct ion and S af e Os cillator Functi on

OSC

FUNCTION

CPU

CLOCK FILTER

OSC

SFOSC

FUNCTION

CPU

SAFE OSCILLATOR

22/140

ST72104G, ST72215G, ST72216G, ST72254G

7.5 CLOCK RESET AND SUPPLY REGISTER DESCRIPTION (CRSR)

Read/Write Reset Value: 000x 000x (XXh)

000

LVD

CSSIECSSDWDG

Bit 1 = CSSD This bit indicates that the safe oscillator of the clock security system block h as been select ed by hardware due to a dist urbance on the main clock signal (f reading the CRSR register when the original oscillato r recovers.

Clock security system detecti o n

). It is set by hardware and c lea red by

OSC

0: Safe oscillator is not active

Bit 7:5 = Reserved, always read as 0.

1: Safe oscillator has been activated When the CSS is disabled by option byte, the CSSD bit value is forced to 0.

Bit 4 = LV DRF This bit indicates that the last RESET was generated by the LVD block. It is set by hardware (LVD reset) and cleared by software (writing zero). See WDGRF flag description for more details. When the LVD is disabled by option by te, the LV DRF bit value is undefined.

LVD reset flag

Bit 0 = WDGRF

Watchdog reset flag

This bit indicates that the last RESET was generated by the watchdog peripheral. It is set by hardware (Watchdog RESET) and cleared by software (writing zero) or an LVD RESET (to ensure a stable cleared state of the WDGRF flag when the CPU starts).

Bit 3 = R eserved , always read as 0.

Bit 2 = CSSIE

Clock security syst. interrupt enable

This bit enables the interrupt when a disturbance is detected by the clock security syste m (CSSD bit set). It is set and cleared by software.

Combined with the LVDRF flag information, the flag description is given by the following table.

RESET Sources LVDRF WDGRF

External RESET Watchdog 0 1 LVD 1 X

pin 0 0

0: Clock security system interrupt disabled 1: Clock security system interrupt enabled Refer to Table 5, “Interrupt Mapping,” o n page 26

for more details on the CSS interrupt vector. When the CSS is disabled by option byte, the CSSIE bit has no effect.

Application notes

The LVDRF flag is not cleared when another RESET type occurs (external or watchdog), the LVDRF flag remains set to keep t race of the original failure. In this case, a watchdog reset can be detected by software while an external reset can not.

Table 4. Clock, Reset and Supply Register Map and Reset Values

Address

(Hex.)

0025h

Label

CRSR

Reset Value 0 0 0

76543210

LVDRF

CSSIE0CSSD0WDGRF

23/140

ST72104G, ST72215G, ST72216G, ST 72254G

7.6 MAIN CLOCK CONTROLLER (MCC)

The Main Clock Controller (MCC) supplies the clock for the ST7 CPU and its internal peripherals. It allows SLOW power saving mode to be managed by the application.

All functions are managed by the Miscellaneous register 1 (MISCR1).

The MCC block consists of:

■ A programmable CPU clock prescaler

■ A clock-out signal to supply external devices

The prescaler allows the selection of the main clock frequency and i s controlled by three bits of the MISCR1: CP1, CP0 and SMS.

The clock-out capability consists of a dedicated I/O port pin configurable as an f drive external devices. It is controlled by the M CO bit in the MISCR1 register.

See Section 11 "MISCELLANEOUS REGIS-

TERS" on page 36 for more details.

Figure 14. Main Clock Controller (MCC) Block Diagram

PORT

ALTERNATE

OSC

MISCR1

FUNCTION

MCO ----

CP1 CP 0

SMS

cloc k out p ut t o

CPU

CLOCK TO CAN

PERIPHERAL

MCO

OSC

DIV 2

DIV 2, 4, 8, 16

CPU

CPU CLOCK

TO CPU AND

PERIPHERALS

24/140

8 INTE RRUPTS

ST72104G, ST72215G, ST72216G, ST72254G

The ST7 core may be interrupted by one of two different methods: maskable hardware interrupts as listed in the Interrupt Mapping Table and a nonmaskable software interrupt (TRAP). The Interrupt processing flowchart is shown in F igure 1. The maskable interrupts must be enabled clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsec tion) .

When an interrupt has to be serviced:

– No rmal processing is susp ended at the end of

the current instruction execution.

– The PC, X, A and CC registers are saved onto

the stack.

– The I bit of the CC register is set to prevent addi-

tional interrupts.

– The PC is then loaded with the interrupt vector of

the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the Interrupt Mapping Table for vector addresses).

The interrupt service routine should finish with the IRET instruction which c auses the contents o f the saved registers to be recovered from the stack.

Note: As a consequence of the IRET instruction, the I bit will be cleared a nd the main pro gram will resume.

Priority Management

By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware entering in interrupt routine.

In the case when several inte rrupt s are simultaneously pending, an hardware priority defines which one will be serviced first (see the Interrupt Mapping Table).

Interrupts and Low Power Mode

All interrupts allow the processor to leave the WAIT low power mode. Only external and specifically mentioned interrupts allow the processor to leave the HALT low power mode (refer to the “Exit from HALT“ column in the I nterrupt Mapping Table).

8.1 NON MASKABLE SOFTWARE INTERRUPT

This interrupt is entered when the TRAP instruction is executed regardless of the state of the I bit.

It will be serviced according to the flowchart on

Figure 1.

8.2 EXTERNAL INTERRUPTS

External interrupt vectors can be loaded into the PC register if the corresponding ext ernal interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the Halt low power mode.

The external interrupt polarity is selected through the miscellaneous register or interrupt register (if available).

An external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine.

If several input pins, connected to the same interrupt vector, are configured as interrupts, their signals are logically ANDed before entering the edge/ level detection block.

Caution: The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies to the ei source. In case of an ANDed source (as described on the I/O ports section), a low level on an I/O pin configured as input with interrupt, masks the interrupt request even in case of risingedge sensitivity.

8.3 PERIPHERAL INTERRUPTS

Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both:

– The I bit of the CC register is cleared. – The corresponding enable bit is set in the control

If any of these two conditions is false, the interrupt is latched and thus remains pending.

Clearing an interrupt request is done by: – Writing “0” to the corresponding bit in the status

– Access to the status register while the f lag i s set

followed by a read or write of an associated register.

Note: the clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being enabled) will therefore be lost if the clear sequence is executed.

25/140

ST72104G, ST72215G, ST72216G, ST 72254G

INTERRUPTS (Cont’d) Figure 15. Inte rru pt P rocessing Flow chart

FROM RESET

INTER RUPT

PENDING?

STACK PC, X, A, CC

SET I BIT

LOAD PC FROM INTERRUPT VECTOR

EXECUTE INSTRUCTION

RESTORE PC, X, A, CC FROM STACK

I BIT SET?

FETCH NEXT INSTRUCTION

THIS CLEARS I BIT BY DEFAULT

IRET?

Table 5. Int errupt Mappin g

N°

Source

Block

Description

RESET Reset

TRAP Soft ware Interr upt no FFFCh-FFFDh 0 ei0 External Interrupt Port A7..0 (C5..0 1 ei1 External Interrupt Port B7..0 (C5..0

)

) FFF8h-FFF9h

Label

N/A

Priority

Order

Highest

Priority

2 CSS Clock Security System Interrupt CRSR 3 SPI SPI Peripheral Interrupts SPISR FFF4h-FFF5h 4 TIMER A TIMER A Peripheral Interrupts TASR FFF2h-FFF3h 5 Not used FFF0h-FFF1h 6 TIMER B TIMER B Peripheral Interrupts TBSR no FFEEh-FFEFh 7 Not used FFECh-FFEDh 8 Not used FFEA h-FFE Bh 9 Not used FFE8h-FFE9h

10 Not used FFE6h-FFE7h 11 I²C I²C Peripheral Interrupt I2CSRx no FFE4h-FFE5h

12 Not Used FFE2h-FFE3h 13 Not Used FFE0h-FFE1h

Lowest

Priority

Exit from

HALT

Address

Vector

yes FFFEh-FFFFh

yes

FFFAh-FFFBh

FFF6h-FFF7h

Note

1. Configurable by option byte.

26/140

9 POWER SAVIN G MO DES

ST72104G, ST72215G, ST72216G, ST72254G

9.1 INTRODUCTION

To give a large measure of flexibility to the application in terms of power consumption, three main power saving modes are implemented in the ST7 (see Figure 16).

After a RESET the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided by 2 (f

CPU

From Run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status.

Figure 16. P ower Saving Mo de Transitions

High

RUN

SLOW

WAIT

9.2 SLOW MODE

This mode has two targets:

– To reduce power consumption by decreasing the

internal clock in the device,

– To adapt the internal clock frequency (f

CPU

) to

the available supply voltage.

SLOW mode is controlled by three bits in the MISCR1 register: the SMS bit which enables or disables Slow mode and two CPx bits which select the internal slow frequency (f

CPU

In this mode, the oscillator frequency can be divided by 4, 8, 16 or 32 instead of 2 in norm al ope ra ting mode. The CPU and peripherals are clocked at this lower frequency.

Note: SLOW-WAIT mode is activated when entering WAIT mode while the device is already in SLOW mode.

Figure 17. SLOW Mode Clock Transitions

CPU

OSC

CP1:0

/4 f

OSC

00 01

/8 f

OSC

SLOW WAIT

HALT

Low

POWER CONSUMPTION

SMS

MISCR1

NORMALRUN MODE

NEW SLOW

FREQUENCY

REQUEST

27/140

ST72104G, ST72215G, ST72216G, ST 72254G

POWER SAVING MODES (Cont’d)

9.3 WAIT MODE

WAIT mode places the MCU in a low power consumption mode by stopping the CPU. This pow er s av in g mode is s elected by ca llin g the “WFI” ST7 software instruction. All peripherals remain active. During WAIT mode, the I bit of the CC register is forced to 0, to enable all interrupts. All other registers and mem ory remain unchanged. The MCU remains in WAIT mode until an interrupt or Reset occu rs, where upon the Program Counter branc hes to the starting address of the interrupt or Reset service routine. The MCU will r e main in W AIT mod e unt il a Rese t or an Interrupt occurs, causing it to wake up.

Refer to Figure 18.

Figure 18. WAIT Mode Flow-chart

OSCILLATOR

WFI INSTRUCTION

INTERRUPT

PERIPHERALS CPU I BIT

RESET

OSCILLATOR PERIPHERALS CPU I BIT

4096 CPU CL OCK CYCLE

DELAY

OSCILLATOR PERIPHERALS CPU I BIT

ON ON

OFF

ON ON ON

FETCH RESE T VECTOR

OR SERVICE INTERRUPT

Note:

1. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.

28/140

POWER SAVING MODES (Cont’d)

ST72104G, ST72215G, ST72216G, ST72254G

9.4 HALT MODE

The HALT mode is the lowest power consumption mode of the MCU. It is entered by executing the ST7 HALT instruction (see Figure 20).

The MCU can exit HALT m ode on reception of either a specific interrupt (see Table 5, “Interrupt

Mapping,” on page 26) or a RESET. When exiting

HALT mode by means of a RESET or an interrupt, the oscillator is immediately turned on and the 4096 CPU cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes operation by servicing the i nterrupt or by fetching the reset vector which woke it up (see Figure 19).

When entering HALT mode, the I bit in the CC register is forced to 0 to e nable interrupt s. Therefore, if an interrupt is pending, the MCU wakes immediately.

In the HALT mode the m ain oscillator is t urned o ff causing all internal processing to be stopped, including the operation of the on-chip peripherals. All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator).

The compatibility of Watchdog operation with HALT mode is configured by t he “WD GHA LT” option bit of the option byte. The HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog RESET (see

Section 16.1 "OPTION BYTES" on page 133 for

more details).

Figure 19. HALT Mode Timing Overview

HALTRUN RUN

4096 CPU CYCLE

DELAY

Figure 20. HALT Mode Fl ow-chart

HALT INSTRUCTION

WDGHALT

WATCHDOG

RESET

INTERRUPT

ENABLE

OSCILLATOR PERIPHERALS CPU I BIT

4096 CPU CL OCK CYCLE

OSCILLATOR PERIPHERALS CPU I BIT

FETCH RESE T VECTOR

OR SERVIC E INTERRUPT

WATCHDO G

RESET

DELAY

DISABLE

OFF

OFF OFF

OFF

ON ON ON

HALT

INSTRUCTION

INTERRUPT

RESET

FETCH

VECTOR

Notes:

1. WDGHALT is an option bit. See option byte section for more details.

2. Peripheral clocked with an external clock source can still be active.

3. Only some spec ific interrupt s can exit the MCU from HALT mode (su ch as ex ternal i nterrupt). Refer to Table 5, “Interrupt Mapping,” on page 26 for more details.

4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.

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ST72104G, ST72215G, ST72216G, ST 72254G

10 I/O P ORTS

10.1 INTRODUCTION

The I/O ports offer different functional modes:

– transfer of data through digital inputs and outputs and for specific pins:

– external interrupt generat ion – alterna te signal input/output for the on-chip pe-

ripherals.

An I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output.

10.2 FUNCTIONAL DESCRIPTION

Each port has 2 main registers: – Data Register (DR) – Data Direction Register (DDR) and one optional register: – Option Register (OR) Each I/O pin may be programmed using the corre-

sponding register bits in the DDR and OR registers: bit X corresponding to pin X of the port. The same correspondence is used for the DR register.

The following description takes into account the OR register, (for specific ports which do not provide this register refer to the I/O Port Implem entation section). The generic I/O block diagram is shown in Figure 21

10.2.1 Input Modes

The input configuration is sele cted by clearing the corresponding DDR register bit.

In this case, reading the DR register returns the digital value applied to the external I/O pin.

Different input modes can be selected by software through the OR register.

Notes:

1. Writing the DR register modifies the latc h valu e but does not affect the pin status.

2. When switching from input to output mode, the DR register has to be written first to drive the correct level on the pin as soon as the port is configured as an output.

External interrupt function

When an I/O is configured as Input with Interrupt, an event on this I/O can generate an external interrupt request to the CPU.

Each pin can independent ly generate an int errupt request. The interrupt sensitivity is independently

programmable using the sensitivity bits in the Miscellaneous register.

Each external interrupt vector is linked t o a dedicated group of I/O port pins (see pinout description and interrupt section). If several input pins are selected simultaneously as interrupt source, these are logically ANDed. For t his reason if one of the interrupt pins is tied low, it masks the other ones.

In case of a floating input with interrupt configuration, special care must be taken when changing the configuration (see Fi gure 22).

The external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. To clear an unwanted pending interrupt by software, the sensitivity bits in the Miscellaneous register must be modified.

10.2.2 Output Modes

The output configuration is selecte d by setting the corresponding DDR register bit. In this case, writing the DR register applies this digital value to the I/O pin through the latch. Then reading the DR register returns the previously stored value.

Two different output modes can be selected by software through the OR register: Output push-pull and open-drain.

DR register value and output pin status:

DR Push-pull Open-drain

0V 1V

SS DD

Vss

Floating

10.2.3 Alternate Functions

When an on-chip peripheral is configured to use a pin, the alternate function is au tomatically selected. This alternate function takes priority over the standard I/O programming.

When the signal is coming from an on-chip peripheral, the I/O pin is autom atically conf igured in ou tput mode (push-pull or open drain according to the peripheral).

When the signal is goi ng to an on-chip peripheral, the I/O pin must be configured in input mode. In this case, the pin state is also digitally readable by addressing the DR register.

Note: Input pull-up configuration can cause unexpected value at the input of the alternate peripheral input. When an on-chip peripheral use a pin as input and output, this pin h as to be configured in input floating mode.

30/140

I/O PORTS (Cont’d) Figure 21. I /O Port General Blo ck Diag ra m

ST72104G, ST72215G, ST72216G, ST72254G

DATA BUS

DDR SEL

DDR

OR SEL

DR SEL

ALTERNATE OUTPUT

ALTERNATE ENABLE

If implemented

PULL-UP CONFIGURATION

N-BUFFER

CMOS SCHMITT TRIGGER

P-BUFFER (see table below)

PULL-UP (see table below)

PAD

DIODES (see table below)

ANALOG

INPUT

EXTERNAL INTERRUPT SOURCE (eix)

POLARITY SELECTION

Table 6. I/O Port Mode Options

Configuration Mode Pull-Up P-Buffe r

Input

Output

Floating with/without Interrupt Off Pull-up with/withou t Interrupt On Push-pull Open Drain (logic level) Off True Open Drain NI NI NI (see note)

Legend: NI - not implemented

Off - implemented not activated On - implemented and activated

FROM OTHER BITS

ALTERNATE

INPUT

Diodes

to V

Off

Note: The diode to V true open drain pads. A local protection between the pad and V vice against positive stress.

is implemented to protect the de-

is not implemented in the

to V

31/140

ST72104G, ST72215G, ST72216G, ST 72254G

I/O PORTS (Cont’d) Table 7. I/O Port Configurations

Hardware Configuration

NOT IMPLEMENTED IN TRUEOPEN DRAIN I/O PORTS

INPUT

NOT IMPLEMENTED IN TRUE OPEN DRAIN

I/O PORTS

OPEN-DRAIN OUTPUT

PAD

PULL-UP CONFIGURATION

FROM

OTHER

PINS

INTERRUPT CONFIGURATION

DR REGISTER ACCESS

ENABLE OUTPUT

POLARITY

SELECTION

DR REGISTER ACCESS

ALTERNATEALTERNATE

ALTERNATE INPUT

EXTERNAL INTERRUPT SOURCE (ei

ANALOG INPUT

R/W

DAT A BUS

)

DATA BUS

NOT IMPLEMENTED IN TRUE OPEN DRAIN

I/O PORTS

PUSH-PULL OUTPUT

PAD

ENABLE OUTPUT

DR REGISTER ACCESS

ALTERNATEALTERNATE

R/W

DATA BUS

Notes:

1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function outp ut status.

2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content.

32/140

I/O PORTS (Cont’d) CAUTION: The alternate function must not be ac-

tivated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts.

Analog alternate function

When the pin is used as an ADC input, the I/O must be configured as floating input. The analo g multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input.

It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it i s recommended not to have clocking pins located close t o a sele cted analog pin.

WARNING: The analog input voltage level must be within the limits stated in the absolute maximum ratings.

10.3 I/O PORT IMPLEMENTATION

ST72104G, ST72215G, ST72216G, ST72254G

Figure 22. Interrupt I/O Port State Transitions

INPUT

floating/pull-up

interrupt

The I/O port register configurations are summarized as follows.

Interrupt Ports PA7, PA5, PA3:0, PB7:0, PC5:0 (with pull-up)

floating input 0 0 pull-up interrupt input 0 1 open drain output 1 0 push-pull output 1 1

INPUT

floating

(reset state)

MODE DDR OR

OUTPUT

open-drain

OUTPUT push-pull

= DDR, OR

The hardware implementation on each I/O port depends on the settings in the DDR and OR regi sters and specific feature of the I/O port such as ADC Input or true open drain.

Switching these I/O ports from one state to anot her should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 22 Other transitions

True Open D rai n In te rru pt Po rts PA6, PA4 (without pull-up)

MODE DDR OR

floating input 0 0 floating interrupt input 0 1 open drain (high sink ports) 1 X

are potentially risky and shou ld be avoide d, since they are likely to present unwanted side-effects such as spurious interrupt generation.

Table 8. Port Configur at io n

Port Pin name

PA7 floating pull-up interrupt open drain push-pull PA6 floating floating interrupt true open-drain

Port A

Port B PB7:0 floating pull-up interrupt open drain push-pull Port C PC7:0 floating pull-up interrupt open drain push-pull

PA5 floating pull-up interrupt open drain push-pull PA4 floating floating interrupt true open-drain PA3:0 floating pull-up interrupt open drain push-pull

Input (DDR = 0) Output (DDR = 1)

OR = 0 OR = 1 OR = 0 OR = 1 High-Sink

Yes

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ST72104G, ST72215G, ST72216G, ST 72254G

I/O PO R T S (Cont’d)

10.4 LOW POWER MODES

Mode Description

WAIT

HALT

No effect on I/O ports. External interrupts cause the device to exit from WAIT mode.

No effect on I/O ports. External interrupts cause the device to exit from HALT mode.

10.5 INTERRUPTS

The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and the I-bit in the CC register is reset (RIM instruction).

Interrupt Event

External interrupt on selected external event

Event

Flag

Enable

Control

Bit

DDRx

ORx

Exit

from

Wait

Yes Yes

Exit

from

Halt

10.6 REGISTER DESCRIPTION

DATA REGISTER (DR)

Port x Data Register PxDR with x = A, B or C.

Read/Write Reset Value: 0000 0000 (00h)

DATA DIRECTION REGISTER (DDR)

Port x Data Direction Register PxDDR with x = A, B or C.

Read/Write Reset Value: 0000 0000 (00h)

DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0

Bit 7:0 = DD[7:0]

Data direction register 8 bits.

The DDR register gives the input /output direction configuration of the pins. Each bit is set and cleared by software.

0: Input mode 1: Output mode

OPTION REGISTER (OR)

Port x Option Register PxOR with x = A, B or C.

Read/Write Reset Value: 0000 0000 (00h)

O7 O6 O5 O4 O3 O2 O1 O0

Bit 7:0 = O[7:0]

Option register 8 bits.

For specific I/O pins, this register is not implement-

D7 D6 D5 D4 D3 D2 D1 D0

ed. In this case the DDR register is enough to select the I/O pin configuration.

The OR register allows to distinguish: in input

Bit 7:0 = D[7:0] The DR register has a specific behaviour accord-

ing to the selected input/output configuration. Writing the DR register is always taken into account even if the pin is configured as an input; this allows always having the expected le ve l on the pin when toggling to output mode. Reading the DR register returns either the DR register latch content (pin configured as output) or the digital value applied to the I /O pin (pin config ured as input).

Data register 8 bits.

mode if the pull-up with interrupt capability or the basic pull-up configuration is selected, in output mode if the push-pull or open drain configuration is selected.

Each bit is set and cleared by software. Input mode:

0: Floating input 1: Pull-up input with or without interrupt

Output mode: 0: Output open drain (with P-Buffer deactivated) 1: Output push-pull (when available)

34/140

I/O PORTS (Cont’d) Table 9. I/O Port Register Map and Reset Values

ST72104G, ST72215G, ST72216G, ST72254G

Address

(Hex.)

Reset Value

of all I/O port registers

0000h PCDR

0002h PCOR 0004h PBDR

0006h PBOR 0008h PADR

000Ah PAOR

Label

76543210

00000000

MSB LSB0001h PCDDR

MSB LSB0005h PBDDR

MSB LSB0009h PADDR

35/140

ST72104G, ST72215G, ST72216G, ST 72254G

11 MISCELLANEOUS REGISTERS

The miscellaneous registers allow control over several different features such as the external interrupts or the I/O alternate functions.

11.1 I/O PORT INTERRUPT SENSITIVITY

The external interrupt sensitivity is controlled by the ISxx bits of the Miscellaneous register and the OPTION BYTE. This control allows having two fully independent external in terrupt source sensit ivities with configurable sources (using EXTIT option bit) as shown in Figure 23 and Figure 24.

Each external interrupt source can be gen erated on four different events on the pin:

■ Falling edge

■ Rising edge

■ Falling and rising edge

■ Falling edge and low level

To guarantee correct functiona lity, the sensitivity bits in the MISCR1 register must be mo dified on ly when the I bit of the CC regist er is set to 1 (interrupt masked). See I/O port register and Miscellaneous register descriptions for more details on the programming.

11.2 I/O PORT ALTERNATE FUNCTIONS

The MISCR registers manage four I/O port miscellaneous alternate functions:

■ Main clock signal (f

■ SPI pin configuration:

pin internal control to use the PB7 I/O port

–SS

) output on PC2

CPU

function while the SPI is active.

– Master output capability on MOSI pin (PB4)

deactivated while the SPI is active.

– Slave output capability on MISO pin (PB5) de-

activated while the SPI is active.

These functions are described in detail in the Sec-

tion 11.3 "MISCELLANEOUS REGISTER DESCRIPTION" on page 37.

Figure 23. Ext. Interrupt Sensitivity (EXTIT=0)

PA7

PA0 PC5

PC0

PB7

PB0

ei0

INTERRUPT

SOURCE

ei1

INTERRUPT

SOURCE

MISCR1

IS00 IS01

SENSITIVITY

CONTROL

MISCR1

IS10 IS11

SENSITIVITY

CONTROL

Figure 24. Ext. Interrupt Sensitivity (EXTIT=1)

MISCR1

IS00 IS01

SENSITIVITY

CONTROL

MISCR1

IS10 IS11

SENSITIVITY

CONTROL

PA7

PA0

PB7

PB0

PC5

PC0

ei0

INTERRUPT

SOURCE

ei1

INTERRUPT

SOURCE

36/140

ST72104G, ST72215G, ST72216G, ST72254G

MISCELLANE OUS REGISTERS (Con t’d)

11.3 MISCELLANEOUS REGISTER DESCRIPTION

MISCELLANEOUS REGISTER 1 (MISCR1)

Read/Write Reset Value: 0000 0000 (00h)

Bit 2:1 = CP[1:0] These bits select the CPU clock prescaler which is applied in the different slow modes. Their action is conditioned by the setting of the SMS bit. These

CPU clock prescaler

two bits are set and cleared by software

in SLOW mode CP1 CP0

CPU

IS11 IS10 MCO IS01 IS00 CP1 CP0 SMS

Bit 7:6 = IS1[1:0]

ei1 sensitivity

The interrupt sensitivity, defined using the IS1[1:0]

/ 4 0 0

OSC

/ 8 1 0

OSC

/ 16 0 1

OSC

/ 32 1 1

OSC

bits, is applied to the ei1 external interrupts. These two bits can be written only when the I bit of the CC register is set to 1 (interrupt masked).

ei1: Port B (C optional)

External Interrupt Sensit ivity IS11 IS10

Falling edge & low level 0 0 Rising edge only 0 1 Falling edge only 1 0 Rising and falling edge 1 1

Bit 5 = MCO

Main clock out selection

Bit 0 = SMS

Slow mode select

This bit is set and cleared by software. 0: Normal mode. f 1: Slow mode. f

= f

/ 2

CPU

OSC

is given by CP1, CP0 See low power consumption mode and MCC chapters for more details.

This bit enables the MCO alternate function on the PC2 I/O port. It is set and cleared by software. 0: MCO alternate function disabled (I/O pin free for

general-purpose I/O)

1: MCO alternate function enabled (f

CPU

on I/O

port)

Bit 4:3 = IS0[1:0]

ei0 sensitivity

The interrupt sensitivity, defined using the IS0[1:0] bits, is applied to the ei0 external interrupts. These two bits can be written only when the I bit of the CC register is set to 1 (interrupt masked).

ei0: Port A (C optional)

External Interrupt Sensitivity IS01 IS00

Falling edge & low level 0 0 Rising edge only 0 1 Falling edge only 1 0 Rising and falling edge 1 1

37/140

ST72104G, ST72215G, ST72216G, ST 72254G

MISCELLANE OUS REGISTERS (Con t’d) MISCELLANEOUS REGISTER 2 (MISCR2)

Read/Write Reset Value: 0000 0000 (00h)

0 0 0 0 MOD SOD SSM SSI

Bit 7:4 = Reserved

Bit 3 = MOD

SPI Master Output Disable

always read as 0

This bit is set and cleared by software. When set, it disables the SPI Master (MOSI) output signal. 0: SPI Master Output enabled. 1: SPI Master Output disabled.

Bit 2 = SOD

SPI Slave Output Disable

This bit is set and cleared by software. When set it disable the SPI Slave (MISO) output signal. 0: SPI Slave Output enabled. 1: SPI Slave Output disabled.

Bit 1 = SSM

SS mode selection

This bit is set and cleared by software. 0: Normal mode - the level of the SPI SS

input from the external SS

pin.

1: I/O mode, the level of the SPI SS

signal is

signal is read

from the SSI bit.

Bit 0 = SSI

SS internal mode

This bit replaces the SS pin of the SPI when the SSM bit is set to 1. (see SPI description). It is set and cleared by software.

Table 10. Miscellaneous Register M ap and Reset Value s

Address

(Hex.)

0020h

0040h

38/140

Label

MISCR1

Reset Value

MISCR2

Reset Value0000

76543210

IS11

IS10

MCO

IS01

IS00

MOD

CP1

SOD

CP0

SSM

SMS

SSI

12 ON-CHIP PER IPHERALS

12.1 WATCHDOG TIMER (WDG)

ST72104G, ST72215G, ST72216G, ST72254G

12.1.1 Introduction

The Watchdog tim er is used to detect t he occurrence of a software fault, usually generated by external interference or by unforeseen logi cal conditions, which causes the application program to abandon its normal seque nce. The W atchdog circuit generates an MCU reset o n expiry of a programmed time period, unless the program refresh-

es the counter’s contents before the T6 bit becomes cleared.

12.1.2 Main Features

■ Programmable timer (64 increments of 12288

CPU cycles)

■ Programmable reset

■ Reset (if watchdog activated) when the T6 bit

reaches zero

■ Optional reset on HALT instruction

(configurable by option byte)

■ Hardware Watchdog selectable by option byte.

12.1.3 Functional Description

The counter value stored in the CR register (bits T6:T0), is decremented every 12,288 machine cy-

Figure 25. Watchdog Block Diagram

cles, and the length of the timeout perio d can be programmed by the user in 64 increments.

If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T6:T0) rolls over from 40h to 3Fh (T6 becom es cleared), it initia tes a reset cycle pulling low the reset pin for typ ically 500ns.

The application program must write in the CR register at regular intervals during normal operation to prevent an MCU reset. The value to be stored in the CR register must be between FFh and C0h (see Table 11 . Watchdog Timing (fCPU = 8

MHz)):

– The WDGA bit is set (watchdog enabled) – The T6 bit is set to prevent generating an imme-

diate reset

– The T5:T0 bits contain the number of increments

which represents the time delay before the watchdog produces a reset.

CPU

RESET

WATCHDOG CONTROL REGISTER (CR)

WDGA

7-BIT DOWNCOUNTER

CLOCK DIVIDER

12288

39/140

ST72104G, ST72215G, ST72216G, ST 72254G

WATCHD OG TI M E R (Cont’d) Table 11. Watchdog Timing (f

CR Register

initial value

Max FFh 98.304

Min C0h 1.536

= 8 MHz)

CPU

WDG timeout period

(ms)

Notes: Following a reset, the watchdog is disa-

bled. Once activated it cannot be disabled, except by a reset.

The T6 bit can be used to generat e a sof t ware reset (the WDGA bit is set and the T6 bit is cleared).

12.1.4 Hardware Watchdog Option

If Hardware Watchdog is selected by option b yte, the watchdog is always active and the WDGA bit in the CR is not used.

Refe r to the device- specif ic Optio n Byte descri ption.

12.1.5 Low Power Modes WAIT Instruction

No effect on Watchdog.

HALT Instruction

If the Watchdog reset on HALT option is selected by option byte, a H ALT instruction causes an im mediate reset generation if th e Watchdog is activated (WDGA bit is set).

12.1.5.1 Using Halt Mode with the WDG (option)

If the Watchdog reset on HALT option is not selected by option byte, the Halt mo de can be used when the watchdog is enabled.

In this case, the HAL T inst ruction stops the osci llator. When the oscillator is stopped, the WDG stops counting and is no longer able to generate a reset until the microcontroller receives an external interrupt or a reset.

If an external interrupt is received, the WDG restarts counting after 4096 CPU clocks. If a reset is generated, the WDG is disabled (reset state).

Recommendations

– Make sure that an external event is available to

wake up the microcontroller from Halt mode.

– Before executing the HALT instruction, refresh

the WDG counter, to avoid an unexpected WDG

reset immediately after waking up the microcontroller.

– When using an external interrupt to wake up the

microcontroller, reinitialize the corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition.

– For the same reaso n, re initialize the level sensi-

tiveness of each external interrupt as a precautionary measure.

– The opcode for the HALT instruction is 0x8E. To

avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8E from memory. For example, avoid defining a constant in ROM with the value 0x8E.

– As the HALT instruction clears the I bit in the CC

register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt).

12.1.6 Interrupts

None.

12.1.7 Register Description CONTROL REGISTER (CR)

Read/Write Reset Value: 0111 1111 (7Fh)

WDGA T6 T5 T4 T3 T2 T1 T0

Bit 7 = WDGA

Activation bit

. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled

Bit 6:0 = T[6:0]

7-bit timer (MSB to LSB).

These bits contain the decremented value. A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared).

40/140

ST72104G, ST72215G, ST72216G, ST72254G

WATCHD OG TI M E R (Cont’d) Table 12. Watchdog Time r Register Map and Rese t Values

Address

(Hex.)

0024h

Label

WDGCR

Reset Value

76543210

WDGA

41/140

ST72104G, ST72215G, ST72216G, ST 72254G

12.2 16-BIT TIMER

12.2.1 Introduction

The timer consists of a 16-bit free-running counter driven by a programmable prescaler.

It may be used for a variety of purposes, including measuring the pulse lengths of up to two input signals (

input capture

waveforms (

) or generating up to two output

output compare

and

PWM

Pulse lengths and waveform perio ds c an be m odulated from a few microseconds to several milliseconds using the timer prescaler and the CPU clock prescaler.

Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and do not share any resources. They are synchronized a fter a MCU reset as long as the timer clock frequencies are not modified.

This description covers one or two 16-bit timers. In ST7 devices with two timers, regi ster names are prefixed with TA (Timer A) or TB (Timer B).

12.2.2 Main Features

■ Programmable prescaler: f

■ Overflow status flag and maskable interrupt

■ External clock inpu t (must be at le ast 4 times

slower than the CPU

clock speed) with the choice

divided by 2, 4 or 8.

CPU

of active edge

■ Output compare functions with:

– 2 dedicated 16-bit registers – 2 dedicated programmable signals – 2 dedicated status flags – 1 dedicated maskable interrupt

■ Input capture functions with:

– 2 dedicated 16-bit registers – 2 dedicated active edge selection signals – 2 dedicated status flags – 1 dedicated maskable interrupt

■ Pulse Width Modulation mode (PWM)

■ One Pulse mode

■ 5 alternate functions on I/O ports (ICAP1, ICAP2,

OCMP1, OCMP2, EXTCLK)*

12.2.3 Functional Description

12.2.3.1 Counter

The main block of the Programmab le Timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high & low.

Counter Register (CR):

– Counter High Register (CHR) is the most sig-

nific a nt byte (MS By te ) .

– Counter Low Register (CLR) is the least sig-

nificant byte (LS Byte).

Alternate Counter Register (ACR)

– Alternate Count er Hi gh Regi ster ( ACHR) is th e

most significant byte (MS Byte).

– Alternate Counter Low Register (ACLR) is the

least significant byt e (LS Byte).

These two read-only 16-bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit (Timer overflow flag), located in the Stat us register (SR). (See note at the end of paragraph titled 16-bit read sequence).

Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in the 16-bit timer). The reset value of both counters is also FFFCh in One Pulse mode and PWM mode.

The timer clock depends on the cloc k control bits of the CR2 register, as illustrated in Table 13 Clock

Control Bits. The value in the counter regi ster re-

peats every 131.072, 262.144 or 524.288 CPU clock cycles depending on the CC[1:0] bits. The timer frequency c an be f

CPU

/2, f

CPU

/4, f

CPU

or an external frequency.

The Block Diagram is shown in Figure 26. *Note: Some timer pins m ay not be av ai lable (not

bonded) in some ST7 devices. Refer to the device pin out description. When reading an input signal on a non-bonded pin, the value will always be ‘1’.

42/140

16-BIT TIMER (Cont’d) Figure 26. Timer Block Diagram

CPU

ST72104G, ST72215G, ST72216G, ST72254G

ST7 INTERNAL BUS

MCU-PERIPHERAL INTERFACE

EXTCLK

EXEDG

1/2 1/4

1/8

CC[1:0]

8 high

COUNTER

ALTERNATE

COUNTER

OVERFLOW

DETECT CIRCUIT

8 low

8-bit

buffer

high

OUTPUT

COMPARE REGISTER

TIMER INTERNAL BUS

OUTPUT COMPARE

CIRCUIT

low

16 16

low

high

OUTPUT COMPARE REGISTER

88 8

high

INPUT CAPTURE REGISTER

EDGE DETECT

CIRCUIT1

EDGE DETECT

CIRCUIT2

8 8 8

low

high

low

INPUT

CAPTURE

ICAP1

ICAP2

(See note)

TIMER INTERRUPT

ICF2ICF1 000OCF2OCF1 TOF

(Status Register) SR

(Control Register 1) CR1

LATCH1

LATCH2

OC2E

PWMOC1E

OPMFOLV2ICIE OLVL1IEDG1OLVL2FOLV1OCIETOIE

EXEDG

IEDG2CC0CC1

(Control Register 2) CR2

Note: If IC, OC and TO interrupt requests have separate vectors then the last O R is not present (Se e device Interrupt Vector Table)

OCMP1

OCMP2

43/140

ST72104G, ST72215G, ST72216G, ST 72254G

16-BIT TIMER (Cont’d) 16-bit Read Sequence: (from either the Counter

Beginning of the sequence

Read

At t0

MS Byte

Other

instructions

Read

At t0 +∆t

LS Byte

Sequence completed

The user must read the MS Byte f irst, then the LS Byte value is buffered automatically.

This buffered value rem ains unchanged until the 16-bit read sequence is completed, even if the user reads the MS Byte several times.

After a complete reading sequence, if only the CLR register or ACLR register are read, they return the LS Byte of the count value at the time of the read.

Whatever the timer mode used (input capture, output compare, One Pulse mo de or P WM m ode) an overflow occurs when the counter rolls over from FFFFh to 0000h then:

– The TOF bit of the SR register is set. – A timer interrupt is generated if:

– TOIE bit of the CR1 register is set and – I bit of the CC register is cleared.

If one of these cond itions is false, the interrupt remains pending to be issued as soon as they are both true.

LS Byte

is buffered

Returns the buffered

LS Byte value at t0

Clearing the overflow interrupt request is done in two steps:

1.Reading the SR register while the TOF bit is set.

2.An access (read or write) to the CLR register. Note: The TOF bit is not cleared by accessing the

ACLR register. The advantage of accessing the ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously.

The timer is not affected by WAIT mode. In HALT mode, the counter stops counting until the

mode is exited. Count ing then resumes from the previous count (MCU awakened by an interrupt) or from the reset count (MCU awakened by a Reset).

12.2.3.2 External Clock

The external clock (wh ere available) is selected if CC0=1 and CC1=1 in the CR2 register.

The status of the EXEDG bit in the CR2 register determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter.

The counter is synchronised with t he falling edge of the internal CPU clock.

A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the CPU clock frequency.

44/140

ST72104G, ST72215G, ST72216G, ST72254G

16-BIT TIMER (Cont’d) Figure 27. Counter Timing Diagram, internal clock divided by 2

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER

TIMER OVERFL OW FLAG (TOF)

FFFD FFFE FFFF 0000 0001 0002 0003

Figure 28. Counter Timing Diagram, internal clock divided by 4

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGI STER

TIMER OVERFLOW FLAG (TOF)

FFFC FFFD 0000 0001

Figure 29. Counter Timing Diagram, internal clock divided by 8

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

FFFC FFFD

0000

Note: The MCU is in reset state when the internal reset signal is high. When it is low, the MCU is running.

45/140

ST72104G, ST72215G, ST72216G, ST 72254G

16-BIT TIMER (Cont’d)

12.2.3.3 Input Capture

In this section, the index, there are 2 input capture functions in the 16-bit timer.

The two input capture 16-bit registers (IC1R and IC2R) are used to latch the valu e of the free running counter after a transition is detected by the ICAP

pin (see figure 5).

MS Byte LS Byte

ICiR IC

The IC

R register is a read-only register.

The active transition is software programmable

through the IEDG Timing resolution is one count of the free running

counter: (

Procedure:

To use the input capture function, select the following in the CR2 register:

– Sele ct the timer clock (CC[1:0]) (see Table 13

Clock Control Bits).

– Select the edge of the active transition on the

ICAP2 pin with the IEDG2 bit (the ICAP2 pin

must be configured as a floating input). And select the following in the CR1 register: – Set the ICI E bit to ge nerat e an in terrupt after an

input capture com ing from e ither the ICAP1 pin

or the ICAP2 pin – Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit (the ICAP1pin must

be configured as a floating input).

CPU

bit of Control Registers (CRi).

/CC[1:0]).

, may be 1 or 2 because

HR ICiLR

When an input capture occurs: – The ICF – The IC

running counter on the active transition on the ICAP

– A timer interrupt is generated if the ICIE bit i s s e t

and the I bit is cleared in the CC register. Otherwise, the interrupt remains pending until both conditions become true.

Clearing the Input Capture in terrupt request (i.e. clearing the ICF

1. Reading the SR register while the ICF

2. A n acc ess (read or write) to the IC

Notes:

1. A fter reading the IC input capture data is inhibited and ICF never be set until the IC read.

2. The IC counter value which corresponds to the most recent input capture.

3. The 2 input capture functions can be used together even if the timer also uses the 2 output compare functions.

4. In One Pulse mode and PWM mode only the input capture 2 function can be used.

5. The alternate inputs (ICAP1 & ICAP2) are always directly connecte d to the timer. So any transitions on these pins activate the input capture function. Moreover if one of th e ICAP as an input and the s econd one as an output, an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set. This can be avoided if the in put capture function

1).

6. The TOF bit can be used with an interrupt in order to measure events that exce ed the timer range (FFFFh).

bit is set.

R register contains t he val ue of the free

pin (see Figure 31).

bit) is done in two steps:

bit is set.

iLR

HR register, the transfer of

will

LR register is also

R register contains the free running

pin is configured

is disabled by reading the ICiHR (see note

46/140

16-BIT TIMER (Cont’d) Figure 30. Input Capture Block Diagram

ST72104G, ST72215G, ST72216G, ST72254G

ICAP1

ICAP2

EDGE DETECT

CIRCUIT2

IC2R Register

16-BIT

EDGE DETECT

CIRCUIT1

IC1R Register

16-BIT FREE RUNNING

COUNTER

Figure 31. Input Capture Timing Diagram

TIMER CLOCK

ICIE

(Control Register 1) CR1

IEDG1

(Status Register) SR

ICF2ICF1 000

(Control Register 2) CR2

IEDG2

CC0

CC1

COUNTER REGISTER

ICAPi PIN

ICAPi FLAG

ICAPi REGISTER

Note: Active edge is rising edge.

FF01 FF02 FF03

FF03

47/140

ST72104G, ST72215G, ST72216G, ST 72254G

16-BIT TIMER (Cont’d)

12.2.3.4 Output Compare

In this section, the index, there are 2 output compare functions in the 16-bit timer .

This function can be used to control an output waveform or indicate when a period of time has elapsed.

When a match is found bet ween the Output Compare register and the free running counter, the output compare function:

– Assigns pins with a programmable value if the

OCIE bit is set – Sets a flag in the status register – Generates an interrupt if enabled

Two 16-bit registers Output Compare Register 1 (OC1R) and Output Compare Register 2 (OC2R) contain the value to be com pared to the counter register each timer clock cycle.

MS Byte LS Byte

ROC

These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OC

R value to 8000h.

Timing resolution is one count of the free running counter: (

CPU/

CC[1:0]

Procedure:

To use the output compare function, select the following in the CR2 register:

– Set the OC

OCMP

E bit if an output is needed then the

pin is dedicated to the output com pare

signal.

– Sele ct the timer clock (CC[1:0]) (see Table 13

Clock Control Bits).

And select the following in the CR1 register: – Select the OLVL

bit to applied to the OCMPi pins

after the match occurs. – Set the OC IE bit to generate an interrupt if it is

needed. When a match is found between OCRi register

and CR register:

– OCF

bit is set.

, may be 1 or 2 because

HR OCiLR

– The OCMP

pin takes OLVLi bit value (OCMPi

pin latch is forced low during reset).

– A timer interrupt is generated if the OCIE bit is

set in the CR2 register and the I bit is cleared in the CC register (CC).

The OC

R register value required for a specific timing application can be c alcul ated using the following f ormula:

∆t * f

∆ OC

R =

CPU

PRESC

Where:

∆t = Output compare period (in seconds)

= CPU clock frequency (in hertz)

CPU

PRESC

= Timer prescaler factor (2, 4 or 8 de-

pending on CC[1:0] bits, see Table 13

Clock Control Bits)

If the timer clock is an external clock, the formula is:

∆ OC

R = ∆t

* fEXT

Where:

∆t = Output compare period (in seconds)

= External timer clock frequency (in hertz)

EXT

Clearing the output compare interrupt request (i.e.

clearing the OCF

1. Reading the SR register while the OCF

set.

2. An access (read or write) to the OC The following procedure is recommended to pre-

vent the OCF it is read and the write to the OC

– Write to the OC

are inhibited).

– Read the SR register (first step of the clearance

of the OCF

– Write to the OC

compare function and clears the OCF

bit) is done by:

LR register.

bit from being set between the time

R register:

HR register (further compares

bit, which may be already set).

LR register (enables the output

bit).

bit is

48/140

16-BIT TIMER (Cont’d) Notes:

1. After a processor write cycle to the OC

iHR

reg-

ister, the output compare function is inhibited

iLR

until the OC

2. If the OC general I/O port and the OLVL

E bit is not set, the OCMPi pin is a

bit will not appear when a match is f ound but an interrupt could be generated if the OCIE bit is set.

3. When the timer clock is f OCMP

are set while the counter value equals

the OC

R register value (see Figure 33 on page

/2, OCFi and

CPU

53). This behaviour is the same in OPM or

PWM mode. When the timer clock is f external clock mode, O CF

/4, f

CPU

and OCMPi are set

while the counter value equals the OC

CPU

/8 or in

R regis-

ter value plus 1 (see Figure 34 on page 53).

4. The output compare functions can be used both for generating external events on the OCMP pins even if the input capture mode is also used.

5. The value in the 16-bit OC OLV

bit should be changed after each suc-

R register and the

cessful comparison in order to control an output waveform or establish a new elapsed timeout.

ST72104G, ST72215G, ST72216G, ST72254G

Forced Compare Output capabili ty

When the FOLV bit is copied to the OCMPi pin. The OLVi bit has to be toggled in ord er to t oggle th e OCMP it is enabled (OC set by hardware, and thus no interrupt request is generated.

FOLVL

bits have no effect in either One-Pulse

mode or PWM mode.

bit is set by software, the OLVL

pin when

E bit=1). The OCFi bit is then not

Figure 32. Output Compare Block Diagram

16 BIT FREE RUNNING

COUNTER

16-bit

OUTPUT COMPARE

CIRCUIT

16-bit

OC1R Register

16-bit

OC2R Register

OC1E CC0CC1

OC2E

(Control Register 2) CR2

(Control Register 1) CR1

FOLV2 FOLV1

(Status Register) SR

OLVL1OLVL2OCIE

000OCF2OCF1

Latch

OCMP1

OCMP2

49/140

ST72104G, ST72215G, ST72216G, ST 72254G

16-BIT TIMER (Cont’d) Figure 33. Output Compare Timing Diagram, f

INTERNAL CPU CLOC K

TIMER CLOCK

TIMER

CPU

COUNTER REGISTER

OUTPUT COMPARE REGISTER

OUTPUT COMPARE FLAG

OCMP

(OCRi)

(OCFi)

PIN (OLVLi=1)

Figure 34. Output Compare Timing Diagram, f

INTERNAL CPU CLOC K

TIMER CLOCK

COUNTER REGISTER

OUTPUT COMPARE REGISTER

COMPARE REGISTER

OUTPUT COMPARE FLAG

(OCRi)

LATCH

(OCFi)

2ED0 2ED1 2ED2

TIMER

CPU

2ED0 2ED 1 2ED2

2ED3

2ED42ECF

50/140

OCMPi PIN (OLVLi=1)

16-BIT TIMER (Cont’d)

12.2.3.5 One Pulse Mode

One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register.

The One Pulse mode uses the Input Capture1 function and the Output Compare1 function.

Procedure:

To use One Pulse mode:

1. Load the OC1R register with the value corresponding to the length of the pulse (see the formula in the opposite column).

2. Select the following in the CR1 register: – Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after the pulse.

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin during the pulse.

– Select the edge of the a ctive trans ition o n th e

ICAP1 pin with the IEDG1 bit

(the ICAP1 pin

must be configured as floating input).

3. Select the following in the CR2 register: – Set the OC1E bit, the OCMP1 pin is then ded-

icated to the Output Compare 1 function. – Set the OPM bit. – Select the timer clock CC[1:0] (see Table 13

Clock Control Bits).

ST72104G, ST72215G, ST72216G, ST72254G

Clearing the Input Capture in terrupt request (i.e. clearing the ICF

1. Reading the SR register while the ICF

2. A n acc ess (read or write) to the IC The OC1R register value required for a specific

timing application can be calculated usi ng the following formula:

Where: t = Pulse period (in seconds)

= CPU clock frequency (in hertz)

CPU

PRESC

= Timer prescaler factor (2, 4 or 8 depend-

If the timer clock is an external clock the formula is:

Wher e: t = Pulse period (in seconds) f

= External timer clock frequency (in hertz)

EXT

When the value of the counter is equal to the value of the contents of t he OC1R register, the OLV L1 bit is output on the OCMP1 pin (see Figure 35).

bit) is done in two steps:

bit is set.

iLR

R Value =

CPU

PRESC

- 5

ing on the CC[1:0] bits, see Table 13

Clock Control Bits)

OCiR = t

* fEXT

-5

One Pulse mode cycle

When

event occurs

on ICAP1

OCMP1 = OLVL2

Counter is reset

to FFFCh

ICF1 bit is set

When

Counter = OC1R

OCMP1 = OLVL1

Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and the OLVL2 bit is loaded on the OCMP1 pin, th e ICF1 bit is set and the value FFFDh is loaded in the IC1R register.

Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the ICIE bit is set.

Notes:

1. The OCF1 bit cannot be set by hardware in One Pulse mode but the OCF2 bit can generate an Output Compare interrupt.

2. W hen the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both set, the PWM mode is the only active one.

3. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin.

4. The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used t o perfo rm input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each time a valid edge o ccurs on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set.

5. When One Pulse m ode is used OC1R is dedicated to this mode. Nevertheless OC2R and OCF2 can be used to indicate that a period of time has elapsed but cannot generate an output waveform because the OLVL2 level is dedicated to One Pulse mode.

51/140

ST72104G, ST72215G, ST72216G, ST 72254G

16-BIT TIMER (Cont’d) Figure 35. One Pulse Mode Timing Example

COUNTER

ICAP1

OCMP1

FFFC FFF D FFFE 2ED0 2ED1 2ED2

OLVL2

compare1

Note: IEDG1=1, OC1R=2ED 0h, OLV L1=0, OLVL2=1

Figure 36. P ul se Wi dt h M odulation Mo de Ti m in g E x am ple

COUNTER

OCMP1

FFFC FFFD FFFE

34E2

OLVL2

2ED0 2ED1 2ED2

compare2 compare1 compare 2

FFFC FFFD

2ED3

OLVL2OLV L1

34E2 FFFC

OLVL2OLV L1

Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1

52/140

16-BIT TIMER (Cont’d)

12.2.3.6 Pulse Width Modulation Mode

Pulse Width Modulation (PWM) mode enables the generation of a signal wi th a frequency a nd pul se length determined by the value of the OC1R and OC2R registers.

The Pulse Width Modulation mode uses the com plete Output Compare 1 funct ion plus the OC2R register, and so these functions cannot be used when the PWM mode is activated.

Procedure

To use Pulse Width Modulation mode:

1. Load the OC2R register with the value corresponding to the period of the signal using the formula in the opposite column.

2. Load the OC1R register with the value corresponding to the period of the p ulse i f OLVL1= 0 and OLVL2=1, using the formula in the opposite column.

3. Select the following in the CR1 register: – Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after a successful comparison with OC1R register.

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin after a successful comparison with OC2R register.

4. Select the following in the CR2 register: – Set OC1E bit: the OCMP1 pin is then dedicat-

ed to the output compare 1 function. – Set the PWM bit. – Select the timer clock (CC[1:0]) (see Table 13

Clock Control Bits).

If OLVL1=1 and O LVL2=0, t he length of t he pos itive pulse is the difference between the OC2R and OC1R registers.

If OLVL1=OLVL2 a c ontinuous s ign al will be seen on the OCMP1 pin.

Pulse Width Modulation cycle

When

Counter

OCMP1 = OLVL1

= OC1R

When

Counter = OC2R

OCMP1 = OLVL2

Counter is reset

to FFFCh

ST72104G, ST72215G, ST72216G, ST72254G

The OC ing application can be c alcul ated using the following f ormula:

Where: t = Signal or pulse period (in seconds)

CPU

PRESC

If the timer clock is an external clock the formula is:

Wher e: t = Signal or pulse period (in seconds) f

EXT

The Output Compare 2 event causes the counter to be initialized to FFFCh (See Figure 36)

Notes:

1. A fter a write instruction to the OC

2. The OCF1 and OCF2 bits cannot be set by

3. The ICF1 bit is set by hardware when the coun-

4. In PWM mod e the ICAP1 pin can not be used

5. W hen the Pulse Width Modulation (PWM) and

R register value required for a specific tim-

R Value =

CPU

PRESC

- 5

= CPU clock frequency (in hertz)

= Timer prescaler factor (2, 4 or 8 depend-

ing on CC[1:0] bits, see Table 13 Clock

Control Bits)

OCiR = t

* fEXT

-5

= External timer clock frequency (in hertz)

HR register,

the output compare function is inhibited until the

LR register is also written.

hardware in PWM mode, therefore the Output Compare interrupt is inhibited.

ter reaches the OC2R value and can produce a timer interrupt if the ICIE bit is set and the I bit is cleared.

to perform input capture because it is disconnected from the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset after each period and ICF1 can also ge nerate an interrupt if ICIE is set.

One Pulse mode (OPM) bits are both set, the PWM mode is the only active one.

ICF1 bit is set

53/140

ST72104G, ST72215G, ST72216G, ST 72254G

16-BIT TIMER (Cont’d)

12.2.4 Low Power Modes

Mode Description

WAIT

HALT

12.2.5 Interrupts

Input Capture 1 event/Counter reset in PWM mode ICF1 Input Capture 2 event ICF2 Yes No Output Compare 1 event (not available in PWM mode) OCF1 Output Compare 2 event (not available in PWM mode) OCF2 Yes No Timer Overflow event TOF TOIE Yes No

No effect on 16-bit Timer. Timer interrupts cause the device to exit from WAIT mode.

16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous

count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter reset value when the MCU is woken up by a RESET.

If an input capture event occurs on the ICAP ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICF the counter value present when exiting from HALT mode is captured into the IC

Interrupt Event

pin, the input capture detection circuitry is armed. Consequent-

bit is set, and

R register.

Event

Flag

Enable

Control

Bit

ICIE

OCIE

Exit from Wait

Yes No

Exit

from

Halt

Note: The 16-bit Timer interrupt ev ents are co nnecte d to the same inte rrupt vector (see In terrupts chap-

ter). These events generate an interrupt if the correspo nding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).

12.2.6 Summary of Timer modes

MODES

Input Capture (1 and/or 2) Yes Yes Yes Yes Output Compare (1 and/or 2) Yes Yes Yes Yes One Pulse mode No Not Recommended PWM Mode No Not Recommended

See note 4 in Section 12.2.3.5 "One Pulse Mode" on page 54

See note 5 in Section 12.2.3.5 "One Pulse Mode" on page 54

See note 4 in Section 12.2.3.6 "Pulse Width Modulation Mode" on page 56

Input Capture 1 Input Capture 2 Output Compare 1 Output Compare 2

AVAILABLE RESO URC ES

No Partially No No

54/140

16-BIT TIMER (Cont’d)

12.2.7 Register Description

Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the count er and the a lternate counter.

ST72104G, ST72215G, ST72216G, ST72254G

Bit 4 = FOLV2 This bit is set and cleared by software. 0: No effect on the OCMP2 pin. 1:Forces the OLVL2 bit to be copied to the

OCMP2 pin, if the OC 2E bit is set and even if there is no successful compariso n.

Forced Output Compare 2.

CONTROL REGISTER 1 (CR1)

Read/Write Reset Value: 0000 0000 (00h)

ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1

Bit 3 = FOLV1 This bit is set and cleared by software. 0: No effect on the OCMP1 pin. 1: Forces OLVL1 to be copied to the OCMP1 pin, if

the OC1E bit is set and e ven if there i s no successful comparison.

Bit 2 = OLVL2

Bit 7 = ICIE

Input Capture Interrupt Enable.

0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the

ICF1 or ICF2 bit of the SR register is set.

This bit is copied to the OCMP2 pin whenev er a successful compa rison occurs with t h e OC2R reg ister and OCxE is set in the CR2 register. This value is copied to the OCMP1 pin in One Pulse mode and Pulse Width Modulation mode.

Bit 1 = IEDG1

Bit 6 = OCIE 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the

OCF1 or OCF2 bit of the SR registe r is set.

Bit 5 = TOIE 0: Interrupt is inhibited. 1: A timer interrupt is enabled whenever the TOF

bit of the SR register is set.

Output Compare Interrupt Enable.

Timer Overflow Interrupt Enable.

This bit determines wh ich type of level transition on the ICAP1 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture.

Bit 0 = OLVL1 The OLVL1 bi t is c opied to t he OCMP1 pin whenever a successful comparison occurs with the OC1R register and the OC 1E bit is s et in the CR2

Forced Output Compare 1.

Output Level 2.

Input Edge 1.

Output Level 1.

55/140

ST72104G, ST72215G, ST72216G, ST 72254G

16-BIT TIMER (Cont’d) CONTROL REGISTER 2 (CR2)

Read/Write Reset Value: 0000 0000 (00h)

OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG

Bit 4 = PWM 0: PWM mode is not active. 1: PWM mode is active, the OCMP 1 pin outputs a

programmable cyclic signal; the length of the pulse depends on the value of OC1R register; the period depends on the value of OC2R register.

Pulse Width Modulation.

Bit 7 = OC1E

Output Compare 1 Pin Enable.

This bit is used only to outp ut the signal from the timer on the OCMP1 pin (OLV1 in Output Compare mode, both OLV1 and OLV2 in PWM and one-pulse mode). Whatever the value of the OC1E bit, the internal Output Compare 1 function of the timer remains active. 0: OCMP1 pin alternate f unction disa bled (I/O pin

free for general-purpose I/O).

1: OCMP1 pin alternate function enabled.

Bit 6 = OC2E

Output Compare 2 Pin Enable.

This bit is used only to outp ut the signal from the timer on the OCMP2 pin (OLV2 in Output Compare mode). Whatever the value of the OC2E bit, the internal Output Compare 2 function of the timer remains active. 0: OCMP2 pin alternate f unction disa bled (I/O pin

free for general-purpose I/O).

1: OCMP2 pin alternate function enabled.

Bit 5 = OPM

One Pulse mode.

0: One Pulse mode is not active. 1: One Pulse mode is active, the ICAP1 pin can be

used to trigger one pulse on the OCMP1 pin; the active transition is g iven by the I EDG1 bit. Th e length of the generated pulse depends on the contents of the OC1R register.

Bits 3:2 = CC[1:0]

Clock Control.

The timer clock mode depends on these bits:

Table 13. Clock Control Bits

Timer Clock CC1 CC 0

/ 4 0 0

CPU

/ 2 0 1

CPU

/ 8 1 0

CPU

External Clock (where

available)

Note: If the external clock pin is not available, programming the external clock configuration stops the counter.

Bit 1 = IEDG2

Input Edge 2.

This bit determines wh ich type of level transition on the ICAP2 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture.

Bit 0 = EXEDG

External Clock Edge.

This bit determines wh ich type of level transition on the external clock pin (EXTCLK) will trigger the counter register. 0: A falling edge triggers the counter register. 1: A rising edge triggers the counter register.

56/140

ST72104G, ST72215G, ST72216G, ST72254G

16-BIT TIMER (Cont’d) STATUS REGISTER (SR)

Read Only Reset Value: 0000 0000 (00h) The three least significant bits are not used.

ICF1 OCF1 TOF ICF2 OCF2 0 0 0

INPUT CAPTURE 1 HIGH REGISTER (IC1HR)

Read Only Reset Value: Undefined

This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event).

Bit 7 = ICF1

Input Capture Flag 1.

0: No input capture (reset value). 1: An input capture has occurred on the ICAP1 pin

or the counter has reached th e OC2R value in PWM mode. To clear this bit, first read the SR register, then read or write the lo w byte of the IC1R (IC1LR) register.

Bit 6 = OCF1

Output Compare Flag 1.

0: No match (reset value). 1: The content of the free running counter matches

the content of the OC1R regis ter. To clear this bit, first read the SR register, then re ad or write the low byte of the OC1R (OC1LR) register.

Bit 5 = TOF

Timer Overflow Flag.

0: No timer overflow (reset value). 1: The free running counter has rolled over from

FFFFh to 0000h. To clear this bit, first read the SR register, then read or write t he low byte of the CR (CLR) register.

Note: Reading or writing the ACLR register does not clear TOF.

Bit 4 = ICF2

Input Capture Flag 2.

0: No input capture (reset value). 1: An input capture has occurred on the ICAP2

pin. To clear this bit, first read the SR register, then read or write the low byte of the IC2R (IC2LR) register.

Bit 3 = OCF2

Output Compare Flag 2.

0: No match (reset value). 1: The content of the free running counter matches

the content of the OC2R regis ter. To clear this bit, first read the SR register, then re ad or write the low byte of the OC2R (OC2LR) register.

Bit 2-0 = Reserved, forced by hardware to 0.

MSB LSB

INPUT CAPTURE 1 LOW REGISTER (IC1LR)

Read Only Reset Value: Undefined

This is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 1 event).

MSB LSB

OUTPUT COMPARE 1 HIGH REGISTER (OC1HR)

Read/Write Reset Value: 1000 0000 (80h)

This is an 8-bit re gister tha t co ntains t he hi gh part of the value to be compared to the CHR register.

MSB LSB

OUTPUT COMPARE 1 LOW REGISTER (OC1LR)

Read/Write Reset Value: 0000 0000 (00h)

This is an 8-bit register that contains the low part of the value to be compared to the CLR register.

MSB LSB

57/140

ST72104G, ST72215G, ST72216G, ST 72254G

16-BIT TIMER (Cont’d) OUTPUT COMPARE 2 HIGH REGISTER

(OC2HR)

Read/Write Reset Value: 1000 0000 (80h)

This is an 8-bit register that cont ains the high part of the value to be compared to the CHR register.

ALTERNATE COUNTER HIGH REGISTER (ACHR)

Read Only Reset Value: 1111 1111 (FFh)

This is an 8-bit re gister tha t co ntains t he hi gh part of the counter value.

MSB LSB

OUTPUT COMPARE 2 LOW REGISTER (OC2LR)

Read/Write Reset Value: 0000 0000 (00h)

This is an 8-bit register that contains the low part of the value to be compared to the CLR register.

MSB LSB

ALTERNATE COUNTER LOW REGISTER (ACLR)

Read Only Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to SR register does no t clear the TOF bit i n SR register.

MSB LSB

COUNTER HIGH REGISTER (CHR)

MSB LSB

Read Only Reset Value: 1111 1111 (FFh)

This is an 8-bit register that cont ains the high part of the counter value.

INPUT CAPTURE 2 HIGH REGISTER (IC2HR) Read Only

Reset Value: Undefined This is an 8-bit read only register that contains the

high part of the counter value (transferred by the

MSB LSB

Input Capture 2 event).

COUNTER LOW REGISTER (CLR)

MSB LSB

Read Only Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after accessing the SR register clears the TOF bit.

INPUT CAPTURE 2 LOW REGISTER (IC2LR)

Read Only Reset Value: Undefined

This is an 8-bit read only register that contains the low part of the counter value (transferred by the Input Capture 2 event).

MSB LSB

58/140

MSB LSB

ST72104G, ST72215G, ST72216G, ST72254G

16-BIT TIMER (Cont’d) Table 14. 16-Bit Timer Register Map and Reset Values

Address

(Hex.)

Timer A: 32 Timer B: 42

Timer A: 31 Timer B: 41

Timer A: 33 Timer B: 43SRReset Value

Timer A: 34 Timer B: 44

Timer A: 35 Timer B: 45

Timer A: 36 Timer B: 46

Timer A: 37 Timer B: 47

Timer A: 3E Timer B: 4E

Timer A: 3F Timer B: 4F

Label

CR1

Reset Value

CR2

Reset Value

ICHR1

Reset Value

ICLR1

Reset Value

OCHR1

Reset Value

OCLR1

Reset Value

OCHR2

Reset Value

OCLR2

Reset Value

76543210

ICIE

OC1E0OC2E

ICF1

MSB

OCIE

OCF1

------

TOIE0FOLV20FOLV10OLVL20IEDG10OLVL1

OPM

TOF

PWM

ICF2

CC1

OCF2

CC0

IEDG20EXEDG

LSB

Timer A: 38 Timer B: 48

Timer A: 39 Timer B: 49

Timer A: 3A Timer B: 4A

Timer A: 3B Timer B: 4B

Timer A: 3C Timer B: 4C

Timer A: 3D Timer B: 4D

CHR

Reset Value

CLR

Reset Value

ACHR

Reset Value

ACLR

Reset Value

ICHR2

Reset Value

ICLR2

Reset Value

MSB

1111111

MSB

1111110

MSB

1111111

MSB

1111110

MSB

------

LSB

59/140

ST72104G, ST72215G, ST72216G, ST 72254G

12.3 SERIAL PERIPHE R AL IN TE R FACE ( SPI)

12.3.1 Introduction

The Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves.

The SPI is normally us ed for communication between the microcontroller and external peripherals or another microcontroller.

Refer to the Pin Description chapter for the devicespecific pin-out.

12.3.2 Main Features

■ Full duplex, three-wire synchronous transfers

■ Master or slave operation

■ Four master mode frequencies

■ Maximum slave mode frequency = fCPU/2.

■ Four programmable master bit rates

■ Programmable clock polarity and phase

■ End of transfer interrupt flag

■ Write collision flag protection

■ Master mode fault protection capability.

12.3.3 General description

The SPI is connect ed to external d evices through 4 alternate pins:

– MISO: Master In Slave Out pin – MOSI: Master Out Slave In pin – SCK: Serial Clock pin –SS

: Slave select pin

A basic example of interconnections between a single master and a single slave is illustrated on

Figure 37.

The MOSI pins are connected together as are MISO pins. In this way data is transferred serially between master and slave (most significant bit first).

When the master device transmits data t o a s lave device via MOSI pin, the slave device responds by sending data to the master device via the MISO pin. This implies full duplex transmission with both data out and data in synchronized with the same clock signal (which is prov ided by the m aster device via the SCK pin).

Thus, the byte transmitted is replaced by the byte received and eliminates the need for separate transmit-empty and recei ve r-full bits. A s tatus f lag is used to indicate that the I/O operation is complete.

Four possible data/clock timing relationship s may be chosen (s ee Figure 40) but m aster and slave must be programmed with the same timing mode.

Figure 37. Serial Peripheral Interface Master/Slave

MASTER

MSBit LS Bit MSBit L SBit 8-BIT SHIFT REGISTE R

SPI

CLOCK

GENERATO R

60/140

MISO

MOSI

SCK

+5V

MISO

MOSI

SCK

SLAVE

8-BIT SHIFT REGISTE R

ST72104G, ST72215G, ST72216G, ST72254G

SERIAL PERIPHERAL INTERFACE (Cont’d) Figure 38. Serial Peripheral Interface Block Diagram

Internal Bus

MOSI

MISO

SCK

Read

Read Buffer

8-Bit Shift Register

Write

MASTER

CONTROL

WCOL

SPIF

SPIE SPE SPR2 MSTR C PHA SPR0SPR1CPOL

MODF

- --

SPI

STATE

CONTROL

request

SERIAL CLOCK GENERATOR

61/140

ST72104G, ST72215G, ST72216G, ST 72254G

SERIAL PERIPHERAL INTERFACE (Cont’d)

12.3.4 Functional Description

Figure 37 shows the serial peripheral interface

(SPI) block diagram. This interface contains 3 dedicated registers:

– A Control Register (CR) – A Status Register (SR) – A Data Register (DR)

Refer to the CR, SR and DR registers in Section

12.3.7for the bit definitions.

In this configuration t he M OSI pin is a data output and to the MISO pin is a data input.

Transmit sequence

The transmit sequence begins when a byte is written the DR register.

The data byte is parallel loaded into the 8-bit shift register (from th e i nte rna l bus) during a write cycl e and then shifted out serially to the MOSI pin most significant bit first.

12.3.4.1 Master Configuration

In a master configuration, the serial clock is generated on the SCK pin.

Procedure

– Select the SPR0 & SPR1 bits to define the se-

rial clock baud rate (see CR register).

– Select the CPOL and CPHA bits to define one

of the four relationships between the data transfer and the serial clock (see Figure 40).

–The SS

pin must be connected to a high level signal during the complete byte tran smit sequence.

– The MSTR and SPE bits must be set (they re-

main set only if the SS

pin is connected to a

high level signal).

When data trans fer is complete:

– The SPIF bit is set by hardware – An interrupt is generated if the SPIE bit is set

and the I bit in the CCR register is cleared.

During the last clock cycle the SPIF bit is set, a copy of the data byte received in the shift register is moved to a buffer. When the DR register is read, the SPI peripheral returns this buffered value.

Clearing the SPIF bit is performed by the following software sequence:

1. An access to the SR register while the SPIF bit is set

2. A read to the DR register.

Note: While the SPIF bit is set, all writes to the DR register are inhibited until the SR register is read.

62/140

SERIAL PERIPHERAL INTERFACE (Cont’d)

12.3.4.2 Slave Configuration

In slave configuration, the serial clock is received on the SCK pin from the master device.

The value of the SPR0 & SPR1 bits is not used for the data transfer.

Procedure

– For correct data transfer, the slave device

must be in the same timing mode as the master device (CPOL and CPHA bits). See Figure

40.

–The SS

pin must be conne cted to a lo w level signal during the complete byte tran smit sequence.

– Clear the MSTR bit and set the SPE bit to as-

sign the pins to alternate function.

In this configuration the MOSI pin is a data input and the MISO pin is a data output.

Transmit Sequence

The data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serial ly t o the M ISO pi n m os t significant bit first.

The transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its MOSI pin.

ST72104G, ST72215G, ST72216G, ST72254G

When data trans fer is complete:

– The SPIF bit is set by hardware – An interrupt is generated if SPIE bit is set and

I bit in CCR register is cleared.

Clearing the SPIF bit is performed by the following software sequence:

1. An access to the SR register while the SPIF bit is set.

2.A read to the DR register.

Notes: While the SPIF bit is set, all writes to the DR register are inhibited until the SR register is read.

The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an overrun condition (see Section 12.3.4.6).

Depending on the CPHA bi t, the S S set to write to the DR regi ster between ea ch data byte transfer to avoid a write collision (see Section

12.3.4.4).

pin has to be

63/140

ST72104G, ST72215G, ST72216G, ST 72254G

SERIAL PERIPHERAL INTERFACE (Cont’d)

12.3.4.3 Data Transfer Format

During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). The serial clock is used to synchronize the data transfer during a sequence of eight clock pulses.

The SS device; the other slave devices that are not selected do not interfere with the SPI transfer.

Clock Phase and Clock Polarity

Four possible timing relationships may be chose n by software, using the CPOL and CPHA bits.

The CPOL (clock polarity) bit cont rols the steady state value of the clock when no data is being transferred. This bit affects both m as ter and sl av e modes.

The combination between the CPOL and CPHA (clock phase) bits selects the data capture clock edge.

Figure 40, shows an SPI transfer with the four

combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the MISO pin, the MOSI pin are directly connected between th e master and the slave device.

The SS be driven by the master device.

pin allows individual selection of a slave

pin is the slave device select input and can

The master device applies data to its MOSI pinclock edge before the capture clock edge.

CPHA bit is set

The second edge on the SCK pin (falling edg e if the CPOL bit is reset, rising edge if the CPOL bit is set) is the MSBit capture strobe. Data is latched on the occurrence of the second clock transition.

No write collision should occur even if the SS

pin stays low during a transfer of s everal bytes (see

Figure 39).

CPHA bit is reset

The first edge on the SCK pin (falling edge if CPOL bit is set, rising ed ge if CPOL bit is reset ) is the MSBit capture strobe. Data is latched on the oc currence of the first clock transition.

The SS

pin must be toggled high and low between

each byte transmitted (see Figure 39). To protect the transmission from a write collision a

low value on the SS

pin of a slave device freezes the data in its DR register and does not allow it to be altered. Therefore the SS

pin must be high to write a new data byte in the DR without producing a write coll is ion .

Figure 39. CPHA / SS

MOSI/MISO

Master

Slave SS

(CPHA=0)

Slave

(CPHA=1)

64/140

Timing Dia gram

Byte 1 Byte 2

Byte 3

VR02131A

SERIAL PERIPHERAL INTERFACE (Cont’d) Figure 40. D at a C lo ck Ti m in g D i agram

SCLK ( w ith

CPOL = 1)

SCLK ( w ith CPOL = 0)

ST72104G, ST72215G, ST72216G, ST72254G

CPHA =1

MISO

(from master)

MOSI

(from slave)

(to slave)

CAPTURE STROBE

CPOL = 1

CPOL = 0

MISO

(from master)

MSBit Bit 6 Bit 5

Bit 4 Bit3 Bit 2 Bit 1 LSBit

CPHA =0

Bit 4 Bit3 Bit 2 Bit 1 LSBit

MOSI

(from slave)

(to slave)

CAPTURE STROBE

Note: This figure should not be used as a replacement for parametric information. Refer to the Electrical Characteristics chapter.

MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit

VR02131B

65/140

ST72104G, ST72215G, ST72216G, ST 72254G

SERIAL PERIPHERAL INTERFACE (Cont’d)

12.3.4.4 Write Collision Error

A write collision occurs when the software tries to write to the DR register while a data transfer is taking place with an external dev ice. When t his happens, the transfer continues uninterrupted; and the software w rit e w ill be uns u c c es s ful.

Write collisions can occur both in master and slave mode.

Note: a "read collision" will never occur since the received data byte is placed in a buffer in which access is always synchronous with the MCU operation.

In Slave mode

When the CPHA bit is set: The slav e device will re ceive a clock (S CK) ed ge

prior to the latch of the first data transfer. This first clock edge will freeze t he d ata in the slave device DR register and output the MSBit on to the external MISO pin of the slave device.

The SS the output of the MSBit onto the MISO pin does not take place until the first data transfer clock edge.

pin low state enables the slave device but

When the CPHA bit is reset: Data is latched on the occurrence of the first clock

transition. The slave device does not have any way of knowing when that transition will occur; therefore, the slave device collision occurs when software attempts to write the DR register after its

pin has been pulled low.

SS For this reason, the SS

pin must be high, between each data byte transfer, to allow the CPU to write in the DR register without generating a write collision.

In Master mode

Collision in the master device is defined as a write of the DR register while the internal serial clock (SCK) is in the process of transfer.

The SS

pin signal must be always high on the

master device.

WCOL bit

The WCOL bit in the SR register is set if a write collision occurs.

No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only).

Clearing the WCOL bit is done through a software sequence (see Figure 41).

Figure 41. Clearing the WCOL bit (Write Collision Flag) Software Sequence

Clearing sequence after SPIF = 1 (end of a data byte transfer)

1st Step

2nd Step

Read SR

THEN

Read DR Write DR

SPIF =0 WCOL=0

Read SR

THEN

SPIF =0 WCOL=0 WCOL=1 if a transfer has started

before the 2nd step

Clearing sequence before SPIF = 1 (during a data byte transfer)

1st Step

2nd Step

Read SR

Read DR

THEN

WCOL=0

Note: Writing in DR register instead of reading in it do not reset WCOL bit

66/140

if no transfer has started

SERIAL PERIPHERAL INTERFACE (Cont’d)

12.3.4.5 Master Mode Fault

Master mode fault occurs when the master device has its SS

pin pulled low, then the MODF bit is set.

Master mode fault affects the SPI peripheral in the following ways:

– The MODF bit is set and an SPI interrupt is

generated if the SPIE bit is set.

– The SPE bit is reset. This blocks all output

from the device and disables the SPI peripheral.

– The MSTR bit is reset, thus forcing the device

into slave mode.

ST72104G, ST72215G, ST72216G, ST72254G

may be restored to their original state during or after this clearing sequence.

Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set except in the MODF bit clearing sequence.

In a slave device the MODF bit can not be set, but in a multi master configuration the device can be in slave mode with this MODF bit set.

The MODF bit indicates that there might have been a multi-master conflict for system control and allows a proper exit from system operation to a reset or default system state using an interrupt routine.

Clearing the MODF bit is done through a software sequence:

1. A read or write access to the SR register while the MODF bit is set.

2. A write to the CR register.

Notes: To avoid any multiple slave conflicts in the case of a system comprising several MCUs, the SS

pin must be pulled high during the clearing se-

quence of the MODF bit. The SPE and MSTR bits

12.3.4.6 Overrun Condition

An overrun condition occurs w hen the mas ter device has sent several data bytes and the slave device has not cleared the S PIF bit issuing from the previous data byte transmitted.

In this case, the rec eiver buffer contains the b yte sent after the SPIF bit was last cleared. A read to the DR register returns this byte. All other bytes are lost.

This condition is not detected by the SPI peripheral.

67/140

ST72104G, ST72215G, ST72216G, ST 72254G

SERIAL PERIPHERAL INTERFACE (Cont’d)

12.3.4.7 Single Master and Multimaster Configurations

There are two types of SPI systems: – Single Master Syste m – Multimaster System

Single Master System

A typical single master system may be configured, using an MCU as the master and four MCUs as slaves (see Figure 42).

The master device selects the individual slave devices by using four pins of a parallel port to control the four SS

The SS

pins of the slave devices.

pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices.

Note: T o prevent a b us conflict on the MISO line the master allows only one active slave device during a transmission.

For more security, the slave device may respond to the master with the received data byte. Then the master will receive the previous byte back from the slave device if all MISO and MOSI pins are connected and the slave has not written its DR register.

Other transmission security methods can use ports for handshake lines or data by tes with command fields.

Multi-master System

A multi-master system may al so be configured by the user. Transfer of master control could be implemented using a handshake method through the I/O ports or by an exchange of code messages through the serial peripheral interface system.

The multi-master system is principally handled by the MSTR bit in the CR register and the MODF bit in the SR register.

Fig u re 42. Singl e Master Confi guration

SCK

Slave MCU

MOSI

MISO

MOSI MOSI MOSIM ISO MISO MISOMISO

SCK

Master

MCU

Ports

Slave MCU

SCK SCK

Slave

MCU

Slave

MCU

68/140

ST72104G, ST72215G, ST72216G, ST72254G

SERIAL PERIPHERAL INTERFACE (Cont’d)

12.3.5 Low Power Modes

Mode Description

WAIT

HALT

12.3.6 Interrupts

No effect on SPI. SPI interrupt events cause the device to exit from WAIT mode.

SPI registers are frozen. In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with

“exit from HALT mode” capability.

Interrupt Event

SPI End of Transfer Event SPIF Master Mode Fault Event MODF Yes No

Event

Flag

Enable

Control

Bit

SPIE

Exit from Wait

Yes No

Note: The SPI interrupt even ts are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt ma sk in the CC register is reset (RIM instruction).

Exit

from

Halt

69/140

ST72104G, ST72215G, ST72216G, ST 72254G

SERIAL PERIPHERAL INTERFACE (Cont’d)

12.3.7 Register Description CONTROL REGISTER (CR)

Read/Write Reset Value: 0000xxxx (0xh)

SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0

Bit 7 = SPIE

Serial peripheral interrupt enable.

This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SPI interrupt is generated whenever SPIF=1

or MODF=1 in the SR register

Bit 6 = SPE

Serial peripheral output enable.

This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS

=0 (see Section 12.3.4.5 "Master Mode Fault" on

page 70).

0: I/O port connected to pins 1: SPI alternate functions connected to pins

The SPE bit is cleared by reset, so the SPI peripheral is not initially connected to the external pins.

Bit 3 = CPOL

Clock polarity.

This bit is set and cleared by software. This bit determines the steady state of the serial Clock. The CPOL bit affects both the master and slave modes. 0: The steady state is a low value at the SCK pin. 1: The steady state is a high value at the SCK pin.

Bit 2 = CPHA

Clock phase.

This bit is set and cleared by software. 0: The first clock transition is the first data capture

edge.

1: The second clock transition is the first capture

edge.

Bit 1:0 = SPR[1:0]

Serial peripheral rate.

These bits are set and c leared by software.Used with the SPR2 bit, they select one of six baud rates to be used as the serial clock when the device is a master.

These 2 bits have no effect in slave mode.

Table 15. Serial P eri pheral Baud Rate

Bit 5 = SPR2

Divider Enable

this bit is set and cleared by software and it is cleared by reset. It is used with the SPR[1:0] bits to set the baud rate. Refer to Table 15. 0: Divider by 2 enabled 1: Divider by 2 disabled

Bit 4 = MSTR

Master.

This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS

=0 (see Section 12.3.4.5 "Master Mode Fault" on

page 70).

0: Slave mode is selected 1: Master mode is selected, the function of the

SCK pin changes from an input to an output and the functions of the MISO and MOSI pins are reversed.

Serial Clock SPR2 SPR1 SPR0

/4 1 0 0

CPU

/8 0 0 0

CPU

/16 0 0 1

CPU

/32 1 1 0

CPU

/64 0 1 0

CPU

/128 0 1 1

CPU

70/140

SERIAL PERIPHERAL INTERFACE (Cont’d) STATUS REGISTER (SR)

Read Only Reset Value: 0000 0000 (00h)

ST72104G, ST72215G, ST72216G, ST72254G

DATA I/O REGISTER (DR)

Read/Write Reset Value: Undefined

SPIFWCOL-MODF----

Bit 7 = SPIF

Serial Peripheral data transfer flag.

This bit is set by hardware when a transfer has been completed. An interrupt is generated if SPIE=1 in the CR register. It is cleared by a software sequence (an access to the SR register followed by a read or write to the DR register). 0: Data transfer is in progress or has been ap-

proved by a clearing sequence.

1: Data transfer between the device and an exter-

nal device has been completed.

Note: While the SPIF bit is set, all writes to the DR register are inhibited.

Bit 6 = WCOL

Write Collision status.

This bit is set by hardware when a write to the DR

D7 D6 D5 D4 D3 D2 D1 D0

The DR register is used to transmit and receive data on the serial bus. In the master device only a write to this register will initiate transmission/reception of another byte.

Notes: During the last clock cycle t he SPIF bit is set, a copy of the received data byte in the shift register is moved to a buffer. When the user reads the serial peripheral data I/O register, the buffer is actually being read.

Warning:

A write to the DR regis ter places da ta directly into the shift reg ister for transmission.

A write to the the DR register returns the valu e located in the buffer and not the contents of the shift

register (See Figure 38 ). register is done during a transmit sequence. It is cleared by a software sequence (see Fi gure 41). 0: No write collision occurred 1: A write collision has been detected

Bit 5 = Unused.

Bit 4 = MODF

Mode Fault flag.

This bit is set by hardware when the SS pin is pulled low in master mode (see Section 12. 3.4.5

"Master Mode Fault" on page 70). An SPI i nterrupt

can be generated if SPIE=1 in the CR register. This bit is cleared by a software sequence (An access to the SR register while MODF=1 followed by a write to the CR register). 0: No master mode fault detected 1: A fault in master mode has been detected

Bits 3-0 = Unused.

71/140

ST72104G, ST72215G, ST72216G, ST 72254G

SERIAL PERIPHERAL INTERFACE (Cont’d) Table 16. SPI Register Map and Reset Values

Address

(Hex.)

0021h

0022h

0023h

Label

SPIDR

Reset Value

SPICR

Reset Value

SPISR

Reset Value

76543210

MSB

xxxxxxx

SPIE

SPIF

SPE

WCOL

SPR20MSTR0CPOL

CPHA

MODF

00000

SPR1

LSB

SPR0

72/140

12.4 I2C BUS INTERFACE (I2C)

ST72104G, ST72215G, ST72216G, ST72254G

12.4.1 Introduction

The I

C Bus Interface serves as an interface between the microcontroller and the serial I provides both multimaster and slave functions, and controls all I

C bus-specific sequencing, pro-

tocol, arbitration and timing. It supports fast I

C bus. It

mode (400 kHz).

12.4.2 Main Features

■ Parallel-bus/I

■ Multi-master capability

■ 7-bit/10-bit Addressing

■ Transmitter/Receiver flag

■ End-of-byte transmission flag

■ Transfer problem detection

C Master Features:

■ Clock generation

■ I

C bus busy flag

■ Arbitration Lost Flag

■ End of byte transmission flag

■ Transmitter/Receiver Flag

■ Start bit detection flag

■ Start and Stop generation

C Slave Features:

■ Stop bit detection

■ I

C bus busy flag

■ Detection of misplaced start or stop condition

■ Programmable I

■ Transfer problem detection

■ End-of-byte transmission flag

■ Transmitter/Receiver flag

C protocol converter

C Address detection

12.4.3 General Description

In addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa, using either an interrupt or polled

Figure 43. I

C BUS Protocol

handshake. The interrupts are enabled or disabled by software. The int erfac e is c onnect ed t o the I bus by a data pin (SDAI) and by a clock pin (SCLI). It can be connected both with a standard I and a Fast I ware.

C bus. This selection is made by soft-

Mode Selection

The interface can operate in the four following modes:

– Slave transmitter/receiver – Master transmitter/receiver By default, it operates in slave mode. The interface automatically switches from slave to

master after it generates a START condition and from master to slave in case of arbitration loss or a STOP generation, allowing then Multi-Master capability.

Communicati on Flow

In Master mode, it initiates a data transfer and generates the clock signal. A serial data tran sfer always begins with a start condition and ends with a stop condition. Both start and stop conditions are generated in master mode by software.

In Slave mode, the interface is capable of recognising its own address (7 or 10-bit), an d the General Call address. The General Call address detection may be enabled or disabled by software.

Data and addresses are transferred as 8-bit bytes, MSB first. The f irst by te(s) following the start condition contain the address (one in 7-bit mode, two in 10-bit mode). The address is always transmitted in Master mode.

A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. Refer to Fig -

ure 43.

C bus

SDA

SCL

CONDITION

START

MSB

ACK

12 89

STOP

CONDITION

VR02119B

73/140

ST72104G, ST72215G, ST72216G, ST 72254G

I2C BUS INTERFACE (Cont’d)

Acknowledge may be enabled and disabled by software.

C interface address and/or general call ad-

The I dress can be selected by software.

The speed of the I between Standard (0-100KHz) and Fast I 400KHz).

SDA/SCL Line Control

Transmitter mode: the interface holds the clock line low before transmission to wait for the microcontroller to write the byte in the Data Register.

Receiver mode: the interface holds the clock line low after reception to wait for the microcontroller to read the byte in the Data Register.

Figure 44. I

C Interface Block Diagram

C interface may be selected

C (100-

The SCL frequency (F grammable clock divider which depends on the

C bus mode.

When the I

C cell is enabled, the SDA a nd SCL

) is controlled by a pro-

scl

ports must be configured as floating inputs. In this case, the value of the external pull-up resistor used depends on the application.

When the I

C cell is disabled, the S DA and SCL

ports revert to being standard I /O port pins.

DATA REG ISTER (DR)

SDA or SDAI

SCL or SCLI

DATA CON TROL

CLOCK CONTROL

CLOCK CONTROL REGISTER (CCR)

CONTRO L REGIST E R (C R)

STATUS REGISTER 1 (SR1)

STATUS REGISTER 2 (SR2)

DATA SHIFT REGISTER

COMPARATOR

OWN ADDRESS REGISTER 1 (OAR1)

OWN ADDRESS REGISTER 2 (OAR2)

CONTROL LOGIC

74/140

INTERRUPT

I2C BUS INTERFACE (Cont’d)

12.4.4 Functional Description

Refer to the CR, SR1 and SR2 registers in Section

12.4.7. for the bit definitions.

By default the I

C interface operates in Slave mode (M/SL bit is cleared) except when it initiates a transmit or receive sequence.

First the interface frequency must be configured using the FRi bits in the OAR2 register.

12.4.4.1 Slave Mode

As soon as a start condition is detected, the address is received from the S DA line and s ent to the shift register; then it is compared with the address of the interface or the General Call address (if selected by software).

Note: In 10-bit addressing mode, the com parisio n includes the header sequence (11110xx0) and the two most significant bits of the address.

Header matched (10-bit mode only): the interface generates an acknowled ge pulse if t he ACK bi t is set.

Address not matched: the interface ignores it and waits for another Start condition.

Address matched: the interface generates in sequence:

– Ack nowle dge pulse if the ACK bit is set. – EVF and ADSL bits are set with an in terrupt if the

ITE bit is set.

Then the interface waits for a read of the SR1 register, holding the SCL line low (see Figure 45 Transfer sequencing EV1). Next, in 7-bit mode read the DR register to determine from the least significant bit (Data Direction Bit) if the slave must enter Receiver or Transmitter mode.

In 10-bit mode, after receiving the address sequence the slave is always in receive mode. It will enter transmit mode on receiving a repeat ed S tart condition followed by the header sequence with matching address bits an d the least sig nificant bit set (11110xx1) .

Slave Receiver

Following the address reception and after SR1 register has been read, the slave receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence:

– Ack nowle dge pulse if the ACK bit is set

ST72104G, ST72215G, ST72216G, ST72254G

– EVF and BTF bits are set with an interrupt if the

ITE bit is set.

Then the interface waits for a read of the SR1 register followed by a read of the DR register, holding the SCL line low (see Figure 45 Transfer se- quencing EV2).

Slave Transmitter

Following the address reception and after SR1 register has been read, the slave sends bytes from the DR register to the SDA line via the internal shift register.

The slave waits for a read of the SR1 register followed by a write in the DR register, holding th e SCL line low (see Figure 45 Transfer sequencing EV3).

When the acknowledge pulse is received: – The EVF and BTF bits are set by hardware with

an interrupt if the ITE bit is set.

Closing slave communication

After the last data byte is trans ferred a Sto p Condition is generated by the master. The interface detects this condition and sets:

– EVF and STOPF bits with an interrupt if the ITE

bit is set.

Then the interface waits for a read of the SR2 register (see Figure 45 Transfer sequencing EV4).

Error Cases

– BERR: Detection of a Stop or a Start condition

during a byte transfer. In this case, the EVF and the BERR bits are set with an interrupt if the ITE bit is set. If it is a Stop then the interface discards the data, released the lines and waits for another Start condition. If it is a Start then the interface discards the data and waits for the next slave address on the bus.

– AF: Detection of a non-acknowledge bit. In this

case, the EVF and AF bits are set with an interrupt if the ITE bit is set.

Note: In both c ases, SCL line is not hel d l ow; however, SDA line can remain low due to possible «0» bits transmitted last. It is then necessary to release both lines by software.

75/140

ST72104G, ST72215G, ST72216G, ST 72254G

I2C BUS INTERFACE (Cont’d) How to release the SDA / SCL lines

Set and subsequently clear the STOP bit while BTF is set. The SDA/SC L lines are released a fter the transfer of the current byte.

12.4.4.2 Master Mode

To switch from default Slave mode to Master mode a Start condition generation is needed.

After completion of this transfer (and acknowledge from the slave if the ACK bit is set):

– The EVF bit is set by hardware with interrupt

generation if the ITE bit is set.

Then the master waits for a read of the SR1 register followed by a write in the CR register (for example set PE bit), hold ing the SCL li ne low (see Fig-

ure 45 Transfer sequencing EV6).

Start condition

Setting the START bit while the BUSY bit is cleared causes the interface to switch to Master mode (M/SL bit set) and generates a Start condition.

Once the Start condition is sent: – The EVF and SB bits are set by hardware with

an interrupt if the ITE bit is set.

Then the master waits for a read of the SR1 register followed by a write in the DR register with the Slave address, holding the SCL line low (see

Figure 45 Transfer sequencing EV5).

Slave address transmission

Then the slave address is sent to the SDA line via the internal shift register.

In 7-bit addressing mode, one address byte is sent.

In 10-bit addressing mode, sending the first byt e including the header sequence causes the following event: – The EVF bit is set by hardware with interrupt

generation if the ITE bit is set. Then the master waits for a read of the SR1 register followed by a write in the DR register, h olding the SCL line low (see Figure 45 Transfer se- quencing EV9). Then the second address byte is sent by the interface.

Next the master must enter Receiver or Transmitter mode.

Note: In 10-bit addressing mode, to switch the master to Receiver mode, software must generate a repeated Start condition and resend the h eader sequence with the least significant bit set (11110xx1).

Master Receiver Following the address transmission and after SR1

and CR registers have been accessed, the master receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence:

– Acknowledge pulse if if the ACK bit is set – EVF and BTF bits are set by hardware with an in-

terrupt if the ITE bit is set.

Then the interface waits for a read of the SR1 register followed by a read of the DR register, holding the SCL line low (see Figure 45 Transfer se- quencing EV7).

To close the communication: before reading the last byte from the DR register, set the STOP bit to generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit cleared).

Note: In order to generate the non-acknowledge pulse after the last received data byte, the ACK bit must be cleared just before reading the second last data byte.

76/140

I2C BUS INTERFACE (Cont’d) Master Transmitter

Following the address transmission and after SR1 register has been read, the master sends bytes from the DR register to the SDA line via the internal shift register.

The master waits for a read of the SR1 register followed by a write in the DR register, holding the SCL li n e low (see Figure 45 T ransfer sequencin g EV8).

When the acknowledge bit is received, the interface sets:

– EV F and BTF bits with an interrupt if the ITE bit

is set. To close the communication: after writing the last

byte to the DR register, set the STOP bit to generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit cleared).

Error Cases

– BERR: Detection of a Stop or a Start condition

during a byte transfer. In this case, the EVF and

ST72104G, ST72215G, ST72216G, ST72254G

BERR bits are set by hardware with an interrupt if ITE is set.

– AF: Detection of a non-acknowledge bit. In this

case, the EVF and AF bits are set by hardware with a n in terrup t i f th e ITE bit i s se t. To res u me, set the START or STOP bit.

– ARLO: Detection of an arbitration lost condition.

In this case the ARLO bit is set by hardware (with an interrupt if the ITE bit is set and the interface goes automatically back to slave mode (the M/SL bit is cleared).

Note: In all these cases, the SCL line is not held low; however, the SDA line can remain low due to possible «0» bits transmitted last. It is then necessary to release both lines by software.

77/140

ST72104G, ST72215G, ST72216G, ST 72254G

I2C BUS INTERFACE (Cont’d) Figure 45. Transfer Sequencing

7-bit Slave receiver:

S A ddress A Data1 A Data2 A

EV1 EV 2 EV2 EV2 EV4

7-bit Slave transmitter:

S A ddress A Data1 A Data2 A

EV1 EV3 EV3 EV3 EV3-1 EV4

7-bit Master receiver:

S Ad dress A Data1 A Data2 A

EV5 EV6 EV7 EV7 EV7

7-bit Master transmitter:

S Ad dress A Data1 A Data2 A

EV5 EV6 EV8 EV8 E V8 EV8

10-bit Slave receiver:

S H eader A Address A Data1 A

EV1 EV2 EV2 EV4

.....

DataN A P

.....

DataN NA P

.....

DataN NA P

.....

DataN A P

.....

DataN A P

10-bit Slave transmitter:

Header A Data1 A

EV1 EV3 E V3 EV3-1 EV4

DataN A P

....

10-bit Master transmitter

S Header A Address A Data1 A

EV5 EV9 EV6 EV8 E V8 EV8

DataN A P

.....

10-bit Master receiver:

Legend: S=Start, S

= Repeated Start, P=Stop, A=Acknowledge, NA=Non-acknowle dge,

Header A D ata1 A

EV5 EV6 EV7 EV7

DataN A P

.....

EVx=Event (with interrupt if ITE=1)

EV1: EVF=1, ADSL=1, cleared by reading SR1 register. EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register. EV3: EVF =1, BTF=1, cleared by reading SR1 register followed by writing DR register. EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading SR1 register. BTF is cleared by releasing the

lines (STOP=1, STOP=0) or by writing DR register (DR=FFh). Note: If lines are released by STOP=1, STOP=0, the subsequ ent EV4 is not seen.

EV4: EVF=1, STOPF=1, cleared by reading SR2 register. EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register. EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1). EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register. EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register. EV9: EVF=1, ADD10=1, cleared by reading SR1 register followed by writing DR register.

78/140

ST72104G, ST72215G, ST72216G, ST72254G

I2C BUS INTERFACE (Cont’d)

12.4.5 Low Power Modes

Mode Description

WAIT

HALT

No effect on I

C interrupts cause the device to exit from WAIT mode.

C registers are frozen.

I In HALT mode, the I

resumes operation when the MCU is woken up by an interrupt with “exit from HALT mode” capability.

12.4.6 Interrupts Figure 46. Event Flags and Interrupt Generation

C interface.

C interface is inactive and does not acknowledge data on the bus. The I2C interface

ADD10

BTF

ADSL

STOPF

ARLO BERR

ITE

INTERRUPT

EVF

EVF can also be set by EV6 or an error from the SR 2 register.

Interrupt Event

10-bit Address Sent Event (Master mode) ADD10 End of Byte Transfer Event BTF Yes No Address Matched Event (Slave mode) ADSEL Yes No Start Bit Generation Event (Master mode) SB Yes No Acknowledge Failure Event AF Yes No Stop Detection Event (Slave mode) STOPF Yes No Arbitration Lost Event (Multimaster configuration) ARLO Yes No Bus Error Event BERR Yes No

Note: The I

C interrupt events are connected to

Event

Flag

Enable

Control

Bit

ITE

Exit from Wait

Yes No

the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the I-bit in the CC register is reset (RIM instruction).

Exit

from

Halt

79/140

ST72104G, ST72215G, ST72216G, ST 72254G

I2C BUS INTERFACE (Cont’d)

12.4.7 Register Description

C CONTROL REGISTER (CR)

Read / Write Reset Value: 0000 0000 (00h)

Bit 2 = ACK This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0). 0: No acknowledge returned 1: Acknowledge returned after an address byte or

0 0 PE ENGC START ACK STOP ITE

a data byte is received

Acknowledge enable.

Bit 7:6 = Reserved. Forced to 0 by hardware. Bit 5 = PE

Peripheral enable.

This bit is set and cleared by software. 0: Peripheral disabled 1: Master/Slave capability Notes: – W hen PE= 0, all the bits of the CR register and

the SR register except the Stop bit are reset. All outputs are released while PE=0

– W hen PE= 1, the correspond ing I/O pins are se-

lected by hardware as alternate functions.

– To enable the I

C interface, write the CR register TWICE with PE=1 as the first write only activates the interface (only PE is set).

Bit 4 = ENGC

Enable General Call.

This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0). The 00h General Call address is acknowledged (01h ignored). 0: General Call disabled 1: General Call enabled

Bit 3 = START

Generation of a Start condition

This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0) or when the Start condition is sent (with interrupt generation if ITE=1).

– In master mode :

0: No start generation 1: Repeated start generation

– In slave mode :

0: No start generation 1: Start generation when the bus is free

Bit 1 = STOP

Generation of a Stop condition

This bit is set and cleared by software. It is also cleared by hardware in master mode. Note: This bit is not cleared when the interface is disabled (PE=0).

– In master mode:

0: No stop generation 1: Stop generation after the current byte transfer or after the current Start condition is sent. The STOP bit is cleared by hardware when the Stop condition is sent.

– In slave mode:

0: No stop generation 1: Release the SCL and SDA lines after the current byte transfer (BTF=1). In this mode the STOP bit has to be cleared by software.

Bit 0 = ITE

Interrupt enable.

This bit is set and cleared by software and cleared by hardware when the interface is disabled (PE=0). 0: Interrupts disabled 1: Interrupts enabled Refer to Figure 46 for the relationship between the events and the interrupt.

SCL is held low when the ADD10, SB, BTF or ADSL flags or an EV6 event (See Figure 45) is de- tected.

80/140

ST72104G, ST72215G, ST72216G, ST72254G

I2C BUS INTERFACE (Cont’d)

C STATUS REGISTER 1 (SR1)

Read Only Reset Value: 0000 0000 (00h)

EVF ADD10 TRA BUSY BTF ADSL M/SL SB

Bit 7 = EVF

Event flag.

This bit is set by hardware as soon as an event occurs. It is cleared by software reading SR2 register in case of error event or as described in Figure 45. It is also cleared by hardware when the interface is disabled (PE=0). 0: No event 1: One of the following events has occurred:

– BTF=1 (Byte received or transmitted) – ADSL=1 (Address matched in Slave mode

while ACK=1 )

– SB=1 (Start condition generated in Master

mode)

– AF=1 (No acknowledge received after byte

transmission)

– STOPF=1 (Stop condition detected in Slave

mode) – ARLO=1 (Arbitration lost in Master mode) – BERR=1 (Bus error, misplaced Start or Stop

condition detected) – ADD10=1 (Master has sent header byte) – Address byte successfully transmitted in Mas-

ter mode.

arbitration (ARLO=1) or when the interface is disabled (PE=0). 0: Data byte received (if BTF=1) 1: Data byte transmitted

Bit 4 = BUSY

Bus busy

. This bit is set by ha rdware on detection of a Start condition and cleared by hardware on detection of a Stop condition. It indicates a communication in progress on the bus. This information is still updated when the interface is disabled (PE=0). 0: No communication on the bus 1: Communication ongoing on the bus

Bit 3 = BTF

Byte transfer finished.

This bit is set by hardware as soon as a byte is correctly received or transmitted with interrupt generation if ITE=1. It is cleared by software reading SR1 register followed by a read or write of DR register. It is also cleared by hardware when the interface is disabled (PE=0).

– Following a byte transmission, this bit is set after

reception of the acknowledge clock pulse. In case an address byte is sent, this bit is set only after the EV6 event (See Figure 45). BTF is cleared by reading SR1 register followed by writing the next byte in DR register.

– Following a byte reception, this bit is set after

transmission of the acknowledge clock pulse if ACK=1. BTF is cleared by reading SR1 register

followed by reading the byte from DR register. The SCL line is held low while BTF=1. 0: Byte transfer not done

1: Byte transfer succeeded

Bit 6 = A DD10

10-bit addressing in Master mode

This bit is set by hardware when the master has sent the first byte in 10-bit address mode. It is cleared by software reading SR2 register followed by a write in the DR register of the second address byte. It is also cleared by hardware when t he peripheral is disabled (PE=0).

0: No ADD10 event occurred. 1: Master has sent first address byte (header)

Bit 5 = TRA

Transmitter/Receiver.

When BTF is set, TRA=1 if a dat a byte has been transmitted. It is cleared automatically when BTF is cleared. It is also cleared by hardware after detection of Stop condition (STOPF=1), loss of bus

Bit 2 = ADSL

Address matched (Slave mode).

This bit is set by hardware as soon as the received slave address matched with the OAR register content or a general call is recognized. A n in terrupt is generated if ITE=1. It is c leared by sof tware reading SR1 register or by hardware when t he interface is disabled (PE=0).

The SCL line is held low while ADSL=1. 0: Address mismatched or not received

1: Received address matched

81/140

ST72104G, ST72215G, ST72216G, ST 72254G

I2C BUS INTERFACE (Cont’d)

Bit 1 = M/SL This bit is set by hardware as soon as the interface is in Master mode (writing START=1). It is cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration (ARLO=1). It is also cleared when the interface is disabled (PE=0). 0: Slave mode 1: Master mode

Bit 0 = SB This bit is set by hardware as soon as the Start condition is generated (following a write START=1). An interrupt is generated if ITE=1. It is cleared by software reading SR1 register followed by writing the address byte in DR register. It is also cleared by hardware when the interface is disabled (PE=0). 0: No Start condition 1: Start condition generated

C STATUS REGISTER 2 (SR2)

Read Only Reset Value: 0000 0000 (00h)

Master/S la ve .

Start bit (Master mode).

Bit 2 = ARLO

Arbitration lost

. This bit is set by hardware when t he in terface loses the arbitration of the bus to another master. An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0).

After an ARLO event the interface switches back automatically to Slave mode (M/SL=0).

The SCL line is not held low while ARLO=1. 0: No arbitration lost detected

1: Arbitration lost detected

Bit 1 = BERR

Bus error.

This bit is set by hardware when the interface detects a misplaced Start or Stop condition. An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0).

The SCL line is not held low while BERR=1. 0: No misplaced Start or Stop condition

1: Misplaced Start or Stop condition

0 0 0 AF STOPF ARLO BERR GCAL

Bit 0 = GCAL This bit is set by hardware when a general call ad-

General Call (Slave mode).

dress is detected on the bu s while ENGC= 1. It is cleared by hardware detecting a Stop condition (STOPF=1) or when the interface is disabled

Bit 7:5 = Reserved. Forced to 0 by hardware.

(PE=0). 0: No general call address detected on bus

Bit 4 = AF

Acknowledge failure

1: general call address detected on bus

This bit is set by hardware when no acknowledg e is returned. An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0).

The SCL line is not held low while AF=1. 0: No acknowledge failure

1: Acknowledge failure

Bit 3 = STOPF

Stop detection (Slave mode).

This bit is set by hardware when a St op condition is detected on the bus after an acknowledge (if ACK=1). An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0).

The SCL line is not held low while STOPF=1. 0: No Stop condition detected

1: Stop condition detected

82/140

ST72104G, ST72215G, ST72216G, ST72254G

I2C BUS INTERFACE (Cont’d)

C CLOCK CONTROL REGISTER (CCR)

C DATA REGISTER (DR)

Read / Write Reset Value: 0000 0000 (00h)

FM/SM CC6 CC5 CC4 CC3 CC2 CC1 CC0

Bit 7 = FM/SM

Fast/Standard I2C mode.

This bit is set and cleared by software. It is not cleared when the interface is disabled (PE=0). 0: Standard I 1: Fast I

Bit 6:0 = CC6-CC0 These bits select the s peed of t he bus (F pending on the I

C mode

7-bit clock divider.

C mode. They are not cleared

SCL

) de-

when the interface is disabled (PE=0). – St andard m ode (FM /SM=0): F

= F

SCL

– Fas t mode (FM /SM =1): F

= F

SCL

Note: The programmed F

/(2x([CC6..CC0]+2))

CPU

SCL

/(3x([CC6..CC0]+2))

CPU

assumes no load on

SCL

<= 100kHz

SCL

> 100kHz

SCL and SDA lines.

Read / Write Reset Value: 0000 0000 (00h)

D7 D6 D5 D4 D3 D2 D1 D0

Bit 7:0 = D7-D0

8-bit Data Register.

These bits contain the byte to be received or transmitted on the bus.

– Transmitter mode: Byte transmission start auto-

matically when the software writes in the DR register.

– Receiver mode: the first data byte is received au-

tomatically in the DR register using the least significant bit of the address. Then, the following data bytes are received one by one after reading the DR register.

83/140

ST72104G, ST72215G, ST72216G, ST 72254G

I2C BUS INTERFACE (Cont’d)

C OWN ADDRESS REGISTER (OAR1)

Read / Write Reset Value: 0000 0000 (00h)

C OWN ADDRESS REGISTER (OAR2)

Read / Write Reset Value: 0100 0000 (40h)

ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0

7-bit Addressing Mode

Bit 7:1 = ADD7-ADD1 These bits define the I

Interface address

C bus address of the inter-

face. They are not cleared when the interface is disabled (PE=0).

Bit 0 = A DD0

Address direction bit.

This bit is don’t care, the interface acknowledges either 0 or 1. It is not cleared when the interface is disabled (PE=0).

FR1 FR0 0 0 0 ADD9 ADD8 0

Bit 7:6 = FR1-FR0

Frequency bits.

These bits are set by software only when the interface is disabled (PE=0). To configure the interface

C specifed delays select the value corre-

to I sponding to the microcontroller frequency F

Range (MHz) FR1 FR0

CPU

2.5 - 6 0 0 6 -10 0 1

10 - 14 1 0 14 - 24 1 1

Note: Address 01h is always ignored.

10-bit Addressing Mode Bit 7:0 = ADD7-ADD0

Interface address

These are the least significan t bits of the I

C bus address of the interface. They are not cleared when the interface is disabled (PE=0).

Bit 5:3 = Reserved

Bit 2:1 = ADD9-ADD8

Interface address

These are the most significant bits of the I address of the i nterface (10-bit mode only). They are not cleared when the interface is disabled (PE=0).

CPU

C bus

84/140

Bit 0 = Reserved.

I²C BUS INTERFACE (Cont’d)

Table 17. I

C Register Map and Reset Values

ST72104G, ST72215G, ST72216G, ST72254G

Address

(Hex.)

0028h

0029h

002Ah

02Bh

02Ch

002Dh

002Eh

Label

I2CCR

Reset Value 0 0

I2CSR1

Reset Value

I2CSR2

Reset Value 0 0 0

I2CCCR

Reset Value

I2COAR1

Reset Value

I2COAR2

Reset Value

I2CDR

Reset Value

76543210

EVF

FM/SM

ADD7

FR1

MSB

0000000

ADD10

CC6

ADD6

FR0

1000

TRA

CC5

ADD5

ENGC0START

BUSY

CC4

ADD4

BTF

STOPF0ARLO

CC3

ADD3

ACK

ADSL

CC2

ADD2

ADD9

STOP

M/SL

BERR

CC1

ADD1

ADD8

ITE

GCAL

CC0

ADD0

LSB

85/140

ST72104G, ST72215G, ST72216G, ST 72254G

12.5 8-BIT A/D CONVERTER (ADC)

12.5.1 Introduction

The on-chip Analog to Digital Converter ( ADC) peripheral is a 8-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has up to 16 m ultiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog vol tage levels from up to 16 different sources.

The result of the conversion is stored in a 8-bit Data Register. The A/D converter is controlled through a Control/Status Register.

12.5.2 Main Features

■ 8-bit conversion

■ Up to 16 channels with multiplexed input

■ Linear successive approximation

■ Data register (DR) which contains the results

■ Conversion complete status flag

■ On/off bit (to reduce consumption)

The block diagram is shown in Figure 1.

Figure 47. ADC Block Diagram

CPU

12.5.3 Functional Description

12.5.3.1 Analog Power Supply

DDA

and V

are the high and low level refer-

SSA

ence voltage pins. In some devices (refer to device pin out description) they are internally connected to the V

and VSS pins.

Conversion accuracy may therefore be impacted by voltage drops a nd no ise in th e ev ent of heavily loaded or badly decoupled power supply lines.

See electrical characteristics section for m ore details.

DIV 2

ADC

86/140

AIN0

AIN1

AINx

ANALOG

MUX

ADC

ADCDR

CH2 CH1CH3COCO 0 ADON 0 CH0

HOLD CONTROL

ADC

ADCCSR

ANALOG TO DIGITAL

CONVERTER

D1D3D7 D6 D5 D4 D0

8-BIT A/D CONVERTER (ADC) (Cont’d)

12.5.3.2 Digital A/D Conversion Result

The conversion is monotonic, meaning that the result never decreases if t he analog i nput does not and never increases if the analog input does not.

If the input voltage (V to V

(high-level voltage reference) then the

DDA

) is greater than or equal

AIN

conversion result in the DR register is FFh (full scale) without overflow indication.

If input voltage (V V

(low-level voltage reference) then the con-

SSA

) is lower than or equal to

AIN

version result in the DR register is 00h. The A/D converter is linear and the digital result of

the conversion is stored in the ADCDR register. The accuracy of the conversion is described in the parametric section.

is the maximum recommended impedance

AIN

for an analog input signal. If the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time.

12.5.3.3 A/D Conversion Phases

The A/D conversion is based on two conversion phases as shown in Figure 2:

■ Sample capacitor loading [duration: t

During this phase, the V measured is loaded into the C

input voltage to b e

AIN

ADC

]

LOAD

sample

capacitor.

■ A/D conversion [duration: t

CONV

] During this phase, the A/D conversion is computed (8 successive approximat ions cycles) and the C

sample capacitor is disconnected

ADC

from the analog input pin to get the optimum analog to digital conversion accuracy.

While the ADC is on, these two phases are continuously repeated.

At the end of each conversion, the sample capacitor is kept loaded with the pr evious measurem ent load. The advantage of this behaviour is that it minimizes the curre nt consum ption on the analog pin in case of single input channel measurement.

12.5.3.4 Software Procedure

Refer to the control/status register (CSR) and data register (DR) in Section 0.1.6 for the bit definitions and to Figure 2 for the timings.

ADC Configuration

The total duration of the A/D conversion is 12 ADC clock periods (1/f

ADC

=2/f

CPU

ST72104G, ST72215G, ST72216G, ST72254G

The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the «I/O ports» chapter. Using thes e pins as analog inputs does not affect the ability of the port to b e read as a logic input.

In the CSR register:

– Select the CH[3:0] bits to assign t he analog

channel to be converted.

ADC Conversion

In the CSR register:

– Set the ADON bit to enable the A/D converter

and to start the first conversion. From this time on, the ADC performs a continuous conversion of the selected channel.

When a conversion is complete

– The COCO bit is set by hardware. – No interrupt is generated. – The result is in the DR register and remains

valid until the next conversion has ended.

A write to the CSR register (with ADON set) aborts the current conversion, resets the COCO bit and starts a new conversion.

Figure 48. ADC Conversion Timings

ADON

HOLD CONTROL

LOAD

CONV

12.5.4 Low Power Modes

Mode Description

WAIT No effect on A/D Converter

A/D Converter disabled.

HALT

After wakeup from Halt mode, the A/D Converter requires a stabilisation time before accurate conversions can be performed.

Note: The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced power consumption when no conversion is needed and between single shot conversions.

12.5.5 Interrupts

None

ADCCSR WRITE

OPERATION

COCO BIT SET

87/140

ST72104G, ST72215G, ST72216G, ST 72254G

8-BIT A/D CONVERTER (ADC) (Cont’d)

12.5.6 Register Description CONTROL/STATUS REGISTER (CS R)

Read/Write Reset Value: 0000 0000 (00h)

COCO 0 ADON 0 CH3 CH2 CH1 CH0

Bit 7 = COCO

Conversion Complete

This bit is set by hardware. It is cleared by software reading the result in the DR register or writing to the CSR register. 0: Conversion is not complete 1: Conversion can be read from the DR register

Bit 6 = R eserved .

Bit 5 = ADON

must always be cleared.

A/D Converter On

DATA REGISTER (DR)

Read Only Reset Value: 0000 0000 (00h)

D7 D6 D5 D4 D3 D2 D1 D0

Bits 7:0 = D[7:0]

Analog Converted Value

This register contains the converted analog value in the range 00h to FFh.

Note: Reading this register reset the COCO flag.

This bit is set and cleared by software. 0: A/D converter is switched off 1: A/D converter is switched on

Bit 4 = R eserved .

must always be cleared.

Bits 3:0 = CH[3:0]

Channel Selection

These bits are set and cleared by software. They select the analog input to convert.

Channel Pin* CH3 CH2 CH1 CH0

AIN0 0 0 0 0 AIN1 0 0 0 1 AIN2 0 0 1 0 AIN3 0 0 1 1 AIN4 0 1 0 0 AIN5 0 1 0 1 AIN6 0 1 1 0 AIN7 0 1 1 1 AIN8 1 0 0 0

AIN9 1 0 0 1 AIN10 1 0 1 0 AIN11 1 0 1 1 AIN12 1 1 0 0 AIN13 1 1 0 1 AIN14 1 1 1 0 AIN15 1 1 1 1

*Note: The number of pins AND the channel selection varies according to the device. Refer to the device pinout.

88/140

8-BIT A/D CONVERTER (ADC) (Cont’d) Table 18. ADC Register Map and Reset Values

ST72104G, ST72215G, ST72216G, ST72254G

Address

(Hex.)

0070h

0071h

Label

ADCDR

Reset Value

ADCCSR

Reset Value

76543210

COCO

ADON

CH3

CH2

CH1

CH0

89/140

ST72104G, ST72215G, ST72216G, ST 72254G

13 INSTRUCTIO N SET

13.1 ST7 ADDRESSING MODES

The ST7 Core features 17 different addressing modes which can be classified in 7 main groups:

Addressing Mode Example

Inherent nop Immediate ld A,#$55 Direct ld A,$55 Indexed ld A,($55,X) Indirect ld A,([$55],X) Relative jrne loop Bit operation bset byte,#5

so, most of the ad dressing modes may be subdivided in two sub-modes called long and short:

– Long addressing mode is more powerful be-

cause it can use the full 64 Kbyte address space, however it uses more bytes and more CPU cycles.

– Short addressing mode is less powerful because

it can generally only access page zero (0000h 00FFh range), but the instruction size is more compact, and faster. All memory to memory instructions use short addressing modes only (CLR, CPL, NEG, BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)

The ST7 Assembler optimizes the use of long and short addressing modes.

The ST7 Instruction set is designed to minimize the number of bytes required per instruction: To do

Table 19. ST7 Addressing Mode Overview

Mode Syntax

Inherent nop + 0 Immediate ld A,#$55 + 1 Short Direct ld A,$10 00..FF + 1 Long Direct ld A,$1000 0000..FFFF + 2

No Offset Direct Indexed ld A,(X) 00..FF Short Direct Indexed ld A,($10,X) 00..1FE + 1

Long Direct Indexed ld A,($1000,X) 0000..FFFF + 2 Short Indirect ld A,[$10] 00..FF 00..FF byte + 2 Long Indirect ld A,[$10.w] 0000..FFFF 00..FF word + 2 Short Indirect Indexed ld A,([$10],X) 00..1FE 00..FF byte + 2 Long Indirect Indexed ld A,([$10.w],X) 0000..FFFF 00..FF word + 2 Relative Direct jrne loop PC-128/PC+127 Relative Indire ct jrne [$10] PC-128 /PC+1 27 Bit Direct bset $10,#7 00..FF + 1 Bit Indirect bset [$10],#7 00..FF 00..FF byte + 2 Bit Direct Relative btjt $10,#7,skip 00..FF + 2 Bit Indirect Relative btjt [$10],#7,skip 00..FF 00..FF byte + 3

Destination/

Source

Pointer

Address

(Hex.)

00..FF byte + 2

Pointer

Size

(Hex.)

Length (Bytes)

+ 0 (with X register) + 1 (with Y register)

+ 1

Note 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx.

90/140

ST7 ADDRESSING MODES (Cont’d)

13.1.1 Inherent

All Inherent instructions consist of a single byte. The opcode fully specifies all the required information for the CPU to process the operation.

Inherent Instruction Function

NOP No operation TRAP S/W Interrupt

WFI

HALT RET Sub-routine Return

IRET Interrupt Sub-routine Return SIM Set Interrupt Mask RIM Reset Interrupt Mask SCF Set Carry Flag RCF Reset Carry Flag RSP Reset Stack Pointer LD Load CLR Clear PUSH/POP Push/Pop to/from the stack INC/DEC Increment/Decrement TNZ Test Negative or Zero CPL, NEG 1 or 2 Complement MUL Byte Multiplicatio n SLL, SRL, SRA, RLC,

RRC SWAP Swap Nibbles

Wait For Interrupt (Low Power Mode)

Halt Oscillator (Lowest Power Mode)

Shift and Rotate Operations

13.1.2 Immediate

Immediate instructions have two bytes, the first byte contains the opcode, the second byte contains the operand value.

Immediate Instruction Function

LD Load CP Compare BCP Bit Compare AND, OR, XOR Logical Operations ADC, ADD, SUB, SBC Arithmetic Operations

ST72104G, ST72215G, ST72216G, ST72254G

13.1.3 Direct

In Direct instructions, the operands are referenced by their memory address.

The direct addressing m ode consists of two submodes:

Direct (short)

The address is a byte, thus requires only one byte after the opcode, but only allows 00 - FF addressing space.

Direct (lon g)

The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode.

13.1.4 Indexed (No Offset, Short, Long)

In this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset.

The indirect addressing mode consists of three sub-modes:

Indexed (No Offset)

There is no offset, (no extra byte after the opcode), and allows 00 - FF addressing space.

Indexed (Short)

The offset is a byte, thus requires only one byte after the opcode and allows 00 - 1FE addressing space.

Indexed (long)

The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 byt es after the opcode.

13.1.5 Indirect (Short, Long)

The required data byte to do the operation is found by its memory address, located in memory (pointer).

The pointer address follows th e op co de. Th e i ndirect addressing mode consists of two sub-modes:

Indirect (short)

The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode.

Indirect (lon g)

The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode.

91/140

ST72104G, ST72215G, ST72216G, ST 72254G

ST7 ADDRESSING MODES (Cont’d)

13.1.6 I ndi rect Indexed (S hort, Long)

This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (X or Y) with a pointer value located in memory. The pointer address follows the opcode.

The indirect indexed addressing mode consists of two sub-modes:

Indirect Indexed (Short)

The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing space, and requires 1 byte after the opcode.

Indirect Inde xed (Long)

The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode.

Table 20. Instructions Supporting Direct, Indexed, Indirect and Indirect Indexed Addressing Modes

SWAP Swap Nibbles CALL, JP Call or Jump subroutine

13.1.7 Relative Mode (Direct, Indirect)

This addressing mode is used to modify the PC register value by adding an 8-bit signed offset to it.

Available Relative Direct/

Indirect Instructions

JRxx Conditional Jump CALLR Call Relative

Function

The relative addressing mode consists of two submodes:

Relative (Direct)

The offset follows the opcode.

Relative (Indirect)

The offset is defined in memory, of which t he address follows the opcode.

Long and Short

Instructions

LD Load CP Compare AND, OR, XOR Logical Operations

ADC, ADD, SUB, SBC BCP Bit Compare

Short Instructions Only Function

CLR Clear INC, DEC Increment/Decrement TNZ Test Negative or Zero CPL, NEG 1 or 2 Complement BSET, BRES Bit Operations

BTJT, BTJF SLL, SRL, SRA, RLC,

RRC

Arithmetic Addition/subtraction operations

Bit Test and Jump Operations

Shift and Rotate Operations

Function

92/140

13.2 INSTRUCTION GROUPS

ST72104G, ST72215G, ST72216G, ST72254G

The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may

Load and Transfer LD CLR Stack operation PUSH POP RSP Increment/Decrement INC DEC Compare and Tests CP TNZ BCP Logical operations AND OR XOR CPL NEG Bit Operation BSET BRES Conditional Bit Test and Branch BTJT BTJF Arithmetic operations ADC ADD SUB SBC MUL Shift and Rotates SLL SRL SRA RLC RRC SWAP SLA Unconditional Jump or Call JRA JRT JRF JP CALL CALLR NOP RET Conditional Branch JRxx Interruption management TRAP WFI HALT IRET Code Condition Flag modification SIM RIM SCF RCF

be subdivided into 13 main groups as illustrated in the following table:

Using a pre-b y te

The instructions are described with one to four bytes.

In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes a re defined . These prebytes modify the meaning of the instruction they precede.

The whole instruction becomes:

PC-2 End of previous instruction PC-1 Prebyte PC Opcode PC+1 Additional word (0 to 2) acc ording to the

number of bytes required to compute the effective address

These prebytes enable instruction in Y as well as indirect addressing modes to be implemented. They precede the opcode of the instruction in X or the instruction using direct addres sing mode . The prebytes are:

PDY 90 Replace an X based instruction using

immediate, direct, indexed, or inherent addressing mode by a Y one.

PIX 92 Replace an instruction using direct, di-

rect bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode.

PIY 91 Replace an in struction using X indirect

indexed addressing mode by a Y one.

93/140

ST72104G, ST72215G, ST72216G, ST 72254G

INSTRUCTION GROUPS (Cont’d)

Mnemo Description Function/Example Dst Src H I N Z C

ADC Add with Carry A = A + M + C A M H N Z C ADD Addition A = A + M A M H N Z C AND Logical And A = A . M A M N Z BCP Bit compare A, Memory tst (A . M) A M N Z BRES Bit Reset bres Byte, #3 M BSET Bit Set bset Byte, #3 M BTJF Jump if bit is false (0) btjf Byte, #3, Jmp1 M C BTJT Jump if bit is true (1) btjt Byte, #3, Jmp1 M C CALL Call subroutine CALLR Call subroutine relative CLR Clear reg, M 0 1 CP Arithmetic Compare tst(Reg - M) reg M N Z C CPL One Complement A = FFH-A reg, M N Z 1 DEC Decrement dec Y reg, M N Z HALT Halt 0 IRET Interrupt routine return Pop CC, A, X, PC H I N Z C INC Increment inc X reg, M N Z JP Absolute Jump jp [TBL.w] JRA Jump relative always JRT Jump relative JRF Never jump jrf * JRIH Jump if ext. interrupt = 1 JRIL Jump if ext. interrupt = 0 JRH Jump if H = 1 H = 1 ? JRNH Jump if H = 0 H = 0 ? JRM Jump if I = 1 I = 1 ? JRNM Jump if I = 0 I = 0 ? JRMI Jump if N = 1 (minus) N = 1 ? JRPL Jump if N = 0 (plus) N = 0 ? JREQ Jump if Z = 1 (equal) Z = 1 ? JRNE Jump if Z = 0 (not equal) Z = 0 ? JRC Jump if C = 1 C = 1 ? JRNC Jump if C = 0 C = 0 ? JRULT Jump if C = 1 Unsigned < JRUGE Jump if C = 0 Jmp if unsigned >= JRUGT Jump if (C + Z = 0) Unsigned >

94/140

ST72104G, ST72215G, ST72216G, ST72254G

INSTRUCTION GROUPS (Cont’d)

Mnemo Description Function/Example Dst Src H I N Z C

JRULE Jump if (C + Z = 1) Unsigned <= LD Load dst <= src reg, M M, reg N Z MUL Multiply X,A = X * A A, X, Y X, Y, A 0 0 NEG Negate (2’s compl) neg $10 reg, M N Z C NOP No Operation OR OR operation A = A + M A M N Z POP Pop from the Stack pop reg reg M

pop CC CC M H I N Z C PUSH Push onto the Stack push Y M reg, CC RCF Reset carry flag C = 0 0 RET Subroutine Return RIM Enable Interrupts I = 0 0 RLC Rotate left true C C <= Dst <= C reg, M N Z C RRC Rotate right true C C => Dst => C reg, M N Z C RSP Reset Stack Pointer S = Max allowed SBC Subtract with Carry A = A - M - C A M N Z C SCF Set carry flag C = 1 1 SIM Disable Interrupts I = 1 1 SLA Shift left Arithmetic C <= Dst <= 0 reg, M N Z C SLL Shift left Logic C <= Dst <= 0 reg, M N Z C SRL Shift right Logic 0 => Dst => C reg, M 0 Z C SRA Shift right Arithmetic Dst7 => Dst => C reg, M N Z C SUB Subtraction A = A - M A M N Z C SWAP SWAP nibbles Dst[7..4] <=> Dst[3..0] reg, M N Z TNZ Test for Neg & Zero tnz lbl1 N Z TRAP S/W trap S/W interrupt 1 WFI Wait for Interrupt 0 XOR Exclusive OR A = A XOR M A M N Z

95/140

ST72104G, ST72215G, ST72216G, ST 72254G

14 ELECTRIC AL CHARACTERISTICS

14.1 PARAMETER CONDITIONS

Unless otherwise specified, all voltages are referred to V

14.1.1 Minimum and Maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient t emperature, supp ly voltage an d frequencies by tests in production on 100% of the devices with an ambient temp erature at T

and T

max (given by the selected temperature

A=TA

=25°C

range). Data based on characterization results, design

simulation and/or technology characteristics are indicated in the table foo tnotes and are not tested in production. Based on characterization, the mi nimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3Σ).

14.1.2 Typical values

Unless otherwise specified, typical data are based on T

=25°C, VDD=5V (for the 4.5V≤VDD≤5.5V

voltage range) and V

=3.3V (for the 3V≤VDD≤4V

voltage range). They are given only as design guidelines and are not tested.

14.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

14.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 49.

14.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 50.

Figure 50. Pin input voltage

ST7 PIN

Figure 49. Pin loading conditions

96/140

ST7 PIN

14.2 ABSOLUTE MAXIMUM RATINGS

ST72104G, ST72215G, ST72216G, ST72254G

Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and func tional operation of the device under these cond i-

14.2.1 Voltage Characteristics

Symbol Ratings Maximum value Unit

- V

1) & 2)

ESD(HBM)

ESD(MM)

Supply voltage 6.5 Input voltage on any pin VSS-0.3 to VDD+0.3 Electro-static discharge voltage (Human Body Model) Electro-static discharge voltage (Machine Model)

14.2.2 Current Characteristics

Symbol Ratings Maximum value Unit

VDD

VSS

Total current into VDD power lines (source) Total current out of VSS ground lines (sink) Output current sunk by any standard I/O and control pin 25

Output current sunk by any high sink I/O pin 50 Output current source by any I/Os and control pin - 25 Injected current on ISPSEL pin ± 5

INJ(PIN)

2) & 4)

Injected current on RESET Injected current on OSC1 and OSC2 pins ± 5

pin ± 5

Injected current on any other pin

INJ(PIN)

Total injected current (sum of all I/O and control pins)

14.2.3 Thermal Characteristics

tions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliabili ty.

see Section 14.7.2 "Absolute Elec-

trical Sensitivity" on page 114

5) & 6)

80 80

± 5

± 20

Symbol Ratings Value Unit

STG

Storage temperature range -65 to +150 °C Maximum junction temperature

(see Section 15.2 "THERMAL CHARACTERISTICS" on page 131)

Notes:

1. Directly connectin g the RES ET

and I/O pins to VDD or V

is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).

could damage the dev ice if an uni ntenti onal int ernal re set

To guarantee safe operation, th is connectio n has to be don e through a pull-up or pull-down r esistor (typic al: 4.7kΩ for

, 10kΩ for I/Os). Unused I/O pins must be tied in the same way to VDD or VSS according to their reset configuration.

RESET

2. When the current limitation is not possible , the V specification. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS.

INJ(PIN)

3. All power (V

) and ground (VSS) lines must always be connected to the external supply.

absolute m aximum rating m ust be respected, otherwis e refer to

4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout

the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken:

- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage

is lower than the specified limits)

- Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject the current as

far as possible from the analog input pins.

5. When several inputs are submitted to a current injection , the maximum ΣI

and negative injected currents (instantaneous values). These results are based on characterisation with ΣI mum current injection on four I/O port pins of the device.

is the absolute sum of the positive

INJ(PIN)

maxi-

6. True open drain I/O port pins do not accept positive injection.

97/140

ST72104G, ST72215G, ST72216G, ST 72254G

14.3 OPERATING CONDITIONS

14.3.1 General Operating Condi tions

Symbol Parameter Conditions Min Max Unit

OSC

Supply voltage see Figure 51 and Figure 52 3.2 5.5 V

3.5V for ROM devices

External clock frequency

≥

4.5V for FLASH devices

≥

3.2V 0

≥

1 Suffix Version 0 70

5 Suffix Version -10 85

Ambient temperatur e range

6 Suffix Version -40 85 7 Suffix Version -40 105 3 Suffix Version -40 125

MHz

°C

Figure 51. f

FUNCTIONALITY

NOT GUARANTE E D

OSC

IN THIS AREA

Maximum Operating Freq uen cy Ve rsus V

[MHz]

OSC

4 1

2.5 3.2 3.5 4 4.5 5 5.5

3.85

Supply Voltage for ROM devices 2)

FUNCTIONALITY GUARANTEED IN THIS AREA

FUNCTIONALITY NOT GUARANTEED IN THIS AREA WITH RESONATOR

SUPPLY VOLTAGE [V]

98/140

OPERATING CONDITIONS (Cont’d)

ST72104G, ST72215G, ST72216G, ST72254G

Figure 52. f

FUNCTIONALITY

NOT GUARANTE E D

OSC

IN THIS AREA

Maximum Operating Freq uen cy Ve rsus V

FUNCTIONALITY

[MHz]

OSC

4 1

2.5 3.2 3.5 4 4.5 5 5.5

NOT GUARANTEED

IN THIS AREA AT T

> 85°C

3.85

Supply Voltage for FLASH devices 2)

FUNCTIONALITY GUARANTEED IN THIS AREA

FUNCTIONALITY NOT GUARANTEED IN THIS AREA WITH RE SO NATOR

SUPPLY VOLTAGE [V]

Notes:

1. Guaranteed by construction. A/D operation and resonator oscillator start-up are not guaranteed below 1MHz.

2. Operating conditions with T

3. FLASH progr amming te sted in pro duction at maximum T

=3.2V, f

CPU

=4MHz.

=-40 to +125°C.

with two diffe rent condi tions: VDD=5.5V, f

=8MHz and

CPU

99/140

ST72104G, ST72215G, ST72216G, ST 72254G

OPERATING CONDITIONS (Cont’d)

14.3.2 Operating Conditions with Low Voltage Detector (LVD)

, f

Subject to general operating conditions for V

Symbol Parameter Conditions Min Typ

IT+

IT-

hyst

POR

g(VDD)

Reset release threshol d (V

rise)

Reset generation threshold (V

fall)

LVD voltage threshold hysteresis V VDD rise time rate Filtered glitch delay on V

Figure 53. High LVD Threshold Versus V

FUNCTIONALITY AND RESET NOT GUARANTEED IN THIS AREA

DEVICEUNDER

RESET

IN THIS AREA

OSC

[MHz]

High Threshold Med. Threshold Low Threshold

IT+-VIT-

Not detected by the LVD 40 ns

and f

FOR TEMPERATURES HIGHER THAN 85°C

, and TA.

OSC

for FLASH devices

OSC

4.10

3.75

3.25

3.85

3.50

3.00 200 250 300 mV

0.2 50 V/ms

Max Unit

4.30

3.90

3.35

4.05

3.65

3.10

4.50

4.05

3.55

4.30

3.95

3.35

FUNCTIONALITY NOT GUARANTEED IN THIS AREA

FUNCTIONAL AREA

2.5 3 3.5 4 4.5 5 5.5

Figure 54. Medium LVD Threshold Versus V

FUNCTIONALITY AND RESET NOT GUARANTEED IN THIS AREA

DEVICEUNDER

RESET

IN THIS AREA

[MHz]

OSC

2.5 3 V

Figure 55. Low LVD Threshold Versus V

[MHz]

OSC

DEVICEUNDER

RESET

IN THIS AREA

2.5 V

≥3V 3.5 4 4.5 5 5.5

IT-

FOR TEMPERATURES HIGHER THAN 85°C

≥3.5V 4 4.5 5 5.5

IT-

FUNCTIONALITY NOT GUARANTEED IN THIS AREA

FOR TEMPERATURES HIGHER THAN 85°C

SEE NOTE 4

3.2

3.85

≥

IT-

and f

OSC

for FLASH devices

OSC

for FLASH devices

2)4)

SUPPLY VOLTAGE [V]

FUNCTIONALITY NOT GUARANTEED IN THIS AREA

FUNCTIONAL AREA

SUPPLY VOLTAGE [V]

FUNCTIONALITY NOT GUARANTEED IN THIS AREA

FUNCTIONAL AREA

SUPPLY VOLTAGE [V]

Notes:

1. LVD typical data are based on T

=25°C. They are given only as design guidelines and are not tested.

2. Data based on characterization results, not tested in production.

3. The V

4. If the low LVD threshold is selected, when V anteed to continue functioning until it goes into reset state. The specified V on phase, but during a power down phase or voltage drop the device will function below this min. level.

rise time rate condition is needed to insure a correct device power-on and LVD reset. Not tested in production.

falls below 3.2V, (VDD minimum operating voltage), the device is guar-

min. value is necessary in the device power

100/140

STMicroelectronics ST72104G, ST72215G, ST72216G, ST72254G Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual